Document No.

IC-3183

(O. D. No.

IC-8683

Date Published

November 1992 P

The information in this document is subject to change without notice.

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75517(A)

4 BIT SINGLE-CHIP MICROCOMPUTER

The

PD75517(A) is a 75X series four-bit single-chip microcomputer which enables data processing

equivalent to that performed by an eight-bit microcomputer. It is a high-performance product, whose

minimum instruction execution time is 0.67

s, shorter than 0.95

s for the conventional

PD75516. The ROM

and RAM capacities are also larger, and the throughput of the 75X series is further increased. The

PD75517(A)

is suited to controllers of electric parts of automobiles.

FEATURES

Higher reliable than the

PD75517

Capacities of program memory, ROM: 24448

8 bits

Capacity of data memory, RAM: 1024

4 bits

Function for specifying the instruction execution time (useful for high-speed operation and saving power)

· 0.67

s/1.33

s/2.67

s/10.7

s (when the main system clock operates at 6.0 MHz)

· 0.95

s/1.91

s/3.82

s/15.3

s (when the main system clock operates at 4.19 MHz)

· 122

s (when the subsystem clock operates at 32.768 kHz)

Built-in A/D converter operable on low voltage

· 8-bit resolution

8 channels (Successive approximation system)

· V

= 2.7 to 6.0 V

Many I/O lines: 64

Enhanced timer function: 4 channels

Built-in 8-bit serial interface: Two channels

Built-in NEC serial bus interface (SBI)

Clock operable with ultra-low power consumption (when 5-

A TYP. operates on 3 V.)

Product with a built-in PROM available:

PD75P518

APPLICATIONS

Controller of electric parts of automobiles

ORDERING INFORMATION

Part number

Package

Quality grade

uPD75517GF(A)-

×××

-3B9

80-pin plastic QFP (14 mm

20 mm)

Special

Remark

×××

: Code number

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC

Corporation to know the specification of quality grade on the devices and its recommended applications.

Printed in Japan

NEC CORPORATION1992

ELECTRON DEVICE

PD75517(A)

FUNCTIONS

ROM

RAM

24448

8 bits

1024

4 bits

(4-bit

8 or 8-bit

4 banks

· 0.67

s/1.33

s/2.67

s/10.7

s (At 6.0 MHz)

· 0.95

s/1.91

s/3.82

s/15.3

s (At 4.19 MHz)

· 122

s (At 32.768 kHz)

16 (Shared with INT, SIO, PPO, and analog input. Seven lines can be pulled

up by software.)

28 (Four lines for LED driving)

· 16 lines can be pulled up by software.

· Four lines can be pulled down by the mask option.

20 (Eight lines for LED driving. Withstand voltage is 10 V. 20 lines can be

pulled up by the mask option.)

8-bit resolution

8 channels (Successive approximation system)

· Capable of low-voltage operation: V

= 2.7 to 6.0 V

Four channels

Timer/event counter

Basic interval timer

Timer/pulse generator (14-bit PWM output enabled)

Clock timer

Two channels

· NEC standard serial bus interface (SBI)/

three-wire SIO: One channel

· General clock synchronous serial interface

(three-wire SIO): One channel

Vectored interrupt : Seven sources

(External: 3, internal: 4)

Test input

: Two sources

(External: 1, internal: 1)

Clock test flag is provided.

Parallel edge detection flag for key scan input is provided.

· Set/reset/test/Boolean operation for bit data

· 4-bit data transfer, arithmetic/logical, increment/decrement, and comparison

instructions

· 8-bit data transfer, arithmetic/logical, increment/decrement, and comparison

instructions

· Ceramic/crystal oscillator for main system clock : 6.0 MHz, 4.19 MHz

· Crystal oscillator for subsystem clock

: 32.768 kHz

= 2.7 to 6.0 V

80-pin plastic QFP (14

20 mm)

Built-in memory

General registers

Instruction cycle

I/O ports

A/D converter

Timer/counter

Serial interface

Interrupt

Instruction set

System clock generator

Operating supply voltage

Package

Item

Functions

Total

Number of CMOS

input lines

Number of CMOS

I/O lines

Number of N-ch

open-drain I/O lines

PD75517(A)

PIN CONFIGURATION (TOP VIEW)

IC: Internally connected. Connect the IC pin to V

Note Be sure to supply power to both the V

pins.

AN1

AN2

AN3

AN4/P150

AN5/P151

AN6/P152

AN7/P153

P120

P121

P122

P123

P130

P131

P132

P133

P140

P141

P142

P143

RESET

XT2

XT1

P00/INT4

P01/SCK0

P02/SO0/SB0

P03/SI0/SB1

P10/INT0

P11/INT1

P12/INT2

P13/ TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

AN0

REF

P113

P112

P111

P110

P103

P102

P101

P100

P93

P92

P91

P90

SI1/P83

SO1/P82

SCK1/P81

PPO/P80

KR7/P73

KR6/P72

KR5/P71

KR4/P70

KR3/P63

KR2/P62

KR1/P61

KR0/P60

P53

P52

P51

P50

P43

P42

P41

P40

P33

P32

P31

Note

PD75517GF(A)-

×××

-3B9

PD75517(A)

INTERNAL BLOCK DIAGRAM

TI0/P13

PTO0/P20

BUZ/P23

PPO/P80

SI0/SB1/P03

SO0/SB0/P02

SCK0/P01

SI1/P83

SO1/P82

SCK1/P81

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0/P60
- KR7/P73

AN0 - AN3

AN4/P150
- AN7/P153

REF

P00 - P03

P10 - P13

P20 - P23

P30 - P33

P40 - P43

Note

P50 - P53

Note

P60 - P63

P70 - P73

P80 - P83

P90 - P93

P100 - P103

P110 - P113

P120 - P123

Note

P130 - P133

Note

P140 - P143

Note

P150 - P153

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

Port 10

Port 11

Port 12

Port 13

Port 14

Port 15

Basic
interval
timer

INTBT

Timer/event
counter #0

INTT0

Watch timer

INTW

Timer/pulse
generator

INTTPG

Serial bus
interface 0

INTCSI0

Serial
interface 1

Interrupt
control

Bit seq.
buffer (16)

A/D
converter

Program counter (15)

ROM program memory

24448

8 bits

ALU

SP(8)

SBS(2)

Bank

Decode and
control

General register

RAM data memory

1024

4 bits

Clock output
control

PCL/P22

Clock divider

Clock generator

Sub

Main

Stand by
control

XT1 XT2 X1 X2

CPU clock

RESET

Note

Port 4, Port 5, Port 12, Port 13, and Port 14 are N-ch open-drain

I/O ports with a medium withstand voltage of 10 V.

PD75517(A)

CONTENTS

PIN FUNCTIONS ........................................................................................................................

1.1

PORT PINS ......................................................................................................................................

1.2

NON-PORT PINS ............................................................................................................................

1.3

PIN INPUT/OUTPUT CIRCUITS ....................................................................................................

1.4

CONNECTION OF UNUSED PINS ................................................................................................

1.5

SELECTION OF A MASK OPTION ................................................................................................

ARCHITECTURE AND MEMORY MAP OF THE

PD75517(A) ..............................................

2.1

DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES ................................

2.2

GENERAL REGISTER BANK CONFIGURATION ..........................................................................

2.3

MEMORY-MAPPED I/O .................................................................................................................

INTERNAL CPU FUNCTIONS ....................................................................................................

3.1

PROGRAM COUNTER (PC) ...........................................................................................................

3.2

PROGRAM MEMORY (ROM) ........................................................................................................

3.3

DATA MEMORY (RAM) .................................................................................................................

3.4

GENERAL REGISTERS ...................................................................................................................

3.5

ACCUMULATORS ..........................................................................................................................

3.6

STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS) .....................................

3.7

PROGRAM STATUS WORD (PSW) ..............................................................................................

3.8

BANK SELECT REGISTER (BS) .....................................................................................................

PERIPHERAL HARDWARE FUNCTIONS ..................................................................................

4.1

DIGITAL I/O PORTS .......................................................................................................................

4.2

CLOCK GENERATOR ......................................................................................................................

4.3

CLOCK OUTPUT CIRCUIT .............................................................................................................

4.4

BASIC INTERVAL TIMER ...............................................................................................................

4.5

CLOCK TIMER .................................................................................................................................

4.6

TIMER/EVENT COUNTER .............................................................................................................

4.7

TIMER/PULSE GENERATOR .........................................................................................................

4.8

SERIAL INTERFACE (CHANNEL 0) ...............................................................................................

4.8.1

Serial Interface (Channel 0) Functions ........................................................................

4.8.2

Configuration of Serial Interface (Channel 0) ............................................................

4.8.3

Register Functions .........................................................................................................

4.8.4

Signals .............................................................................................................................

4.8.5

Serial Interface (Channel 0) Operation .......................................................................

100

4.8.6

Transfer Start in Each Mode ........................................................................................

110

4.8.7

Manipulation of SCK0 Pin Output ...............................................................................

111

PD75517(A)

4.9

SERIAL INTERFACE (CHANNEL 1) ...............................................................................................

112

4.9.1

Serial Interface (Channel 1) Functions ........................................................................

112

4.9.2

Serial Interface (Channel 1) Configuration .................................................................

112

4.9.3

Register Functions .........................................................................................................

114

4.9.4

Serial Interface (Channel 1) Operation .......................................................................

115

4.10

A/D CONVERTER ...........................................................................................................................

117

4.11

BIT SEQUENTIAL BUFFER ............................................................................................................

124

INTERRUPT FUNCTION ............................................................................................................ 125

5.1

CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT ....................................................

125

5.2

HARDWARE OF THE INTERRUPT CONTROL CIRCUIT ..............................................................

127

5.3

INTERRUPT SEQUENCE ................................................................................................................

134

5.4

MULTIPLE INTERRUPT PROCESSING CONTROL ......................................................................

135

5.5

VECTOR ADDRESS SHARE INTERRUPT PROCESSING ............................................................

137

STANDBY FUNCTION ............................................................................................................... 138

6.1

SETTING OF STANDBY MODES AND OPERATION STATUSES .............................................

138

6.2

RELEASE OF THE STANDBY MODES .........................................................................................

139

6.3

OPERATION AFTER A STANDBY MODE IS RELEASED ............................................................

141

RESET FUNCTION ..................................................................................................................... 142

INSTRUCTION SET .................................................................................................................... 144

8.1

PD75517(A) INSTRUCTIONS ......................................................................................................

144

8.2

INSTRUCTION SET AND ITS OPERATION ..................................................................................

147

8.3

INSTRUCTION CODES OF EACH INSTRUCTION .......................................................................

156

ELECTRICAL CHARACTERISTICS ............................................................................................. 162

10. PACKAGE DIMENSIONS ........................................................................................................... 174

11. RECOMMENDED SOLDERING CONDITIONS ......................................................................... 175

APPENDIX A

SERIES PRODUCT FUNCTIONS ............................................................................ 176

APPENDIX B

DEVELOPMENT TOOLS ......................................................................................... 177

PD75517(A)

1. PIN FUNCTIONS

1.1 PORT PINS (1/2)

Notes 1. The circuits enclosed in circles have a Schmitt-triggered input.

2. An LED can be driven directly.

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30

Note 2

P31

Note 2

P32

Note 2

P33

Note 2

P40-P43

Note 2

P50-P53

Note 2

P60

P61

P62

P63

P70

P71

P72

P73

INT4

SCK0

SO0/SB0

SI0/SB1

INT0

INT1

INT2

TI0

PTO0

PCL

BUZ

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

With noise elimination function

4-bit input port (Port 0).

For P01 to P03, pull-up resistors can be

provided by software in units of 3 bits.

4-bit input port (Port 1).

Pull-up resistors can be provided by software

in units of 4 bits.

4-bit I/O port (Port 2).

Pull-up resistors can be provided by software

in units of 4 bits.

Programmable 4-bit I/O port (Port 3).

Input/output can be specified bit by bit.

Pull-up resistors can be provided by software

in units of 4 bits.

N-ch open-drain 4-bit I/O port (Port 4).

A pull-up resistor can be provided bit by bit

(mask option).

Withstand voltage is 10 V in open-drain mode.

N-ch open-drain 4-bit I/O port (Port 5).

A pull-up resistor can be provided bit by bit

(mask option).

Withstand voltage is 10 V in open-drain mode.

Programmable 4-bit I/O port (Port 6).

Input/output can be specified bit by bit.

Pull-up resistors can be provided by software

in units of 4 bits.

4-bit I/O port (Port 7).

Pull-up resistors can be provided by software

in units of 4 bits.

Also
used as

Pin name

I/O

- A

- B

- C

E - B

E - C

- C

- A

8-bit I/O

Input

High level

(when a pull-up

resistor is

provided) or

high impedance

High level

(when a pull-up

resistor is

provided) or

high impedance

Input

When reset

Function

I/O

Note 1

circuit
type

PD75517(A)

1.1 PORT PINS (2/2)

Note The circuits enclosed in circles have a Schmitt-triggered input.

Function

Also
used as

Pin name

I/O

8-bit I/O

When reset

I/O

Note

circuit
type

Input

Low level (when

a pull-down

resistor is

provided) or

high impedance

Input

High level

(when a pull-up

resistor is

provided) or

high impedance

High level

(when a pull-up

resistor is

provided) or

high impedance

High level

(when a pull-up

resistor is

provided) or

high impedance

Input

PPO

SCK1

SO1

SI1

AN4-AN7

I/O

P80

P81

P82

P83

P90-P93

P100-P103

P110-P113

P120-P123

P130-P133

P140-P143

P150-P153

Y - A

4-bit input port (Port 8).

4-bit I/O port (Port 9).

A pull-down resistor can be provided bit by bit

(mask option).

4-bit I/O port (Port 10)

4-bit I/O port (Port 11)

N-ch open-drain, 4-bit I/O port (Port 12).

Pull-up resistors can be provided bit by bit

(mask option).

Withstand voltage is 10 V in open-drain mode.

N-ch open-drain, 4-bit I/O port (Port 13).

Pull-up resistors can be provided bit by bit

(mask option).

Withstand voltage is 10 V in open-drain mode.

N-ch open-drain, 4-bit I/O port (Port 14).

Pull-up resistors can be provided bit by bit

(mask option).

Withstand voltage is 10 V in open-drain mode.

4-bit input port (Port 15)

PD75517(A)

1.2 NON-PORT PINS

Notes 1. The circuits enclosed in circles have a Schmitt-triggered input.

2. Be sure to input V

level to this pin.

Function

Also
used as

Pin name

I/O

Synchronous

Asynchronous

Edge detection vectored interrupt input pin

(The edge to be detected is selectable.)

Edge detection testable input pin

(An rising edge is detected.)

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60-P63

P70-P73

P81

P82

P83

P150-P153

P80

External event pulse input pin for the timer/event counter

Timer/event counter output pin

Clock output pin

Fixed frequency output pin (for buzzer or system clock

trimming)

Serial clock I/O pin

Serial data output pin or serial bus I/O pin

Serial data input pin or serial bus I/O pin

Edge detection vectored interrupt input pin (Either a rising

or falling edge is detected.)

Parallel-falling-edge-sensitive testable input pins

Serial clock I/O pin

Serial data output pin

Serial data input pin

Analog input pins to A/D converter

A/D converter reference voltage input pin

A/D converter reference GND pin

Pin for connection to a crystal/ceramic resonator for main

system clock generation. When external clock is used, it is

input to X1, and its inverted signal is input to X2.

Pin for connection to a crystal resonator for subsystem

clock generation. When external clock is used, it is input to

XT1, and XT2 is left open.

System reset input pin

Timer/pulse generator pulse output pin

Positive power supply pin

Ground pin

Internally connected

Note 2

Input

TI0

PTO0

PCL

BUZ

SCK0

SO0/SB0

SI0/SB1

INT4

INT0

INT1

INT2

KR0-KR3

KR4-KR7

SCK1

SO1

SI1

AN0-AN3

AN4-AN7

REF

X1, X2

XT1

XT2

RESET

PPO

I/O

Note 1

circuit
type

When reset

- C

E - B

- A

- B

- C

- A

Y - A

PD75517(A)

1.5 SELECTION OF A MASK OPTION

The following mask options are provided for pins.

(1) Specification of built-in pull-up and pull-down resistors

Table 1-2 Selection of Pull-Up and Pull-Down Resistors

(2) Specification of built-in feed-back resistors for subsystem clock oscillation

Table 1-3 Selection of Feed-Back Resistors

Caution Even if built-in feed-back resistors are provided when no subsystem clock is used, operation is

not affected except increased power supply current I

P40-P43,

P50-P53,

P120-P123,

P130-P133,

P140-P143

P90-P93

Pin name

No pull-up resistor provided

(Can be specified bit by bit.)

No pull-down resistor provided

(Can be specified bit by bit.)

Pull-up resistors provided

(Can be specified bit by bit.)

Pull-down resistors provided

(Can be specified bit by bit.)

Mask option

XT1, XT2

Feed-back resistors provided

(when a subsystem clock is used)

No feed-back resistors provided

(when no subsystem clock is used)

Mask option

Pin name

PD75517(A)

2. ARCHITECTURE AND MEMORY MAP OF THE

PD75517(A)

The

PD75517(A) has three architectural features:

(a) Data memory bank configuration

(b) General register bank configuration

Each of these features is explained below.

2.1 DATA MEMORY BANK CONFIGURATION AND ADDRESSING MODES

As shown in Fig. 2-1, the data memory space of the

PD75517(A) contains a static RAM (1024 words

bits) at addresses 000H to 3FFH and peripheral hardware (such as I/O ports and timers) at addresses F80H to

FFFH. To address a 12-bit address in this data memory space, the

PD75517(A) uses such a memory bank

configuration that the low-order eight bits are specified with an instruction directly or indirectly, and the high-

order four bits are used to specify a memory bank (MB).

To specify a memory bank (MB), a memory bank enable flag (MBE) and memory bank select register (MBS)

are contained, allowing the addressing indicated in Fig. 2-1 and 2-2 and Table 2-1. (The MBS is a register used

to select a memory bank, and can be set to 0, 1, 2, 3, or 15. The MBE is a flag used to determine whether a

memory bank selected using the MBS register is to be enabled. The MBE is automatically saved or restored

at the time of interrupt processing or subroutine processing, so that it can be freely set in interrupt processing

and subroutine processing.)

In addressing data memory space, the MBE is usually set to 1 (MBE = 1), and the static RAM in the memory

bank specified by the MBS is operated. However, the MBE = 0 mode or the MBE = 1 mode can be selected

for each step of program processing for more efficient programming.

The MBE and MBS are set as indicated below.

Example

SET1 MBE

; MBE

CLR1 MBE

; MBE

SEL MB0

; MBS

SEL MB1

; MBS

SEL MB15

; MBS

· Interrupt processing

· Processing that repeats internal hardware and static RAM operations

· Subroutine processing

· Usual program processing

MBE = 0 mode

MBE = 1 mode

Applicable program processing

PD75517(A)

Table 2-1 Addressing Modes

Bit specified by bit at the address specified by MB and mem. In this case:

When MBE = 0 and mem = 00H-7FH, MB = 0

When MBE = 0 and mem = 80H-FFH, MB = 15

When MBE = 1, MB = MBS

Address specified by MB and mem. In this case:

When MBE = 0 and mem = 00H-7FH, MB = 0

When MBE = 0 and mem = 80H-FFH, MB = 15

When MBE = 1, MB = MBS

Address specified by MB and mem (mem: even address). In this case:

When MBE = 0 and mem = 00H-7FH, MB = 0

When MBE = 0 and mem = 80H-FFH, MB = 15

When MBE = 1, MB = MBS

Address specified by MB and HL.

In this case, MB = MBE·MBS

Address specified by DE in memory bank 0

Address specified by DL in memory bank 0

Address specified by MB and HL (with the L register holding an even number).

In this case, MB = MBE·MBS

Bit specified by bit at the address specified by fmem. In this case:

fmem = FB0H-FBFH (interrupt-related hardware)

fmem = FF0H-FFFH (I/O port)

Bit specified by the low-order 2 bits of the L register at the address specified

by the high-order 10 bits of pmem and the high-order 2 bits of the L register.

In this case, pmem = FC0H-FFFH

Bit specified by bit at the address specified by MB, H, and the low-order 4 bits

of mem.

In this case, MB = MBE·MBS

Address specified by SP in memory bank 0, 1, 2, and 3 selected by SBS

1-bit direct addressing

4-bit direct addressing

8-bit direct addressing

4-bit register indirect

addressing

8-bit register indirect

addressing

Bit manipulation

addressing

Stack addressing

mem.bit

mem

@HL

@HL+

@HL

@DE

@DL

@HL

fmem.bit

pmem.@L

@H+mem.bit

Representation
format

Specified address

Addressing mode

PD75517(A)

As summarized in Table 2-1, the

PD75517(A) allows both direct and indirect addressing in data memory

manipulation for 1-bit data, 4-bit data, and 8-bit data, so that very efficient and simple programming can be

performed.

Examples 1.

The 8-bit data of port 4 and port 5 are transferred to addresses 20H and 21H.

CLR1

MBE

; MBE

XA, PORT4

; XA

Ports 5, 4

MOV

20H, XA

; (21H, 20H)

When P02 is 0, P33 is set.

SKT

PORT0.2

; Skip if bit 2 of port 0 is 1

SET1

PORT3.3

; Set bit 3 of port 3

A different value is output to port 6, depending on the status of P10.

SKF

PORT1.0

; Skip if bit 0 of port 1 is 0

MOV

A, #1010B

; A

1010B (string effect)

MOV

A, #0101B

; A

0101B (string effect)

SEL

MB15

; or CLR1 MBE

OUT

PORT6, A

; Port 6

Fig. 2-2 Updating Static RAM Addresses

INCS D

DECS D

INCS L

DECS L

INCS D

DECS D

INCS E

DECS E

INCS H

DECS H

INCS L

DECS L

INCS H

DECS H

@DL

4-bit transfer

@DE

4-bit transfer

@HL

4-bit
manipulation

8-bit
manipulation

@H + mem.bit

Bit manipulation

Direct
addressing
Bit manipulation
4-bit
8-bit

DECS DE

INCS DE

DECS HL

INCS HL

Automatic
decrement

Automatic
increment

PD75517(A)

2.2 GENERAL REGISTER BANK CONFIGURATION

The

PD75517(A) contains four register banks, each consisting of eight general registers: X, A, B, C, D, E,

H, and L. These registers are mapped to addresses 00H to 1FH in memory bank 0 of the data memory. (See

Fig. 2-3.) To specify a general register bank, a register bank enable flag (RBE) and a register bank select register

(RBS) are contained. The RBS is a register used to select a register bank, and the RBE is a flag used to determine

whether a register bank selected using the RBS is to be enabled. The register bank (RB) enabled at instruction

execution is determined as RB = RBE·RBS

As indicated in Table 2-2, the

PD75517(A) enables the user to create programs in a very efficient manner

by selecting a register bank from the four register banks, depending on whether the processing is normal

processing or interrupt processing. (The RBE is automatically saved and set at the time of interrupt processing,

and is automatically restored upon completion of interrupt processing.)

Table 2-2 Example of the Use of Register Banks with Normal Routines and Interrupt Routines

The RBE and RBS are set as indicated below.

Example

SET1

RBE ; RBE

CLR1

RBE ; RBE

SEL

RB0 ; RBS

SEL

RB3 ; RBS

The general registers allow transfers, comparisons, arithmetic/logical operations, and increments and

decrements not only on a 4-bit basis, but also on an 8-bit basis with the XA, HL, DE, and BC register pairs.

In this case, the register pairs of the register bank that has the inverted value of bit 0 of a register bank specified

by RBE·RBS can be specified as XA', HL', DE', and BC', thus providing eight 8-bit registers. (See Fig. 2-4.)

Example

SET1

RBE

; RBE

SEL

RB2

; RBS

MOV

XA, #18H ; XA

18H

ADDS HL, XA

; HL

HL+XA

SUBS

HL', XA

; HL'

HL'XA (HL' is HL of register bank 3)

INCS

; HL

HL+1

MOV

XA, #00H ; XA

00H (string effect)

MOV

XA, #10H ; XA

10H (string effect)

Normal processing

Single interrupt processing

Dual interrupt processing

Multiple (triple or more) interrupt processing

Use register banks 2 and 3 with RBE = 1.

Use register bank 0 with RBE = 0.

Use register bank 1 with RBE = 1.

(In this case, the RBS needs to be saved and restored.)

Save the registers with PUSH or POP.

PD75517(A)

2.3 MEMORY-MAPPED I/O

The

PD75517(A) employs memory-mapped I/O, which maps peripheral hardware such as timers and I/O

ports to addresses F80H to FFFH in the data memory space as shown in Fig. 2-1. This means that there is no

particular instruction to control peripheral hardware, but all peripheral hardware is controlled using memory

manipulation instructions. (Some mnemonics for hardware control are available to make programs readable.)

To manipulate peripheral hardware, the addressing modes listed in Table 2-3 can be used.

Table 2-3 Addressing Modes Applicable to Peripheral Hardware

Fig. 2-5 summarizes the I/O map of the

PD75517(A).

The items in Fig. 2-5 have the following meanings:

· Symbol:

Name representing the address of incorporated hardware, which can be coded in the operand

field of an instruction

· R/W

Indicates whether the hardware allows read/write operation.

R/W: Both read and write operations possible

: Read only

: Write only

· Number of manipulatable bits:

Indicates the number of bits that can be processed in hardware manipulation

: Bits can be manipulated on an indicated bit (1-, 4-, or 8-bit) basis.

: Particular bits can be manipulated. For these bits, see Remarks.

: Bits cannot be manipulated on an indicated bit (1-, 4-, or 8-bit) basis.

· Bit manipulation addressing:

Bit manipulation addressing applicable in hardware bit manipulation

Bit manipulation

4-bit manipulation

8-bit manipulation

Direct addressing mode specifying mem.bit with MBE = 0 or

(MBE = 1, MBS = 15)

Direct addressing mode specifying fmem.bit regardless of MBE

and MBS setting

Indirect addressing mode specifying pmem.@L regardless of

MBE and MBS setting

Direct addressing mode specifying mem with MBE = 0 or (MBE

= 1, MBS = 15)

Direct addressing mode specifying mem (even address) with

MBE = 0 or (MBE = 1, MBS = 15)

All hardware allowing bit

manipulation

IST0, IST1, MBE, RBE, EOT,

×××

, IRQ

×××

, PORTn.

BSBn.

PORTn.

All hardware allowing 4-bit

manipulation

All hardware allowing 8-bit

manipulation addressing

Applicable addressing mode

Applicable hardware

PD75517(A)

Fig. 2-5

PD75517(A) I/O Map (1/4)

Notes 1.

Can be operated separately as the RBS and MBS during 4-bit manipulation.

Can also be operated as the BS during 8-bit manipulation.

TOE0: Timer/event counter 0 output enable flag (W)

R/W

Address

F80H

F85H

F86H

F98H

FA0H

FA2H

FA4H

FA6H

TOE0

Note 2

mem.bit

Remarks

Bit
manipulation
addressing

Bit 0 is fixed
to 0

Hardware name (symbol)

Number of bits that

Stack pointer (SP)

Basic interval timer mode register (BTM)

Basic interval timer (BT)

Clock mode register (WM)

Timer/event counter 0 mode register (TM0)

Timer/event counter 0 count register (T0)

Timer/event counter 0 modulo register (TMOD0)

Only bit 3
allows bit
manipulation.

Only bit 3 can
be manipulat-
ed

1 bit

4 bits

8 bits

F82H

F83H

F84H

Memory bank select register
(MBS)

Bank select
register (BS)

Stack bank select register (SBS)

R/W

Bits 3 and 2
are always
set to 0.

Note 1

F90H

F94H

Timer pulse generator (TPGM)

mem.bit

Only bit 3 can
be manipulat-
ed

F96H

Timer/pulse generator modulo register (MODL)

R/W

Timer/pulse generator modulo register (MODH)

R/W

can be manipulated

PD75517(A)

Fig. 2-5

PD75517(A) I/O Map (2/4)

Remarks 1. IE

×××

: Interrupt enable flag

2. IRQ

×××

: Interrupt request flag

R/W

Address

FB0H

FB2H

FB3H

FC0H

FC2H

FC3H

fmem.bit

mem.bit

pmem.@L

RBE

MBE

IST0

IST1

R/W

fmem.bit

FB4H

FB5H

FB6H

FB7H

FB8H

FBAH

FBCH

FBDH

FBEH

FBFH

IE4

IRQ4

IEBT

IRQBT

IEW

IRQW

IET0

IRQT0

IECSI0

IRQCSI0

IE0

IRQ0

IE2

IRQ2

IE1

IRQ1

R/W

FC1H

Remarks

Bit
manipulation
addressing

Hardware name (symbol)

1 bit

4 bits

8 bits

Program status word (PSW)

Processor clock control register (PCC)

INT0 mode register (IM0)

INT1 mode resistor (IM1)

INT2 mode register (IM2)

System clock control register (SCC)

Bit sequential buffer 0 (BSB0)

Bit sequential buffer 1 (BSB1)

Bit sequential buffer 2 (BSB2)

Bit sequential buffer 3 (BSB3)

Manipulated
with EI/DI
instruction

Bit 2 is fixed
to 0

Bits 3, 2, and
1 are fixed to
0

Bits 3 and 2
are fixed to
0

Bits 2 and 1
are fixed to 0

Interrupt priority select register (IPS)

FBBH

IETPG

IRQTPG

FB9H

EOT

R/W

FC8H

Serial operation mode register 1 (CSIM1)

Only bit 7
allows bit
manipulation.

FCCH

Serial I/O shift register 1 (SIO1)

CSIE1

R/W

mem.bit

Number of bits that
can be manipulated

PD75517(A)

Fig. 2-5

PD75517(A) I/O Map (3/4)

Note When developing a program, set 0 to the following two bits of the port mode register group C (PMGC):

FEEH, b0 (Equivalent to PM8)

FEFH, b3 (Equivalent to PM15)

For, while this port on the chip side is used for input only, the corresponding port on the emulator

is an I/O port.

R/W

Address

FD0H

FD8H

FDAH

FDCH

EOC

SOC

b3: 1-bit write
b2: 1-bit read

R/W

FE0H

FE2H

FE4H

mem.bit

FE6H

R/W

mem.bit

FE8H

FEEH

PM32

PM33

PM31

PM30

PM10

PM11

PM9

Note

PM62

PM63

PM61

PM60

PM14

PM13

PM12

R/W

Remarks

Bit
manipulation
addressing

Hardware name (symbol)

1 bit

4 bits

8 bits

Clock output mode register (CLOM)

A /D conversion mode register (ADM)

SA register (SA)

Pull-up resistor specification register group A
(POGA)

Serial operation mode register 0 (CSIM0)

SBI control register (SBIC)

Serial I/O shift register 0 (SIO0)

Slave address register (SVA)

Port mode register group A (PMGA)

Port mode register group C (PMGC)

b6: 1-bit read

All bits allow
bit manipula-
tion only

COI

CSIE0

WUP

RELD

CMDD

CMDT

RELT

ACKD

BSYE

ACKE

ACKT

FECH

PM2

PM7

PM5

PM4

Port mode register group B (PMGB)

Note

Number of bits that
can be manipulated

PD75517(A)

3. INTERNAL CPU FUNCTIONS

3.1 PROGRAM COUNTER (PC): 15 BITS

The program counter is a 15-bit binary counter for holding program memory address information.

Fig. 3-1 Program Counter Format

Note that the reset start address must be set within a space of 16K bytes (0000H to 3FFFH). This is because

a RESET input sets the low-order six bits of program memory address 0000H in PC13 to PC8, and the contents

of address 0001H in PC7 to PC0, and 0 in PC14 for initialization.

3.2 PROGRAM MEMORY (ROM): 24448 WORDS

8 BITS

The program memory is a mask-programmable ROM with a configuration of 24448 words

8 bits for storing

programs, table data, and so forth.

Program memory is addressed by the program counter. Table data can be referenced using the table

reference instruction (MOVT).

Fig. 3-2 shows the allowable branch address ranges for the branch instructions and subroutine call

instructions. The whole-space branch instruction (BRA !addr1) and the whole-space call instruction (CALLA

!addr1) allow a direct branch throughout the whole space 0000H-5F7FH. The relative branch instruction (BR

$addr) allows a branch to addresses (PC - 15 to PC - 1 and PC + 2 to PC + 16) regardless of block boundaries.

The program memory is located at addresses 0000H to 5F7FH containing the following specially assigned

addresses. (All areas excluding 0000H and 0001H can be used as normal program memory.)

· 0000H to 0001H

Vector table for holding the RBE and MBE setting values and program start address at the time of a RESET

input. A reset start can be performed at an arbitrary address within a 16K-byte space (0000H to 3FFFH).

· 0002H to 000DH

Vector table for holding the RBE and MBE setting values and program start address at the time of each

vectored interrupt occurrence. Interrupt processing can be started at an arbitrary address within a 16K-

byte space (0000H to 3FFFH).

· 0020H to 007FH

Table area referenced by the GETI instruction

Note

Note The GETI instruction can represent an arbitrary 2-byte or 3-byte instruction or two 1-byte instructions

in 1 byte, thus reducing the number of program steps. (See Section 8.1.)

PC12

PC11

PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PC13

PC14

PD75517(A)

Fig. 3-2 Program Memory Map

Caution The start address of an interrupt vector shown above consists of 14 bits. So, the start address

must be set within a 16K-byte space (0000H to 3FFFH).

Remark In addition to the above, the BR PCDE and BR PCXA instructions can cause a branch to an address

with only the low-order 8 bits of the PC changed.

MBE

RBE

0000H

MBE

RBE

0002H

MBE

RBE

0004H

MBE

RBE

0006H

MBE

RBE

0008H

MBE

RBE

000AH

007FH

0080H

0020H

0FFFH

1000H

2FFFH

3000H

5F7FH

Internal reset start address (high-order 6 bits)

Internal reset start address (low-order 8 bits)

INTBT/INT4 start address (high-order 6 bits)

INTBT/INT4 start address (low-order 8 bits)

INT0 start address (high-order 6 bits)

INT0 start address (low-order 8 bits)

INT1 start address (high-order 6 bits)

INT1 start address (low-order 8 bits)

INTCSI0 start address

(high-order 6 bits)

INTCSI0 start address

(low-order 8 bits)

INTT0 start address (high-order 6 bits)

INTT0 start address (low-order 8 bits)

INTTPG start address (high-order 6 bits)

INTTPG start address (low-order 8 bits)

GETI instruction reference table

BR !addr
instruction
branch
address

CALL !addr
instruction
branch
address

Branch/call
address specified
in GETI
insturction

CALLF
!faddr
instruction
entry
address

BRCB
!caddr
instruction
branch
address

MBE

RBE

000CH

BRCB !caddr instruction
branch address

5000H

4FFFH

4000H

3FFFH

2000H

1FFFH

07FFH

0800H

BR BCDE
BR BCXA
branch address

BRA !addr
instruction
branch address

CALLA !addr
instruction branch
address

BR $addr
instruction
relative
branch address
(15 to 1,
+2 to +16)

PD75517(A)

(1) Data area

The data area consists of a static RAM, and is used for storing data and as stack memory for subroutine

and interrupt execution. The memory can hold data even if CPU operation is stopped in the standby mode,

so that it is suitable for holding memory contents with a battery for a long time. The data area can be

manipulated with memory manipulation instructions.

The static RAM is mapped in memory banks 0, 1, 2, and 3, with each made up of 256

4 bits. Bank 0 is

used as a data area, but can also be used as a general register area (000H to 01FH).

Whole addresses of memory banks 0, 1, 2, and 3 (000H to 3FFH) can be used as a stack area.

The static RAM has a configuration of four bits per address. However, use of manipulation instructions

enables 1-, 4-, and 8-bit manipulation. Note that an even address must be specified in an 8-bit manipulation

instruction.

(a) General register area

The general register area can be manipulated with either general register manipulation instructions

or memory manipulation instructions. Up to 32 4-bit registers are available. Of the 32 general

registers, registers not used by the program can be used as a data area or stack area.

(b) Stack memory area

The stack area can be allocated within a bank with the stack pointer (SP). The bank for the stack area

is selected from the memory banks 0, 1, 2, and 3 with the stack bank select register (SBS). Stack area

can be used as a save area for subroutine or interrupt execution.

Use memory manipulation instructions to manipulate the stack bank select register (SBS) and the

stack pointer (SP).

(2) Peripheral hardware area

The peripheral hardware area is mapped at addresses F80H to FFFH of memory bank 15.

Memory manipulation instructions are used to manipulate the peripheral hardware area as well as the

static RAM area. Note that, however, the number of bits to be manipulated at a time varies according to

the individual addresses. Addresses to which no peripheral hardware is assigned cannot be accessed

since such address locations contain no data memory.

PD75517(A)

3.4 GENERAL REGISTERS: 8

4 BITS

4 BANKS

The general registers are mapped to particular addresses in data memory. Four banks of registers are

provided, with each bank consisting of eight 4-bit registers (B, C, D, E, H, L, X, A).

The register bank (RB) to be enabled at the time of instruction execution is determined by

RB = RBE·RBS: (RBS = 0 to 3)

Each general register allows 4-bit manipulation. In addition, BC, DE, HL, or XA serves as a register pair

for 8-bit manipulation. DL also makes a register pair as well as DE and HL; these three register pairs can be

used as data pointers.

A general register area can be addressed and accessed as normal RAM, regardless of whether it is used

as a register.

Fig. 3-4 General Register Format

Fig. 3-5 Register Pair Format

Address

000H

001H

002H

003H

004H

005H

006H

007H

008H

00FH

010H

017H

018H

01FH

A register

X register

L register

H register

E register

D register

C register

B register

Same as bank 0

···········

Data memory

PD75517(A)

3.5 ACCUMULATORS

In the

PD75517(A), the A register and the XA register pair function as accumulators. The A register is mainly

used for 4-bit data processing instructions, and the XA register pair is mainly used for 8-bit data processing

instructions.

For a bit manipulation instruction, the carry flag (CY) functions as a bit accumulator.

Fig. 3-6 Accumulators

3.6 STACK POINTER (SP) AND STACK BANK SELECT REGISTER (SBS)

The

PD75517(A) uses static RAM as stack memory (LIFO scheme), and the 8-bit register holding the start

address of the stack area is the stack pointer (SP).

The stack area is located at addresses 000H to 3FFH in memory banks 0, 1, 2, and 3. Either of the memory

banks is selected according to the value of the 2-bit SBS. (See Table 3-1.)

Table 3-1 Stack Area to Be Selected by the SBS

The SP is decremented before a write (save) operation to stack memory, and is incremented after a read

(restoration) operation from stack memory. The SBS is set with a 4-bit memory manipulation instruction. Note

that the high-order two bits are always set to 00.

Fig. 3-8 and 3-9 show data saved to and restored from stack memory in these stack operations.

To place the stack area at a given location, the SP can be initialized with an 8-bit memory manipulation

instruction, and the SBS can be initialized with a 4-bit memory manipulation instruction. Both can be read

from as well.

When the SP is initialized to 00H, a stack operation starts at the high-order address (nFFH) of memory bank

(n) specified with the SBS.

A stack area must be within the memory bank specified with the SBS. If a stack operation exceeds address

n00H, the operation returns to address nFFH of the same bank. Stacking beyond memory bank boundaries

is enabled only by resetting the SBS.

A RESET signal occurrence causes the contents of the SP and the SBS to be undefined, so that the SP must

always be initialized to a desired value at the start of the program.

Bit accumulator

4-bit accumulator

8-bit accumulator

SBS2

SBS

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

Stack area

- - - - - - - - - - - - - - - - - - - -

SBS1

PD75517(A)

Fig. 3-8 Data Saved to Stack Memory

Fig. 3-9 Data Restored from Stack Memory

Note A PSW other than the MBE or RBE is not saved/restored.

Remark Data marked with * is undefined.

SP 6

SP 4

PC3 - PC0

PC7 - PC4

SP 2

IST1

SP 5

SP 3

SP 1

Stack

PC14 PC13 PC12

IST0

SK2

MBE

SK1

RBE

SK0

Interrupt

PSW

SP 6

PC11 - PC8

SP 2

SP 5

SP 1

Stack

PC14 PC13 PC12

CALL, CALLA, or CALLF instruction

SP 2

Lower bits of pair register

Upper bits of pair register

SP 1

Stack

PUSH instruction

SP 4

PC3 - PC0

PC7 - PC4

SP 3

MBE RBE

PC11 - PC8

Note

SP + 2

PC3 - PC0

PC7 - PC4

SP + 4

IST1

SP + 6

SP + 1

SP + 3

SP + 5

Stack

PC14 PC13 PC12

IST0

SK2

MBE

SK1

RBE

SK0

RETI instruction

PSW

PC11 - PC8

SP + 4

SP + 6

SP + 1

SP + 5

Stack

PC14 PC13 PC12

RET or RETS instruction

Lower bits of pair register

Upper bits of pair register

SP + 2

SP + 1

Stack

POP instruction

SP + 2

PC3 - PC0

PC7 - PC4

SP + 3

MBE RBE

PC11 - PC8

Note

PD75517(A)

(1) Carry flag (CY)

The carry flag is a 1-bit flag used to store overflow or underflow occurrence information when an arithmetic

operation with a carry (ADDC, SUBC) is executed.

The carry flag also has the function of a bit accumulator, and therefore can be used to store the result of

a Boolean operation performed on the CY and bit at a specified data memory bit address.

The carry flag is manipulated using special instructions, independently of the other PSW bits.

A RESET signal occurrence causes the carry flag to be undefined.

Table 3-3 Carry Flag Manipulation Instructions

Remark

mem*.bit represents the following three addressing modes:

fmem.bit

pmem.@L

@H+mem.bit

Example

Bit 3 at address 3FH is ANDed with P33, then the result is output to P50.

MOV

H, #3H

; Set high-order 4 bits in register H

MOV1

CY, @H+0FH.3 ; CY

Bit 3 at 3FH

AND1

CY, PORT3.3

; CY

CY P33

MOV1

PORT5.0, CY

; P50

(2) Skip flags (SK2, SK1, SK0)

The skip flags are used to store skip status, and are automatically set or reset when the CPU executes an

instruction.

The user cannot directly manipulate these flags as operands.

(3) Interrupt status flag (IST1, IST0)

The interrupt status flag is a 2-bit flag used to store the status of processing being performed. (For detailed

information, see Table 5-3.)

Instruction dedicated to

carry flag manipulation

Bit transfer instruction

Bit Boolean instruction

Interrupt handling

SET1 CY

CLR1 CY

NOT1 CY

SKT CY

MOV1 mem*.bit,CY

MOV1 CY,mem*.bit

AND1 CY,mem*.bit

OR1 CY,mem*.bit

XOR1 CY,mem*.bit

Interrupt execution

RETI

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

Sets CY to 1.

Clears CY to 0.

Inverts the contents of CY.

Skips if CY is set to 1.

Transfers the contents of CY to a specified bit.

Transfers the contents of a specified bit to CY.

ANDs, ORs, or XORs CY with the contents of a specified bit, then

sets the result in CY.

Saves CY and all other PSW bits to stack memory in parallel.

Restores CY together with the other PSW bits from stack memory.

Carry flag operation/processing

Instruction (mnemonic)

PD75517(A)

Table 3-4 Information Indicated by the Interrupt Status Flag

The interrupt priority control circuit (see Fig. 5-1) checks this flag to control multiple interrupts.

The contents of the IST1 and IST0 are saved as part of the PSW to stack memory if an interrupt is accepted,

then are automatically set to a one-step higher status. The RETI instruction restores the contents present

before an interrupt occurs.

The interrupt status flag can be manipulated using a memory manipulation instruction, and the status of

processing being performed can be changed by program control.

Caution The user must always disable interrupts with the DI instruction before manipulating this flag,

and must enable interrupts with the EI instruction after manipulating this flag.

(4) Memory bank enable flag (MBE)

The memory bank enable flag is a 1-bit flag used to specify the address information generation mode for

the high-order four bits of a 12-bit data memory address.

When the MBE is set to 1, the data memory address space is expanded, allowing all data memory space

to be addressed.

When the MBE is reset to 0, the data memory address space is fixed, regardless of MBS setting. (See Fig.

2-1.)

A RESET signal occurrence automatically initializes the MBE by setting the MBE to the content of bit 7

at program memory address 0.

In vectored interrupt processing, the MBE is automatically set to the content of bit 7 in the vector address

table for servicing the interrupt.

Usually, the MBE is set to 0 in interrupt processing, and static RAM in memory bank 0 is used.

(5) Register bank enable flag (RBE)

The register bank enable flag is a 1-bit flag used to determine whether to expand the general register bank

configuration.

When the RBE is set to 1, a set of general registers can be selected from register banks 0 to 3, depending

on the setting of the register bank select register (RBS).

When the RBE is reset to 0, register bank 0 is always selected as general registers, regardless of the setting

of the RBS.

A RESET signal occurrence automatically initializes the RBE by setting the RBE to the content of bit 6 at

program memory address 0.

When a vectored interrupt occurs, the RBE is automatically set to the content of bit 6 in the vector address

table for servicing the interrupt. Usually, the RBE is set to 0 in interrupt processing. Register bank 0 is

used for 4-bit processing, and register banks 0 and 1 are used for 8-bit processing.

Normal program processing is being performed.

Any interrupts are acceptable.

A lower- or higher-priority interrupt is being serviced.

Higher-priority interrupts are acceptable.

A higher-priority interrupt is being serviced.

No interrupts are acceptable.

Not to be set

IST1

IST0

Status 0

Status 1

Status 2

Status of processing
being performed

Processing and interrupt control

PD75517(A)

3.8 BANK SELECT REGISTER (BS)

The bank select register consists of a register bank select register (RBS) and memory bank select register

(MBS), which specify a register bank and memory bank to be used, respectively.

The RBS and MBS are set using the SEL RBn instruction and SEL MBn instruction, respectively.

The contents of BS can be saved to or restored from a stack area eight bits at a time by using the PUSH

BS/POP BS instruction.

Fig. 3-11 Bank Select Register Format

(1) Memory bank select register (MBS)

The memory bank select register is a 4-bit register used to store the high-order four bits of a 12-bit data

memory address. The contents of this register specify a memory bank to be accessed. Note, however,

that the

PD75517(A) allows only memory banks 0, 1, 2, 3, and 15 to be specified.

The MBS is set with the SEL MBn instruction (n = 0, 1, 2, 3, 15)

Fig. 2-1 shows the range of addressing using MBE and MBS settings.

A RESET signal occurrence initializes the MBS to 0.

(2) Register bank select register (RBS)

The register bank select register specifies a register bank to be used as general registers; a register bank

can be selected from register banks 0 to 3.

The RBS is set with the SEL RBn instruction (n = 0 to 3).

A RESET signal occurrence initializes the RBS to 0.

Table 3-5 Register Bank to Be Selected with the RBE and RBS

Remark

: Don't care

Symbol

MBS3 MBS2 MBS1 MBS0

RBS1

RBS0

F83H

MBS

F82H

RBS

Address

Bank 0 is always selected.

Bank 0 is selected.

Bank 1 is selected.

Bank 2 is selected.

Bank 3 is selected.

RBS

RBE

Always 0

PD75517(A)

4. PERIPHERAL HARDWARE FUNCTIONS

4.1 DIGITAL I/O PORTS

The

PD75517(A) employs memory-mapped I/O, enabling all I/O ports to be mapped to data memory space.

Fig. 4-1 Data Memory Address Assigned to Digital Port

Table 4-1 lists the I/O port manipulation instructions. These instructions provide a wide range of control

including 8-bit I/O and bit manipulation as well as 4-bit I/O.

Examples 1. Test the state of P13, then output different values to ports 4 and 5 according to the test result.

SKT

PORT1.3

; Skip if bit 3 of port 1 is 1

MOV XA, #18H

; XA

18H

Consecutive

MOV XA, #14H

; XA

14H

SEL

MB15

; or CLR1 MBE

OUT PORT4, XA ; Ports 5 and 4

2. SET1 PORT4.@L

; Set the bit of ports 4 to 7 specified by the L register to 1

P03

P02

P01

PORT 0

FF0H

P00

Symbol

Address

P13

P12

P11

PORT 1

FF1H

P10

P23

P22

P21

PORT 2

FF2H

P20

P33

P32

P31

PORT 3

FF3H

P30

P43

P42

P41

PORT 4

FF4H

P40

P53

P52

P51

PORT 5

FF5H

P50

P63

P62

P61

PORT 6

FF6H

P60

P73

P72

P71

PORT 7

FF7H

P70

P83

P82

P81

PORT 8

FF8H

P80

P93

P92

P91

PORT 9

FF9H

P90

P103

P102

P101

PORT 10

FFAH

P100

P113

P112

P111

PORT 11

FFBH

P110

P123

P122

P121

PORT 12

FFCH

P120

P133

P132

P131

PORT 13

FFDH

P130

P143

P142

P141

PORT 14

FFEH

P140

P153

P152

P151

PORT 15

FFFH

P150

PD75517(A)

Table 4-1 I/O Pin Manipulation Instructions

Notes 1. Before an instruction is executed, MBE must be set to 0, or MBS must be set to 15 when MBE

is 1.

2. The lower 2 bits of an address and a bit address are specified indirectly with the L register.

Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port

IN A, PORTn

Note 1

IN XA, PORTn

Note 1

OUT PORTn.A

Note 1

OUT PORTn.XA

Note 1

SET1 PORTn.bit

SET1 PORTn.@L

Note 2

CLR1 PORTn.bit

CLR1 PORTn.@L

Note 2

SKT PORTn.bit

SKT PORTn.@L

Note 2

SKF PORTn.bit

SKF PORTn.@L

Note 2

MOV1 CY, PORTn.bit

MOV1 CY, PORTn.@L

Note 2

MOV1 PORTn.bit, CY

MOV1 PORTn.@L, CY

Note 2

AND1 CY, PORTn.bit

AND1 CY, PORTn.@L

Note 2

OR1 CY, PORTn.bit

OR1 CY, PORTn.@L

Note 2

XOR1 CY, PORTn.bit

XOR1 CY, PORTn.@L

Note 2

PD75517(A)

(1) Types, features, and configurations of digital I/O ports

Table 4-2 lists the types of digital I/O ports.

Fig. 4-2 through 4-8 present the configurations of the ports.

Table 4-2 Types and Features of Digital Ports

Note This port can directly drive the LED.

P10 is also used as an external vectored interrupt input pin. This input is provided with a noise eliminator.

(See Section 5.2 for details.)

The use of pull-up resistors can be specified for ports 0 (excluding pin P00/INT4), 1 to 3, 6, and 7 by software.

Also used as INT4, SCK0, SO0/

SB0, and SI0/SB1.

Also used as INT0 to INT2, and

TI0.

Also used as PTO0, PCL, and BUZ.

The use of pull-up resistors can

be specified by mask options in

units of bits.

Also used as KR0 to KR3.

Also used as KR4 to KR7.

Also used as PPO, SCK1, SO1,

and SI1.

The use of a pull-down resistor

can be specified by a mask op-

tion in units of bits.

The use of pull-up resistors can

be specified by mask options in

units of bits.

Also used as AN4 to AN7.

Port name

Function

Operation and feature

Remarks

PORT0

PORT1

PORT2

PORT3

Note

PORT4

Note

PORT5

Note

PORT6

PORT7

PORT8

PORT9

PORT10

PORT11

PORT12

PORT13

PORT14

PORT15

4-bit input

4-bit I/O

4-bit I/O (N-chan-

nel open-drain 10 V)

4-bit I/O

4-bit input

4-bit I/O

4-bit I/O (N-chan-

nel open-drain 10 V)

4-bit input

Allows read and test at any time regardless of

the operation modes of dual function pins.

Allows input or output mode setting in units

of 4 bits.

Allows input or output mode setting in units

of 1 or 4 bits.

Allows input or output

mode setting in units

of 4 bits.

Allows input or output

mode setting in units

of 1 or 4 bits.

Allows input or output

mode setting in units

of 4 bits.

Allows read and test at any time regardless of

the operation modes of dual function pins.

Allows input or output mode setting in units

of 4 bits.

Allows input or output mode setting in units

of 4 bits.

Allows input or output mode setting in units

of 4 bits.

Allows read and test at any time regardless of

the operation modes of dual function pins.

Ports 4 and 5 may be

paired, allowing data

I/O in units of 8 bits.

Ports 6 and 7 may be

paired, allowing data

I/O in units of 8 bits.

PD75517(A)

Fig. 4-9 Formats of Port Mode Registers

(a) Port mode register group A

(b) Port mode register group B

(c) Port mode register group C

Note To develop a program, these bits must be set to 0. They correspond to PM8 and PM15. While this

chip is an input-only device, an emulator has I/O ports.

PM63

PM62

PM61

PM60

PM33

PM31

PM32

PM30

FE8H

Address

PMGA

Symbol

P30 I/O specification

P31 I/O specification

P32 I/O specification

P33 I/O specification

P60 I/O specification

P61 I/O specification

P62 I/O specification

P63 I/O specification

PM14

PM13

PM12

PM11

PM9

PM10

FEEH

Address

PMGC

Symbol

Port 9 (P90 - P93) I/O specification

Port 10 (P100 - P103) I/O specification

Port 11 (P110 - P113) I/O specification

Port 12 (P120 - P123) I/O specification

Port 13 (P130 - P133) I/O specification

Port 14 (P140 - P143) I/O specification

Input mode (Output buffer off)

Output mode (Output buffer on)

Contents of specification

PM7

PM5

PM4

PM2

FECH

Address

PMGB

Symbol

Port 2 (P20-P23) I/O specification

Port 4 (P40-P43) I/O specification

Port 5 (P50-P53) I/O specification

Port 7 (P70-P73) I/O specification

Note

PD75517(A)

(4) Use of pull-up and pull-down resistors

Ports 0 (excluding pin P00/INT4), 1 to 3, 6, and 7 can be provided with pull-up resistors by software.

Ports 4, 5, and 12 to 14 can be provided with pull-up resistors by mask options. Port 9 can also be provided

with pull-down resistors by mask options.

Table 4-4 Specifying the Use of Pull-Up and Pull-Down Resistors

Note The P00 pin cannot be provided with a pull-up resistor.

Fig. 4-10 Format of the Register Group A Specifying the Use of Pull-Up Resistors

PO7

PO6

PO3

PO1

PO2

PO0

FDCH

Address

POGA

Symbol

No built-in pull-up resistor provided

Built-in pull-up resistor provided

Specification contents

Port 0 (P01 - P03)

Port 1 (P10 - P13)

Port 2 (P20 - P23)

Port 3 (P30 - P33)

Port 6 (P60 - P63)

Port 7 (P70 - P73)

Port (pin name)

Specifying the use of pull-up and pull-down resistor

Bit in POGA

The use of pull-up resistors is specified in units of 3 bits

by software.

The use of pull-up resistors is specified in units of 4 bits

by software.

The use of pull-up resistors is specified in units of bits

by mask options.

The use of pull-down resistors is specified in units of bits

by mask options.

bit 0

bit 1

bit 2

bit 3

bit 6

bit 7

Port 0 (P01-P03)

Note

Port 1 (P10-P13)

Port 2 (P20-P23)

Port 3 (P30-P33)

Port 6 (P60-P63)

Port 7 (P70-P73)

Port 4 (P40-P43)

Port 5 (P50-P53)

Port 12 (P120-P123)

Port 13 (P130-P133)

Port 14 (P140-P143)

Port 9 (P90-P93)

PD75517(A)

4.2 CLOCK GENERATOR

(1) Configuration of the clock generator

The clock generator supplies various clock signals to the CPU and peripheral hardware. Fig. 4-11 shows

the configuration of the clock generator.

Fig. 4-11 Block Diagram of the Clock Generator

Note Instruction execution

Remarks 1. f

: Main system clock frequency

2. f

: Subsystem clock frequency

3. PCC : Processor clock control register

4. SCC: System clock control register

Subsystem
clock generator

Main system
clock generator

Clock timer

Basic interval timer (BT)

Timer/event counter

Serial interface

Clock timer

Clock output circuit

A /D converter

1/8 to 1/4096

Frequency divider

Selec-
tor

Frequency
divider

CPU
clock

Oscillator
disable
signal

Internal bus

HALT

Note

STOP

Note

PCC2, PCC3
clear signal

Wait release signal from BT

Standby release signal from
interrupt control circuit

RESET signal

XT1

XT2

SCC

SCC3

SCC0

PCC

PCC0

PCC1

PCC2

PCC3

STOP F/F

HALT F/F

1/2

1/16

1/4

Timer/pulse
generator

PD75517(A)

(2) Functions of the clock generator

The clock generator generates the clock signals listed below, and controls the standby mode and other

CPU operation modes.

· Main system clock f

· Subsystem clock f

· CPU clock

· Clocks for peripheral hardware

The operation of the clock generator is determined by the processor clock control register (PCC) and

system clock control register (SCC). The clock generator functions and operates as described below.

(a) The generation of a RESET signal selects the lowest-speed mode

Note 1

for the main system clock.

(PCC = 0, SCC = 0)

(b) When the main system clock is selected, the PCC can be set to select one of four CPU clocks

Note 2

available.

(d) The SCC can be set to select the subsystem clock for very low-speed, low-current operation (122

at 32.768 kHz). In this case, the PCC set value does not affect the CPU clock signal.

(e) When the subsystem clock is selected, main system clock generation can be stopped with the SCC.

In addition, the HALT mode can be used, but the STOP mode cannot be used. (Subsystem clock

generation cannot be stopped.)

(f)

Clocks for peripheral hardware are produced by dividing the main system clock signal. Only to the

watch timer, the subsystem clock can be directly supplied so that the watch and buzzer output

functions can operate continuously even in a standby mode.

(g) When the subsystem clock is selected, the watch timer can operate normally, but other hardware

cannot be used because they operate with the main system clock.

Notes 1. 10.7

s (at 6.0 MHz) or 15.3

s (at 4.19 MHz)

2. 0.67

s, 1.33

s, 2.67

s, 10.7

s (at 6.0 MHz), or 0.95

s, 1.91

s, 3.82

s, 15.3

s (at 4.19 MHz)

PD75517(A)

(3) Processor clock control register (PCC)

The PCC is a 4-bit register for selecting a CPU clock with the low-order two bits and for selecting a CPU

operation mode with the high-order two bits. (See Fig. 4-12.)

When bit 3 or bit 2 is set to 1, the standby mode is set. When this is released by the standby release signal,

these bits are automatically cleared to return to the normal operation mode. (See Chapter 6 for detailed

information.)

A 4-bit memory manipulation instruction is used to set the low-order two bits of the PCC. (The high-order

two bits are set to 0.)

Bit 3 and bit 2 are set to 1 using the STOP instruction and HALT instruction, respectively.

The STOP instruction and HALT instruction can be executed regardless of MBE setting.

A CPU clock can be selected only when the main system clock is used for operation. When the subsystem

clock is selected for operation, the low-order two bits of the PCC are invalidated, and f

/4 is automatically

set. The STOP instruction can be executed only when the main system clock is used for operation.

The generation of a RESET signal clears the PCC to 0.

Examples 1.

The machine cycle is set to 0.95

s (at 4.19 MHz).

SEL

MB15

MOV A, #0011B

MOV PCC, A

The STOP mode is set. (A STOP instruction or HALT instruction must always be followed

by an NOP instruction.)

STOP

NOP

PD75517(A)

Fig. 4-12 Format of the Processor Clock Control Register

Remarks 1. f

: Output frequency from the main system clock oscillator

: Output frequency from the subsystem clock oscillator

Address

FB3H

PCC3

PCC2

PCC1

PCC0

Symbol

PCC

CPU clock selection bit
Operation with fx = 6.0 MHz

( ) indicates f

= 6.0 MHz

CPU clock frequency

= f

/64 (93.7 kHz)

1 machine cycle

SCC = 0

( ) indicates f

= 32.768 kHz

SCC = 1

CPU clock frequency

= f

/4 (8.192 kHz)

= f

/16 (375 kHz)

2.67 s

Not to be set

= f

/8 (750 kHz)

= f

/4 (1.5 MHz)

1.33 s

0.67 s

= f

/4 (8.192 kHz)

122 s

Operation with f

= 4.19 MHz

( ) indicates f

= 4.19 MHz

CPU clock frequency

= f

/64 (65.5 kHz)

1 machine cycle

SCC = 0

( ) indicates f

= 32.768 kHz

SCC = 1

CPU clock frequency

= f

/4 (8.192 kHz)

= f

/16 (262 kHz)

= f

/8 (524 kHz)

= f

/4 (1.05 MHz)

1.91 s

15.3 s

122 s

= f

/4 (8.192 kHz)

122 s

Normal operation mode

HALT mode

STOP mode

Not to be set

CPU operation mode control bits

10.7 s

3.82 s

0.95 s

Not to be set

PD75517(A)

(4) System clock control register (SCC)

The SCC is a 4-bit register for selecting CPU clock

with the least significant bit and for controlling the

termination of main system clock generation with the most significant bit. (See Fig. 4-13.)

SCC.0 and SCC.3 are located at the same data memory address, but both bits cannot be changed at the

same time. Accordingly, SCC.0 and SCC.3 are set using bit manipulation instructions. SCC.0 and SCC.3

can be manipulated regardless of MBE setting.

Main system clock generation can be terminated by setting SCC.3 only when the subsystem clock is used

for operation. The STOP instruction must be used for generation termination when the main system clock

is used for operation.

The generation of a RESET signal clears the SCC to 0.

Fig. 4-13 Format of the System Clock Control Register

Cautions 1. A time period of up to 1/f

is needed to change the system clock. This means that to

terminate main system clock generation, SCC.3 must be set when the machine cycles

indicated in Table 4-5 or more have elapsed after the clock is switched from the main system

clock to the subsystem clock.

2. When the main system clock is used for operation, setting SCC.3 to stop clock generation

does not enter the normal STOP mode.

3. When SCC.3 is set to 1, the X1 input pin is connected to V

(GND electric potential) to

prevent leakage in the crystal oscillator. When an external clock is used as the main system

clock, never set SCC.3 to 1.

4. When the four bits of PCC are set to 0001B (

= f

/16), do not set SCC.0 to 1. Before switching

the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other

than 0001B is set. When the system operates on the subsystem clock, the PCC bits must

also be other than 0001B.

Address

FB7H

SCC3

SCC0

Symbol

SCC

CPU clock frequency

Main system clock

Main system clock operation

Subsystem clock

Can oscillate

Subsystem clock

Oscillation stopped

SCC0

SCC3

Not to be set

PD75517(A)

(6) Time required to change the system clock and CPU clock

The system clock and CPU clock can be changed by using the least significant bit of the SCC and the low-

order two bits of the PCC. This switching is not performed immediately after the contents of the registers

are rewritten, but the system operates with the previous clock for some machine cycles. Accordingly, after

this time period, the STOP instruction must be executed or SCC.3 must be set to 1 to terminate main system

clock generation.

Table 4-5 Maximum Time Required to Change the System Clock and CPU Clock

Remarks 1. Time enclosed in parentheses is required when f

= 6.0 MHz and f

= 32.768 kHz.

: Don't care

3. CPU clock

is supplied to the CPU. The reciprocal of this frequency is a minimum instruction

time (defined as one machine cycle in this manual).

Caution When the four bits of PCC are set to 0001B (

= f

/16), do not set SCC.0 to 1. Before switching

the main system clock to the subsystem clock, be sure to manipulate the PCC bits so other than

0001B is set. When the system operates on the subsystem clock, the PCC bits must also be

other than 0001B.

PCC1

PCC0

SCC0

PCC1

PCC0

SCC0

PCC1

PCC0

SCC0

PCC1

PCC0

SCC0

PCC1

PCC0

Setting before
switching

Setting after switching

1 machine cycle

8 machine cycles

16 machine cycles

Not to be set

1 machine cycle

4 machine cycles

16 machine cycles

1 machine cycle

4 machine cycles

8 machine cycles

1 machine cycle

4 machine cycles

8 machine cycles

16 machine cycles

1 machine cycle

SCC0

/64f

machine

cycles

(3 machine cycles)

Not to be set

/8f

T machine

cycles

(23 machine cycles)

/4f

T machine

cycles

(46 machine cycles)

PCC

SCC

PD75517(A)

(7) Procedure for changing the system clock and CPU clock

The procedure for changing the system clock and CPU clock is explained using Fig. 4-16.

Fig. 4-16 Changing the System Clock and CPU Clock

The generation of a RESET signal starts CPU operation at the lowest speed of the main system

clock

Note 1

after a wait time

Note 2

for stable oscillation.

The PCC is rewritten for highest-speed operation after a time elapse which is sufficient for the voltage

on the V

pin to be high enough for highest-speed operation.

The removal of commercial power is detected using, for example, an interrupt input (INT4 is useful),

then SCC.0 is set to operate with the subsystem clock. (In this case, the start of subsystem clock

generation must be confirmed beforehand.) After a time (32 machine cycles) required to switch to

the subsystem clock elapses, SCC.3 is set to terminate main system clock generation.

After detecting the input of commercial power by using an interrupt, SCC.3 is cleared to start main

system clock generation. After a time required for stable generation, SCC.0 is cleared to operate at

highest speed.

Notes 1. 10.7

s (at 6.0 MHz) or 15.3

s (at 4.19 MHz)

2. 21.8 ms (at 6.0 MHz) or 31.3 ms (at 4.19 MHz)

OFF

Commercial
power
line voltage

pin voltage

RESET signal

System clock

CPU clock

Wait (31.3 ms)

= 4.19 MHz

= 32.768 kHz

15.3 s

0.95 s

122 s

0.95 s

Internal reset
operation

PD75517(A)

4.3 CLOCK OUTPUT CIRCUIT

(1) Configuration of the clock output circuit

Fig. 4-17 shows the configuration of the clock output circuit.

(2) Functions of the clock output circuit

The clock output circuit outputs a clock pulse signal on the P22/PCL pin for remote control or for supplying

clock pulses to a peripheral LSI device.

The procedure for outputting a clock pulse signal is as follows:

(a) Select a clock output frequency, and disable clock output.

(b) Write a 0 in the P22 output latch.

(d) Enable clock output.

Fig. 4-17 Configuration of the Clock Output Circuit

Remark The clock output circuit is designed so that pulses with short widths do not appear in enabling

or disabling clock output.

From the clock
generator

CLOM

Selector

Output
buffer

Port 2 input/
output mode
specification bit

P22 output
latch

PCL/P22

Internal bus

PORT2.2

Bit 2 of PMGB

CLOM0

CLOM1

CLOM3

PD75517(A)

(3) Clock output mode register (CLOM)

The CLOM is a 4-bit register to control clock output.

The CLOM is set with a 4-bit memory manipulation instruction. No read operation is allowed on this

Example

CPU clock

is output on the PCL/P22 pin.

SEL MB15 ; or CLR1 MBE

MOV A, #1000B

MOV CLOM, A

The generation of a RESET signal clears the CLOM to 0, disabling clock output.

Fig. 4-18 Format of the Clock Output Mode Register

Caution

Be sure to write a 0 in bit 2 of the CLOM.

Address

FD0H

CLOM0

Symbol

CLOM

Output

Note

(1.05 MHz, 524 kHz, 262 kHz, 65.5 kHz)

Output f

(524 kHz)

Output f

(262 kHz)

CLOM1

CLOM3

Output f

(65.5 kHz)

(Frequency when f

= 4.19 MHz)

Note

is the CPU clock supply selected by PCC.

Output disable

Output enable

Clock output enable/disable bit

Output

Note

(1.50 MHz, 750 kHz, 375 kHz, 93.7 kHz)

Output f

(750 kHz)

Output f

(375 kHz)

Output f

(93.7 kHz)

Clock output frequency selection bit
(Frequency when f

= 6.0 MHz)

PD75517(A)

Fig. 4-21 Format of the Basic Interval Timer Mode Register

Address

F85H

BTM3

BTM2

BTM1

BTM0

Symbol

BTM

Input clock specification

When "1" is written to this bit, the basic interval timer operation starts (the counter

and the interrupt request flag are cleared).

When the operation starts, this bit is automatically reset to 0.

Basic interval timer start control bit

Interrupt interval time

(wait time for releasing standby)

(1.02 kHz)

(8.18 kHz)

(32.768 kHz)

(131 kHz)

(250 ms)

(31.3 ms)

(7.82 ms)

(1.95 ms)

Not to be set

Input clock specification

Other
setting

Interrupt interval time

(wait time for releasing standby)

(1.46 kHz)

(11.7 kHz)

(46.9 kHz)

(188 kHz)

(175 ms)

(21.8 ms)

(5.46 ms)

(1.37 ms)

Not to be set

(Frequency when f

= 6.0 MHz)

(Frequency when f

= 4.19 MHz)

Other
setting

PD75517(A)

(4) Operation of the basic interval timer

The basic interval timer (BT) is always incremented by the clock supplied from the clock generator, and

when it overflows, the interrupt request flag (IRQBT) is set. The count operation of BT cannot be stopped.

One of four interrupt generation intervals can be selected by setting BTM. (See Fig. 4-21.)

The basic interval timer and the interrupt request flag can be cleared by setting bit 3 of BTM to 1 (instruction

for starting as an interval timer).

The count status can be read by using an 8-bit manipulation instruction. No data can be loaded to the

timer.

Caution

When reading the count value of the basic interval timer, execute a read instruction twice so

that unstable data which has been counted will not be read. If the two read values are

reasonable, use the second one as the result. If the two read values are far apart, retry from

the beginning.

Example

Read the count value of BT.

SET1 MBE

SEL

MB15

MOV HL, #BT

; Set the BT address in HL

LOOP:

MOV XA, @HL

; First read

MOV BC, XA

MOV XA, @HL

; Second read

SKE

XA, BC

LOOP

To allow the system clock to stabilize after releasing the STOP mode, a wait function is available which

stops the operation of the CPU until the basic interval timer overflows.

The wait time after generation of a RESET signal is fixed. On the other hand, a wait time can be selected

by setting BTM when releasing the STOP mode with an interrupt occurrence. In this case, the wait times

are the same as the interval times shown in Fig. 4-21. BTM must be set before the STOP mode is set. (For

details, see Chapter 6.)

PD75517(A)

4.5 CLOCK TIMER

(1) Clock timer

The

PD75517(A) contains one channel for a clock timer. Fig. 4-22 shows the configuration of the timer.

(2) Clock timer functions

(a) The clock timer sets the test flag (IRQW) every 0.5 seconds.

The standby mode can be released with IRQW.

(b) Either the main system clock or subsystem clock can produce 0.5-second intervals.

debugging and testing.

(d) A fixed frequency (2.048 kHz) can be output to the P23/BUZ pin, so that it can be used for sounding

the buzzer and system clock frequency trimming.

(e) The frequency divider can be cleared, so the clock can start from zero seconds.

Caution

When the main system clock operates at 6.0 MHz, a time interval of 0.5 s cannot be produced.

Before producing this time interval, the main system clock must be changed to the subsystem

clock.

Fig. 4-22 Block Diagram of the Clock Timer

Remark The values in parentheses are for f

= 4.194304 MHz and f

= 32.768 kHz

P23/BUZ

Internal bus

From the
clock
generator

128

(32.768 kHz)

Selector

Frequency divider

Selector

INTW
IRQW
set signal

2 Hz
0.5 sec

WM7

WM2

WM1

WM0

P23 output
latch

Bit 2 of PMGB

PORT2.3

Output buffer

Clear signal

(32.768 kHz)

Port 2 input/
output mode

(256 Hz: 3.91 ms)

(2.048 kHz)

PD75517(A)

(3) Clock mode register

The clock mode register (WM) is an 8-bit register that controls the clock timer, and that is set with an

8-bit memory manipulation instruction. Fig. 4-23 shows the format.

The generation of a RESET signal clears all bits to 0.

Example

Use the main system clock (4.19 MHz) for setting time, and enable buzzer output.

CLR1

MBE

MOV

XA, #84H

MOV

WM, XA

; Set WM

Fig. 4-23 Format of the Clock Mode Register

Address

F98H

Symbol

WM0

WM1

WM2

WM7

WM0

Selects divided system clock output:

Selects subsystem clock: f

Count clock (fW) selection bit

WM1

Normal clock mode ( : sets IRQW at 0.5 s)

Advanced clock mode ( : sets IRQW at 3.91 ms)

Operation mode selection bit

WM2

Disables clock operation (clears the frequency dividing circuit)

Enables clock operation

Clock operation enable/disable bit

128

WM7

Disables BUZ output

Enables BUZ output

BUZ output enable/disable bit

PD75517(A)

4.6 TIMER/EVENT COUNTER

(1) Configuration of the timer/event counter

The

PD75517(A) contains one channel of timer/event counter, which is configured as shown in Fig.

4-24.

(2) Functions of the timer/event counter

The timer/event counter has the following functions.

(a) Programmable interval timer operation

(b) Output of a square wave at a given frequency to the PTO0 pin

(d) Frequency divider operation that divides TI0 pin input by N and outputs the result to the PTO0 pin

(e) Supply of serial shift clock signal to a serial interface circuit

(f)

Function of reading the state of counting

(3) Timer/event counter mode register (TM0) and timer/event counter output enable flag (TOE0)

The timer/event counter mode register (TM0) is an 8-bit register for controlling the timer/event counter.

Fig. 4-25 shows its format.

An 8-bit memory manipulation instruction is used to set the timer/event counter mode register.

Bit 3 is the timer start bit, and can be set independently of the other bits. Bit 3 is automatically reset to

0 when the timer starts operation.

Examples 1.

The timer is started in the interval timer mode with CP = 4.09 kHz.

SEL

MB15

; or CLR1 MBE

MOV

XA, #01001100B

MOV

TM0, XA

; TM0

4CH

The timer is restarted according to the setting of the timer/event counter mode register.

SEL

MB15

; or CLR1 MBE

SET1

TM0.3

; TM0.bit3

The generation of a RESET signal clears all bits to 0.

The timer/event counter output enable flag (TOE0) enables or disables output of the timer out F/F (TOUT

F/F) status to the PTO0 pin.

The timer out F/F (TOUT F/F) is inverted by a match signal transmitted from the comparator.

The timer out F/F is reset when an instruction sets bit 3 of the timer mode register (TM0).

The generation of a RESET signal clears the TOE0 and TOUT F/F to 0.

PD75517(A)

Fig. 4-25 Format of the Timer/Event Counter Mode Register

Address

FA0H

Symbol

TM0

TM04

TM06

TM02

TM03

TM05

Operation mode

Count operation

Halts (retains
the contents of
counting)

Count
operation

Timer start specification bit

When "1" is written to this bit, the counter and the IRQT0
flag are cleared. Count operation starts if bit 2 has been
set to 1.

Count pulse (CP) select bit
(Frequency when f

= 6.0 MHz)

TM05

TM06

TM04

Count pulse (CP)

TI0 input rising edge

TI0 input falling edge

(5.86 kHz)

(23.4 kHz)

(93.8 kHz)

(375 kHz)

Other setting

Not to be set

TM05

TM06

TM04

Count pulse (CP)

TI0 input rising edge

TI0 input falling edge

(4.09 kHz)

(16.4 kHz)

(65.5 kHz)

(262 kHz)

Other setting

Not to be set

(Frequency when f

= 4.19 MHz)

PD75517(A)

(b) Count operation mode

This mode is set when bit 2 of TM0 is set to 1. In this mode, a count pulse signal selected with bits

4 to 6 is supplied to the count register for count operation as shown in Fig. 4-28.

Timer operation is usually started in the following steps:

A count value is set in the modulo register (TMOD0).

An operation mode, count clock, and start instruction are set in the mode register (TM0).

An 8-bit data transfer instruction is used to set the modulo register.

Caution A value other than 0 must be set in the modulo register.

Example The value 3FH is set in the modulo register of channel 0.

SEL

MB15

; or CLR1 MBE

MOV

XA, #3FH

MOV

TMOD0, XA

If the value set in the modulo register matches the contents of the count register, the match signal

is generated. Then, the TOUT F/F is inverted, and the counter register is cleared.

The interval time of the generation of the match signal is calculated as follows:

(Set value of the modulo register + 1)

resolution

The resolution is 1/count pulse frequency.

Table 4-6 indicates the resolution and maximum set time (when FFH is set in the modulo register),

depending on a selected count pulse.

Table 4-6 Resolution and Maximum Set Time

(When f

= 6.0 MHz)

(When f

= 4.19 MHz)

Mode register

TM04

TM06

TM05

Maximum set time

43.7 ms

10.9 ms

2.73 ms

683

Resolution

171

42.7

10.7

2.67

Timer channel 0

Mode register

TM04

TM06

TM05

Maximum set time

62.5 ms

15.6 ms

3.91 ms

977

Resolution

244

61.1

15.3

3.81

Timer channel 0

PD75517(A)

4.7 TIMER/PULSE GENERATOR

(1) Timer/pulse generator functions

The

PD75517(A) contains one channel for a timer/pulse generator that can be used as a timer or a pulse

generator. It has the following functions:

(a) Functions available when the timer/pulse generator is used in the timer mode

8-bit interval timer operation using one of five clock sources (occurrence of IRQTPG)

Square wave output to the PPO pin

(b) Functions available when the timer/pulse generator is used in the PWM pulse generation mode

PWM pulse output to the PPO pin with an accuracy of 14 bits (applicable for electronic tuning when

used as an D/A converter)

Generation of interrupts at regular intervals (2

)

Note

Note 2

= 5.46 ms (at 6.0 MHz) or 7.81 ms (at 4.19 MHz)

If pulse output is unnecessary, the PPO pin can be used as a 1-bit output port.

Caution

If the timer/pulse generator is operating when the STOP mode is set, it may malfunction. So

the timer/pulse generator must be disabled with the mode register in advance.

PD75517(A)

(2) Timer/pulse generator mode register (TPGM)

The timer/pulse generator mode register (TPGM) is an 8-bit register that controls operation of the timer/

pulse generator. Fig. 4-29 shows the format of the register.

TPGM is set with an 8-bit memory manipulation instruction.

Bit 3 enables or disables the transfer (reloading) of the timer/pulse generator modulo register (MODH and

MODL) contents to the modulo latch. Bit 3 can be manipulated independently of the other bits.

By setting TPGM1 to 0, timer/pulse generator operation can be stopped to decrease current consumption.

The generation of a RESET signal clears all bits to 0.

Fig. 4-29 Format of Timer/Pulse Generator Mode Register

TPGM7

TPGM5 TPGM4 TPGM3

TPGM1 TPGM0

Address

F90H

Symbol

TPGM

TPGM0

Select PWM pulse generation mode

Select timer mode

Timer/pulse generator operation mode selection bit

TPGM1

Disable timer/pulse generator operation

Enable timer/pulse generator operation

Timer/pulse generator operation enable/disable bit

TPGM3

Disable reloading of modulo register

Enable reloading of modulo register

Modulo register reload enable/disable bit

TPGM4

Output 0 to PPO output latch

Output 1 to PPO output latch

PPO output latch data

TPGM5

Static output on PPO pin

Pulse output (square wave/PWM) on PPO pin

PPO pin output selection bit static/pulse

TPGM7

Disable output on PPO pin (high-impedance)

Enable output on PPO pin

PPO pin output enable/disable bit

PD75517(A)

(3) Configuration and operation when the timer/pulse generator is used in the timer mode

Fig. 4-30 shows the configuration when the timer/pulse generator is used in the timer mode.

The timer mode is selected by setting bit 0 of TPGM to 1. In the timer mode, TPGM3 must be set to 1,

allowing a modulo register to be reloaded at any time.

In the timer mode, a prescaler is selected with the modulo register L (MODL), and a frequency or interrupt

interval value is set in the modulo register H (MODH). The timer starts when the TPGM1 is changed from

0 to 1.

Fig. 4-31 shows the operation timing for the MODH setting, and Table 4-7 shows the setting of a frequency

or interrupt interval.

The output to the PPO pin can be switched between the square wave output and static output. To output

a square wave, set TPGM5 and TPGM7 to 1.

Fig. 4-30 Block Diagram of the Timer/Pulse Generator (Timer Mode)

Internal bus

Modulo register L (8)

MODL

Modulo register H (8)

MODH

TPGM3
(Set to 1)

TPGM1

1/2

Frequency
divider

Prescaler select latch (5)

Modulo latch H (8)

Comparator (8)

Count register (8)

Clear

Set

T F/F

Selec-
tor

TPGM4

TPGM5

TPGM7

INTTPG
IRQTPG
set signal

Output
buffer

PPO

Match

PD75517(A)

Fig. 4-31 Timer Mode Operation Timing

Table 4-7 Modulo Register Settings

(When f

= 6.0 MHz)

(When f

= 4.19 MHz)

Cautions 1. A value other than the above cannot be set in MODL. Bits 0, 1, and 7 must be set to 0.

2. N is the set value of MODH. 0 must not be set for N. Be sure to set a value from 1 to 255

for N.

T F/F

(PPO)

Count

MODH

Generate IRQTPG.

Set TPGM1.

MODL bits 2-6

Interrupt generation interval

= 6.0 MHz)

Square wave output frequency

= 6.0 MHz)

256 (N+1)/f

= 85.3

s - 10.9 ms

128 (N+1)/f

= 42.7

s - 5.46 ms

64 (N+1)/f

= 21.3

s - 2.73 ms

32 (N+1)/f

= 10.7

s - 1.37 ms

16 (N+1)/f

= 5.33

s - 683

/256 (N+1) = 91.6 Hz - 11.7 kHz

/128 (N+1) = 183 Hz - 23.4 kHz

/64 (N+1) = 366 Hz - 46.9 kHz

/32 (N+1) = 732 Hz - 93.8 kHz

/16 (N+1) = 1465 Hz - 188 kHz

MODL bits 2-6

Interrupt generation interval

= 4.19 MHz)

Square wave output frequency

= 4.19 MHz)

256 (N+1)/f

= 122

s - 15.6 ms

128 (N+1)/f

= 61.0

s - 7.81 ms

64 (N+1)/f

= 30.5

s - 3.91 ms

32 (N+1)/f

= 15.3

s - 1.95 ms

16 (N+1)/f

= 7.63

s - 977

/256 (N+1) =64 Hz - 8 kHz

/128 (N+1) = 128 Hz - 16 kHz

/64 (N+1) = 256 Hz - 32 kHz

/32 (N+1) = 512 Hz - 65 kHz

/16 (N+1) = 1024 Hz - 131 kHz

PD75517(A)

(4) Configuration and operation when the timer/pulse generator is used in the PWM pulse generation mode

Fig. 4-32 shows the configuration when the timer/pulse generator is used in the PWM pulse generation

mode.

The PWM pulse generation mode is selected by setting TPGM0 to 0. TPGM5 and TPGM7 are set to 1 to

enable pulse output. In the PWM mode, the PWM pulse signal can be output on the PPO pin, and IRQTPG

can be set at intervals of a fixed time period (2

= 5.46 ms: at 6.0 MHz or 2

= 7.81 ms: At 4.19 MHz).

PWM pulses output by the

PD75517(A) are active-low and have an accuracy of 14 bits. This pulse signal

is applicable for electronic tuning and control of a DC motor when it is integrated by an external low-pass

filter and is converted to analog voltage. (See Fig. 4-33.)

The PWM pulse signal is generated by combining the basic period determined by 2

and the secondary

period by 2

so that the time constant of the external low-pass filter can be decreased.

Table 4-8 lists the basic and secondary periods by oscillator frequency.

Table 4-8 Basic and Secondary Periods

The low-level width of a PWM pulse depends on the 14-bit modulo latch value. The upper 8 bits of the

modulo latch are transferred from the 8 bits of MODH, and the lower 6 bits of the latch are transferred

from the upper 6 bits of MODL.

When the PWM pulse signal is converted to analog form, the voltage level of the analog output is obtained

as follows:

Value of modulo latch

= V

ref

: Reference voltage of external switching circuitry

To prevent an incorrect PWM pulse from being output by unstable modulo latch data being rewritten, the

PD75517(A) allows correct data to be written in MODH and MODL beforehand with 8-bit manipulation

instructions, then in the 14-bit data which is to be transferred to the modulo latch at one time. This transfer

is referred to as reloading, and it is controlled by TPGM3. If TPGM3 is 0, reloading is disabled, and if it

is 1, reloading is enabled. Follow the procedure below to rewrite the modulo latch contents:

(i)

Clear TPGM3 to disable reloading.

(ii)

Change the MODH and MODL contents.

(iii)

Set TPGM3 to enable reloading.

Cautions 1.

If the modulo register H (MODH) is set to 0, the PWM pulse generator cannot function

normally. So be sure to set MODH to a value from 1 to 255.

If the lower 2 bits of the modulo register L (MODL) is read, the read result is unpredictable.

If the modulo latch is changed in a shorter period than the PWM pulse basic period

(171

s: at 6.0 MHz or 244

s: at 4.19 MHz), PWM pulses do not change.

= 6.0 MHz

171

5.46 ms

= 4.19 MHz

244

7.81 ms

Basic period (2

)

Secondary period (2

)

PD75517(A)

4.8.1 Serial Interface (Channel 0) Functions

The clock synchronous 8-bit serial interface is contained in the

PD75517(A) and has four modes.

The functions of the four modes are outlined below.

Operation halt mode

This mode is used when serial transfer is not performed. This mode reduces power consumption.

Three-wire serial I/O mode

In this mode, 8-bit data is transferred through three lines: Serial clock (SCK0), serial output (SO0), and serial

input (SI0).

The three-wire serial I/O mode allows full-duplex transmission, so data transfer can be performed at higher

speed.

The user can choose 8-bit data transfer starting with the MSB or LSB, so devices starting with either the

MSB or LSB can be connected.

The three-wire serial I/O mode enables connections to be made with the 75X series, 78K series, and many

other types of peripheral I/O devices.

Two-wire serial I/O mode

In this mode, 8-bit data is transferred through two lines: Serial clock (SCK0) and serial data bus (SB0 or

SB1). By controlling output levels on the two lines by software, communication with multiple devices is

enabled.

The output levels of SCK0 and SB0 (or SB1) can be controlled by software, so the user can match an arbitrary

transfer format. This means that a line that has been required for handshaking to connect multiple lines

can be eliminated for more efficient I/O port utilization.

Serial bus interface (SBI) mode

In this mode, communication with multiple devices can be performed using two lines: Serial clock (SCK0)

and serial data bus (SB0 or SB1).

This mode conforms to the NEC serial bus format.

In this mode, the transmitter can output, on the serial data bus, an address for selecting a device subject

to serial communication, commands directed to the remote device, and data. The receiver can identify an

address, commands, and data from received data by hardware. This function enables more efficient I/O

port utilization as in the case of the two-wire serial I/O mode. In addition, this function can simplify the

serial interface control portion of an application program.

4.8.2 Configuration of Serial Interface (Channel 0)

Fig. 4-34 shows the block diagram of the serial interface (channel 0).

PD75517(A)

4.8.3 Register Functions

(1) Serial operation mode register 0 (CSIM0)

Fig. 4-35 shows the format of serial operation mode register 0 (CSIM0).

CSIM0 is an 8-bit register which specifies a serial interface (channel 0) operation mode, serial clock, wake-

up function, and so forth.

CSIM0 is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be

manipulated bit by bit. Each bit can be manipulated using its name.

Each bit may or may not allow read and/or write operation. (See Fig. 4-35.) Bit 6 allows bit test operation

only; any data written to this bit is invalid.

When the RESET signal is input, this register is set to 00H.

Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (1/3)

Remark

(R) : Read only

(W) : Write only

CSIE0

COI

WUP

CSIM04 CSIM03

CSIM01

CSIM02

CSIM00

Address

CSIM0

Symbol

Serial clock selection bit (W)

FE0H

Serial interface operation enable/disable specification bit (W)

Serial interface operation mode selection bit (W)

Wake-up function specification bit (W)

Signal from address comparator (R)

PD75517(A)

Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (2/3)

Serial clock selection bit (W)

Note

The values in parentheses are for f

= 4.19 MHz or 6.0 MHz.

Serial interface operation mode selection bit (W)

Remark

: Don't care

Wake-up function specification bit (W)

Caution When WUP = 1 is set during BUSY signal output, BUSY is not released. In the SBI mode, the

BUSY signal is output until the next falling edge of the serial clock (SCK0) appears after release

of BUSY is directed. Before setting WUP = 1, be sure to confirm that the SB0 (or SB1) pin is high

after releasing BUSY.

Serial clock

SBI mode

2-wire serial I/O mode

3-wire serial I/O mode

External clock applied to SCK0 pin

Time/event counter output (T0)

(262 kHz or 375 kHz)

Note

(524 kHz or 750 kHz)

Note

CSIM01

CSIM00

(65.5 kHz or

93.8 kHz)

Note

SCK0 pin mode

Input

Output

Operation mode

CSIM04

CSIM03

CSIM02

Bit sequence of

shift register 0

SIO0

7-0

(Transfer starting

with MSB)

SIO0

0-7

(Transfer starting

with LSB)

SIO0

7-0

(Transfer starting

with MSB)

SIO0

7-0

(Transfer starting

with MSB)

SI0 pin function

SO0 pin function

SO0/P02

(CMOS output)

SB0/P02

(N-ch open-drain

input/output)

P02 input

SB0/P02

(N-ch open-drain

input/output)

P02 input

SI0/P03

(Input)

P03 input

SB1/P03

(N-ch open-drain

input/output)

P03 input

SB1/P03

(N-ch open-drain

input/output)

3-wire serial I/O

mode

SBI mode

2-wire serial I/O

mode

Sets IRQCSI0 each time serial transfer is completed in each mode.

Used in the SBI mode only to set IRQCSI0 only when an address received after bus release matches

the data in the slave address register (wake-up state). SB0/SB1 goes to high-impedance state.

WUP

PD75517(A)

Fig. 4-35 Format of Serial Operation Mode Register 0 (CSIM0) (3/3)

Signal from address comparator (R)

Note

COI can be read only before serial transfer is started or after serial transfer is completed. An

undefined value may be read during transfer.

COI data written by an 8-bit manipulation instruction is ignored.

Serial interface operation enable/disable specification bit (W)

Remarks 1. Each mode can be selected by setting CSIE0, CSIM03, and CSIM02.

2. The P01/SCK0 pin assumes the following state according to the setting of CSIE0, CSIM01, and

CSIM00:

Condition for being set (COI = 1)

When the slave address register (SVA) matches the

data of the shift register

COI

Note

Condition for being cleared (COI = 0)

When the slave address register (SVA) does not match

the data of the shift register

Serial clock counter

Cleared

Count operation

IRQCSI0 flag

Held

Can be set.

SO0/SB0, SI0/SB1 pin

Used only for port 0

Used in each mode as

well as for port 0

CSIE0

Shift register operation

Shift operation disabled

Shift operation enabled

CSIE0

CSIM03

CSIM02

Operation mode

Operation halt mode

Three-wire serial I/O mode

SBI mode

Two-wire serial I/O mode

CSIE0

CSIM01

CSIM00

P01/SCK0 pin state

Input port

High impedance

High level output

Serial clock output (High level output)

PD75517(A)

(2) Serial bus interface control register (SBIC)

Fig. 4-36 shows the format of the serial bus interface control register (SBIC).

SBIC is an 8-bit register consisting of bits for controlling the serial bus and flags for indicating the states

of input data from the serial bus. SBIC is used mainly in the SBI mode.

SBIC is manipulated using a bit manipulation instruction. SBIC cannot be manipulated using a 4-bit or

8-bit memory manipulation instruction.

Each bit may or may not allow read and/or write operation. (See Fig. 4-36.)

When the RESET signal is input, this register is set to 00H.

Caution

Only the following bits can be used in the three-wire and two-wire serial I/O modes:

Bus release trigger bit (RELT):

Sets the SO0 latch.

Command trigger bit (CMDT):

Clears the SO0 latch.

Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (1/3)

Remark

(R)

: Read only

(W)

: Write only

(R/W) : Read/write

BSYE

ACKD

ACKE

ACKT

CMDD

CMDT

RELD

RELT

Address

SBIC

Symbol

Bus release trigger bit (W)

FE2H

Command trigger bit (W)

Bus release detection flag (R)

Command detection flag (R)

Acknowledge trigger bit (W)

Acknowledge enable bit (R/ W)

Acknowledge detection flag (R)

Busy enable bit (R/ W)

PD75517(A)

Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (2/3)

Bus release trigger bit (W)

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial

transfer.

Command trigger bit (W)

Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or after serial

transfer.

Bus release detection flag (R)

Command detection flag (R)

Acknowledge trigger bit (W)

Cautions 1.

Never set ACKT before or during serial transfer.

ACKT cannot be cleared by software.

Before setting ACKT, set ACKE = 0.

Acknowledge enable bit (R/W)

Control bit for bus release signal (REL) trigger output.

By setting RELT = 1, the SO0 latch is set to 1. Then the RELT bit is automatically cleared to 0.

RELT

Condition for being set (RELD = 1)

The bus release signal (REL) is detected.

RELD

Condition for being cleared (RELD = 0)

The transfer start instruction is executed.

The RESET signal is entered.

CSIE0 = 0 (See Fig. 4-35.)

SVA does not match SIO0 when an address is

received.

Control bit for command signal (CMD) trigger output.

By setting CMDT = 1, the SO0 latch is cleared to 0. Then the CMDT bit is automatically cleared to 0.

CMDT

Condition for being set (CMDD = 1)

The command signal (CMD) is detected.

CMDD

Condition for being cleared (CMDD = 0)

The transfer start instruction is executed.

The bus release signal (REL) is detected.

The RESET signal is entered.

CSIE0 = 0 (See Fig. 4-35.)

When set after transfer, ACK is output in phase with the next SCK0. After ACK signal output, this bit is auto-

matically cleared to 0.

ACKT

Disables automatic output of the acknowledge signal (ACK). (Output by ACKT is possible.)

ACKE

When set before transfer

When set after transfer

ACK is output in phase with the 9th clock of SCK0.

ACK is output in phase with SCK0 immediately following set

instruction execution.

PD75517(A)

Fig. 4-36 Format of Serial Bus Interface Control Register (SBIC) (3/3)

Acknowledge detection flag (R)

Busy enable bit (R/W)

Examples 1. A command signal is output.

SEL

MB15

; or CLR1 MBE

SET1

CMDT

2. RELD and CMDD are tested to identify the types of received data and the types of processing

accordingly.

By setting WUP = 1, this interrupt routine is processed only when an address match is found.

SEL

MB15

SKF

RELD

; RELD test

!ADRS

SKT

CMDD

; CMDD test

!DATA

CMD

· · · · · · · · ·

; Command analysis

DATA :

· · · · · · · · ·

; Data processing

ADRS :

· · · · · · · · ·

; Address decode

Condition for being set (ACKD = 1)

The acknowledge signal (ACK) is detected (in phase

with the rising edge of SCK0).

ACKD

Condition for being cleared (ACKD = 0)

The transfer start instruction is executed.

The RESET signal is entered.

The busy signal is automatically disabled.

Busy signal output is stopped in phase with the falling edge of SCK0 immediately after clear

instruction execution.

The busy signal is output after the acknowledge signal in phase with the falling edge of SCK0.

BSYE

PD75517(A)

(3) Shift register (SIO0)

Fig. 4-37 shows the configuration of peripheral hardware of shift register 0. SIO0 is an 8-bit register which

performs parallel-serial conversion and serial transfer (shift) operation in phase with the serial clock.

Serial transfer is started by writing data to SIO0.

In transmission, data written to SIO0 is output on the serial output (SO0) or serial data bus (SB0/SB1). In

reception, data is read from the serial input (SI0) or SB0/SB1 into SIO0.

Data can be read from or written to SIO0 by using an 8-bit manipulation instruction.

When the RESET signal is entered during operation, the value of SIO0 is undefined. When the RESET signal

is entered in the standby mode, the value of SIO0 is preserved.

Shift operation is stopped after 8-bit transmission or reception is completed.

Fig. 4-37 Peripheral Hardware of Shift Register 0

The timing for reading SIO0 and start of serial transfer (writing to SIO0) is as follows:

· When the serial interface operation enable/disable bit (CSIE0) = 1. However, the case where CSIE0 is

set to 1 after data is written to the shift register 0 is excluded.

· When the serial clock is masked after 8-bit serial transfer

· SCK0 is high.

SET

CLR

RELT

CMDT

CLK

BUSY/ACK

Internal bus

Address
comparator

Shift register (SIO0)

SO0 latch

Shift clock

N-ch open-drain output

CSIM0

PD75517(A)

(4) Slave address register (SVA)

The slave address register (SVA) has the two functions described below.

SVA is manipulated using an 8-bit manipulation instruction. SVA allows only write operation.

When the RESET signal is entered, the value of SVA is undefined. However, the value of SVA is preserved

when the RESET signal is entered in the standby mode.

· Slave address detection

[In the SBI mode]

SVA is used when the

PD75517(A) is connected as a slave device to the serial bus. SVA is an 8-bit

to the connected slaves to select a particular slave. Two data values (a slave address output from the

master and the value of SVA) are compared with each other by the address comparator. If a match

is found, the slave is selected.

At this time, bit 6 (COI) of serial operation mode register 0 (CSIM0) is set to 1.

Cautions 1. Slave selection or nonselection state is detected by detecting a match for a slave address

received after bus release (in the state of RELD = 1).

For this match detection, an address match interrupt (IRQCSI0) generated when WUP is set

to 1 is usually used. So detect selection/nonselection state by slave address when WUP

is set to 1.

2. When detecting selection/nonselection state without using an interrupt when WUP is 0,

do not use the address match detection method. Instead, use transfer of commands set

in advance in a program.

· Error detection

[In the two-wire serial I/O mode or SBI mode]

SVA detects an error in either of the following cases:

· When addresses, commands, or data is transferred with the

PD75517(A) operating as the master

· When data is transferred with the

PD75517(A) operating as a slave

4.8.4 Signals

Table 4-10 lists signals. Fig. 4-38 to 4-43 show operations of signals and flags.

PD75517(A)

Table 4-10 Various Signals (1/2)

SCK0

SB0 (SB1)

"H"

SCK0

SB0 (SB1)

Rising edge of SB0

(SB1) when SCK0 = 1

Falling edge of SB0

(SB1) when SCK0 = 1

Low level signal

output on SB0 (SB1)

during one SCK0 clock

cycle after serial

reception is completed

Low level signal

output on SB0 (SB1)

after acknowledge

signal

High level signal

output on SB0 (SB1)

before serial transfer

is started or after

serial transfer is

completed

Bus release signal

(REL)

Command signal

(CMD)

Acknowledge

signal

(ACK)

Busy signal

(BUSY)

Ready signal

(READY)

Output
device

Definition

· RELT is set.

· CMDT is set.

ACKE = 1

ACKT is set.

· BSYE = 1

BSYE = 0

Execution of

instruction to

write data to

SIO0 (Transfer

start request)

Condition for
output

· RELD is set.

· CMDD is clear-

ed.

· CMDD is set.

· ACKD is set.

Flag
operation

Meaning
of signal

Indicates that CMD

signal follows and

data transmitted is

address data.

(1)

(2)

Indicates completion

of reception.

Indicates that serial

transfer is disabled

because processing

is in progress.

Indicates that serial

transfar is enabled.

Signal name

Timing chart

READY

ACK

SCK0

(SB1)

SB0

BUSY

ACK

BUSY

Master

Master/

slave

Slave

Data transmitted

after REL signal

output is address.

(Data transmitted,

with REL signal

not being output,

is command.

PD75517(A)

Table 4-10 Various Signals (2/2)

Synchronous clock for

outputting address/

command/data, ACK

signal, synchronous

BUSY signal, and so on.

Address/command/data

is output during first 8

clock cycles.

8-bit data transferred in

phase with SCK0 after

REL signal and CMD

signal output

8-bit data transferred in

phase with SCK0 after

only CMD signal is

output, with REL signal

not being output

8-bit data transferred in

phase with SCK0, with

neither REL signal nor

CMD signal being

output

Serial clock

(SCK0)

Address

(A7 - A0)

Command

(C7 - C0)

Data

(D7 - D0)

Output
device

Definition

Execution of

instruction to

write data to SIO0

when CSIE0 = 1

(serial transfer

start request)

Note 2

Condition for
output

IRQCSI0 is set (on

rising edge of 9th

clock)

Note 1

Flag
operation

Meaning
of signal

Timing of signal

output on serial data

bus

Address of slave

device on serial bus

Directions and

messages to slave

device

Data processed by

slave or master

Signal name

Timing chart

Master

Master/

slave

Notes 1. When WUP = 0, IRQCSI0 is always set on the 9th rising edge of SCK0.

When WUP = 1, IRQCSI0 is set on the 9th rising edge of SCK0 only if a received address matches the value of the slave address register (SVA).

2. If the BUSY state is present, data transfer is started after the READY state is set.

SCK0

SB0
(SB1)

SCK0

SB0
(SB1)

SCK0

SB0
(SB1)

CMD

REL

CMD

SCK0

SB0
(SB1)

100

PD75517(A)

4.8.5 Serial Interface (Channel 0) Operation

(1) Operation halt mode

The operation halt mode is used when serial transfer is not performed. This mode reduces power

consumption.

The shift register 0 does not perform shift operation in this mode, so the shift register can be used as a

normal 8-bit register. When the RESET signal is entered, the operation halt mode is set.

The P02/SO0/SB0 pin and P03/SI0/SBI pin function as input-only port pins. The P01/SCK0 pin can be used

as an input port pin by setting the serial operation mode register 0.

(2) Three-wire serial I/O mode operations

The three-wire serial I/O mode is compatible with other modes used in the 75X series,

PD7500 series,

and 78K series.

Communication is performed using three lines: Serial clock (SCK0), serial output (SO0), and serial input

(SI0).

(a) Communication operation

The three-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by

bit in phase with the serial clock.

The shift register performs shift operation on the falling edge of the serial clock (SCK0). Transmit data

is latched on the SO0 latch, and is output on the SO0 pin. Receive data applied to the SI0 pin is latched

in the shift register 0 on the rising edge of SCK0.

When eight bits have been transferred, shift register 0 operation automatically terminates setting the

interrupt request flag (IRQCSI0).

Fig. 4-44 Timing of Three-Wire Serial I/O Mode

SCK0

SI0

IRQCSI0

SO0

DI0

DO0

DI1

DO1

DI2

DO2

DI3

DO3

DI4

DO4

DI5

DO5

DI6

DO6

DI7

DO7

Transfer is started in phase with falling edge of SCK0.

Execution of instruction that writes data to SIO0 (Transfer start request)

Completion of transfer

101

PD75517(A)

The SO0 pin becomes a CMOS output and outputs the state of the SO0 latch. So the output state of

the SO0 pin can be manipulated by setting the RELT bit and CMDT bit.

However, this manipulation must not be performed during serial transfer.

The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output

mode (internal system clock mode). (See Section 4.8.7.)

(b) Switching between MSB and LSB as the first transfer bit

The three-wire serial I/O mode has a function that can switch between the MSB and LSB as the first

bit of transfer.

Fig. 4-45 shows the configuration of shift register 0 (SIO0) and internal bus. As shown in Fig. 4-45,

read or write operation can be performed by switching between the MSB and LSB.

This switching can be specified using bit 2 of serial operation mode register 0 (CSIM0).

Fig. 4-45 Transfer Bit Switching Circuit

The first bit is switched by changing the order of data bits written to shift register 0 (SIO0). The shift

operation order of SIO0 is always the same.

Accordingly, the first bit must be switched between the MSB and LSB before writing data to the shift

SCK0

Internal bus

LSB first

MSB first

SI0

SO0

Read/write gate

Shift resister0 (SIO0)

SO0 latch

Read/write gate

102

PD75517(A)

(3) Two-wire serial I/O mode

The two-wire serial I/O mode can be made compatible with any communication format by programming.

In this mode, communication is basically performed using two lines: Serial clock (SCK0) and serial data

input/output (SB0 or SB1).

(a) Communication operation

The two-wire serial I/O mode transfers data, with eight bits as one block. Data is transferred bit by

bit in phase with the serial clock.

The shift register 0 performs shift operation on the falling edge of the serial clock (SCK0). Transmit

data is latched on the SO0 latch, and is output on the SB0/P02 pin or SB1/P03 pin starting with the

MSB. Receive data applied to the SB0 pin or SB1 pin is latched in the shift register on the rising edge

of SCK0.

When eight bits have been transferred, shift register 0 operation automatically terminates setting the

interrupt request flag (IRQCSI0).

Fig. 4-46 Timing of Two-Wire Serial I/O Mode

The SB0 or SB1 pin becomes an N-ch open-drain I/O when specified as the serial data bus, so the

voltage level on that pin must be pulled up externally.

The state of the SO0 latch is output on the SB0 or SB1 pin, so the SB0 or SB1 pin output states can

be controlled by setting the RELT or CMDT bit.

However, this operation must not be performed during serial transfer.

The output state of the SCK0 pin can be controlled by manipulating the P01 output latch in the output

mode (internal system clock mode). (See Section 4.8.7.)

SCK0

SB0/SB1

IRQCSI0

Transfer is started in phase with falling edge of SCK0.

Execution of instruction that writes date to SIO0 (Transfer start request)

Completion of transfer

103

PD75517(A)

(4) SBI mode operation

The SBI (serial bus interface) is a high-speed serial interface that conforms to the NEC serial bus format.

To allow communication with multiple devices on a single-master and high-speed serial bus using two

signal lines, the SBI has a bus configuration function added to the clock synchronous serial I/O method.

So the SBI can reduce ports and wires on boards when multiple microcomputers and peripheral ICs are

used to configure a serial bus.

Fig. 4-47 is an example of the SBI system configuration.

Fig. 4-47 Example of SBI System Configuration

Cautions 1. In the SBI mode, the serial data bus pin SB0 (or SB1) is an open-drain output. So the serial

data bus line is placed in the wired OR state. A pull-up resistor is required for the serial data

bus line.

2. To switch between the master and slave, a pull-up resistor is required also for the serial clock

line (SCK0), because SCK0 input/output switching is performed between the master and

slave asynchronously.

SCK0

SB0 (SB1)

Master CPU

SCK0

SB0 (SB1)

SCK0

SB0 (SB1)

SCK0

SB0 (SB1)

Serial data bus

Serial clock

Address 1

Slave CPU

Address 2

Slave CPU

Address N

Slave IC

105

PD75517(A)

Fig. 4-48 Timing of SBI Transfer

(b) Communication operation

In the SBI mode, the master usually selects a slave device to communicate with from multiple devices

by outputting the address of the slave in the serial bus.

After selecting a device to communicate with, the master exchanges commands and data with the

slave device, thus establishing serial communication.

Fig. 4-49 to 4-52 show the timing charts of data communication operations.

In the SBI mode, the shift register 0 performs shift operation on the falling edge of the serial clock

(SCK0). Transmit data is held on the SO0 latch, and is output on the SB0/P02 or SB1/P03 pin starting

with the MSB. Receive data applied to the SB0 (or SB1) pin is latched in the shift register 0 on the

rising edge of SCK0.

SCK0

SB0/SB1

BUSY

ACK

SCK0

SB0/SB1

READY

C0 ACK

BUSY

SCK0

SB0/SB1

READY

D0 ACK

BUSY

Address transfer

Bus release signal

Command transfer

Command signal

Data transfer

110

PD75517(A)

4.8.6 Transfer Start in Each Mode

In each of the three-wire serial I/O, two-wire serial I/O, and SBI modes, serial transfer is started by writing

transfer data in shift register 0 (SIO0). However, the following two conditions must be satisfied:

The serial interface operation enable/disable bit (CSIE0) is set to 1.

The internal serial clock is not operating after 8-bit serial transfer, or SCK0 is high.

Caution Transfer cannot be started by setting CSIE0 to 1 after writing data to the shift register 0.

When eight bits have been transferred, serial transfer automatically terminates setting the interrupt request

flag (IRQCSI0).

[In the two-wire serial I/O mode]

Caution The N-ch transistor needs to be turned off when data is received. So FFH must be written to SIO0

beforehand.

[In the SBI mode]

Cautions 1.

The N-ch transistor needs to be turned off when data is received. So FFH must be written

to SIO0 beforehand.

However, when the wake-up function specification bit (WUP) is set to 1, the N-ch transistor

is always off. So FFH need not be written to SIO0 beforehand for reception.

If data is written to SIO0 when the slave is busy, the data is not lost.

Transfer is started when the busy state is released and input to SB0 (or SB1) goes high.

Example When RAM data specified by the HL register is transferred to SIO0, SIO0 data is loaded into the

accumulator at the same time, and serial transfer is started.

MOV

XA, @HL

; Extracts transmit data from RAM

SEL

MB15

; or CLR1 MBE

XCH

XA, SIO0

; Exchanges transmit data with receive data and starts transfer

111

PD75517(A)

4.8.7 Manipulation of SCK0 Pin Output

The SCK0/P01 pin has a built-in output latch, so that this pin allows static output by software manipulation

in addition to normal serial clock output.

The number of SCK0s can be software-set arbitrarily by manipulating the P01 output latch. (The SO0/SB0/

SB1 pin is controlled by manipulating the RELT and CMDT bits of SBIC.)

The procedure for manipulating SCK0/P01 pin output is explained below.

Set serial operation mode register 0 (CSIM0) (SCK0 pin: output mode). When serial transfer is

halted, SCK0 from the serial clock control circuit is set to 1.

Manipulate the P01 output latch by using a bit manipulation instruction.

Example To output one clock cycle on the SCK0/P01 pin by software

SEL

MB15

; or CLR1 MBE

MOV

XA, #10000011B ; SCK0 (f

), output mode

MOV

CSIM0, XA

CLR1

0FF0H.1

; SCK0/P01

SET1

0FF0H.1

; SCK0/P01

Fig. 4-53 SCK0/P01 Pin Circuit Configuration

The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to 1.

Cautions 1.

During normal serial transfer, the P01 output latch must be set to 1.

The P01 output latch cannot be addressed by specifying PORT0.1 (as described below). The

address of the latch (0FF0H.1) must be coded in the operand of an instruction directly.

However, MBE = 0 (or MBE = 1, MBS = 15) must be specified before the instruction is

executed.

CLR1 PORT0.1

Not allowed

SET1 PORT0.1

CLR1 0FF0H.1

Allowed

SET1 0FF0H.1

P01/SCK0

P01
output
latch

SCK0

To internal circuit

Address
FF0H.1

When CSIE0=1 and CSIM01
and CSIM00 are not 00

From the serial clock
control circuit

114

PD75517(A)

4.9.3 Register Functions

(1) Serial operation mode register 1 (CSIM1)

Fig. 4-55 shows the format of serial operation mode register 1 (CSIM1).

CSIM1 is an 8-bit register which specifies a serial interface (channel 1) operation mode and serial clock.

CSIM1 is manipulated using an 8-bit memory manipulation instruction. Only the high-order one bit can

be manipulated independently. Each bit can be manipulated using its name.

When the RESET signal is input, this register is set to 00H.

Fig. 4-55 Format of Serial Operation Mode Register 1 (CSIM1)

Remark (W): Write only

Serial clock selection bit (W)

Note The values at 4.19 MHz and 6.0 MHz are indicated in parentheses.

Serial interface operation enable/disable specification bit (W)

Caution Be sure to write 0 in bits 2 to 6 of the serial operation mode register 1 (CSIM1).

CSIE1

CSIM11

CSIM10

Address

CSIM1

Symbol

Serial clock selection bit (W)

FC8H

Serial interface operation enable/disable specification bit (W)

Serial clock (3-wire serial I/O mode)

CSIM11

CSIM10

External clock applied to SCK1 pin

Not to be set

(262 kHz or 375 kHz)

Note

(524 kHz or 750 kHz)

Note

SCK1 pin mode

Input

Output

Serial clock counter

Cleared

Count operation

EOT flag

Held

Can be set.

SO1, SI1 pin

Used only for port 8

Used in serial interface as

well as for port 8

CSIE1

Shift register operation

Shift operation disabled

Shift operation enabled

115

PD75517(A)

Example

To select f

as the serial clock, and set the serial transfer end flag EOT to 1 each time serial

transfer terminates

SEL

MB15

; Or CLR1 MBE

MOV XA, #10000010B

MOV CSIM1, XA

; CSIM1

10000010B

(2) Shift register 1 (SIO1)

SIO1 is an 8-bit register which performs parallel-serial conversion and serial transfer (shift) operation in

phase with the serial clock.

Serial transfer is started by writing data to SIO1. The MSB is used as the first bit of transfer.

In transmission, data written to SIO1 is output on the serial output (SO1). In reception, data is read from

the serial input (SI1) into SIO1.

Data can be read from or written to SIO1 using an 8-bit manipulation instruction.

When the RESET signal is entered during operation, the value of SIO1 is undefined. When the RESET signal

is entered in the standby mode, the value of SIO1 is preserved.

Shift operation is stopped after 8-bit transmission or reception is completed.

The timing for reading SIO1 and start of serial transfer (writing to SIO1) is as follows:

· When the serial interface operation enable/disable bit (CSIE1) is set to 1. However, the case where CSIE1

is set to 1 after data is written to the shift register 1 is excluded.

· When the serial clock is masked after 8-bit serial transfer

· When SCK1 is high

4.9.4 Serial Interface (Channel 1) Operation

(1) Operation halt mode

The operation halt mode is used when serial transfer is not performed, which is set by setting 0 in CSIE1.

This mode reduces power consumption.

Shift register 1 does not perform shift operation in this mode, so the shift register can be used as a normal

8-bit register.

When the RESET signal is entered, the operation halt mode is set. The P82/SO1 pin and P83/SI1 pin

function as input-only port pins. The P81/SCK1 pin can be used as an input port pin by setting serial

operation mode register 1.

116

PD75517(A)

(2) Three-wire serial I/O mode operations

The three-wire serial I/O mode is compatible with other modes used in the 75X series,

PD7500 series,

and 78K series. This mode is set by setting CSIE1 to 1.

Communication is performed using three lines: Serial clock (SCK1), serial output (SO1), and serial input

(SI1).

The three-wire serial I/O mode transfers data with eight bits as one block. Data is transferred bit by bit

in phase with the serial clock.

Shift register 1 performs shift operation on the falling edge of the serial clock (SCK1). Transmit data is

latched on the SO1 latch, and is output on the SO1 pin. Receive data applied to the SI1 pin is latched in

the shift register 1 on the rising edge of SCK1.

When eight bits have been transferred, operation of shift register 1 automatically terminates setting the

serial transfer end flag (EOT).

Setting the serial transfer and flag (EOT) cannot release the standby function.

Fig. 4-56 Timing of the Three-Wire Serial I/O Mode

Example

To transfer the RAM data specified by the HL register pair to SIO1, load the SIO1 data to the

accumulator, and start serial transfer:

MOV

XA, @HL

; Fetch transmit data from RAM

SEL

MB15

; Or CLR1 MBE

XCH

XA, SIO1

; Exchange transmit data and receive data, and start transfer

SCK1

SI1

EOT

SO1

DI0

DO0

DI1

DO1

DI2

DO2

DI3

DO3

DI4

DO4

DI5

DO5

DI6

DO6

DI7

DO7

Transfer is started in phase with falling edge of SCK1.

Execution of instruction that writes data to SIO1 (Transfer start request)

Completion of transfer

118

PD75517(A)

(2) Pins of the A/D converter

(a) AN0 to AN7

AN0 to AN7 are the input pins for eight analog signal channels. Analog signals subject to A/D

conversion are applied to these pins.

The A/D converter contains a sample-and-hold circuit, and analog input voltages are internally

maintained during A/D conversion.

(b) AV

REF

, AV

A reference voltage for the A/D converter is applied to these pins.

By using an applied voltage across AV

REF

and AV

, signals applied to AN0 to AN7 are converted to

digital signals.

must be always V

(3) A/D conversion mode register

The A/D conversion mode register (ADM) is an 8-bit register which operates as follows:

Selects analog input channels.

Selects comparator bias voltage.

Note

Directs the start of conversion and detects the completion of conversion.

ADM is set with an 8-bit manipulation instruction.

Bit 2 (EOC) and bit 3 (SOC) can be manipulated on a bit-by-bit basis.

The generation of a RESET signal initializes ADM to 04H. That is, only EOC is set to 1, with all bits cleared

to 0.

Note If the reference voltage (AV

REF

) of the A/D converter does not exceed 0.65V

, the accuracy of

conversion may be lowered. To correct such lowered accuracy, selecting comparator bias

voltage is provided.

119

PD75517(A)

Fig. 4-58 Format of the A/D Conversion Mode Register

Caution A/D conversion is started a maximum of 2

seconds (2.67

s at f

= 6.0 MHz)

Note

after SOC

is set. (For details, see item (5).)

Note 2

seconds = 3.81

s for f

= 4.19 MHz

ADM6

ADM5

ADM4

SOC

ADM1

EOC

Address

ADM

Symbol

FD8H

End of conversion flag (R)

Start of conversion bit (W)

Analog channel selection bit (W)

EOC

SOC

Conversion under way

Conversion completed

Setting this bit starts conversion.
After conversion is started, the bit is reset
automatically.

ADM6

ADM5

ADM4

Analog channel

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Comparator bias voltage selection

REF

0.6V

REF

0.65V

ADM1

Reamark This bit may be set to either 0 or 1 for

0.6V

REF

0.65V

120

PD75517(A)

(4) SA register (successive approximation register)

The SA register is an 8-bit register to hold the result of A/D conversion in successive approximation.

SA is read with an 8-bit manipulation instruction. No data can be written to SA by software.

The generation of a RESET signal makes SA undefined.

SA is mapped to address FDAH.

(5) A/D converter operation

Analog input signals subject to A/D conversion are specified by setting bits 6, 5, and 4 in the A/D conversion

mode register (ADM6, ADM5, and ADM4). Comparator bias voltage selection is specified by setting bit

1 in the A/D conversion mode register (ADM1).

A/D conversion is started by setting bit 3 (SOC) of ADM to 1. After that, SOC is automatically cleared to

0. A/D conversion is performed by hardware using the successive-approximation method. The resultant

8-bit data is loaded into the SA register. Upon completion of A/D conversion, ADM bit 2 (EOC) is set to 1.

Fig. 4-59 shows the timing chart of A/D conversion.

The A/D converter is used as follows:

Select analog input channels and comparator bias voltage (by setting ADM6, ADM5, ADM4, and

ADM1).

Direct the start of A/D conversion (by setting SOC).

Wait for the completion of A/D conversion (wait for EOC to be set or wait using a software timer).

Read the result of A/D conversion (read the SA register).

Cautions 1.

and

above can be performed at the same time.

2. There is a delay of up to 2

seconds (f

= 6.0 MHz: 2.67

s, or f

= 4.19 MHz: 3.81

s) from

the setting of SOC to the clearing of EOC after A/D conversion is started. EOC must be tested

when a time indicated in Table 4-11 has elapsed after the setting of SOC. Table 4-11 also

indicates A/D conversion times.

Table 4-11 Setting of SCC and PCC

Note 40.1

s for f

= 4.19 MHz

Remark

: Don't care

SCC0

PCC1

PCC0

Setting values of SCC, PCC

A/D conversion time

Wait time from SOC setting
to EOC test

168/f

Note

(28.0

s/f

= 6.0 MHz)

Conversion stopped

Wait time from SOC setting
to A/D conversion comple-
tion

Waiting not required

1 machine cycle

2 machine cycles

4 machine cycles

Waiting not required

3 machine cycles

11 machine cycles

21 machine cycles

42 machine cycles

Waiting not required

SCC1

122

PD75517(A)

(6) Notes on the standby mode

The A/D converter operates with the main system clock. So its operation stops in the STOP mode, or when

the subsystem clock is used, in the HALT mode. A current flows through the AV

REF

pin even when the

A/D converter is stopped, so that the current must be stopped to reduce overall system power consump-

tion. Since the P113 pin has a higher drive capability than the other ports, it can supply voltage to the

REF

pin directly.

In this case, however, the actual AV

REF

voltage does not provide precision. This means that the value

resulting from conversion does not provide precision and can be used only for relative comparison. In

the standby mode, outputting a low on the P113 can reduce power consumption.

Fig. 4-61 Reducing Power Consumption in the Standby Mode

Note The drive capability of P-ch is higher than that of other ports.

PD75517(A)

P-ch

Note

P113

REF

= V

123

PD75517(A)

(7) Other notes on use

(a) AN0 to AN7 input range

Specified voltages must be applied to AN0 to AN7 inputs. If a voltage higher than V

or lower than

is applied even when the maximum absolute rating is not exceeded, the conversion result for an

associated channel becomes unpredictable. In addition, the conversion results for other channels

may be affected.

(b) Noise protection

To maintain 8-bit resolution, the user should pay attention to noise that may be applied to the AV

REF

and AN0 to AN7 pins. Noise adversely affects operation to a greater extent when the analog input

source has a higher output impedance. As shown in Fig. 4-62, a capacitor should be externally

connected.

Fig. 4-62 Analog Input Pin Connection

AN4/P150 to AN7/P153 pins

The analog input pins (AN4 to AN7) are also used for an input port (PORT15).

When any of AN4 to AN7 is selected for A/D conversion, no input instruction must be executed for

PORT15 during A/D conversion. Otherwise, the accuracy of conversion may deteriorate.

If a digital pulse signal is applied to a pin adjacent to a pin being used for A/D conversion, an expected

A/D conversion value may not be obtained because of coupling noise.

So no digital pulse signal should be applied to the adjacent pin being used for A/D conversion.

REF

, AN0 to AN7

C = 100 1000 pF

PD75517(A)

If it is anticipated that noise voltages do not fall in the
range of V

to V

, clamp this point using a diode with

a low V

(not higher than 0.3 V).

124

PD75517(A)

4.11 BIT SEQUENTIAL BUFFER: 16 BITS

The bit sequential buffer is special data memory for bit manipulations. In particular, the buffer allows bit

manipulations to be performed very easily by sequentially changing address and bit specifications. So the

buffer is useful in processing long data bit by bit.

This data memory consists of 16 bits, and allows pmem.@L addressing with a bit manipulation instruction

and also allows indirect bit specification using the L register. In this case, only by incrementing or

decrementing the L register in a program loop, the bit to be manipulated can be sequentially shifted for

continued processing.

Fig. 4-63 Format of the Bit Sequential Buffer

Remark In pmem.@L addressing, bit specification is shifted according to the L register.

Data can also be manipulated using direct addressing. The buffer can be used for applications such as

continuous 1-bit data input or output operations by combining direct 1-bit, 4-bit, and 8-bit addressing with

pmem.@L addressing. In 8-bit manipulation, the higher eight bits or lower eight bits can be manipulated by

specifying BSB0 or BSB2.

Example

The 16-bit data of BUFF1 and BUFF2 are output from bit 0 of port 3 in serial mode.

Program example

CLR1

MBE

MOV

XA, BUFF1

MOV

BSB0, XA

; Set BSB0, 1

MOV

XA, BUFF2

MOV

BSB2, XA

; Set BSB2, 3

MOV

L, #0

LOOP0:

SKT

BSB0, @L

; Test specified BSB bit

LOOP1

NOP

; Dummy (timing adjustment)

SET1

PORT3.0

; Set bit 0 of port 3

LOOP2

LOOP1:

CLR1

PORT3.0

; Clear bit 0 of port 3

NOP

; Dummy (timing adjustment)

NOP

LOOP2:

INCS

; L

L+1

LOOP0

RET

BSB3

BSB2

BSB1

BSB0

FC3H

FC2H

FC1H

FC0H

L = F

L = C L = B

L = 8 L = 7

L = 4 L = 3

L = 0

DECS L

INCS L

Address

Bit

L register

Symbol

125

PD75517(A)

5. INTERRUPT FUNCTION

The

PD75517(A) has nine interrupt sources and can handle multiple interrupts with a priority.

The

PD75517(A) is also provided with two features for accepting testable interrupts.

Table 5-1 Interrupt Sources

Notes 1. The priority is used when two or more interrupt requests are issued at a time.

2. See (3) in Section 5.2 for details on INT2.

The following functions are provided for the interrupt control circuit of the

PD75517(A).

(a) Vectored interrupt function under hardware control which can determine whether to accept an interrupt

by an interrupt enable flag (IE

×××

) and the interrupt master enable flag (IME)

(b) Any interrupt start address can be set.

(IPS)

(d) Test function of an interrupt request flag (IRQ

×××

)

(The software can confirm that an interrupt occurred.)

(e) Release of the standby mode (Interrupts released by an interrupt enable flag can be selected.)

5.1 CONFIGURATION OF THE INTERRUPT CONTROL CIRCUIT

The interrupt control circuit of the

PD75517(A) is configured as shown in Fig. 5-1. Each hardware item

is mapped in the data memory space.

Vectored interrupt

request signal (vector

table address)

In/out

INTBT

(Reference time interval signal from basic

interval timer)

INT4

(Detection of both rising and falling edges)

INT0

(Rising/falling edge detection specification)

INT1

INTCSI0

(Serial data transfer completion signal)

INTT0

(Match signal between programmable timer/

counter count register and modulo register)

INTTPG

(Match signal from timer/pulse generator)

INT2

(Rising edge detection for an INT2 pin input

signal, or falling edge detection for either of

KR0 to KR7 pin input signals)

Note 2

INTW

(Signal from clock timer)

Interrupt source

Out

Priority

Note 1

VRQ1 (0002H)

VRQ2 (0004H)

VRQ3 (0006H)

VRQ4 (0008H)

VRQ5 (000AH)

VRQ6 (000CH)

Testable input signal (Sets IRQ2 and IRQW.)

127

PD75517(A)

5.2 HARDWARE OF THE INTERRUPT CONTROL CIRCUIT

(1) Interrupt request flag and interrupt enable flag

The following nine interrupt request flags (IRQ

×××

) corresponding to the interrupt sources are available.

INT0 interrupt request flag (IRQ0)

Serial interface interrupt request flag (IRQCSI0)

INT1 interrupt request flag (IRQ1)

Timer/event counter 0 interrupt request flag (IRQT0)

INT2 interrupt request flag (IRQ2)

Timer/pulse generator interrupt request flag (IRQTPG)

INT4 interrupt request flag (IRQ4)

Clock timer interrupt request flag (IRQW)

BT interrupt request flag (IRQBT)

The interrupt request flag is set to 1 when an interrupt request is issued, and is automatically cleared to

0 when the CPU is interrupted. Since the IRQBT and IRQ4 share the vector address, the clear operation

varies. (See Section 5.5.)

The following nine interrupt enable flags (IE

×××

) corresponding to the interrupt request flags are available.

INT0 interrupt enable flag (IE0)

Serial interface enable flag (IECSI0)

INT1 interrupt enable flag (IE1)

Timer/event counter 0 interrupt enable flag (IET0)

INT2 interrupt enable flag (IE2)

Timer/pulse generator interrupt enable flag (IETPG)

INT4 interrupt enable flag (IE4)

Clock timer interrupt enable flag (IEW)

BT interrupt enable flag (IEBT)

When an interrupt request flag is set, the interrupt enable flag corresponding to that interrupt request flag

enables the request interrupt. When an interrupt request flag is cleared, the interrupt enable flag

corresponding to that interrupt request flag disables the interrupt.

When an interrupt request flag is set and its corresponding interrupt enable flag enables the requested

interrupt, a vectored interrupt request (VRQn) is issued. This signal is also used for releasing the standby

mode.

The interrupt request flags and interrupt enable flags are manipulated with bit manipulating instructions

and 4-bit memory manipulation instructions. When a bit manipulation instruction is used, the flags can

always be manipulated directly irrespective of the MBE setting. The interrupt enable flags are manipulated

with EI IE

×××

and DI IE

×××

instructions. An SKTCLR instruction is normally used to test an interrupt request

flag.

Example EI

IE0

;Enables INT0.

IE1

;Disables INT1.

SKTCLR IRQCSI0 ; Skips and clears the interrupt request flag if IRQCSI0 is 1.

When an interrupt request flag is set with an instruction, a vectored interrupt is executed irrespective of

whether an interrupt occurs.

When a RESET signal is generated, an interrupt request flag and its corresponding interrupt enable flag

are cleared and all interrupts are disabled.

128

PD75517(A)

Table 5-2 Set Signals of Interrupt Request Flags

(2) Configurations of INT0, INT1, and INT4 pins

(a) As shown in Fig. 5-2 (a), INT0 is configured as an external interrupt pin that enables detection edge

selection.

In addition, the INT0 pin is provided with a noise elimination function using a sampling clock. The

noise eliminator eliminates pulses narrower than two-sampling-clock-cycle pulses (2t

Note

or 128/

) as noise and accepts pulses wider than as interrupt signals.

INT0 has two sampling clocks

and f

/64, either of which can be selected according to bit 3 (IM03)

of the edge detection mode register (IM0).

Bits 0 and 1 (IM00 and IM01) of the edge detection mode register (IM0) are used to select a detection

edge.

Fig. 5-3 (a) shows the format of IM0. A 4-bit memory manipulation instruction is used to set IM0. A

RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected.

Note t

represents a cycle time.

Cautions 1. Since the INT0 input is sampled with a clock, INT0 does not operate in a standby mode.

2. Input a pulse wider than two sampling clock cycles to the INT0/P10 pin. Otherwise, the

pulse is suppressed as noise by the noise eliminator when the pin is used as a port.

(b) As shown in Fig. 5-2 (b), INT1 is configured as an external interrupt pin that enables detection edge

selection.

The edge detection mode register (IM1) is used to select a detection edge.

Fig. 5-3 (b) shows the format of IM1. A 4-bit memory manipulation instruction is used to set IM1. A

RESET signal occurrence clears all bits to 0, and a rising edge is specified to be detected.

rising and falling edges.

IEBT

IE4

IE0

IE1

IECSI0

IET0

IETPG

IEW

IE2

Set by a reference time interval signal from the basic interval timer.

Set by a detected rising or falling edge of an INT4/P00 pin input signal.

Set by a detected edge of an INT0/P10 pin input signal. The detection edge is specified

by the INT0 mode register (IM0).

Set by a detected edge of an INT1/P11 pin input signal. The detection edge is specified

by the INT1 mode register (IM1).

Set by a serial data transfer completion signal for the serial interface.

Set by a match signal from timer/event counter 0.

Set by a match signal from the timer/pulse generator.

Set by a signal from the clock timer.

Set by a detected rising edge of an INT2/P12 pin input signal, or a detected falling edge

of one of a KR0/P60-KR7/P73 pin input signals.

IRQBT

IRQ4

IRQ0

IRQ1

IRQCSI0

IRQT0

IRQTPG

IRQW

IRQ2

Set signal of interrupt request flag

Interrupt
enable flag

Interrupt
request flag

130

PD75517(A)

Fig. 5-3 Format of Edge Detection Mode Registers

(a) INT0 edge detection mode register (IM0)

(b) INT1 edge detection mode register (IM1)

(c) INT2 edge detection mode register (IM2)

Caution Since changing or setting the edge detection mode register may set an interrupt request flag,

disable the interrupts before changing the edge detection mode register. Then clear the

interrupt request flag with a CLR1 instruction and enable the interrupts. When f

/64 is selected

as a sampling clock pulse in changing IM0, wait for 16 machine cycles after changing the mode

register and clear the interrupt request flag.

IM10

FB5H

IM1

Specifies rising edge.

Specifies falling edge.

IM03

IM01

IM00

FB4H

Address

IM0

Symbol

Sampling clock

Detection edge specification

Specifies rising edge.

Specifies falling edge.

Specifies both rising and falling edges.

Ignored (interrupt request flag is not set.)

/64 (at 10.7 s/6.0 MHz, or 15.3 s/4.19 MHz)

IM21

IM20

FB6H

IM2

IM21

IM20

INT2 interrupt source

Specifies rising edge of INT2 pin input.

Interrupt input pin

INT2 (1)

KR4 - KR7 (4)

KR2 - KR7 (6)

KR0 - KR7 (8)

Specifies falling edge of any of KR

inputs.

131

PD75517(A)

(3) Configuration of INT2 and KR0 to KR7 (key interrupt) pins

Fig. 5-4 shows the configuration of INT2 and KR0 to KR7. IRQ2 is set in one of the following modes with

the edge detection mode register (IM2):

(a) Detection of a rising edge of the INT2 pin input

When a rising edge of the INT2 pin input is detected, IRQ2 is set.

(b) Detection of a falling edge of one of the KR0 to KR7 pin inputs (key interrupt)

One of the pins KR0 to KR7 is selected to be used for interrupt input with the edge detection mode

is set.

Example If KR4 to KR7 are selected, and the level of signals input to KR4 to KR7 are all high, a falling

edge appearing on any one of these inputs sets IRQ2.

Caution If any of the selected pins has been input a low-level signal, a falling edge appearing on

another pin does not set IRQ2.

Fig. 5-3 (c) shows the format of IM2. A 4-bit memory manipulation instruction is used to set IM2. A

RESET signal occurrence clears all bits to 0, and a rising edge is selected for INT2.

133

PD75517(A)

(4) Interrupt priority specification register (IPS)

The interrupt priority specification register specifies an interrupt with a higher priority from multiple

interrupts using the low-order three bits.

Bit 3, interrupt master enable flag (IME), specifies whether to disable all interrupts.

The IPS is set with a 4-bit memory manipulation instruction. Bit 3 is set with an EI instruction and reset

with a DI instruction.

When a RESET signal is generated, all bits are cleared.

Caution Disable interrupts before setting the IPS.

Fig. 5-5 Interrupt Priority Specification Register

IPS0

IPS1

IPS2

IPS3

IPS

Symbol

FB2H

Address

High-order interrupt selection

All low-order interrupt

VRQ1 (INTBT/INT4)

VRQ2 (INT0)

VRQ3 (INT1)

VRQ4 (INTCSI0)

VRQ5 (INTT0)

VRQ6 (INTTPG)

This status is disabled.

The listed vectored
interrupts are treated
as high-order interrupts.

Interrupt master enable flag (IME)

All interrupts are disabled and no vectored interrupt is
activated.

The interrupt enable flag corresponding to an interrupt
request flag controls interrupt enabling/disabling.

134

PD75517(A)

5.3 INTERRUPT SEQUENCE

The following flowchart shows the sequence of an interrupt.

Notes 1. IST1 and IST0: Interrupt status flags (Bits 3 and 2 of PSW. See Table 5-3.)

2. Each vector table must store the start address of the interrupt service program and the set values

of the MBE and RBE at the start of an interrupt.

YES

Interrupt (INT

×××

) occurrence

IRQ

×××

setting

×××

set?

Hold until IE

×××

is set.

Corresponding VRQn occurrence

IME = 1

Hold until IME
is set.

Is VRQn

high-order

interrupt?

Note 1

IST1, 0 = 00 or 01

Note 1

IST1, 0 = 00

If two or more VRQns occur,
select one VRQn according to
Table 5-1.

Selected
VRQn

Remaining
VRQns

Save contents of PC and PSW in stack memory and set data

Note 2

in vector table

corresponding to activated VRQn to PC, RBE, and MBE.

Change contents of IST0 and IST1 from 00 to 01
or from 01 to 10.

Reset accepted IRQ

×××

See Section 5.5 when those interrupt
sources share vector address.

Jump to the start address for processing the interrupt service program.

Hold until process-
ing being executed
is finished

135

PD75517(A)

5.4 MULTIPLE INTERRUPT PROCESSING CONTROL

The

PD75517(A) can handle multiple interrupts by either of the following methods.

(1) Multiple interrupt processing by a high-order interrupt

In this method, the

PD75517(A) selects an interrupt source among multiple interrupt sources, enabling

double interrupt processing.

That is, the high-order interrupt specified by the interrupt priority specification register (IPS) is enabled

when the processing status is 0 or 1. Other interrupts (interrupts lower than the specified high-order

interrupt) are enabled only when the status is 0. (See Fig. 5-6 and Table 5-3.)

Fig. 5-6 Multiple Interrupt Processing by a High-Order Interrupt

Table 5-3 Interrupt Processing Statuses of IST1 and IST0

IST1 and IST0 are saved with the remaining PSW in the stack memory when an interrupt is accepted and

the status of IST0 and IST1 changes to a status one level higher. When an RETI instruction is executed,

the former values of IST0 and IST1 are returned.

Normal
processing
(Status 0)

Low- or high-order
interrupt processing
(Status 1)

High-order
interrupt
processing
(Status 2)

Interrupt is disabled.

IPS setting

Interrupt is enabled.

Low- or high-order
interrupt occurrence

High-order
interrupt
occurrence

IST1

IST0

CPU operation

Interrupts that can be accepted

IST0

IST1

Is processing the normal

program.

Is processing a low- or high-

order interrupt.

Is processing a high-order

interrupt.

All

Only high-order interrupts

Processing

status

After acceptance

Status 0

Status 1

Status 2

This status is disabled.

136

PD75517(A)

(2) Multiple interrupt processing by changing the interrupt status flags

As shown in Table 5-3, changing the interrupt status flags with the program causes multiple interrupts

to be enabled. That is, when the interrupt processing program changes both IST1 and IST0 to 0 (status

0), multiple interrupt processing is enabled.

This method is used when two or more interrupts are to be enabled at a time or when the processing of

three or more interrupts is to be performed.

When changing IST1 and IST0, interrupts must be disabled beforehand with a DI instruction.

Fig. 5-7 Multiple Interrupt Processing by Changing the Interrupt Status Flags

Low- or high-order
interrupt occurrence

Normal processing
(status 0)

Single interrupt

Multiple interrupts

Interrupt is enabled.

Low- or high-order
interrupt occurrence

Interrupt is
disabled.

Modification
of IST

Interrupt is
enabled.

Status 1

Status 0

Status 1

IPS setting

Interrupt is disabled.

137

PD75517(A)

5.5 VECTOR ADDRESS SHARE INTERRUPT PROCESSING

Since interrupt sources INTBT and INT4 share the vector table, the following two cases must be considered.

(1) When using only one interrupt source

The interrupt enable flag corresponding to the required interrupt source of the two interrupt sources

sharing the vector table is set and the other interrupt enable flag is cleared. In this case, the enabled

interrupt source (IE

×××

= 1) issues an interrupt request. If this request is accepted, the corresponding

interrupt request flag is reset.

(2) When using both interrupt sources

The interrupt enable flags corresponding to the two interrupt sources are set. In this case, the logical and

of the interrupt request flags corresponding to the two interrupt sources is an interrupt request.

Even if one or both of the interrupt request flags are set and an interrupt request is accepted, neither of

the interrupt request flags is reset.

The interrupt service routine must therefore judge which interrupt source caused an interrupt. This is done

by executing a DI instruction at the beginning of the interrupt service routine and checking the interrupt

request flags with an SKTCLR instruction.

Remark When only one interrupt is enabled, its interrupt source can be clearly identified, so that the

interrupt request flag is reset by hardware at acceptance of the interrupt. However, when both

interrupts are enabled, the interrupt source cannot be identified, so that the interrupt request

flags cannot be reset by hardware. For this reason, the interrupt request flags are checked by

software to determine the interrupt source.

138

PD75517(A)

6. STANDBY FUNCTION

To reduce the power consumption when the program is in the wait state, the

PD75517(A) has two standby

modes, STOP and HALT.

6.1 SETTING OF STANDBY MODES AND OPERATION STATUSES

Table 6-1 Operation Statuses in the Standby Mode

Instruction for setting

System clock at setting

HALT instruction

This mode can be set when either the main

system clock or the subsystem clock is

used.

Only CPU clock

is stopped (with oscilla-

tion continued).

Operation is continued (to set IRQBT at

reference time intervals).

Operation is possible only when the main

system clock operates or external SCK0 is

used.

Operation is possible only when the main

system clock operates.

Operation is possible only when the main

system clock operates.

Operation is possible.

Operation is possible only when the main

system clock operates.

Operation is possible only when the main

system clock operates.

STOP mode

HALT mode

STOP instruction

This mode can be set only when the main

system clock is used.

Only the main system clock is stopped.

Operation is stopped.

Operation is possible only when external

SCK0 input is selected for the serial clock.

Operation is possible only when external

SCK1 input is selected for the serial clock.

Operation is possible only when TI0 pin

input is selected for the count clock.

Operation is possible only when f

is se-

lected for the count clock.

Operation is stopped.

Clock generator

Basic interval

timer

Serial interface

(Channel 0)

Serial interface

(Channel 1)

Timer/event

counter

Watch timer

A/D converter

Timer/pulse

generator

External interrupt

CPU

INT0 is disabled. INT1, INT2, and INT4 are enabled.

Operation is stopped.

Interrupt request signals transmitted from hardware, which are enabled by interrupt

enable flags, or RESET input.

Opera-

tion

status

Release signal

139

PD75517(A)

A STOP instruction is used to set the STOP mode, and a HALT instruction is used to set the HALT mode.

(A STOP instruction sets bit 3 of PCC, and a HALT instruction sets bit 2 of PCC.) A STOP instruction or HALT

instruction must always be followed by an NOP instruction.

When changing a CPU operation clock pulse with the low-order two bits of PCC, a time lag may occur from

the time when PCC is rewritten to the time when the CPU clock signal is changed. When changing an operation

clock pulse before the standby mode or a CPU clock signal after the standby mode is released, it is necessary

to rewrite PCC and set the standby mode after the number of machine cycles required to change the CPU clock

pulse elapses.

In a standby mode, the contents of all registers and data memory that are stopped during the standby mode,

including general registers, flags, mode registers, and output latches, are retained.

Cautions 1. When the STOP mode is set, the X1 input is internally connected to GND (GND potential) to

suppress leakage at the crystal oscillator circuitry. This means that the STOP mode cannot

be used with a system that uses an external clock.

2. Reset all the interrupt request flags before setting the standby mode.

If an interrupt source whose interrupt request flag and interrupt enable flag are both set exists,

the initiated standby mode is released immediately after it is set (see Fig. 5-1). When the STOP

mode is set, however, the

PD75517(A) enters the HALT mode immediately after the STOP

instruction is executed, then returns to the operation mode after the wait time specified by

the BTM register has elapsed.

6.2 RELEASE OF THE STANDBY MODES

The STOP mode and HALT mode are released by a RESET input or the generation of an interrupt request

signal that is enabled with the interrupt enable flag. Fig. 6-1 shows how the STOP and HALT modes are

released.

140

PD75517(A)

STOP instruction

Standby
release
signal

Clock

Operating
mode

STOP mode

HALT mode

Operating
mode

No oscillation

Oscillation

Wait

(Time set by BTM)

HALT instruction

Standby
release
signal

Clock

HALT mode

Operating mode

Oscillation

Operating mode

Fig. 6-1 Standby Mode Release Operation

(a) Release of the STOP mode by RESET input

Note A wait time is 31.3 ms when operating at 4.19 MHz.

(b) Release of the STOP mode by the occurrence of an interrupt

Remark

The dashed line indicates the case where the interrupt request that releases the standby
mode is accepted.

(c) Release of the HALT mode by RESET input

Note A wait time is 31.3 ms when operating at 4.19 MHz.

(d) Release of the HALT mode by the occurrence of an interrupt

Remark

The dashed line indicates the case where the interrupt request that releases the standby

mode is accepted.

HALT instruction

RESET
signal

Clock

Operating
mode

HALT mode

Operating
mode

Oscillation

Wait

approximately
21.8 ms/6.0 MHz

Note

STOP instruction

Wait

approximately
21.8 ms/6.0 MHz

RESET
signal

Clock

Operating
mode

STOP mode

HALT mode

Operating
mode

No oscillation

Oscillation

Note

141

PD75517(A)

The wait times used when the STOP mode is released do not include a time (a in Fig. 6-2) required before

clock generation is started following the release of the STOP mode, regardless of whether the STOP mode

is released by RESET signal input or the generation of an interrupt.

Fig. 6-2 Start of Clock Generation

When the STOP mode is released by the occurrence of an interrupt, a wait time is determined by BTM.

(See Table 6-2.)

Table 6-2 Selection of a Wait Time with BTM

(When f

= 4.19 MHz)

(When f

= 4.19 MHz)

Note This time does not include the time from the release of the STOP mode to the start of oscillation.

6.3 OPERATION AFTER A STANDBY MODE IS RELEASED

(1) If a standby mode is released by a RESET input, normal reset operation is performed.

(2) If a standby mode is released by the occurrence of an interrupt request, the interrupt master enable flag

(IME) determines whether to perform a vectored interrupt when the CPU resumes instruction execution.

(a) When IME = 0

After the standby mode is released, execution of an instruction is restarted immediately after the

instruction which set the standby mode.

The interrupt request flag is held.

(b) When IME = 1

After the standby mode is released, two instructions are executed, then a vectored interrupt is caused.

However, when the standby mode is released by INTW or INT2 (input of a testable signal), no vectored

interrupt is caused and the same processing as (a) above is performed.

STOP mode release

Wave-form
at the X1 pin

GND

BTM3

BTM2

BTM1

BTM0

Other than above

BTM3

BTM2

BTM1

BTM0

Other than above

Wait time

Note

. ( ) indicates the value for f

= 6.0 MH

Approx. 2

(Approx. 175 ms)

Approx. 2

(Approx. 21.8 ms)

Approx. 2

(Approx. 5.46 ms)

Approx. 2

(Approx. 1.37 ms)

Use prohibited

Wait time

Note

. ( ) indicates the value for f

= 4.19 MH

Approx. 2

(Approx. 250 ms)

Approx. 2

(Approx. 31.3 ms)

Approx. 2

(Approx. 7.82 ms)

Approx. 2

(Approx. 1.95 ms)

Use prohibited

142

PD75517(A)

7. RESET FUNCTION

The

PD75517(A) is reset by RESET signal input. When reset, the hardware is initialized as indicated in Table

7-1. Fig. 7-1 shows the timing of reset operation.

Fig. 7-1 Reset Operation by RESET Input

Note A wait time is 31.3 ms when operating at 4.19 MHz.

Table 7-1 Statuses of the Hardware after a Reset (1/2)

Note RESET signal input causes data at addresses 0F8H-0FDH in data memory to be undefined.

RESET input

Operation mode or
standby mode

HALT mode

Operation mode

Internal reset operation

Wait

(approximately 21.8 ms/6.0 MHz)

Note

Program counter (PC)

PSW

Data memory (RAM)

General registers (X, A, H, L, D, E, B, C)

Bank select register (MBS, RBS)

Stack pointer (SP)

Stack bank select register (SBS)

Basic interval

timer

Timer/event

counter

Timer/pulse

generator

Watch timer

Hardware

Low-order 6 bits at address 0000H

in program memory are set in PC

bits 13 to 8, and the data at address

0001H are set in PC bits 7 to 0.

Held

Bit 6 at address 0000H in pro-

gram memory is set in RBE, and

bit 7 is set in MBE.

Held

Note

Held

0, 0

Undefined

FFH

0, 0

Held

Low-order 6 bits at address 0000H

in program memory are set in PC

bits 13 to 8, and the data at address

0001H are set in PC bits 7 to 0.

Undefined

Bit 6 at address 0000H in pro-

gram memory is set in RBE, and

bit 7 is set in MBE.

Undefined

0, 0

Undefined

FFH

0, 0

Held

Carry flag (CY)

Skip flags (SK0 to SK2)

Interrupt status flags (IST0, IST1)

Bank enable flags (MBE, RBE)

Counter (BT)

Mode register (BTM)

Counter (T0)

Modulo register (TMOD0)

Mode register (TM0)

TOE0, TOUT F/F

Modulo registers (MODH, MODL)

Mode register (TPGM)

Mode register (WM)

RESET input during operation

RESET input in a standby mode

143

PD75517(A)

Table 7-1 Statuses of the Hardware after a Reset (2/2)

Hardware

Held

04H (EOC = 1)

Undefined

Held

Reset (0)

0, 0, 0

Off

Clear (0)

Held

Serial bus inter-

face

(Channel 0)

A/D converter

Clock genera-

tor, clock out-

put circuit

Serial interface

(Channel 1)

Interrupt

Digital ports

Undefined

04H (EOC = 1)

Undefined

Reset (0)

0, 0, 0

Off

Clear (0)

Undefined

Shift register 0 (SIO0)

Operation mode register 0 (CSIM0)

SBI control register (SBIC)

Slave address register (SVA)

P01/SCK0 output latch

Mode register (ADM), EOC

SA register

Processor clock control register

(PCC)

System clock control register (SCC)

Clock output mode register (CLOM)

Shift register (SIO1)

Operation mode register 1 (CSIM1)

Serial transfer end flag (EOT)

Interrupt request flag (IRQ

×××

)

Interrupt enable flag (IE

×××

)

Interrupt master enable flag (IME)

INT0, INT1 and INT2 mode regis-

ters (IM0, IM1, IM2)

Output buffer

Output latch

I/O mode registers (PMGA, PMGB,

PMGC)

Pull-up resistor specification regis-

ter (POGA)

Bit sequential buffers (BSB0 to BSB3)

RESET input in a standby mode

RESET input during operation

144

PD75517(A)

8. INSTRUCTION SET

8.1

PD75517(A) INSTRUCTIONS

(1) GETI instruction

The GETI instruction references a two-byte table in the program memory and performs the following

three types of operations. This 1-byte instruction is very useful in reducing the number of program steps.

(a) A subroutine call is made to all the spaces, regarding data in a table as the call address of a call

instruction.

(b) A branch is made to all the spaces, regarding data in a table as the branch address of a branch

instruction.

The tables to be referenced by a GETI instruction are located at addresses 0020H to 007FH in the program

memory. That is, data can be set in up to 48 tables.

When describing a table address as an operand, describe an even address.

Cautions 1. A two-byte instruction which can be referenced by a GETI instruction must be a two-

machine-cycle instruction. (Except for the BRCB and CALLF instructions)

2. When referencing two 1-byte instructions with a GETI instruction, only the combinations

listed in the table below are valid.

3. Branch and subroutine instructions can be referenced by the GETI instruction only when

their destination addresses are in the 16K-byte space (0000H to 3FFFH). A branch or

subroutine instruction to an address from 4000H to 5F7FH cannot be referenced by the GETI

instruction.

Instruction of second byte

Instruction of first byte

MOV A,@HL

MOV @HL,A

XCH A,@HL

MOV A,@DE

XCH A,@DE

MOV A,@DL

XCH A,@DL

INCS

DECS

INCS

DECS

INCS

DECS

INCS

DECS

INCS

DECS

INCS

DECS

145

PD75517(A)

Addressing

fmem.bit

pmem.@L

@H+mem.bit

Specifiable bit address range

FB0H to FBFH

FF0H to FFFH

FC0H to FFFH

All the bits of the memory bank specified by

MB (bit-manipulatable)

Specifiable peripheral hardware

RBE/MBE/IST1, IST0/EOT

×××

/IRQ

×××

Port 0 to Port 15

BSB0

Ports 0, 4, 8, and 12

All the peripheral hardware (bit-

manipulatable)

Since PC does not increment the counter during execution of a GETI instruction, control returns to the

address next to the GETI instruction after the execution of the GETI instruction.

When the instruction before a GETI instruction has the skip function, the GETI instruction is skipped in

the same way as for other 1-byte instructions. When the instruction referenced by a GETI instruction has

the skip function, the instructions after the GETI instruction are skipped.

When a string effect instruction is referenced by a GETI instruction, the following results are obtained.

When the group of the string effect instruction before the GETI instruction is the same as that of the

instruction referenced by the GETI instruction, the effect of the string effect instruction is canceled and

the referenced instruction is not skipped.

When the group of the instruction after the GETI instruction is the same as that of the instruction

referenced by the GETI instruction, the effect of the string effect instruction caused by the referenced

instruction is valid and the instructions after the referenced instruction are skipped.

(2) Bit manipulation instructions

The

PD75517(A) is provided with bit test instructions, bit transfer instructions, and bit Boolean instruc-

tions (AND, OR, and XOR) in addition to normal bit manipulation instructions (set instruction and clear

instruction). Manipulation bits are specified by bit manipulation addressing.

There are three types of bit manipulation addressing. The table below lists the bits manipulated by each

addressing.

×××

: 0, 1, 2, 4, BT, T0, W, CSI0, TPG

MB = MBE·MBS

146

PD75517(A)

(3) String effect instructions

When two or more instructions in the same group (group A or B) are placed at two or more string effect

addresses, the instruction placed at the start point of the string effect instructions is executed. After that,

each string effect instruction is executed as an NOP instruction.

Group A: MOV A, #n4, MOV XA, #n8

Group B: MOV HL, #n8

(4) Base conversion instruction

The

PD75517(A) is provided with base conversion instructions to convert the results of addition and

subtraction of 4-bit data to a base-n number.

When a base-m number is to be obtained, the following combinations of instructions are used for

adjustment.

· For addition

ADDS A, #16-m

ADDC A, @HL

ADDS A, #m

· For subtraction SUBC A, @HL

ADDS A, #m

The result of adding or subtracting the contents of the accumulator and the memory addressed by the

HL register pair is converted to a base-m number. However, for subtraction, the complement of the

obtained result (base-m number) is set in the accumulator. An overflow or underflow is reflected in the

carry flag. (In the above combinations, the skip function of the ADDS A, #m instruction is prohibited.)

147

PD75517(A)

8.2 INSTRUCTION SET AND ITS OPERATION

(1) Representation format and description method of operands

An operand is described in the operand field of each instruction according to the description method

corresponding to the operand representation format of the instruction. Refer to the assembler specifi-

cations for details. When two or more elements are described in the description method field, select one

of them. Uppercase letters, a plus sign (+), and a minus sign (-) are keywords, so they can be used without

alteration.

Specify an appropriate numeric value or label for immediate data.

Note Only even addresses can be specified for 8-bit data processing.

Representa-

tion format

reg

reg1

rp1

rp2

rp'

rp'1

rpa

rpa1

mem

bit

fmem

pmem

addr

addr1

caddr

faddr

taddr

PORTn

×××

RBn

MBn

X, A, B, C, D, E, H, L

X, B, C, D, E, H, L

XA, BC, DE, HL

BC, DE, HL

BC, DE

XA, BC, DE, HL, XA', BC', DE', HL'

BC, DE, HL, XA', BC', DE', HL'

HL, HL+, HL-, DE, DL

DE, DL

4-bit immediate data or label

8-bit immediate data or label

Note

2-bit immediate data or label

FB0H-FBFH/FF0H-FFFH immediate data or label

FC0H-FFFH immediate data or label

0000H-3F7FH immediate data or label

0000H-5F7FH immediate data or label

12-bit immediate data or label

11-bit immediate data or label

20H-7FH immediate data (bit 0 = 0) or label

PORT0-PORT15

IEBT, IECSI0, IET0, IE0, IE1, IE2, IE4, IEW, IETPG

RB0-RB3

MB0, MB1, MB2, MB3, MB15

Description method

148

PD75517(A)

(2) Legend

A register, 4-bit accumulator

B register, 4-bit accumulator

C register, 4-bit accumulator

D register, 4-bit accumulator

E register, 4-bit accumulator

H register, 4-bit accumulator

L register, 4-bit accumulator

X register, 4-bit accumulator

XA'

Extended register pair (XA')

BC'

Extended register pair (BC')

DE'

Extended register pair (DE')

HL'

Extended register pair (HL')

Program counter

Stack pointer

Carry flag, bit accumulator

PSW

Program status word

MBE

Memory bank enable flag

RBE

PORTn:

Port n (n = 0 to 15)

IME

Interrupt master enable flag

IPS

Interrupt priority specification register

×××

Interrupt enable flag

RBS

MBS

Memory bank select register

PCC

Processor clock control register

Address/bit delimiter

(

××

)

Contents addressed by

××

Hexadecimal data

149

PD75517(A)

(3) Explanation of the symbols in the addressing area field

Remarks 1.

MB indicates an accessible memory bank.

For *2, MB is always 0 irrespective of MBE and MBS.

For *4 and *5, MB is always 15 irrespective of MBE and MBS.

*6 to *11 indicate each addressable area.

(4) Explanation of the machine cycle column

S represents the number of machine cycles required when a skip instruction with the skip function

performs a skip operation. S assumes one of the following values:

· When no skip operation is performed:

S = 0

· When a 1-byte instruction or 2-byte instruction is skipped: S = 1

· When a 3-byte instruction

Note

is skipped:

S = 2

Note 3-byte instruction: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1 instructions

Caution The GETI instruction is skipped in one machine cycle.

One machine cycle is equal to one cycle of the CPU clock, and three types of times are available for selection

according to the PCC setting.

MB = MBE·MBS

(MBS = 0, 1, 2, 3, or 15)

MB = 0

MBE = 0: MB = 0 (00H-7FH)

MB = 15 (80H-FFH)

MBE = 1: MB = MBS (MBS = 0, 1, 2, 3, or 15)

MB = 15, fmem = FB0H-FBFH or

FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 0000H-3F7FH

addr = (Current PC) - 15 to (Current PC) - 1 or

(Current PC) + 2 to (Current PC) + 16

caddr = 0000H-0FFFH (PC

14,13,12

= 000B) or

1000H-1FFFH (PC

14,13,12

= 001B) or

2000H-2FFFH (PC

14,13,12

= 010B) or

3000H-3FFFH (PC

14,13,12

= 011B) or

4000H-4FFFH (PC

14,13,12

= 100B) or

5000H-5F7FH (PC

14,13,12

= 101B)

faddr = 0000H-07FFH

taddr = 0020H-007FH

addr1 = 0000H-5F7FH

*10

*11

Data memory

addressing

Program

memory

addressing

150

PD75517(A)

Note Only lower three bits are valid in the B register.

2 + S

reg1

rp2

(HL)

(HL), then L

L + 1

(HL), then L

L - 1

(rpa1)

(HL)

(mem)

reg

rp'

reg1

rp'1

(HL)

(HL), then L

L + 1

(HL), then L

L - 1

(rpa1)

(HL)

(mem)

reg1

rp'

(PC

14-8

+DE)

ROM

(PC

14-8

+XA)

ROM

2-0

+CDE)

ROM

2-0

+CXA)

ROM

*11

String effect A

String effect B

L = 0

L = FH

L = 0

L = FH

Transfer

instruc-

tion

A,#n4

reg1,#n4

XA,#n8

HL,#n8

rp2,#n8

A,@HL

A,@HL+

A,@HL-

A,@rpa1

XA,@HL

@HL,A

@HL,XA

A,mem

XA,mem

mem,A

mem,XA

A,reg

XA,rp'

reg1,A

rp'1,XA

A,@HL

A,@HL+

A,@HL-

A,@rpa1

XA,@HL

A,mem

XA,mem

A,reg1

XA,rp'

XA,@PCDE

XA,@PCXA

XA, @BCDE

Note

XA, @BCXA

Note

Number

of bytes

Machine

cycle

Operand

Mnemonic

Instruction

Operation

Address-

ing area

Skip

condition

MOV

XCH

MOVT

151

PD75517(A)

Bit

transfer

instruc-

tion

Arithme-

tic/logical

instruc-

tion

MOV1

ADDS

ADDC

SUBS

SUBC

AND

XOR

CY,fmem.bit

CY,pmem.@L

CY,@H+mem.bit

fmem.bit,CY

pmem.@L,CY

@H+mem.bit,CY

A,#n4

XA,#n8

A,@HL

XA,rp'

rp'1,XA

A,@HL

XA,rp'

rp'1,XA

A,@HL

XA,rp'

rp'1,XA

A,@HL

XA,rp'

rp'1,XA

A,#n4

A,@HL

XA,rp'

rp'1,XA

A,#n4

A,@HL

XA,rp'

rp'1,XA

A,#n4

A,@HL

XA,rp'

rp'1,XA

carry

borrow

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

A + n4

XA + n8

A + (HL)

XA + rp'

rp'1

rp'1 + XA

A,CY

A + (HL) + CY

XA,CY

XA + rp' + CY

rp'1,CY

rp'1 + XA + CY

A - (HL)

XA - rp'

rp'1

rp'1 - XA

A,CY

A - (HL) - CY

XA,CY

XA - rp' - CY

rp'1,CY

rp'1 - XA - CY

(HL)

rp'

rp'1

(HL)

rp'

rp'1

(HL)

rp'

rp'1

Number

of bytes

Machine

cycle

Operand

Mnemonic

Instruction

Operation

Address-

ing area

Skip

condition

152

PD75517(A)

RORC

NOT

INCS

DECS

SKE

SET1

CLR1

SKT

NOT1

reg

rp1

@HL

mem

reg

rp'

reg,#n4

@HL,#n4

A,@HL

XA,@HL

A,reg

XA,rp'

reg = 0

rp1 = 00H

(HL) = 0

(mem) = 0

reg = FH

rp' = FFH

reg = n4

(HL) = n4

A = (HL)

XA = (HL)

A = reg

XA = rp'

CY = 1

Accumula-

tor manipu-

lation

instruction

Increment/

decrement

instruction

Compari-

son

instruction

Carry flag

manipula-

tion

instruction

CY, A

n-1

reg

reg + 1

rp1

rp1 + 1

(HL)

(HL) + 1

(mem)

(mem) + 1

reg

reg - 1

rp'

rp' - 1

Skip if reg = n4

Skip if (HL) = n4

Skip if A = (HL)

Skip if XA = (HL)

Skip if A = reg

Skip if XA = rp'

Skip if CY = 1

1 + S

2 + S

1 + S

2 + S

1 + S

2 + S

1 + S

Number

of bytes

Machine

cycle

Operand

Mnemonic

Instruction

Operation

Address-

ing area

Skip

condition

153

PD75517(A)

Note Only lower three bits are valid in the B register.

Memory

bit

manipula-

tion

instruc-

tion

Branch

instruc-

tion

SET1

CLR1

SKT

SKF

SKTCLR

AND1

OR1

XOR1

BRA

BRCB

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

mem.bit

fmem.bit

pmem.@L

@H+mem.bit

fmem.bit

pmem.@L

@H+mem.bit

CY,fmem.bit

CY,pmem.@L

CY,@H+mem.bit

CY,fmem.bit

CY,pmem.@L

CY,@H+mem.bit

CY,fmem.bit

CY,pmem.@L

CY,@H+mem.bit

addr1

$addr

!addr

PCDE

PCXA

BCDE

Note

BCXA

Note

!addr1

!caddr

*11

(mem.bit) = 1

(fmem.bit) = 1

(pmem.@L) = 1

(@H+mem.bit) = 1

(mem.bit) = 0

(fmem.bit) = 0

(pmem.@L) = 0

(@H+mem.bit) = 0

(fmem.bit) = 1

(pmem.@L) = 1

(@H+mem.bit) = 1

2 + S

(The assembler selects an appropri-
ate instruction from the BR !addr, BRA
!addr1, BRCB !caddr, and BR $addr
instructions.)

Number

of bytes

Machine

cycle

Operand

Mnemonic

Instruction

Operation

Address-

ing area

Skip

condition

(mem.bit)

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

(mem.bit)

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

Skip if (mem.bit) = 1

Skip if (fmem.bit) = 1

Skip if (pmem

7-2

3-2

.bit(L

1-0

)) = 1

Skip if (H+mem

3-0

.bit) = 1

Skip if (mem.bit) = 0

Skip if (fmem.bit) = 0

Skip if (pmem

7-2

3-2

.bit(L

1-0

)) = 0

Skip if (H+mem

3-0

.bit) = 0

Skip if (fmem.bit) = 1 and clear

Skip if (pmem

7-2

+ L

3-2

.bit(L

1-0

)) = 1 and clear

Skip if (H+mem

3-0

.bit) = 1 and clear

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

(fmem.bit)

(pmem

7-2

3-2

.bit(L

1-0

))

(H+mem

3-0

.bit)

14-0

addr1

14-0

addr

0, PC

13-0

addr

14-0

14-8

+ DE

14-0

14-8

+ XA

14-0

2-0

+ CDE

14-0

2-0

+ CXA

14-0

addr1

14-0

14,13,12

+ caddr

11-0

154

PD75517(A)

Note MBE = 0, or MBE = 1 and MBS = 15 must be set when an IN/OUT instruction is executed.

Subrou-

tine stack

control

instruction

Interrupt

control

instruction

I/O

instruction

CPU

control

instruction

!addr

!addr1

!faddr

×××

A,PORTn

XA,PORTn

PORTn,A

PORTn,XA

*11

Uncondition-

ally

3 + S

(SP-2)

,MBE,RBE

(SP-6)(SP-3)(SP-4)

11-0

(SP-5)

0,PC

,PC

, PC

0, PC

13-0

addr, SP

SP - 6

(SP-2)

,MBE,RBE

(SP-6)(SP-3)(SP-4)

11-0

(SP-5)

0,PC

,PC

, PC

14-0

addr, SP

SP - 6

(SP-2)

,MBE,RBE

(SP-6)(SP-3)(SP-4)

11-0

(SP-5)

0,PC

,PC

, PC

14-0

0000 + faddr, SP

SP - 6

11-0

(SP)(SP+3)(SP+2)

,PC

(SP+1)

,MBE,RBE

(SP+4)

SP + 6

11-0

(SP)(SP+3)(SP+2)

,PC

(SP+1)

,MBE,RBE

(SP+4)

SP + 6

then skip unconditionally

11-0

(SP)(SP+3)(SP+2)

,PC14,PC13,PC12

(SP+1)

PSW

(SP+4)(SP+5), SP

SP + 6

(SP-1)(SP-2)

rp, SP

SP - 2

(SP-1)

MBS, (SP-2)

RBS, SP

SP - 2

(SP+1)(SP), SP

SP + 2

MBS

(SP+1), RBS

(SP), SP

SP + 2

IME(IPS.3)

×××

IME(IPS.3)

×××

PORTn (n=0-15)

PORTn

,PORTn (n=4,6)

PORTn

A (n=2-7,9-14)

PORTn

,PORTn

XA (n=4,6)

Set HALT Mode (PCC.2

Set STOP Mode (PCC.3

No Operation

CALL

CALLA

CALLF

RET

RETS

RETI

PUSH

POP

Note

OUT

Note

HALT

STOP

NOP

Number

of bytes

Machine

cycle

Operand

Mnemonic

Instruction

Operation

Address-

ing area

Skip

condition

156

PD75517(A)

8.3 INSTRUCTION CODES OF EACH INSTRUCTION

(1) Explanations of the symbols for the instruction codes

Immediate data for n4 or n8

Immediate data for mem

Immediate data for bit

Immediate data for n or IE

×××

Immediate data for taddr

1/2

Immediate data for the relative address distance (2 to 16) for the branch destination address minus

one

Immediate data for the ones complement of the relative address distance (15 to 1) for the branch

destination address

reg-pair

XA'

HL'

DE'

BC'

reg

reg1

rp'

rp'1

addressing

@HL

@HL+

@HL

@DE

@DL

@rpa1

reg-pair

rp2

rp1

×××

IEBT

IEW

IETPG

IET0

IECSI0

IE0

IE2

IE4

IE1

@rpa

reg

158

PD75517(A)

Mnemonic

MOV

XCH

MOVT

MOV1

1 I

1 P

0 Q

1 Q

1 R

Transfer

instruc-

tion

1 R

1 P

0 R

0 P

Bit
transfer
instruction

Instruction code

Instruc-

tion

Operand

A, #n4

reg1, #n4

rp, #n8

A, @rpa

XA, @HL

@HL, A

@HL, XA

A, mem

XA, mem

mem, A

mem, XA

A, reg

XA, rp'

reg1, A

rp'1, XA

A, @rpa

XA, @HL

A, mem

XA, mem

A, reg1

XA, rp'

XA, @PCDE

XA, @PCXA

XA, @BCDE

XA, @BCXA

CY, *1

*1 , CY

159

PD75517(A)

Instruction code

Mnemonic

ADDS

ADDC

SUBS

SUBC

AND

XOR

RORC

NOT

Operand

A, #n4

XA, #n8

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

A, #n4

A, @HL

XA, rp'

rp'1, XA

0 I

Arithme-

tic/logical

instruc-

tion

Accumulator
manipulation
instruction

1 P

0 P

1 P

0 P

1 P

0 P

1 P

0 P

1 I

1 P

0 P

0 I

1 P

0 P

1 I

1 P

0 P

Instruc-

tion

160

PD75517(A)

Instruction code

0 R

1 P

1 R

0 B

Operand

reg

rp1

@HL

mem

reg

rp'

reg, #n4

@HL, #n4

A, @HL

XA, @HL

A, reg

XA, rp'

mem.bit

CY, *1

1 P

0 R

0 I

1 R

1 P

Incre-

ment/

decre-

ment

instruc-

tion

Compari-

son

instruc-

tion

Carry flag

manipu-

lation

instruc-

tion

Memory

bit

manipu-

lation

instruc-

tion

INCS

DECS

SKE

SET1

CLR1

SKT

NOT1

SET1

CLR1

SKT

SKF

SKTCLR

AND1

OR1

XOR1

Mnemonic

Instruc-

tion

161

PD75517(A)

Mnemonic

BRA

BRCB

CALL

CALLA

CALLF

RET

RETS

RETI

PUSH

POP

OUT

HALT

STOP

NOP

SEL

GETI

Operand

!addr

$addr

PCDE

PCXA

BCDE

BCXA

!addr1

!caddr

!addr

!addr1

!faddr

A, PORTn

XA, PORTn

PORTn, A

PORTn, XA

×××

RBn

MBn

taddr

0 A

1 S

1 P

0 T

Branch

instruc-

tion

Subrou-

tine stack

instruc-

tion

I/O

instruc-

tion

Interrupt

control

instruc-

tion

CPU

control

instruc-

tion

Special

instruc-

tion

addr

caddr

addr

addr1

(+16) to (+2)

(-1) to (-15)

faddr

1 N

0 N

1 N

0 N

1 N

0 N

1 N

Instruction code

Instruc-

tion

162

PD75517(A)

9. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Note Calculate rms with [rms] = [peak value]

duty.

OPERATING SUPPLY VOLTAGE

Supply voltage

Ambient temperature

Supply voltage

Ambient temperature

Supply voltage

Ambient temperature

A/D converter

Timer/pulse

generator

Other circuits

Parameter

Symbol

Conditions

Unit

°C

Max.

6.0

+85

6.0

+85

6.0

+85

Min.

2.7

4.5

2.7

Parameter

Supply voltage

Input voltage

Output voltage

High-level output

current

Low-level output

current

Operating

temperature

Storage tempera-

ture

Unit

°C

Rated value

0.3 to +7.0

0.3 to V

+ 0.3

0.3 to V

+ 0.3

0.3 to +13

0.3 to V

+ 0.3

100

40 to +85

65 to +150

Symbol

Note

opt

stg

Built-in pull-up resistor

Open drain

Ports other than ports 4, 5, and 12 to 14

Each pin

Total of all pins

Each pin

Total of all pins of ports 0, 2, 3,

and 4

Total of all pins of ports 5 to 11

Total of all pins of ports 12 to

Ports 4, 5,
and 12 to
14

Peak value

rms

Peak value

rms

Peak value

rms

Peak value

rms

Conditions

163

PD75517(A)

CHARACTERISTICS OF THE MAIN SYSTEM CLOCK OSCILLATOR (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Notes 1.

The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.

The oscillation settling time means the time required for the oscillation to settle after V

applied or after the STOP mode is released.

CHARACTERISTICS OF THE SUBSYSTEM CLOCK OSCILLATOR (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Notes 1.

The oscillator frequency and input frequency indicate only the oscillator characteristics. See the
item of AC characteristics for the instruction execution time.

The oscillation settling time means the time required for the oscillation to settle after V

applied or after the STOP mode is released.

CAPACITANCE (T

= 25

C, V

= 0 V)

Recommended
constant

Ceramic

resonator

Crystal

resonator

External

clock

Oscillator

frequency

)

Note 1

Oscillation

settling

time

Note 2

Oscillator

frequency

)

Note 1

Oscillation
settling

time

Note 2

X1 input

frequency
(f

)

Note 1

X1 input

high/low

level width
(t

, t

)

MHz

6.2

500

1.0

4.19

= oscillation

voltage range

After V

reaches

Min. of the oscilla-

tion voltage range

= 4.5 to 6.0 V

PD74HCU04

Resonator

Parameter

Min.

Typ.

Max.

Unit

Conditions

Recommended
constant

kHz

32.768

1.0

Oscillator

frequency

)

Note 1

Oscillation

settling

time

Note 2

XT1 input

frequency

)

Note 1

XT1 input

high/low

level width

XTH

, t

XTL

)

Crystal

resonator

External

clock

= 4.5 to 6.0 V

100

XT1

XT2

XT1

XT2

Open

Resonator

Parameter

Min.

Typ.

Max.

Unit

Conditions

Input capacitance

Output capacitance

I/O capacitance

f = 1 MHz

0 V for pins other than pins to be

measured

Conditions

Unit

Max.

Typ.

Min.

Symbol

Parameter

164

PD75517(A)

DC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

Symbol

IH1

IH2

IH3

IH4

IL1

IL2

IL3

LIH1

LIH2

LIH3

LIL1

LIL2

LOH1

LOH2

LOL

Min.

0.7V

0.8V

0.7V

0.5

1.0

0.5

Typ.

0.4

Max.

0.3V

0.2V

0.4

2.0

0.4

0.5

0.2V

300

140

Unit

= 4.5 to 6.0 V, I

= 15 mA

Open drain

Pull-up resistor: 1 k

or more

Other than X1, X2, and XT1

X1, X2, and XT1

Ports 4, 5, and 12 to 14

(open drain)

Other than X1, X2, and XT1

X1, X2, and XT1

Other than ports 4, 5, and 12

to 14

Ports 4, 5, and 12 to 14

(open drain)

Parameter

High-level input

voltage

Low-level input

voltage

High-level output

voltage

Low-level output

voltage

High-level input

leakage current

Low-level input

leakage current

High-level output

leakage current

Low-level output

leakage current

Built-in pull-up

resistor

Built-in pull-down

resistor

Ports 0, 1, 2, 3, 6, and

7 (excl. P00)

= 0 V

Ports 4, 5, and 12 to 14

= V

2.0 V

= 2 V

Ports 2, 3, and 9 to 11, P80, and P82

Ports 0, 1, 6, 7, and 15, P81, P83, and RESET

X1, X2, and XT1

Ports 2 to 5 and 9 to 14, P80, and P82

Ports 0, 1, 6, 7, and 15, P81, P83, and RESET

X1, X2, and XT1

= 4.5 to 6.0 V, I

= 1 mA

= 100

Built-in pull-up resistor

Open drain

Ports 4, 5,

and 12 to 14

Conditions

Ports 3, 4,

and 5

= 4.5 to 6.0 V, I

= 1.6 mA

= 400

SB0 and

SB1

= V

= 10 V

= 0 V

= V

= 10 V

= 0 V

= 5.0 V

10 %

= 3.0 V

10 %

= 5.0 V

10 %

= 3.0 V

10 %

Port 9

165

PD75517(A)

Notes 1.

This current excludes the current which flows through the built-in pull-up resistors.

Value when the processor clock control register (PCC) is set to 0011 and the

PD75517(A) is

operated in the high-speed mode

Value when the PCC is set to 0000 and the

PD75517(A) is operated in the low-speed mode

Parameter

Power supply

current

Note 1

Min.

Conditions

Unit

Max.

Typ.

DD1

DD2

DD1

DD2

DD3

DD4

DD5

Symbol

Operation

mode

HALT

mode

Operation

mode

HALT

mode

Operation

mode

HALT

mode

4.5

0.6

700

250

0.55

600

200

0.5

0.3

13.5

1.8

2100

750

1.5

1800

600

120

6.0 MHz

crystal

resonance

C1 = C2
= 22 pF

4.19 MHz

crystal

resonance

C1 = C2
= 22 pF

32.768 kHz
crystal
resonance

XT1 = 0 V
STOP mode

= 5 V

10 %

3 V

10 %

= 25 °C

= 5 V

10 %

Note 2

= 3 V

10 %

Note 3

= 5 V

10 %

= 3 V

10 %

= 5 V

10 %

Note 3

= 3 V

10 %

Note 3

= 5 V

10 %

= 3 V

10 %

= 3 V

10 %

= 3 V

10 %

166

PD75517(A)

AC CHARACTERISTICS (T

= -40 to +85

C, V

= 2.7 to 6.0 V)

(1) Basic operation

Notes 1. The cycle time (minimum instruction

execution time) depends on the con-

nected resonator frequency, the sys-

tem clock control register (SCC), and

the processor clock control register

(PCC). The figure on the next page

shows the cycle time t

characteris-

tics for the supply voltage V

during

main system clock operation.

2. This value becomes 2t

or 128/f

ac-

cording to the setting of the interrupt

mode register (IM0).

Cycle time (minimum

instruction execution

time)

Note 1

TI0 input frequency

TI0 input high/low level

width

Interrupt input high/low

level width

RESET low level width

TIH

TIL

INTH

INTL

RSL

0.67

2.6

114

0.48

1.8

125

275

= 4.5 to 6.0 V

122

Parameter

Typ.

Max.

Unit

Conditions

Symbol

MHz

kHz

Operated by subsystem clock pulse

= 4.5 to 6.0 V

INT0

INT1, INT2, and INT4

KR0 to KR7

Note 2

Operated by main
system clock
pulse

Min.

Guaranteed operating
range

0.5

Supply voltage V

[V]

Cycle time t

[ s]

vs V

(When the main system clock is operating)

167

PD75517(A)

Symbol

KCY1

KL1

KH1

SIK1

KSI1

KSO1

Typ.

Min.

1600

1340

3800

2680

KCY

/2 50

KCY

/2 150

150

400

= 4.5 to 6.0 V

250

1000

= 1 k

= 100 pF

Note

Max.

Conditions

= 4.5 to 6.0 V f

= 4.19 MHz

= 4.5 to 6.0 V f

= 6.0 MHz

= 4.19 MHz

= 6.0 MHz

= 4.5 to 6.0 V

Unit

Parameter

SCK cycle time

SCK high/low level

width

SI setup time

(referred to SCK

)

SI hold time

(referred to SCK

)

SCK

SO output

delay time

Conditions

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

= 4.5 to 6.0 V

Symbol

KCY2

KL2

KH2

SIK2

KSI2

KSO2

Min.

800

3200

400

1600

100

400

Typ.

Max.

300

1000

Unit

(2) Serial transfer

(a) Two-wire and three-wire serial I/O modes (SCK ... Internal clock output):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

(b) Two-wire and three-wire serial I/O modes (SCK ... External clock input):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

Parameter

SCK cycle time

SCK high/low level

width

SI setup time

(referred to SCK

)

SI hold time

(referred to SCK

)

SCK

SO output

delay time

168

PD75517(A)

(c) SBI mode (SCK ... Internal clock output (master)):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

(d) SBI mode (SCK ... External clock input (slave)):

Note R

and C

are the resistance and capacitance of the SO output line load respectively.

SCK cycle time

SCK high/low level

width

SB0/SB1 setup time

(referred to SCK

)

SB0/SB1 hold time

(referred to SCK

)

SCK

SB0/SB1

output delay time

SCK

SB0/SB1

SCK

SB0/SB1 low level

width

SB0/SB1 high level

width

Symbol

Parameter

1600

1340

3800

2680

KCY

/2 - 50

150

KCY

250

1000

Max.

Unit

= 4.5 to 6.0 V f

= 4.19 MHz

= 4.5 to 6.0 V f

= 6.0 MHz

= 4.19 MHz

= 6.0 MHz

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

KCY3

KL3

KH3

SIK3

KSI3

KSO3

KSB

SBK

SBL

SBH

= 4.5 to 6.0 V

Typ.

Conditions

Min.

KCY

/2 - 150

SCK cycle time

SCK high/low level

width

SB0/SB1 setup time

(referred to SCK

)

SB0/SB1 hold time

(referred to SCK

)

SCK

SB0/SB1

output delay time

SCK

SB0/SB1

SCK

SB0/SB1 low level

width

SB0/SB1 high level

width

Symbol

Parameter

800

3200

400

1600

100

KCY

Min.

Typ.

300

1000

Max.

Unit

= 4.5 to 6.0 V

= 1 k

= 100 pF

Note

Conditions

KCY4

KL4

KH4

SIK4

KSI4

KSO4

KSB

SBK

SBL

SBH

= 4.5 to 6.0 V

169

PD75517(A)

(3) A/D converter (T

= -40 to +85

C, V

= 2.7 to 6.0 V, AV

= V

= 0 V)

Notes 1. Absolute accuracy excluding quantization error (

1/2 LSB)

2. 2.5 V

REF

ADM1 is set to 0 or 1 depending on the A/D converter reference voltage (AV

REF

) as follows:

When 0.6 V

REF

0.65 V

, ADM1 can be set to either 0 or 1.

3. Time from the execution of a conversion start instruction till the end of conversion (EOC = 1)

(28.0

s: f

= 6.0 MHz, 40.1

s: f

= 4.19 MHz)

4. Time from the execution of a conversion start instruction till the end of sampling (7.33

s: f

= 6.0 MHz, 10.5

s: f

= 4.19 MHz)

Resolution

Absolute accuracy

Note 1

Conversion time

Note 3

Sampling time

Note 4

Analog input voltage

Analog input imped-

ance

AREF

current

Symbol

Parameter

VSS

Min.

Max.

Unit

CONV

SAMP

IAN

AREF

1000

1.0

bit

LSB

1.5

2.0

168/f

44/f

REF

2.0

Typ.

Conditions

-10

+85°C

-40

Ta < -10°C

2.5 V

REF

Note 2

2.5 V

0.6V

0.65V

(2.7 to 6.0 V)

ADM1 = 0

ADM1 = 1

REF

173

PD75517(A)

DATA HOLD CHARACTERISTICS BY LOW SUPPLY VOLTAGE IN DATA MEMORY STOP MODE

= -40 to +85

Notes 1.

Excluding the current which flows through the built-in pull-up resistors

CPU operation stop time for preventing unstable operation at the beginning of oscillation

This value depends on the settings of the basic interval timer mode register (BTM) shown below.

Data Hold Timing (STOP Mode Release by RESET)

Data Hold Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Conditions

Data hold supply voltage

Data hold supply current

Note 1

Release signal setting time

Oscillation settling

time

Note 2

DDDR

SREL

WAIT

2.0

0.1

Note 3

6.0

DDDR

= 2.0 V

Release by RESET

Release by interrupt request

= 4.19 MHz

(approx. 175 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

= 6.0 MHz

(approx. 175 ms)

(approx. 21.8 ms)

(approx. 5.46 ms)

(approx. 1.37 ms)

Wait time

BTM0

BTM1

BTM2

BTM3

RESET

DDDR

SREL

WAIT

Internal reset operation

HALT mode

Operation
mode

STOP instruction execution

Data hold mode

STOP mode

Standby release signal
(Interrupt request)

DDDR

SREL

WAIT

HALT mode

Operation
mode

STOP instruction execution

Data hold mode

STOP mode

175

PD75517(A)

11. RECOMMENDED SOLDERING CONDITIONS

The following conditions must be met when soldering the

PD75517(A).

Please consult with our sales offices in case other soldering process is used, or in case soldering is done

under different conditions.

Table 11-1 Recommended Soldering Conditions

Table 11-2 Soldering Conditions

Note Exposure limit before soldering after dry-pack package is opened. Storage conditions: 25

C and

relative humidity at 65 % or less.

Caution Do not apply more than a single process at a time, except for "Partial heating method."

For more details, refer to our document "SMT MANUAL" (IEI-1207).

Symbol

WS60-162-1

IR30-162-1

VP15-162-1

Partial heating method

Part number

Package

PD75517GF(A)-

×××

-3B9

80-pin plastic QFP (14 mm

20 mm)

Soldering conditions

Soldering process

Symbol

Wave soldering

Infrared ray reflow

VPS

Partial heating method

WS60-162-1

IR30-162-1

VP15-162-1

Partial heating

method

Temperature in the soldering vessel: 260 °C or less

Soldering time: 10 seconds or less

Number of soldering processes: 1

Exposure limit

Note

: 2 days

(16 hours pre-baking is required at 125 °C afterwards)

Pre-heating temperature: 120 °C max.

(package surface temperature)

Peak package's surface temperature: 230 °C

Reflow time: 30 seconds or below (at 210 °C or more)

Number of reflow processes: 1

Exposure limit

Note

: 2 days

(16 hours pre-baking is required at 125 °C afterwards)

Peak package's surface temperature: 215 °C

Reflow time: 40 seconds or below (at 200 °C or more)

Number of reflow processes: 1

Exposure limit

Note

: 2 days

(16 hours pre-baking is required at 125 °C afterwards)

Terminal temperature: 300 °C or less

Flow time: 3 seconds or less (one side per device)

176

PD75517(A)

APPENDIX A SERIES PRODUCT FUNCTIONS

Notes 1.

No mask option is provided for the

PD75P516 and

PD75P518.

Only in the

PD75P516 and

PD75P518

PD75517

PD75517(A)

24448

PD75516

PD75516(A)

16256

PD75P516

16256 (PROM)

Product

Item

PD75P518

32640 (PROM)

ROM (bytes)

RAM (

4 bits)

General register

Machine

cycle

I/O port

A/D converter

Operating

voltage

Timer/counter

Serial interface

Interrupt

Instruction set

Operating supply

voltage

Package

Main-

system

clock

Subsystem

clock

Total

CMOS

input

CMOS I/O

N-ch

open-

drain I/O

0.95

s/1.91

s/15.3

s (at 4.19 MHz)

Note 1

1024

512

(4 bits

8 or 8 bits

4 banks

0.67

s/1.33

s/2.67

s/10.7

s (at 6.0 MHz)

0.95

s/1.91

s/3.82

s/15.3

s (at 4.19 MHz)

122

s (at 32.768 kHz)

16 (Shared with INT and SIO. Seven lines can be pulled up by software)

28 (LED direct driving and shared with SIO and PPO)

· 16 lines can be pulled up by software.

· Four lines can be pulled down by the mask option.

20 (Eight lines for driving LEDs. Withstand

voltage is 10 V. 20 lines can be pulled up

by the mask option.)

· 8-bit resolution

8 ch (successive approximation)

= 2.7 to 6.0 V

= 3.5 to 6.0 V

4 channels

· Timer/event counter

· Basic interval timer

· Timer/pulse generator (14-bit PWM output possible)

· Clock timer

2 channels

· NEC standard serial bus interface (SBI)/three-wire SIO : One channel

· General synchronous serial interface (three-wire SIO) : One channel

· Vectored interrupt: Seven sources (External: 3, Internal: 4)

· Test input:

Two sources

(External: 1, Internal: 1)

· Clock test flag is provided.

· Parallel-edge-sensitive flag for key scan input is provided.

· Set/reset/test/Boolean operation for bit data

· 4-bit data transfer, arithmetic/logical, addition/subtraction and comparison

· 8-bit data transfer, arithmetic/logical, addition/subtraction and comparison

2.7 to 6.0 V

4.75 to 5.5 V

· 80-pin plastic QFP

· 80-pin ceramic LCC with a window

Note 2

20 (Eight lines for driving LEDs. Withstand

voltage is 9 V. 20 lines can be pulled up by

the mask option.)

177

PD75517(A)

APPENDIX B DEVELOPMENT TOOLS

The following development tools are provided for developing a system which employs the

PD75517(A).

Language processor

PROM programming tools

RA75X relocatable assembler

MS-DOS

Ver. 3.10

Ver. 3.30C

PC DOS

(Ver. 3.1)

Distribution media

3.5-inch 2HD

5-inch 2HD

5-inch 2HC

Part number

S5A13RA75X

S5A10RA75X

S7B10RA75X

Hardware

Software

The PG-1500 PROM programmer is used together with an accessory board

and optional program adapter. It allows the user to program a single chip

microcomputer containing PROM from a standalone terminal or a host

machine. The PG-1500 can be used to program typical 256K-bit to 1M-bit

PROMs.

The PA-75P516GF is a dedicated PROM programmer for the

PD75P516GF

and

PD75P518GF. This programmer is connected to the PG-1500.

The PA-75P516K is a dedicated PROM programmer for the

PD75P516K and

PD75P518K. This programmer is connected to the PG-1500.

This program enables the host machine to control the PG-1500 through the

serial and parallel interfaces.

MS-DOS

Ver. 3.10

Ver. 3.30C

PC DOS

(Ver. 3.1)

PG-1500

PA-75P516GF

PA-75P516K

PG-1500 controller

Distribution media

3.5-inch 2HD

5-inch 2HD

5-inch 2HC

Part number

S5A13PG1500

S5A10PG1500

S7B10PG1500

Host machine

PC-9800 series

IBM PC series

Host machine

PC-9800 series

IBM PC series

178

PD75517(A)

Debugging tools

Note

Maintenance service only

Remark

NEC is not responsible for the operation of any software unless it runs on a host machine with

the operating system listed above.

Hardware

Software

The IE-75000-R is an in-circuit emulator available for the 75X series. This

emulator is used together with the emulation probe to develop application

systems of the

PD75517(A). For efficient debugging, the emulator is

connected to the host machine and PROM programmer.

The IE-75000-R-EM is an emulation board for the IE-75000-R and IE-75001-

R. The IE-75000-R contains the emulation board. The emulation board is

used together with the IE-75000-R or IE-75001-R to evaluate the

PD75517(A).

The IE-75001-R is an in-circuit emulator available for the 75X series. This

emulator is used together with the IE-75000-R-EM

emulation board (option)

and emulation probe to develop application systems of the

PD75517(A).

For efficient debugging, the emulator is connected to the host machine and

PROM programmer.

The EP-75516GF-R is an emulation probe for the

PD755

××

series. The

emulation probe is connected to the IE-75000-R or IE-75001-R when it is used.

A 80-pin conversion socket, the EV-9200G-80, attached to the probe facili-

tates the connection of the prove with the user system.

This program enables the host machine to control the IE-75000-R or IE-

75001-R through the RS-232-C interface.

IE-75000-R

Note

IE-75000-R-EM

IE-75001-R

EP-75516GF-R

EV-9200G-80

IE control program

Distribution media

3.5-inch 2HD

5-inch 2HD

5-inch 2HC

Part number

S5A13IE75X

S5A10IE75X

S7B10IE75X

MS-DOS

Ver. 3.10

Ver. 3.30C

PC DOS

(Ver. 3.1)

Host machine

PC-9800 series

IBM PC series

PD75517(A)

MS-DOS

is a trademark of Microsoft Corporation.

PC DOS

is a trademark of IBM Corporation.

[MEMO]

No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of such
device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual
property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor
control systems and life support systems. If customers intend to use NEC devices for above applications or they
intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales
people in advance.
Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment, Ma-

chine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.

M4 92.6

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75517A

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75517A