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Электронный компонент: UPD75P0076

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1995
DATA SHEET
The
PD75P0076 replaces the
PD750068's internal mask ROM with a one-time PROM and features expanded ROM
capacity.
Because the
PD75P0076 supports programming by users, it is suitable for use in prototype testing for system
development using the
PD750064, 750066, and 750068 products, and for use in small-lot production.
Detailed information about function is provided in the following user's manual.
Be sure to read it before designing:
PD750068 User's Manual: U10670E
FEATURES
Compatible with
PD750068
Memory capacity:
PROM : 16384 x 8 bits
RAM
: 512 x 4 bits
Can operate with same power supply voltage as the mask ROM version
PD750068
V
DD
= 1.8 to 5.5 V
On-chip A/D converter capable of low-voltage operation (AV
REF
= 1.8 to 5.5 V)
8-bit resolution x 8 channels
Small shrink SOP package
ORDERING INFORMATION
Part Number
Package
PD75P0076CU
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
PD75P0076GT
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
Caution On-chip pull-up resistors by mask option cannot be provided.
Document No. U10232EJ1V0DS00 (1st edition)
Date Published December 1996 N
Printed in Japan
PD75P0076
MOS INTEGRATED CIRCUIT
4-BIT SINGLE-CHIP MICROCONTROLLER
The information in this document is subject to change without notice.
The mark
shows major revised points.
PD75P0076
2
Functional Outline
Parameter
Function
Instruction execution time
0.95, 1.91, 3.81, 15.3
s (@ 4.19 MHz with main system clock)
0.67, 1.33, 2.67, 10.7
s (@ 6.0 MHz with main system clock)
122
s (@ 32.768 kHz with subsystem clock)
On-chip memory
PROM
16384 x 8 bits
RAM
512 x 4 bits
General-purpose register
4-bit operation: 8 x 4 banks
8-bit operation: 4 x 4 banks
Input/
CMOS input
12
Connections of on-chip pull-up resistors can be specified by software: 7
output
Also used for analog input pins: 4
port
CMOS input/output
12
Connections of on-chip pull-up resistors can be specified by software: 12
Also used for analog input pins: 4
N-ch open-drain
8
13-V withstand voltage
input/output pins
Total
32
Timer
4 channels
8-bit timer/event counter: 2 channels (can be used as the 16-bit timer/event counter)
8-bit basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Serial interface
3-wire serial I/O mode MSB or LSB can be selected for transferring first bit
2-wire serial I/O mode
A/D converter
8-bit resolution x 8 channels (1.8 V
AV
REF
V
DD
)
Bit sequential buffer
16 bits
Clock output (PCL)
, 1.05 MHz, 262 kHz, 65.5 kHz (@ 4.19 MHz with main system clock)
, 1.5 MHz, 375 kHz, 93.8 kHz (@ 6.0 MHz with main system clock)
Buzzer output (BUZ)
2, 4, 32 kHz (@ 4.19 MHz with main system clock or
@ 32.768 kHz with subsystem clock)
2.93, 5.86, 46.9 kHz (@ 6.0 MHz with main system clock)
Vectored interrupts
External: 3, Internal: 4
Test input
External: 1, Internal: 1
System clock oscillator
Ceramic or crystal oscillator for main system clock oscillation
Crystal oscillator for subsystem clock oscillation
Standby function
STOP/HALT mode
Operating ambient temperature
T
A
= 40 to +85 C
Power supply voltage
V
DD
= 1.8 to 5.5 V
Package
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD75P0076
3
CONTENTS
1. PIN CONFIGURATION (Top View) ...................................................................................................
4
2. BLOCK DIAGRAM ............................................................................................................................
5
3. PIN FUNCTIONS ...............................................................................................................................
6
3.1
Port Pins ...................................................................................................................................................
6
3.2
Non-port Pins ...........................................................................................................................................
7
3.3
Equivalent Circuits for Pins ....................................................................................................................
9
3.4
Handling of Unused Pins ......................................................................................................................... 12
4. SWITCHING BETWEEN Mk I AND Mk II MODES ............................................................................ 13
4.1
Difference betweens Mk I Mode and Mk II Mode .................................................................................... 13
4.2
Setting of Stack Bank Selection (SBS) Register .................................................................................... 14
5. DIFFERENCES BETWEEN
PD75P0076 AND
PD750064, 750066 AND 750068 ........................ 15
6. MEMORY CONFIGURATION ............................................................................................................ 16
7. INSTRUCTION SET ........................................................................................................................... 18
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .................................................... 29
8.1
Operation Modes for Program Memory Write/Verify ............................................................................. 29
8.2
Steps in Program Memory Write Operation ............................................................................................ 30
8.3
Steps in Program Memory Read Operation ............................................................................................ 31
8.4
One-time PROM Screening ..................................................................................................................... 32
9. ELECTRICAL SPECIFICATIONS ...................................................................................................... 33
10. CHARACTERISTICS CURVES (REFERENCE VALUES) ................................................................ 49
11. PACKAGE DRAWINGS .................................................................................................................... 51
12. RECOMMENDED SOLDERING CONDITIONS ................................................................................. 53
APPENDIX A DIFFERENCES AMONG
PD75068, 750068 AND 75P0076 ......................................... 54
APPENDIX B DEVELOPMENT TOOLS ................................................................................................. 55
APPENDIX C RELATED DOCUMENTS ................................................................................................. 58
PD75P0076
4
1. PIN CONFIGURATION (Top View)
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
PD75P0076CU
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
PD75P0076GT
Pin Identification
AN0 to AN7
: Analog Input 0 to 7
P110 to P113 : Port 11
AV
REF
: Analog Reference
PCL
: Programmable Clock
AV
SS
: Analog Ground
PTO0, PTO1 : Programmable Timer Output 0, 1
BUZ
: Buzzer Clock
RESET
: Reset Input
D0 to D7
: Data Bus 0 to 7
SB0, SB1
: Serial Data Bus 0, 1
INT0, INT1, INT4 : External Vectored Interrupt 0, 1, 4
SCK
: Serial Clock
INT2
: External Test Input 2
SI
: Serial Input
KR0 to KR3
: Key Return
SO
: Serial Output
MD0 to MD3
: Mode Selection 0 to 3
TI0, TI1
: Timer Input 0, 1
P00 to P03
: Port 0
V
DD
: Positive Power Supply
P10 to P13
: Port 1
V
PP
: Programmable Power Supply
P20 to P23
: Port 2
V
SS
: Ground
P30 to P33
: Port 3
X1, X2
: Main System Clock Oscillation 1, 2
P40 to P43
: Port 4
XT1, XT2
: Subsystem Clock Oscillation 1, 2
P50 to P53
: Port 5
P60 to P63
: Port 6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
XT1
XT2
RESET
X1
X2
P33/MD3
P32/MD2
P31/MD1
P30/MD0
AV
SS
P63/KR3/AN7
P62/KR2/AN6
P61/KR1/AN5
P60/KR0/AN4
P113/AN3
P112/AN2
P111/AN1
P110/AN0
AV
REF
V
PP
V
DD
V
SS
P40/D0
P41/D1
P42/D2
P43/D3
P50/D4
P51/D5
P52/D6
P53/D7
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0
P11/INT1
P12/TI1/INT2
P13/TI0
P20/PTO0
P21/PTO1
P22/PCL
P23/BUZ
In normal operation mode, make sure to connect V
PP
directly to V
DD
.
PD75P0076
5
2. BLOCK DIAGRAM
BASIC INTERVAL
TIMER/WATCHDOG
TIMER
WATCH TIMER
8-BIT
TIMER/
EVENT
COUNTER#0
8-BIT
TIMER/
EVENT
COUNTER#1
CASCADED
16-BIT
TIMER/
EVENT
COUNTER
CLOCKED SERIAL
INTERFACE
INTERRUPT
CONTROL
A/D CONVERTER
INTBT
INTW
INTT0
INTW
INTT1
TOUT0
INTCSI
BUZ/P23
TI0/P13
PTO0/P20
TI1/P12/INT2
PTO1/P21
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT0/P10
INT1/P11
INT4/P00
INT2/P12/TI1
KR0/P60 to
KR3/P63
AN0/P110 to
AN3/P113
AN4/P60 to
AN7/P63
AV
REF
AV
SS
CY
SP (8)
SBS
BANK
PROGRAM COUNTER
PROGRAM
MEMORY
(PROM)
16384 x 8 BITS
DECODE
AND
CONTROL
GENERAL REG.
DATA MEMORY
(RAM)
512 x 4BITS
PORT0
PORT1
PORT2
PORT3
PORT4
PORT5
PORT6
PORT11
BIT SEQ. BUFFER (16)
P00 to P03
4
4
4
4
4
4
P10 to P13
P20 to P23
P30/MD0 to
P33/MD3
P40/D0 to
P43/D3
P50/D4 to
P53/D7
P60 to P63
P110 to P113
fx/2
N
CPU CLOCK
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
SUB
MAIN
SYSTEM CLOCK
GENERATOR
STAND BY
CONTROL
PCL/P22
XT1 XT2 X1 X2
V
PP
V
DD
V
SS
RESET
ALU
4
4
4
4
4
PD75P0076
6
3. PIN FUNCTIONS
3.1 Port Pins
Pin name
I/O
Alternate function
Function
8-bit
After
I/O circuit
accessible
reset
type
Note 1
P00
I
INT4
This is a 4-bit input port (PORT0).
Not
Input
<B>
For P01 to P03, on-chip pull-up resistors are
available
P01
I/O
SCK
software-specifiable in 3-bit units.
<F>-A
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
I
INT0
This is a 4-bit input port (PORT1).
Not
Input
<B>-C
Connections of on-chip pull-up resistors are
available
P11
INT1
software-specifiable in 4-bit units. P10/INT0
can select a noise elimination circuit.
P12
TI1/INT2
P13
TI0
P20
I/O
PTO0
This is a 4-bit I/O port (PORT2).
Not
Input
E-B
Connections of on-chip pull-up resistors are
available
P21
PTO1
software-specifiable in 4-bit units.
P22
PCL
P23
BUZ
P30
I/O
MD0
This is a programmable 4-bit I/O port (PORT3).
Not
Input
E-B
Input and output can be specified in single-bit
available
P31
MD1
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
P32
MD2
P33
MD3
P40
Note 2
I/O
D0
This is an N-ch open-drain 4-bit I/O port
Available
High
(PORT4). In the open-drain mode, withstands
impedance
M-E
P41
Note 2
D1
up to 13 V. Also used as data I/O pin
(lower 4 bits) for program memory (PROM)
P42
Note 2
D2
write/verify.
P43
Note 2
D3
P50
Note 2
I/O
D4
This is an N-ch open-drain 4-bit I/O port
High
(PORT5). In the open-drain mode, withstands
impedance
M-E
P51
Note 2
D5
up to 13 V. Also used as data I/O pin
(upper 4 bits) for program memory (PROM)
P52
Note 2
D6
write/verify.
P53
Note 2
D7
P60
I/O
KR0/AN4
This is a programmable 4-bit I/O port (PORT6).
Not
Input
<Y>-D
Input and output can be specified in single-bit
available
P61
KR1/AN5
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
P62
KR2/AN6
P63
KR3/AN7
P110
I
AN0
This is a 4-bit input port (PORT11).
Not
Input
Y-A
available
P111
AN1
P112
AN2
P113
AN3
Notes 1. Circuit types enclosed in brackets indicate Schmitt triggered inputs.
2. Low-level input current leakage increases when input instructions or bit manipulation instructions are executed.
PD75P0076
7
3.2 Non-port Pins (1/2)
Pin name
I/O
Alternate function
Function
After
Circuit
reset
type
Note
TI0
I
P13
Inputs external event pulses to the timer/event
Input
<B>-C
TI1
P12/INT2
counter.
PTO0
O
P20
Timer/event counter output
Input
E-B
PTO1
P21
PCL
P22
Clock output
BUZ
P23
Optional frequency output (for buzzer output or
system clock trimming)
SCK
I/O
P01
Serial clock I/O
Input
<F>-A
SO/SB0
P02
Serial data output
<F>-B
Serial data bus I/O
SI/SB1
P03
Serial data input
<M>-C
Serial data bus I/O
INT4
I
P00
Edge detection vectored interrupt input (both rising
<B>
edge and falling edge detection)
INT0
I
P10
Edge detection vectored
Noise eliminator/
Input
<B>-C
interrupt input (detection
asynchronous selection
INT1
P11
edge can be selected).
Asynchronous
INT0/P10 can select a noise
eliminator.
INT2
P12/TI1
Rising edge detection
Asynchronous
testable input
KR0 to KR3
I
P60/AN4 to
Falling edge detection testable input
Input
<Y>-D
P63/AN7
AN0 to AN3
I
P110 to P113
Analog signal input
Input
Y-A
AN4 to AN7
P60/KR0 to
<Y>-D
P63/KR3
AV
REF
--
--
A/D converter reference voltage
--
Z-N
AV
SS
--
--
A/D converter reference GND potential
--
Z-N
X1
I
--
Crystal/ceramic connection pin for the main system
--
--
X2
--
clock oscillator. When inputting the external clock,
input the external clock to pin X1, and the inverted
phase of the external clock to pin X2.
XT1
I
--
Crystal connection pin for the subsystem clock
--
--
XT2
--
oscillator. When the external clock is used, input the
external clock to pin XT1, and the inverted phase of
the external clock to pin XT2. Pin XT1 can be used
as a 1-bit input (test) pin.
RESET
I
--
System reset input (low-level active)
--
<B>
Note
Circuit types enclosed in brackets indicate Schmitt triggered inputs.
PD75P0076
8
3.2 Non-port Pins (2/2)
Pin name
I/O
Alternate function
Function
After
Circuit
reset
type
MD0 to MD3
I
P30 to 33
Mode selection for program memory (PROM)
Input
E-B
write/verify.
D0 to D3
I/O
P40 to 43
Data bus pin for program memory (PROM) write/verify.
Input
M-E
D4 to D7
P50 to 53
V
PP
Note
--
--
Programmable voltage supply in program memory
--
--
(PROM) write/verify mode.
In normal operation mode, connect directly to V
DD
.
Apply +12.5 V in PROM write/verify mode.
V
DD
--
--
Positive power supply
--
--
V
SS
--
--
Ground
--
--
Note
During normal operation, the V
PP
pin will not operate normally unless connected to V
DD
pin.
PD75P0076
9
3.3 Equivalent Circuits for Pins
The equivalent circuits for the
PD75P0076's pin are shown in schematic diagrams below.
IN
V
DD
P-ch
N-ch
V
DD
P-ch
N-ch
OUT
Data
Output
disable
IN
V
DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type A
V
DD
P-ch
P.U.R.
enable
P.U.R.
P.U.R. : Pull-Up Resistor
IN
V
DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type B
CMOS standard input buffer
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
Schmitt trigger input with hysteresis characteristics.
TYPE A
TYPE D
(1/3)
TYPE E-B
TYPE B
TYPE B-C
TYPE F-A
Schmitt trigger input with hysteresis characteristics.
PD75P0076
10
Output
disable
(P)
Output
disable
Data
Output
disable
(N)
P.U.R.
enable
P-ch
P.U.R.
IN/OUT
P-ch
N-ch
V
DD
V
DD
P.U.R. : Pull-Up Resistor
TYPE F-B
TYPE Y
IN
P-ch
N-ch
V
DD
V
DD
AV
SS
AV
SS
Input
enable
Reference voltage
(from the voltage tap of
the serial resistor string)
TYPE Y-A
Input butfer
Type A
Type Y
IN
TYPE M-C
Input
instruction
(+13 V withstand
voltage)
P-ch
P.U.R.
Note
V
DD
P.U.R. : Pull-Up Resistor
TYPE M-E*
IN instruction
Sampling C
Output
disable
Data
N-ch
IN/OUT
Note This is a pull-up resistor which only
operates when an input instruction
is executed (when the pin is low
a current flows from V
DD
to the pin).
Output
disable
Data
P.U.R.
enable
P-ch
P.U.R.
IN/OUT
N-ch
V
DD
+
(2/3)
Voltage
control
circuit
(+13 V withstand
voltage)
PD75P0076
11
TYPE Z-N
P.U.R.
enable
P.U.R.
V
DD
P-ch
IN/OUT
P.U.R.: Pull-Up Resistor
TYPE Y-D
Data
Output
disable
Type Y
Type D
Type B
ADEN
Reference
voltage
AV
REF
N-ch
AV
SS
(3/3)
PD75P0076
12
3.4 Handling of Unused Pins
Pin
Recommended connection
P00/INT4
Connect to V
SS
or V
DD
P01/SCK
Independently connect to V
SS
or V
DD
through
P02/SO/SB0
resistor
P03/SI/SB1
Connected to V
SS
P10/INT0, P11/INT1
Connect to V
SS
or V
DD
P12/TI1/INT2
P13/TI0
P20/PTO0
Input mode
: independently connected to V
SS
P21/PTO1
or V
DD
through resistor
P22/PCL
Output mode : open
P23/BUZ
P30/MD0 to P33/MD3
P40/D0 to P43/D3
Connected to V
SS
P50/D4 to P53/D7
P60/KR0/AN4 to P63/KR3/AN7
Input mode
: independently connected to V
SS
or V
DD
through resistor
Output mode : open
P110/AN0 to P113/AN3
Connected to V
SS
or V
DD
XT1
Note
Connect to V
SS
or V
DD
XT2
Note
Open
V
PP
Make sure to connect directly to V
DD
AV
REF
Connect to V
SS
AV
SS
Note
When the subsystem clock is not used, set SOS.0 = 1 (on-chip feedback resistor is not used).
PD75P0076
13
4. SWITCHING BETWEEN Mk I AND Mk II MODES
Setting a stack bank selection (SBS) register for the
PD75P0076 enables the program memory to be switched between
the Mk I mode and the Mk II mode. This capability enables the evaluation of the
PD750064, 750066, and 750068 using
the
PD75P0076.
When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of
PD750064, 750066, and 750068)
When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of
PD750064, 750066, and 750068)
4.1 Differences between Mk I Mode and Mk II Mode
Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the
PD75P0076.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC
13 to 0
Program memory (bytes)
16384
Data memory (bits)
512 x 4
Stack
Stack bank
Selectable from memory banks 0 and 1
Stack bytes
2 bytes
3 bytes
Instruction
BRA !addr1
Not provided
Provided
CALLA !addr1
Instruction
CALL !addr
3 machine cycles
4 machine cycles
execution time CALLF !faddr
2 machine cycles
3 machine cycles
Supported mask ROM versions and
Mk I mode of
PD750064, 750066,
Mk II mode of
PD750064, 750066,
mode
and 750068
and 750068
Caution
The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore, when
a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine cycle.
Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
PD75P0076
14
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the format
for doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100xB
Note
at the beginning of the program. When using the Mk II mode,
be sure to initialize it to 000xB
Note
.
Note Set the desired value for x.
Figure 4-1. Format of Stack Bank Selection Register
Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode. When
using instructions for the Mk II mode, set SBS3 to "0" to enter the Mk II mode before using the
instructions.
2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
SBS3
SBS2
SBS1
SBS0
F84H
Address
3
2
1
0
SBS
0
0
1
1
0
1
0
1
Symbol
Stack area specification
Memory bank 0
Memory bank 1
0
Be sure to enter "0" for bit 2.
0
1
Mk II mode
Mk I mode
Mode selection specification
Setting prohibited
PD75P0076
15
5. DIFFERENCES BETWEEN
PD75P0076 AND
PD750064, 750066 AND 750068
The
PD75P0076 replaces the internal mask ROM in the
PD750064, 750066, and 750068 with a one-time PROM and
features expanded ROM capacity. The
PD75P0076's Mk I mode supports the Mk I mode in the
PD750064, 750066,
and 750068 and the
PD75P0076's Mk II mode supports the Mk II mode in the
PD750064, 750066, and 750068.
Table 5-1 lists differences among the
PD75P0076 and the
PD750064, 750066, 750068. Be sure to check the
differences between corresponding versions beforehand, especially when a PROM version is used for debugging or
prototype testing of application systems and later the corresponding mask ROM version is used for full-scale production.
For further description of CPU functions and internal hardware, see the
PD750064 and 750068 Preliminary Product
Information (U10165E).
Table 5-1. Differences between
PD75P0076 and
PD750064, 750066, 750068
Item
PD750064
PD750066
PD750068
PD75P0076
Program counter
12-bit
13-bit
14-bit
Program memory (bytes)
Mask ROM
Mask ROM
Mask ROM
One-time PROM
4096
6144
8192
16384
Data memory (x 4 bits)
512
Mask options
Pull-up resistor for
Yes (on-chip specifiable)
No (off chip)
ports 4 and 5
Wait time when
Yes (2
17
/f
X
, 2
15
/f
X
selectable)
Note
No (fixed at 2
15
/f
X
)
Note
RESET
Feedback resistor of
Yes (Use/not use selectable)
No (Use)
subsystem clock
Pin configuration
Pins 6 to 9
P33 to P30
P33/MD3 to P30/MD0
Pin 20
IC
V
PP
Pins 34 to 37
P53 to P50
P53/D7 to P53/D4
Pins 38 to 41
P43 to P40
P43/D3 to P40/D0
Other
Noise resistance and noise radiation may differ due to different circuit complexities
and mask layouts.
Note
2
17
/f
X
is 21.8 ms in 6.0 MHz operation and 31.3 ms in 4.19 MHz operation.
2
15
/f
X
is 5.46 ms in 6.0 MHz operation and 7.81 ms in 4.19 MHz operation.
Caution
Noise resistance and noise radiation are different in PROM version and mask ROM versions. If using
a mask ROM version instead of the PROM version for processes between prototype development and
full production, be sure to fully evaluate the CS of the mask ROM version (not ES).
PD75P0076
16
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
Note
Can be used only in Mk II mode.
Remark
For instructions other than those noted above, the "BR PCDE" and "BR PCXA" instructions can be used to
branch to addresses with changes in the PC's lower 8 bits only.
MBE
MBE
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
RBE
RBE
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
INT1 start address (upper 6 bits)
INT1 start address (lower 8 bits)
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
INTT1 start address (upper 6 bits)
INTT1 start address (lower 8 bits)
Reference table for GETI instruction
0000H
0002H
0004H
0006H
0008H
000AH
000CH
0020H
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
CALLF
!faddr instruction
entry address
Branch address for
the following instructions
CALL !addr instruction
subroutine
entry address
BR $addr instruction
relative branch address
(15 to 1,
+2 to +16)
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
Note
Note
7
6
0
BR BCDE
BR BCXA
BR !addr
BRA !addr1
CALLA !addr1
Branch destination
address specified by
GETI instruction,
subroutine entry
address
PD75P0076
17
Figure 6-2. Data Memory Map
Note Either memory bank 0 or 1 can be selected as the stack area.
(32 x 4)
256 x 4
(224 x 4)
256 x 4
128 x 4
0
1
15
000H
01FH
020H
0FFH
100H
1FFH
F80H
FFFH
General
register
area
Data area
static RAM
(512 x 4)
Stack area
Note
Peripheral hardware area
Data memory
Memory bank
Unimplemented
PD75P0076
18
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's
operand representations (for further description, see the RA75X Assembler Package User's ManualLanguage (EEU-
1363)). When there are several codes, select and use just one. Uppercase letters, and + and symbols are key words
that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for further description,
see the
PD750068 User's Manual (U10670E)). Labels that can be entered for fmem and pmem are restricted.
Representation
Coding format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
rp'1
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label
Note
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
0000H to 3FFFH immediate data or label
addr1
000H to 3FFFH immediate data or label (in Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0 to PORT6, PORT11
IEXXX
IEBT, IECSI, IET0, IET1, IE0 to IE2, IE4, IEW
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
Note
When processing 8-bit data, only even addresses can be specified.
PD75P0076
19
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA'
: Expansion register pair (XA')
BC'
: Expansion register pair (BC')
DE'
: Expansion register pair (DE')
HL'
: Expansion register pair (HL')
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 6, 11)
IME
: Interrupt master enable flag
IPS
: Interrupt priority select register
IExxx
: Interrupt enable flag
RBS
: Register bank select register
MBS
: Memory bank select register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(xx)
: Contents of address xx
xxH
: Hexadecimal data
PD75P0076
20
(3) Description of symbols used in addressing area
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MB = MBS
MBS = 0, 1, 15
MB = MBE MBS
MBS = 0, 1, 15
*1
MB = 0
*2
MBE = 1 :
MBE = 0 :
*3
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
addr = 0000H to 3FFFH
*4
*5
*6
addr, addr1 =
*7
(Current PC) 15 to (Current PC) 1
(Current PC) +2 to (Current PC) +16
*8
caddr = 0000H to 0FFFH (PC
13
,
12
= 00B) or
1000H to 1FFFH (PC
13
,
12
= 01B) or
2000H to 2FFFH (PC
13
,
12
= 10B) or
3000H to 3FFFH (PC
13
,
12
= 11B)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
addr1 = 0000H to 3FFFH (Mk II mode only)
*9
*10
*11
Program memory
addressing
Data memory
addressing
PD75P0076
21
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as
shown below.
No skip .......................................................................... S = 0
Skipped instruction is 1-byte or 2-byte instruction ......... S = 1
Skipped instruction is 3-byte instruction
Note
................... S = 2
Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1
Caution
The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= t
CY
) of the CPU clock
. Use the PCC setting to select among four cycle times.
PD75P0076
22
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Transfer
MOV
A, #n4
1
1
A
n4
String-effect A
reg1, #n4
2
2
reg1
n4
XA, #n8
2
2
XA
n8
String-effect A
HL, #n8
2
2
HL
n8
String-effect B
rp2, #n8
2
2
rp2
n8
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2 + S
A
(HL), then L
L + 1
*1
L = 0
A, @HL
1
2 + S
A
(HL), then L
L 1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
@HL, A
1
1
(HL)
A
*1
@HL, XA
2
2
(HL)
XA
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
mem, A
2
2
(mem)
A
*3
mem, XA
2
2
(mem)
XA
*3
A, reg1
2
2
A
reg1
XA, rp'
2
2
XA
rp'
reg1, A
2
2
reg1
A
rp'1, XA
2
2
rp'1
XA
XCH
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2 + S
A
(HL), then L
L + 1
*1
L = 0
A, @HL
1
2 + S
A
(HL), then L
L 1
*1
L = FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
A, reg1
1
1
A
reg1
XA, rp'
2
2
XA
rp'
Table
MOVT
XA, @PCDE
1
3
XA
(PC
13-8
+ DE)
ROM
reference
XA, @PCXA
1
3
XA
(PC
13-8
+ XA)
ROM
XA, @BCDE
1
3
XA
(BCDE)
ROM
Note
*11
XA, @BCXA
1
3
XA
(BCXA)
ROM
Note
*11
Note
As for the B register, only the lower 2 bits are valid.
PD75P0076
23
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Bit transfer
MOV1
CY, fmem.bit
2
2
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
*5
CY, @H + mem.bit
2
2
CY
(H + mem
3-0
.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)
CY
*4
pmem.@L, CY
2
2
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
CY
*5
@H + mem.bit, CY
2
2
(H + mem
3-0
.bit)
CY
*1
Operation
ADDS
A, #n4
1
1 + S
A
A + n4
carry
XA, #n8
2
2 + S
XA
XA + n8
carry
A, @HL
1
1 + S
A
A + (HL)
*1
carry
XA, rp'
2
2 + S
XA
XA + rp'
carry
rp'1, XA
2
2 + S
rp'1
rp'1 + XA
carry
ADDC
A, @HL
1
1
A, CY
A + (HL) + CY
*1
XA, rp'
2
2
XA, CY
XA + rp' + CY
rp'1, XA
2
2
rp'1, CY
rp'1 + XA + CY
SUBS
A, @HL
1
1 + S
A
A (HL)
*1
borrow
XA, rp'
2
2 + S
XA
XA rp'
borrow
rp'1, XA
2
2 + S
rp'1
rp'1 XA
borrow
SUBC
A, @HL
1
1
A, CY
A (HL) CY
*1
XA, rp'
2
2
XA, CY
XA rp' CY
rp'1, XA
2
2
rp'1, CY
rp'1 XA CY
AND
A, #n4
2
2
A
A
^
n4
A, @HL
1
1
A
A
^
(HL)
*1
XA, rp'
2
2
XA
XA
^
rp'
rp'1, XA
2
2
rp'1
rp'1
^
XA
OR
A, #n4
2
2
A
Avn4
A, @HL
1
1
A
Av(HL)
*1
XA, rp'
2
2
XA
XAvrp'
rp'1, XA
2
2
rp'1
rp'1vXA
XOR
A, #n4
2
2
A
Avn4
A, @HL
1
1
A
Av(HL)
*1
XA, rp'
2
2
XA
XAvrp'
rp'1, XA
2
2
rp'1
rp'1vXA
PD75P0076
24
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Accumulator
RORC
A
1
1
CY
A
0
, A
3
CY, A
n-1
A
n
manipulate
NOT
A
2
2
A
A
Increment/
INCS
reg
1
1 + S
reg
reg + 1
reg = 0
decrement
rp1
1
1 + S
rp1
rp1 + 1
rp1 = 00H
@HL
2
2 + S
(HL)
(HL) + 1
*1
(HL) = 0
mem
2
2 + S
(mem)
(mem) + 1
*3
(mem) = 0
DECS
reg
1
1 + S
reg
reg 1
reg = FH
rp'
2
2 + S
rp'
rp' 1
rp' = FFH
Compare
SKE
reg, #n4
2
2 + S
Skip if reg = n4
reg = n4
@HL, #n4
2
2 + S
Skip if (HL) = n4
*1
(HL) = n4
A, @HL
1
1 + S
Skip if A = (HL)
*1
A = (HL)
XA, @HL
2
2 + S
Skip if XA = (HL)
*1
XA = (HL)
A, reg
2
2 + S
Skip if A = reg
A = reg
XA, rp'
2
2 + S
Skip if XA = rp'
XA = rp'
Carry flag
SET1
CY
1
1
CY
1
manipulate
CLR1
CY
1
1
CY
0
SKT
CY
1
1 + S
Skip if CY = 1
CY = 1
NOT1
CY
1
1
CY
CY
PD75P0076
25
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Memory bit
SET1
mem.bit
2
2
(mem.bit)
1
*3
manipulate
fmem.bit
2
2
(fmem.bit)
1
*4
pmem.@L
2
2
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
1
*5
@H + mem.bit
2
2
(H + mem
3-0
.bit)
1
*1
CLR1
mem.bit
2
2
(mem.bit)
0
*3
fmem.bit
2
2
(fmem.bit)
0
*4
pmem.@L
2
2
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
0
*5
@H + mem.bit
2
2
(H + mem
3-0
.bit)
0
*1
SKT
mem.bit
2
2 + S
Skip if(mem.bit) = 1
*3
(mem.bit) = 1
fmem.bit
2
2 + S
Skip if(fmem.bit) = 1
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if(pmem
7-2
+ L
3-2
.bit(L
1-0
)) = 1
*5
(pmem.@L) = 1
@H + mem.bit
2
2 + S
Skip if(H + mem
3-0
.bit) = 1
*1
(@H+mem.bit) = 1
SKF
mem.bit
2
2 + S
Skip if(mem.bit) = 0
*3
(mem.bit) = 0
fmem.bit
2
2 + S
Skip if(fmem.bit) = 0
*4
(fmem.bit) = 0
pmem.@L
2
2 + S
Skip if(pmem
7-2
+ L
3-2
.bit(L
1-0
)) = 0
*5
(pmem.@L) = 0
@H + mem.bit
2
2 + S
Skip if(H + mem
3-0
.bit) = 0
*1
(@H+mem.bit) = 0
SKTCLR
fmem.bit
2
2 + S
Skip if(fmem.bit) = 1 and clear
*4
(fmem.bit) = 1
pmem.@L
2
2 + S
Skip if(pmem
7-2
+ L
3-2
.bit(L
1-0
)) = 1 and clear
*5
(pmem.@L) = 1
@H + mem.bit
2
2 + S
Skip if(H + mem
3-0
.bit) = 1 and clear
*1
(@H+mem.bit) = 1
AND1
CY, fmem.bit
2
2
CY
CY
^
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
^
(pmem
7-2
+ L
3-2
.bit(L
1-0
))
*5
CY, @H + mem.bit 2
2
CY
CY
^
(H + mem
3-0
.bit)
*1
OR1
CY, fmem.bit
2
2
CY
CYv(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CYv(pmem
7-2
+ L
3-2
.bit(L
1-0
))
*5
CY, @H + mem.bit 2
2
CY
CYv(H + mem
3-0
.bit)
*1
XOR1
CY, fmem.bit
2
2
CY
CYv(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CYv(pmem
7-2
+ L
3-2
.bit(L
1-0
))
*5
CY, @H + mem.bit 2
2
CY
CYv(H + mem
3-0
.bit)
*1
PD75P0076
26
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Branch
BR
Note 1
addr
--
--
PC
13-0
addr
*6
Assembler selects the most
appropriate instruction among
the following:
BR !addr
BRCB !caddr
BR $addr
addr1
--
--
PC
13-0
addr1
*11
Assembler selects the most
appropriate instruction among
the following:
BRA !addr1
BR !addr
BRCB !caddr
BR $addr1
!addr
3
3
PC
13-0
addr
*6
$addr
1
2
PC
13-0
addr
*7
$addr1
1
2
PC
13-0
addr1
PCDE
2
3
PC
13-0
PC
13-8
+ DE
PCXA
2
3
PC
13-0
PC
13-8
+ XA
BCDE
2
3
PC
13-0
BCDE
Note 2
*6
BCXA
2
3
PC
13-0
BCXA
Note 2
*6
BRA
Note 1
!addr1
3
3
PC
13-0
addr1
*11
BRCB
!caddr
2
2
PC
13-0
PC
13, 12
+ caddr
11-0
*8
Notes 1. Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
2. As for the B register, only the lower 2 bits are valid.
PD75P0076
27
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Subroutine
CALLA
Note
!addr1
3
3
(SP 6)(SP 3)(SP 4)
PC
11-0
*11
stack control
(SP 5)
0, 0, PC
13,12
(SP 2)
X, X, MBE, RBE
PC
13-0
addr1, SP
SP 6
CALL
Note
!addr
3
3
(SP 4)(SP 1)(SP 2)
PC
11-0
*6
(SP 3)
MBE, RBE, PC
13, 12
PC
13-0
addr, SP
SP 4
4
(SP 6)(SP 3)(SP 4)
PC
11-0
(SP 5)
0, 0, PC
13, 12
(SP 2)
X, X, MBE, RBE
PC
13-0
addr, SP
SP 6
CALLF
Note
!faddr
2
2
(SP 4)(SP 1)(SP 2)
PC
11-0
*9
(SP 3)
MBE, RBE, PC
13, 12
PC
13-0
000 + faddr, SP
SP 4
3
(SP 6)(SP 3)(SP 4)
PC
11-0
(SP 5)
0, 0, PC
13, 12
(SP 2)
X, X, MBE, RBE
PC
13-0
000 + faddr, SP
SP 6
RET
Note
1
3
MBE, RBE, PC
13, 12
(SP + 1)
PC
11-0
(SP)(SP + 3)(SP + 2)
SP
SP + 4
X, X, MBE, RBE
(SP + 4)
PC
11-0
(SP)(SP + 3)(SP + 2)
0, 0, PC
13, 12
(SP + 1)
SP
SP + 6
RETS
Note
1
3 + S
MBE, RBE, PC
13, 12
(SP + 1)
Unconditional
PC
11-0
(SP)(SP + 3)(SP + 2)
SP
SP + 4
then skip unconditionally
X, X, MBE, RBE
(SP + 4)
PC
11-0
(SP)(SP + 3)(SP + 2)
0, 0, PC
13, 12
(SP + 1)
SP
SP + 6
then skip unconditionally
RETI
1
3
MBE, RBE, PC
13, 12
(SP + 1)
PC
11-0
(SP)(SP + 3)(SP + 2)
PSW
(SP + 4)(SP + 5), SP
SP + 6
0, 0, PC
13, 12
SP + 1
PC
11-0
(SP)(SP + 3)(SP + 2)
PSW
(SP + 4)(SP + 5), SP
SP + 6
Note
Double boxes indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
PD75P0076
28
Group
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
bytes
cycle
area
condition
Subroutine
PUSH
rp
1
1
(SP 1)(SP 2)
rp, SP
SP 2
stack control
BS
2
2
(SP 1)
MBS, (SP 2)
RBS, SP
SP 2
POP
rp
1
1
rp
(SP + 1)(SP), SP
SP + 2
BS
2
2
MBS
(SP + 1), RBS
(SP), SP
SP + 2
Interrupt
EI
2
2
IME(IPS.3)
1
control
IEXXX
2
2
IEXXX
1
DI
2
2
IME(IPS.3)
0
IEXXX
2
2
IEXXX
0
I/O
IN
Note 1
A, PORTn
2
2
A
PORTn
(n = 0 to 6, 11)
XA, PORTn
2
2
XA
PORTn
+ 1
, PORTn (n = 4)
OUT
Note 1
PORTn, A
2
2
PORTn
A
(n = 2 to 6)
PORTn, XA
2
2
PORTn
+ 1
, PORTn
XA (n = 4)
CPU control
HALT
2
2
Set HALT Mode (PCC.2
1)
STOP
2
2
Set STOP Mode (PCC.3
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
n (n = 0 to 3)
MBn
2
2
MBS
n (n = 0, 1, 15)
GETI
Note 2, 3
taddr
1
3
When using TBR instruction
*10
PC
13-0
(taddr)
5-0
+ (taddr + 1)
When using TCALL instruction
(SP 4)(SP 1)(SP 2)
PC
11-0
(SP 3)
MBE, RBE, PC
13, 12
PC
13-0
(taddr)
5-0
+ (taddr + 1)
SP
SP 4
When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr + 1) instructions
instruction
1
3
When using TBR instruction
*10
PC
13-0
(taddr)
5-0
+ (taddr + 1)
4
When using TCALL instruction
(SP 6)(SP 3)(SP 4)
PC
11-0
(SP 5)
0, 0, PC
13, 12
(SP 2)
X, X, MBE, RBE
PC
13-0
(taddr)
5-0
+ (taddr + 1)
SP
SP 6
3
When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr + 1) instructions
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.
2. TBR and TCALL instructions are assembler pseudo-instructions for the GETI instruction's table definitions.
3. Double box indicates support for the Mk II mode only. Other areas indicate support for the Mk I mode only.
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
PD75P0076
29
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory in the
PD75P0076 is a 16384 x 8-bit electronic write-enabled one-time PROM. The pins listed
in the table below are used for this PROM's write/verify operations. Clock input from the X1 pins is used instead of address
input as a method for updating addresses.
Pin name
Function
V
PP
Pin (usually V
DD
) where programming voltage is applied during
program memory write/verify
X1, X2
Clock input pin for address updating during program memory
write/verify. Input the X1 pin's inverted signal to the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/verify
D0/P40 to D3/P43 (lower 4)
8-bit data I/O pin for program memory write/verify
D4/P50 to D7/P53 (upper 4)
V
DD
Pin where power supply voltage is applied. Power voltage
range for normal operation is 1.8 to 5.5 V. Apply 6 V for program
memory write/verify.
Caution
Pins not used for program memory write/verify should be handled as follows.
All unused pins except XT2 ...... Connect to Vss via a pull-down resistor
XT2 pin ........................................ Leave open
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the
PD75P0076's V
DD
pin and +12.5 V is applied to its V
PP
pin, program memory write/verify
modes are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3
as shown below.
Operation mode specification
Operation mode
V
PP
V
DD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
PD75P0076
30
8.2 Steps in Program Memory Write Operation
High-speed program memory write can be executed via the following steps.
(1)
Pull down unused pins to V
SS
via resistors. Set the X1 pin to low.
(2)
Apply +5 V to the V
DD
and V
PP
pins.
(3)
Wait 10
s.
(4)
Zero-clear mode for program memory addresses.
(5)
Apply +6 V to V
DD
and +12.5 V to V
PP
.
(6)
Write data using 1-ms write mode.
(7)
Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) to (7).
(8)
X [= number of write operations from steps (6) to (7)] x 1 ms additional write
(9)
4 pulse inputs to the X1 pin updates (increments +1) the program memory address.
(10) Repeat steps (6) to (9) until the last address is completed.
(11) Zero-clear mode for program memory addresses.
(12) Apply +5 V to the V
DD
and V
PP
pins.
(13) Power supply OFF
The following diagram illustrates steps (2) to (9).
V
PP
V
DD
V
DD
+ 1
V
DD
V
PP
V
DD
X1
D0/P40-D3/P43
D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
X repetitions
Write
Verify
Additional
write
Address
increment
Data input
Data output
Data input
PD75P0076
31
8.3 Steps in Program Memory Read Operation
The
PD75P0076 can read out the program memory contents via the following steps.
(1)
Pull down unused pins to V
SS
via resistors. Set the X1 pin to low.
(2)
Apply +5 V to the V
DD
and V
PP
pins.
(3)
Wait 10
s.
(4)
Zero-clear mode for program memory addresses.
(5)
Apply +6 V to V
DD
and +12.5 V to V
PP
.
(6)
Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a time based
on a cycle of four pulse inputs.
(7)
Zero-clear mode for program memory addresses.
(8)
Apply +5 V to the V
DD
and V
PP
pins.
(9)
Power supply OFF
The following diagram illustrates steps (2) to (7).
V
PP
V
DD
V
DD
+ 1
V
DD
V
PP
V
DD
X1
D0/P40-D3/P43
D4/P50-D7/P53
Data output
Data output
MD0/P30
MD2/P32
MD3/P33
MD1/P31
"L"
PD75P0076
32
8.4 One-Time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
the screening process, that is, after the required data is written to the PROM and the PROM is stored under the high-
temperature conditions shown below, the PROM should be verified.
Storage temperature
Storage time
125 C
24 hours
PD75P0076
33
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25C)
Parameter
Symbol
Test Conditions
Rating
Unit
Power supply voltage
V
DD
0.3 to +7.0
V
PROM power supply
V
PP
0.3 to +13.5
V
voltage
Input voltage
V
I1
Except ports 4, 5
0.3 to V
DD
+0.3
V
V
I2
Ports 4, 5 (N-ch open drain)
0.3 to +14
V
Output voltage
V
O
0.3 to V
DD
+0.3
V
Output current high
I
OH
Per pin
10
mA
Total of all pins
30
mA
Output current low
I
OL
Per pin
30
mA
Total of all pins
220
mA
Operating ambient
T
A
40 to +85
C
temperature
Storage temperature
T
stg
65 to +150
C
Caution If any of the parameters exceeds the absolute maximum ratings, even momentarily, the reliability of the
product may be impaired. The absolute maximum ratings are values that may physically damage the
products. Be sure to use the products within the ratings.
CAPACITANCE (T
A
= 25C,V
DD
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f = 1 MHz
15
pF
Output capacitance
C
OUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
C
IO
15
pF
PD75P0076
34
MAIN SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended constant
Parameter
Test conditions
MIN.
TYP.
MAX.
Unit
Ceramic
Oscillation
1.0
6.0
Note 2
MHz
resonator
frequency (fx)
Note 1
Oscillation
After V
DD
reaches oscil-
4
ms
stabilization time
Note 3
lation voltage range MIN.
Crystal
Oscillation
1.0
6.0
Note 2
MHz
resonator
frequency (fx)
Note 1
Oscillation
V
DD
= 4.5 to 5.5 V
10
ms
stabilization time
Note 3
30
External
X1 input
1.0
6.0
Note 2
MHz
clock
frequency (fx)
Note 1
X1 input
83.3
500
ns
high-/low-level width
(t
XH
, t
XL
)
Notes 1. The oscillation frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to AC Characteristics.
2. When the power supply voltage is 1.8 V
V
DD
< 2.7 V and the oscillation frequency is 4.19 MHz < fx
6.0 MHz,
setting the processor clock control register (PCC) to 0011 results in 1 machine cycle being less than the required
0.95
s. Therefore, set PCC to a value other than 0011.
3. The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
or releasing the STOP
mode.
Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as V
SS
.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
X1
X2
X2
X1
C1
C2
X2
X1
C1
C2
PD75P0076
35
XT1
XT2
SUBSYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended constant
Parameter
Test conditions
MIN.
TYP.
MAX.
Unit
Crystal
Oscillation
32
32.768
35
kHz
resonator
frequency (f
XT
)
Note 1
Oscillation
V
DD
= 4.5 to 5.5 V
1.0
2
s
stabilization time
Note 2
10
External
XT1 input frequency
32
100
kHz
clock
(f
XT
)
Note 1
XT1 input high-/low-level
5
15
s
width (t
XTH
, t
XTL
)
Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
.
Caution
When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should
be carried out as follows to avoid an adverse effect from wiring capacitance.
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as V
SS
.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
The subsystem clock oscillator is designed as a low amplification circuit to provide low consumption
current, causing misoperation by noise more frequently than the main system clock oscillation
circuit. Special care should therefore be taken for wiring method when the subsystem clock is used.
XT2
XT1
C4
C3
R
PD75P0076
36
RECOMMENDED OSCILLATION CIRCUIT CONSTANTS
CERAMIC RESONATOR (T
A
= 20 to +80 C)
Frequency
Oscillation Circuit
Oscillation Voltage
Manufacturer
Product Name
(MHz)
Constants (pF)
Range (V
DD
)
Remarks
C1
C2
MIN.
MAX.
Murata Mfg.
CSB1000J
Note
1.0
100
100
2.2
5.5
Rd = 5.6 K
Co., Ltd.
CSA2.00MG040
2.0
100
100
2.0
--
CST2.00MG040
--
--
With on-chip capacitor
CSA4.00MG
4.0
30
30
1.8
--
CST4.00MGW
--
--
With on-chip capacitor
CSA4.19MG
4.19
30
30
--
CST4.19MGW
--
--
With on-chip capacitor
CSA6.00MG
6.0
30
30
2.6
--
CST6.00MGW
--
--
With on-chip capacitor
CSA6.00MGU
30
30
1.8
--
CST6.00MGWU
--
--
With on-chip capacitor
Note
When the CSB1000J (1.0 MHz) manufactured by Murata Mfg. is used as a ceramic resonator, a limiting resistor
(Rd = 5.6 k
) is required (see the figure below). Other recommended resonators do not require such a limiting
resistor.
X2
X1
CSB1000J
C2
C1
Rd
Caution
The oscillation circuit constants and oscillation voltage range only indicate the conditions under which
the circuit can oscillate stably, and do not guarantee the oscillation frequency accuracy. If oscillation
frequency accuracy is required in the actual circuit, it is necessary to adjust oscillation frequencies in
the actual circuit, and you should consult directly with the manufacturer of the resonator used.
PD75P0076
37
DC CHARACTERISTICS (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Output current low
I
OL
Per pin
15
mA
Total of all pins
150
mA
Input voltage high
V
IH1
Ports 2, 3, and 11
2.7
V
DD
5.5 V
0.7V
DD
V
DD
V
1.8
V
DD
< 2.7 V
0.9V
DD
V
DD
V
V
IH2
Ports 0, 1, 6, RESET
2.7
V
DD
5.5 V
0.8V
DD
V
DD
V
1.8
V
DD
< 2.7 V
0.9V
DD
V
DD
V
V
IH3
Ports 4, 5
2.7
V
DD
5.5 V
0.7V
DD
13
V
(N-ch open-drain)
1.8
V
DD
< 2.7 V
0.9V
DD
13
V
V
IH4
X1, XT1
V
DD
0.1
V
DD
V
Input voltage low
V
IL1
Ports 2-5, 11
2.7
V
DD
5.5 V
0
0.3V
DD
V
1.8
V
DD
< 2.7 V
0
0.1V
DD
V
V
IL2
Ports 0, 1, 6, RESET
2.7
V
DD
5.5 V
0
0.2V
DD
V
1.8
V
DD
< 2.7 V
0
0.1V
DD
V
V
IL3
X1, XT1
0
0.1
V
Output voltage high
V
OH
SCK, SO, Ports 2, 3, 6 I
OH
= 1.0 mA
V
DD
0.5
V
Output voltage low
V
OL1
SCK, SO, Ports 2-6
I
OL
= 15 mA,
0.2
2.0
V
V
DD
= 4.5 to 5.5 V
I
OL
= 1.6 mA
0.4
V
V
OL2
SB0, SB1
When N-ch open-drain
0.2V
DD
V
pull-up resistor
1 k
Input leakage
I
LIH1
V
IN
= V
DD
Pins other than X1, XT1
3
A
current high
I
LIH2
X1, XT1
20
A
I
LIH3
V
IN
= 13 V
Ports 4, 5 (N-ch open-drain)
20
A
Input leakage
I
LIL1
V
IN
= 0 V
Ports 4, 5, pins other than X1, XT1
3
A
current low
I
LIL2
X1, XT1
20
A
Ports 4, 5 (N-ch open-drain)
3
A
When input instruction is not executed
I
LIL3
Ports 4, 5 (N-ch open-
30
A
drain) When input
V
DD
= 5.0 V
10
27
A
instruction is executed
V
DD
= 3.0 V
3
8
A
Output leakage
I
LOH1
V
OUT
= V
DD
SCK, SO/SB0, SB1, Ports 2, 3, 6
3
A
current high
I
LOH2
V
OUT
= 13 V
Ports 4, 5 (N-ch open-drain)
20
A
Output leakage
I
LOL
V
OUT
= 0 V
3
A
current low
On-chip pull-up resistor
R
L
V
IN
= 0 V
Ports 0-3, 6 (Excluding P00 pin)
50
100
200
k
PD75P0076
38
DC CHARACTERISTICS (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Supply current
Note 1
I
DD1
6.0 MHz
Note 2
V
DD
= 5.0 V
10%
Note 3
3.4
10.2
mA
Crystal oscillation
V
DD
= 3.0 V
10%
Note 4
0.8
2.4
mA
I
DD2
C1 = C2 = 22 pF
HALT mode
V
DD
= 5.0 V
10%
0.9
2.7
mA
V
DD
= 3.0 V
10%
0.5
1.5
mA
I
DD1
4.19 MHz
Note 2
V
DD
= 5.0 V
10%
Note 3
2.7
7.4
mA
Crystal oscillation
V
DD
= 3.0 V
10%
Note 4
0.6
1.8
mA
I
DD2
C1 = C2 = 22 pF
HALT mode
V
DD
= 5.0 V
10%
0.8
2.4
mA
V
DD
= 3.0 V
10%
0.4
1.2
mA
I
DD3
32.768 kHz
Note 5
Low-voltage
V
DD
= 3.0 V
10%
42
126
A
Crystal oscillation
mode
Note 6
V
DD
= 2.0 V
10%
23
69
A
V
DD
= 3.0 V, T
A
= 25C
42
84
A
Low current con-
V
DD
= 3.0 V
10%
40
120
A
sumption mode
Note 7
V
DD
= 3.0 V, T
A
= 25C
40
80
A
I
DD4
HALT mode
Low-
V
DD
= 3.0 V
10%
8
24
A
voltage
V
DD
= 2.0 V
10%
4
12
A
mode
Note 6
V
DD
= 3.0 V, T
A
= 25C
8
16
A
Low current V
DD
= 3.0 V
10%
7
21
A
consumption V
DD
= 3.0 V,
7
14
A
mode
Note 7
T
A
= 25C
I
DD5
XT1 = 0 V
V
DD
= 5.0 V
10%
0.05
10
A
STOP mode
Note 8
V
DD
= 3.0 V
0.02
5.0
A
10%
T
A
= 25C
0.02
3.0
A
Notes 1. Not including currents flowing in on-chip pull-up resistors.
2. Including oscillation of the subsystem clock.
3. When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-speed
mode.
4. When PCC is set to 0000 and the device is operated in the low-speed mode.
5. When the system clock control register (SCC) is set to 1001 and the device is operated on the subsystem clock,
with main system clock oscillation stopped.
6. When the sub-oscillation circuit control register (SOS) is set to 0000.
7. When SOS is set to 0010.
8. When SOS is set to 00
1, the feedback resistors of the sub-oscillation circuit is cutoff. (
: don't care)
PD75P0076
39
AC CHARACTERISTICS (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle
t
CY
Operating on
V
DD
= 2.7 to 5.5 V
0.67
64
s
time
Note 1
main system clock
0.95
64
s
(Minimum instruction execution
Operating on
114
122
125
s
time = 1 machine cycle)
subsystem clock
TI0, TI1 input
f
TI
V
DD
= 2.7 to 5.5 V
0
1.0
MHz
frequency
0
275
kHz
TI0, TI1 input
t
TIH
, t
TIL
V
DD
= 2.7 to 5.5 V
0.48
s
high-/low-level width
1.8
s
Interrupt input high-/
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
s
low-level width
IM02 = 1
10
s
INT1, 2, 4
10
s
KR0 to KR3
10
s
RESET low-level width
t
RSL
10
s
Notes 1. The cycle time (minimum instruction
execution time) of the CPU clock (
)
is determined by the oscillation
frequency of the connected resonator
(and external clock), the system clock
control register (SCC) and the
processor clock control register
(PCC). The figure at the right
indicates the cycle time t
CY
versus
supply voltage V
DD
characteristic with
the main system clock operating.
2. 2t
CY
or 128/fx is set by setting the
interrupt mode register (IM0).
1
0
2
3
4
5
6
0.5
1
3
2
4
5
6
60
64
Supply Voltage V
DD
[V]
t
CY
vs V
DD
(At main system clock operation)
Cycle Time t
CY
[
s]
Guaranteed Operation
Range
PD75P0076
40
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high-/low-level
t
KL1
, t
KH1
V
DD
= 2.7 to 5.5 V
t
KCY1
/250
ns
width
t
KCY1
/2150
ns
SI
Note 1
setup time
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
(to SCK
)
500
ns
SI
Note 1
hold time
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
600
ns
SCK
SO
Note 1
output
t
KSO1
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
250
ns
delay time
C
L
= 100 pF
Note 2
0
1000
ns
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.
2. R
L
and C
L
are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T
A
= 40 to +85C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high-/low-level
t
KL2
,
t
KH2
V
DD
= 2.7 to 5.5 V
400
ns
width
1600
ns
SI
Note 1
setup time
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
(to SCK
)
150
ns
SI
Note 1
hold time
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
600
ns
SCK
SO
Note 1
output
t
KSO2
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
300
ns
delay time
C
L
= 100 pF
Note 2
0
1000
ns
Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.
2. R
L
and C
L
are the load resistance and load capacitance of the SO output lines.
PD75P0076
41
A/D CONVERTER CHARACTERISTICS (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V, 1.8 V
AV
REF
V
DD
)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Resolution
8
8
8
bit
Absolute accuracy
Note 1
V
DD
= AV
REF
2.7
V
DD
1.5
LSB
1.8 V
V
DD
< 2.7 V
3
LSB
V
DD
AV
REF
3
LSB
Conversion time
Note 2
t
CONV
168/f
X
s
Sampling time
Note 3
t
SAMP
44/f
X
s
Analog input voltage
V
IAN
AV
SS
AV
REF
V
Analog input impedance
R
AN
1000
M
AV
REF
current
I
REF
0.25
2.0
mA
Notes 1. Absolute accuracy excluding quantization error (
1/2 LSB).
2. Time after execution of conversion start instruction until completion of conversion (EOC = 1) (40.1
s: in f
X
=
4.19 MHz operation)
3. Time after conversion start instruction until completion of sampling (10.5
s: in f
X
= 4.19 MHz operation)
PD75P0076
42
AC Timing Test Point (Excluding X1, XT1 Input)
Clock Timing
TI0, TI1 Timing
X1 Input
1/f
X
t
XL
t
XH
0.1 V
V
DD
0.1 V
XT1 Input
1/f
XT
t
XTL
t
XTH
0.1 V
V
DD
0.1 V
V
IH
(MIN.)
V
IL
(MAX.)
V
IH
(MIN.)
V
IL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
TI0, TI1
1/f
TI
t
TIL
t
TIH
PD75P0076
43
t
KCY1, 2
t
KL1, 2
t
KH1, 2
SCK
SI
SO
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
Input Data
Output Data
t
KSO1, 2
t
SIK1, 2
t
KL1, 2
t
KH1, 2
SCK
t
KSI1, 2
SB0, 1
t
KCY1, 2
Serial Transfer Timing
3-wire serial I/O mode
2-wire serial I/O mode
PD75P0076
44
Interrupt input timing
RESET input timing
t
RSL
RESET
t
INTL
t
INTH
INT0, 1, 2, 4
KR0 to 3
PD75P0076
45
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(T
A
= 40 to +85C)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Release signal set time
t
SREL
0
s
Oscillation stabilization
t
WAIT
Release by RESET
2
15
/f
X
ms
wait time
Note 1
Release by interrupt request
Note 2
ms
Notes 1. The oscillation stabilization wait time is the time during which the CPU operation is stopped to prevent unstable
operation at the oscillation start.
2. Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait time
fx = at 4.19 MHz
fx = at 6.0 MHz
--
0
0
0
2
20
/fx (approx. 250 ms)
2
20
/fx (approx. 175 ms)
--
0
1
1
2
17
/fx (approx. 31.3 ms)
2
17
/fx (approx. 21.8 ms)
--
1
0
1
2
15
/fx (approx. 7.81 ms)
2
15
/fx (approx. 5.46 ms)
--
1
1
1
2
13
/fx (approx. 1.95 ms)
2
13
/fx (approx. 1.37 ms)
PD75P0076
46
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
RESET
STOP Instruction Execution
STOP Mode
Data Retention Mode
Internal Reset Operation
HALT Mode
Operating Mode
V
DDDR
t
SREL
t
WAIT
t
SREL
t
WAIT
V
DD
STOP Instruction Execution
STOP Mode
Data Retention Mode
HALT Mode
Operating Mode
Standby Release Signal
(Interrupt Request)
V
DDDR
PD75P0076
47
DC PROGRAMMING CHARACTERISTICS (T
A
= 25
5C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
= 0 V)
Parameter
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
Input voltage high
V
IH1
Except X1, X2
0.7V
DD
V
DD
V
V
IH2
X1, X2
V
DD
0.5
V
DD
V
Input voltage low
V
IL1
Except X1, X2
0
0.3V
DD
V
V
IL2
X1, X2
0
0.4
V
Input leakage current
I
LI
V
IN
= V
IL
or V
IH
10
A
Output voltage high
V
OH
I
OH
= 1 mA
V
DD
1.0
V
Output voltage low
V
OL
I
OL
= 1.6 mA
0.4
V
V
DD
power supply current
I
DD
30
mA
V
PP
power supply current
I
PP
MD0 = V
IL
, MD1 = V
IH
30
mA
Cautions 1. Avoid exceeding +13.5 V for V
PP
including the overshoot.
2. V
DD
must be applied before V
PP
, and cut after V
PP
.
AC PROGRAMMING CHARACTERISTICS (T
A
= 25
5C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
= 0 V)
Parameter
Symbol
Note 1
Test conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
(to MD0
)
t
AS
t
AS
2
s
MD1 setup time (to MD0
)
t
M1S
t
OES
2
s
Data setup time (to MD0
)
t
DS
t
DS
2
s
Address hold time
Note 2
(from MD0
)
t
AH
t
AH
2
s
Data hold time (from MD0
)
t
DH
t
DH
2
s
MD0
data output float delay time
t
DF
t
DF
0
130
ns
V
PP
setup time (to MD3
)
t
VPS
t
VPS
2
s
V
DD
setup time (to MD3
)
t
VDS
t
VCS
2
s
Initial program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
MD0 setup time (to MD1
)
t
M0S
t
CES
2
s
MD0
data output delay time
t
DV
t
DV
MD0 = MD1 = V
IL
1
s
MD1 hold time (from MD0
)
t
M1H
t
OEH
t
M1H
+ t
M1R
50
s
2
s
MD1 recovery time (from MD0
)
t
M1R
t
OR
2
s
Program counter reset time
t
PCR
10
s
X1 input high-/low-level width
t
XH
,
t
XL
0.125
s
X1 input frequency
f
X
4.19
MHz
Initial mode set time
t
I
2
s
MD3 setup time (to MD1
)
t
M3S
2
s
MD3 hold time (from MD1
)
t
M3H
2
s
MD3 setup time (to MD0
)
t
M3SR
During program memory read
2
s
Address
Note 2
data output delay time
t
DAD
t
ACC
During program memory read
2
s
Address
Note 2
data output hold time
t
HAD
t
OH
During program memory read
0
130
ns
MD3 hold time (from MD0
)
t
M3HR
During program memory read
2
s
MD3
data output float delay time
t
DFR
During program memory read
2
s
Notes 1. Corresponding symbol of
PD27C256A
2. The internal address signal is incremented by 1 at the rising edge of the fourth X1 input and is not
connected to the pin.
PD75P0076
48
Program Memory Write Timing
Program Memory Read Timing
t
VPS
t
VDS
V
PP
V
DD
V
DD
+1
V
DD
V
PP
V
DD
t
XH
t
XL
t
HAD
t
DAD
t
DV
t
I
t
M3HR
t
DFR
t
PCR
t
M3SR
X1
D0/P40-D3/P43
D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
Data output
Data output
t
VPS
t
VDS
t
XH
t
XL
t
I
t
DS
t
DH
t
DV
t
DF
t
DS
t
DH
t
AH
t
AS
t
PW
t
M1R
t
M0S
t
OPW
t
M1S
t
M1H
t
PCR
t
M3S
t
M3H
Data input
Data output
Data input
Data input
V
PP
V
DD
V
DD
+1
V
DD
V
PP
V
DD
X1
D0/P40-D3/P43
D4/P50-D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
PD75P0076
49
10. CHARACTERISTICS CURVES (REFERENCE VALUES)
10
5.0
1.0
0.5
0.1
0.05
0.01
0.005
0.001
0
1
2
3
4
5
6
7
8
(T
A
= 25
C)
Supply Voltage V
DD
(V)
Supply Current I
DD
(mA)
PCC = 0010
PCC = 0001
PCC = 0000
Main system clock
HALT mode + 32-kHz oscillation
XT1
XT2
X1
X2
Crystal resonator
6.0 MHz
Crystal resonator
32.768 kHz
330 k
22 pF
22 pF
33 pF
33 pF
I
DD
vs V
DD
(Main System Clock: 6.0-MHz Crystal Resonator)
PCC = 0011
Subsystem clock HALT
mode (SOS.1 = 0) and
main system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 0)
Subsystem clock HALT mode
(SOS.1 = 1) and main
system clock STOP mode
+ 32-kHz oscillation
(SOS.1 = 1)
Subsystem clock operation
mode (SOS.1 = 0)
PD75P0076
50
10
5.0
1.0
0.5
0.1
0.05
0.01
0.005
0.001
0
1
2
3
4
5
6
7
8
XT1
XT2
X1
X2
Crystal resonator
4.19 MHz
Crystal resonator
32.768 kHz 330 k
22 pF
22 pF
33 pF
33 pF
Supply Voltage V
DD
(V)
Supply Current I
DD
(mA)
PCC = 0010
Main system clock
HALT mode + 32-kHz oscillation
Subsystem clock HALT mode
(SOS.1 = 0) and main sysyem
clock STOP mode + 32-kHz
oscillation (SOS.1 = 0)
Subsystem clock operation
mode (SOS.1 = 0)
I
DD
vs V
DD
(Main System Clock: 4.19-MHz Crystal Resonator)
(T
A
= 25
C)
main system clock STOP
mode + 32-kHz oscillation
(SOS.1 = 1)
PCC = 0001
PCC = 0000
PCC = 0011
Subsystem clock HALT
mode (SOS.1 = 1) and
PD75P0076
51
11. PACKAGE DRAWINGS
42PIN PLASTIC SHRINK DIP (600 mil)
ITEM
MILLIMETERS
INCHES
A
B
C
F
G
H
I
J
K
39.13 MAX.
1.778 (T.P.)
3.20.3
0.51 MIN.
4.31 MAX.
1.78 MAX.
0.17
15.24 (T.P.)
5.08 MAX.
N
0.9 MIN.
R
1.541 MAX.
0.070 MAX.
0.035 MIN.
0.1260.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.600 (T.P.)
0.007
0.070 (T.P.)
P42C-70-600A-1
A
C
D
G
NOTES
1) Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
D
0.500.10
0.020
M
0.25
0.010
+0.10
0.05
0~15
0~15
+0.004
0.003
+0.004
0.005
M
K
N
L
13.2
0.520
2) Item "K" to center of leads when formed parallel.
42
1
22
21
L
M
R
B
F
H
J
I
PD75P0076
52
42 PIN PLASTIC SHRINK SOP (375 mil)
1
21
A
42
22
detail of lead end
C
M
M
N
B
D
E
F
G
I
J
H
K
L
3
+7
3
S42GT-80-375B-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
18.16 MAX.
0.8 (T.P.)
2.9 MAX.
2.50.2
10.30.3
1.13 MAX.
0.715 MAX.
0.0050.003
0.115 MAX.
0.406
0.281
0.044 MAX.
NOTE
M
N
0.10
0.80.2
1.60.2
7.150.2
0.004
0.031
+0.009
0.008
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
0.0630.008
0.098
0.031 (T.P.)
0.15
0.006
0.10
0.004
0.014
0.35
0.1250.075
+0.004
0.002
+0.009
0.008
+0.10
0.05
+0.004
0.003
E
+0.012
0.013
+0.009
0.008
+0.10
0.05
PD75P0076
53
12. RECOMMENDED SOLDERING CONDITIONS
The
PD75P0076 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual" (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
PD75P0076GT: 42-pin plastic shrink SOP (375 mil, 0.8 mm pitch)
Soldering
Soldering Conditions
Symbol
Method
Infrared reflow
Package peak temperature: 235C, Time: 30 seconds or less (at 210C or higher),
IR35-00-2
Number of reflow processes: Twice or less
VPS
Package peak temperature: 215C, Time: 40 seconds or less (at 200C or higher),
VP15-00-2
Number of reflow processes: Twice or less
Wave soldering
Solder temperature: 260C or below, Time: 10 seconds or less, Number of flow
WS60-00-1
process: 1, Preheating temperature: 120C or below (Package surface temperature)
Partial heating
Pin temperature: 300C or below, Time : 3 seconds or less (per device side)
--
Caution
Use of more than one soldering method should be avoided (except for partial heating).
Table 12-2. Insertion Type Soldering Conditions
PD75P0076CU: 42-pin plastic shrink DIP (600 mil, 1.778 mm pitch)
Soldering Method
Soldering Conditions
Wave soldering (pins only)
Solder bath temperature: 260 C or less, Time: 10 seconds or less
Partial heating
Pin temperature: 300 C or below, Time: 3 seconds or less (per device side)
Caution
Ensure that the application of wave soldering is limited to the pins and no solder touches the
main unit directly.
PD75P0076
54
APPENDIX A DIFFERENCES AMONG
PD75068, 750068 AND 75P0076
Parameter
PD75068
PD750068
PD75P0076
Program memory
Mask ROM
Mask ROM
One-time PROM
0000H to 1F7FH
0000H to 1FFFH
0000H to 3FFFH
(8064 x 8 bits)
(8192 x 8 bits)
(16384 x 8 bits)
Data memory
000H to 1FFH
(512 x 4 bits)
CPU
75X Standard CPU
75XL CPU
General-purpose register
4 bits x 8 or 8 bits x 4
(4 bits x 8 or 8 bits x 4) x 4 banks
Instruction
When main system
0.95, 1.91, 15.3
s
0.67, 1.33, 2.67, 10.7
s (during 6.0-MHz operation)
execution
clock is selected
(during 4.19-MHz operation)
0.95, 1.91, 3.81, 15.3
s (during 4.19-MHz operation)
time
When subsystem
122
s (during 32.768-kHz operation)
clock is selected
I/O port
CMOS input
12 (Connections of on-chip pull-up resistor specified by software: 7)
CMOS input/output
12 (Connections of on-chip pull-up resistor specified by software)
N-ch open-drain
8 (on-chip pull-up resistor
8 (on-chip pull-up resistor
8 (no mask option)
input/output
specified by mask option)
specified by mask option)
Withstand voltage is 13 V
Withstand voltage is 10 V
Withstand voltage is 13 V
Total
32
Timer
3 channels
4 channels
8-bit timer/event counter
8-bit timer/event counter 0 (watch timer output added)
8-bit basic interval timer
8-bit timer/event counter 1 (can be used as a 16-bit timer/
Watch timer
event counter)
8-bit basic interval timer/watchdog timer
Watch timer
A/D converter
8-bit resolution x 8 channels
8-bit resolution x 8 channels
(successive approximation)
(successive approximation)
Can operate at the voltage
Can operate at the voltage from V
DD
= 1.8 V
from V
DD
= 2.7 V
Clock output (PCL)
, 524, 262, 65.5 kHz
, 1.05 MHz, 262 kHz, 65.5 kHz
(Main system clock:
(Main system clock: during 4.19-MHz operation)
during 4.19-MHz operation)
, 1.5 MHz, 375 kHz, 93.8 kHz
(Main system clock: during 6.0-MHz operation)
Buzzer output (BUZ)
2, 4, 32 kHz
2, 4, 32 kHz
(Main system clock:
(Main system clock: during 4.19-MHz operation or
during 4.19-MHz operation
subsystem clock: during 32.768-kHz operation)
or subsystem clock: during
2.93, 5.86, 46.9 kHz
32.768-kHz operation)
(Main system clock: during 6.0-MHz operation)
Serial interface
3 modes supported
2 modes supported
3-wire serial I/O mode
3-wire serial I/O mode...MSB/LSB first selectable
...MSB/LSB first selectable
2-wire serial I/O mode
2-wire serial I/O mode
SBI mode
Vectored interrupt
3 external, 3 internal
3 external, 4 internal
Test inputs
1 external, 1 internal
Power supply voltage
V
DD
= 2.7 to 6.0 V
V
DD
= 1.8 to 5.5 V
Operating ambient temperature
T
A
= 40 to +85 C
Package
42-pin plastic shrink DIP
42-pin plastic shrink DIP (600 mil, 1.778-mm pitch)
(600 mil)
44-pin plastic QFP
42-pin plastic shrink SOP (375 mil, 0.8-mm pitch)
(10 x 10 mm)
Note Under development
PD75P0076
55
APPENDIX B DEVELOPMENT TOOLS
The following development tools are provided for system development using the
PD75P0076. In the 75XL series, the
common relocatable assembler of the series is used together with device files according to the product.
RA75X relocatable assembler
Host machine
Order code (Part No.)
OS
Supply Medium
PC-9800 Series
MS-DOS
TM
3.5" 2HD
S5A13RA75X
Ver.3.30 to
5" 2HD
S5A10RA75X
Ver.6.2
Note
IBM PC/AT
TM
Refer to OS for
3.5" 2HC
S7B13RA75X
or compatible
IBM PCs
5" 2HC
S7B10RA75X
Device file
Host machine
Order code (Part No.)
OS
Supply Medium
PC-9800 Series
MS-DOS
3.5" 2HD
S5A13DF750068
Ver.3.30 to
5" 2HD
S5A10DF750068
Ver.6.2
Note
IBM PC/AT
Refer to OS for
3.5" 2HC
S7B13DF750068
or compatible
IBM PCs
5" 2HC
S7B10DF750068
Note
Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remark
Operation of the assembler and device file is guaranteed only when using the host machine and OS described
above.
PROM Write Tools
Hardware
PG-1500
This is a PROM programmer which enables you to program a single-chip microcontroller with
on-chip PROM by stand-alone or host machine operation by connecting an attached board and
a programmer adapter (sold separately).
In addition, typical PROMs in capacities ranging from 256 K to 4 M bits can be programmed.
PA-75P0076CU
This is a PROM programmer adapter dedicated for the
PD75P0076CU and 75P0076GT. It
can be used when connected to a PG-1500.
Software
PG-1500 controller
PG-1500 and a host machine are connected by serial and parallel interfaces and PG-1500 is
controlled on the host machine.
Host machine
Order code (Part No.)
OS
Supply medium
PC-9800 Series
MS-DOS
3.5" 2HD
S5A13PG1500
Ver.3.30 to
5" 2HD
S5A10PG1500
Ver.6.2
Note
IBM PC/AT
Refer to OS for
3.5" 2HD
S7B13PG1500
or compatible
IBM PCs
5" 2HC
S7B10PG1500
Note
Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.
PD75P0076
56
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the
PD75P0076.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-R
Note 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. For development
of the
PD750068 subseries, the IE-75000-R is used with a separately sold emulation board (IE-
75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
The IE-75000-R can include a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems that use 75X or 75XL Series products. The IE-75001-R is
used with a separately sold emulation board (IE-75300-R-EM) and emulation probe.
These products can be applied for highly efficient debugging when connected to a host machine
and PROM programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems that use the
PD750068
subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.
EP-750068CU-R
This is an emulation probe for the
PD75P0076CU.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
EP-750068GT-R
This is an emulation probe for the
PD75P0076GT.
EV-9500GT-42
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.
It includes a flexible board (EV-9500GT-42) to facilitate connections with target systems.
Software
IE control program
This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine
Order code (Part No.)
OS
Supply Medium
PC-9800 Series
MS-DOS
3.5" 2HD
S5A13IE75X
Ver.3.30 to
5" 2HD
S5A10IE75X
Ver.6.2
Note 2
IBM PC/AT
Refer to OS for
3.5" 2HC
S7B13IE75X
or compatible
IBM PCs
5" 2HC
S7B10IE75X
Notes 1. This is a service part provided for maintenance purpose only.
2. Ver. 5.00 or later include a task swapping function, but this software is not able to use that function.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described
above.
2. The generic name for the
PD750064, 750066, 750068, and 75P0076 is the
PD750068 subseries.
PD75P0076
57
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
Version
PC DOS
TM
Ver.5.02 to Ver.6.3
J6.1/V
Note
to J6.3/V
Note
MS-DOS
Ver.5.0 to Ver.6.22
5.0/V
Note
to 6.2/V
Note
IBM DOS
TM
J5.02/V
Note
Note
Only the English mode is supported.
Caution
Ver 5.0 and above include a task swapping function, but this software is not able to use that function.
PD75P0076
58
APPENDIX C RELATED DOCUMENTS
The related documents indicated in this publication may include preliminary versions. However, preliminary versions are
not marked as such.
Documents related to device
Document Name
Document No.
English
Japanese
PD750064, 750066, 750068, 750064(A), 750066(A), 750068(A) Data Sheet
U10165E
Note
U10165J
PD75P0076 Data Sheet
This document
U10232J
PD750068 User's Manual
U10670E
U10670J
PD750068 Instruction Table
--
IEM-5606
75XL Series Selection Guide
U10453E
U10453J
Note
Preliminary product information
Documents related to development tool
Document Name
Document No.
English
Japanese
Hardware
IE-75000-R/IE-75001-R User's Manual
EEU-1416
EEU-846
IE-75300-R-EM User's Manual
U11345E
U11354J
EP-750068GT-R User's Manual
U10950E
U10950J
PG-1500 User's Manual
EEU-1335
EEU-651
Software
RA75X Assembler Package User's Manual
Operation
EEU-1346
EEU-731
Language
EEU-1363
EEU-730
PG-1500 Controller User's Manual
PC-9800 Series
EEU-1291
EEU-704
(MS-DOS) base
IBM PC Series
U10540E
EEU-5008
(PC DOS) base
Other related documents
Document Name
Document No.
English
Japanese
IC Package Manual
C10943X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
NEC Semiconductor Device Quality Grades
C11531E
C11531J
NEC Semiconductor Device Reliability and Quality Control
C10983E
C10983J
Electrostatic Discharge (ESD) Test
--
MEM-539
Semiconductor Device Quality Assurance Guide
MEI-1202
MEI-603
Microcontroller-related Product Guide --Third Party Products--
--
U11416J
Caution
The contents of the documents listed above are subject to change without prior notice to users. Make
sure to use the latest edition when starting design.
PD75P0076
59
[MEMO]
PD75P0076
60
NOTES FOR CMOS DEVICES
(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
(2) HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD75P0076
61
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J96. 8
PD75P0076
MS-DOS is a trademark of Microsoft Corporation.
PC DOS, PC/AT, and IBM DOS are trademarks of IBM Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without
governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country
other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5