NEC Corporation 1991

DATA SHEET

MOS Integrated Circuit

PD75P036

4-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The

PD75P036 is a 4-bit signgle-chip microcontroller that replaced the

PD75028's on-chip ROM with

one-time PROM or EPROM. Because this device can operate at the same supply voltage as its mask

version, it is suited for preproduction in development stage or small-scale production.

The one-time PROM version is programmable only once and is useful for small-scale production of many

different products and time-to-market of a new product. The EPROM version is programmable, erasable,

and reprogrammable, and is suited for the evaluation of application systems.

Detailed functions are described in the followig user's manual. Be sure to read it for designing.

PD75028 User's Manual: IEU-1280

FEATURES

PD75028 compatible

· At full production, the

PD75P036 can be replaced with the

PD75028 which incorporates mask ROM

Memory capacity

· Program memory (PROM): 16256 x 8 bits

· Data memory (RAM): 1024 x 4 bits

Internal pull-up resistors can be specified by software: Ports 0-3, 6-8

Internal pull-down resistors can be specified by software: Port 9

Open-drain input/output: Ports 4, 5, 10

Can operate at low voltage: V

= 2.7 to 6.0 V

ORDERING INFORMATION

Part Number

Package

Internal ROM

Quality Grade

PD75P036CW

64-pin plastic shrink DIP (750 mils)

One-time PROM

Standard

PD75P036GC-AB8

64-pin plastic QFP (14 x 14 mm)

One-time PROM

Standard

PD75P036KG

64-pin ceramic WQFN

EPROM

Not applicable

Caution

Internal pull-up/pull-down resistors cannot be specified by mask option as for this device.

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation
to know the specification of quality grade on e devices and its recommended applications.

The reliability of the EPROM version,

PD75P036KG, is not guaranteed when used in mass-produced application

sets. Please use this device only experimentally or for evaluation during trial manufacture.

The function common to the one-time PROM and EPROM versions is referred to as PROM throughout this document.

The information in this document is subject to change without notice.

The mark

shows revised points.

Document No.

U10051EJ3V0DS00 (3rd edition)

(Previous No.

IC-2967

Date Published September 1995 P
Printed in Japan

PD75P036

PIN CONFIGURATIONS (Top View)

· 64-pin plastic shrink DIP (750 mils)

· 64-pin plastic QFP (14 x 14 mm)

· 64-pin ceramic WQFN

SB1/SI/P03

SB0/SO/P02

SCK/P01

INT4/P00

BUZ/P23

PCL/P22

PPO/P21

PTO0/P20

MAT/P103
MAZ/P102

MAI/P101

MAR/P100

RESET

X1
X2

XT1
XT2

REF+

REF-

AN7

AN6
AN5
AN4

AN3/P113
AN2/P112
AN1/P111
AN0/P110

TIO/P13

64
63
62
61
60

59
58
57
56

55
54
53
52

51
50
49
48

47
46
45

44
43
42
41
40
39

37
36
35

34
33

1
2
3

5
6
7
8
9

10
11

12
13
14
15
16
17
18
19

20
21
22
23
24
25
26

27
28
29
30
31
32

P30/MD0
P31/MD1
P32/MD2
P33/MD3

P40
P41
P42
P43
P50

P51

P62/KR2

P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P80
P81
P82
P83

P90
P91

P92
P93
P10/INT0
P11/INT1

P12/INT2

P43

P42
P41

P40

MD3/P33

MD2/P32
MD1/P31

SB1/SI/P03

SB0/SO/P02

SCK/P01

INT4/P00

BUZ/P23

PCL/P22

PPO/P21

MD0/P30

P90

P91
P92

P93
P10/INT0

P11/INT1
P12/INT2

AN0/P110

AN1/P111
AN2/P112
AN3/P113

AN4
AN5
AN6

TI0/P13

P50 P51

P52

P53 P60/KR0

P61/KR1

P62/KR2

P71/KR5

P72/KR6 P73/KR7

P80

P81

P82

P83

P70/KR4

P63/KR3

PTO0/P20 MAT/P103

MAZ/P102

MAI/P101 MAR/P100

RESET

XT1

XT2 V

REF+

REF-

AN7

51 50 49

48
47

45
44
43
42
41

39
38
37

36
35
34

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15

1718 19

P52
P53
P60/KR0
P61/KR1

PD75P036CW

PD75P036GC-AB8

PD75P036KG

PD75P036

PIN IDENTIFICATION

P00-P03

: Port 0

INT0, INT1, INT4 : External Vectored Interrupt

P10-P13

: Port 1

INT2

: External Test Input

P20-P23

: Port 2

X1, X2

: Main System Clock Oscillation

P30-P33

: Port 3

XT1, XT2

: Subsystem Clock Oscillation

P40-P43

: Port 4

MAR

: Reference Integration

P50-P53

: Port 5

Control

P60-P63

: Port 6

MAI

: Integration Control

P70-P73

: Port 7

MAZ

: Autozero Control

P80-P83

: Port 8

MAT

: External Comparate

P90-P93

: Port 9

Timing Input

P100-P103 : Port 10

PPO

: Programmable Pulse Output

P110-P113 : Port 11

··· MFT timer mode

KR0-KR7

: Key Return

AN0-AN7

: Analog Input

SCK

: Serial Clock

REF+

: Analog Reference (+)

: Serial Input

REF

: Analog Reference ()

: Serial Output

: Analog V

SB0, SB1

: Serial Bus

: Analog V

RESET

: Reset Input

: Positive Power Supply

TI0

: Timer Input

: Ground

PTO0

: Programmable Timer Output

MD0-MD3

: Mode Selection

BUZ

: Buzzer Clock

: Programming/Verifying Power Supply

PCL

: Programmable Clock

Remark

MFT: Multifunction Timer

MFT A/D mode

PD75P036

BLOCK DIAGRAM

BASIC
INTERVAL
TIMER

TIMER
/COUNTER
#0

SERIAL
INTER-
FACE

INTBT

INTT0

INTCSI

INTER-
RUPT
CONTROL

WATCH
TIMER

A/D
CON-
VERTER

MULTI-
FUNCTION
TIMER

INTW

INTMFT

TI0/P13

PTO0/P20

SI/SB1/P03

SO/SB0/P02

SCK/P01

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0-KR3/P60-P63
KR4-KR7/P70-P73

AN0-AN3/P110-P113

AN4-AN7

BUZ/P23

REF

REF+

PPO/P21

MAT/P103

MAZ/P102

MAI/P101

MAR/P100

PCL/P22

CPU CLOCK

CLOCK
DIVIDER

CLOCK
OUTPUT
CONTROL

SUB

MAIN

CLOCK GENERATOR

STAND BY
CONTROL

XT1 XT2

X1 X2

RESET

PROGRAM
COUNTER

PROM

PROGRAM

MEMORY

16256 x 4 BITS

DECODE

AND

CONTROL

BIT SEQ.
BUFFER

RAM

DATA

MEMORY

1024 x 4 BITS

GENERAL

REG.

BANK

ALU

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT 10

PORT 11

P00P03

P10P13

P20P23

P30/MD0-P33/MD3

P40P43

P50P53

P60P63

P70P73

P80P83

P90P93

P100P103

P110P113

PD75P036

CONTENTS

PIN FUNCTIONS ... 6

1.1

Port Pins ... 6

1.2

Non-Port Pins ... 8

1.3

Pin Input/Output Circuits ... 10

1.4

Recommended Connection of Unused Pins ... 13

MEMORY ... 14

2.1

Differences between

PD75P036 and

PD75028/75036 ... 14

2.2

Program Memory (ROM) ... 15

2.3

Data Memory (RAM) ... 17

WRITING AND VERIFYING PROM (PROGRAM MEMORY) ... 19

3.1

Operation Modes For Writing/Verifying Program Memory ... 19

3.2

Program Memory Write Procedure ... 20

3.3

Program Memory Read Procedure ... 21

3.4

Erasure (

PD75P036KG only) ... 22

ELECTRICAL SPECIFICATIONS ... 23

CHARACTERISTIC CURVES ... 38

PACKAGE DRAWINGS ... 44

RECOMMENDED SOLDERING CONDITIONS ... 47

APPENDIX A.

DEVELOPMENT TOOLS ... 48

APPENDIX B.

RELATED DOCUMENTS ... 49

PD75P036

Pin Name Input/Output

Alternate

Function

8-Bit I/O

When Reset

Input/Output

Function

Circuit

Type

Note 1

P00

Input

INT4

4-bit input port (PORT0).

Input

P01

Input/Output

SCK

Internal pull-up resistors can be specified in

F - A

P02

Input/Output

SO/SB0

3-bit units for the P01 to P03 pins by

F - B

P03

Input/Output

SI/SBI

software.

M - C

P10

Input

INT0

With noise elimination function

Input

B - C

P11

INT1

4-bit input port (PORT1).

P12

INT2

Internal pull-up resistors can be specified in

P13

TI0

4-bit units by software.

P20

Input/Output

PTO0

4-bit input/output port (PORT2).

Input

E - B

P21

PPO

Internal pull-up resistors can be specified in

P22

PCL

4-bit units by software.

P23

BUZ

P30

Note 2

Input/Output

MD0

Programmable 4-bit input/output port

Input

E - B

P31

Note 2

MD1

(PORT3).

P32

Note 2

MD2

This port can be specified for input/output

P33

Note 2

MD3

in bit units.

Internal pull-up resistors can be specified in

4-bit units by software.

Note 2

N-ch open-drain 4-bit input/output port

Yes

Input

M - A

P40-P43

Input/Output

(PORT4).

Withstands up to 10 V.

Data input/output pin for writing and verifying

of program memory (PROM) (lower 4 bits).

Note 2

Input/Output

N-ch open-drain 4-bit input/output port

Input

M - A

P50-P53

(PORT5).

Withstands up to 10 V.

Data input/output pin for writing and verifying

of program memory (PROM) (upper 4 bits).

PIN FUNCTIONS

1.1 Port Pins (1/2)

Notes 1. Circles indicate Schmitt-triggerred inputs.

2. Can directly drive LEDs.

PD75P036

Pin Name Input/Output

Alternate

Function

8-Bit I/O

When Reset

Input/Output

Function

Circuit

Type

Note 1

P60

Input/Output

KR0

Programmable 4-bit input/output port

Yes

Input

F - A

P61

KR1

(PORT6).

P62

KR2

Internal pull-up resistors can be specified in

P63

KR3

4-bit units by software.

P70

Input/Output

KR4

4-bit input/output port (PORT7).

Input

F - A

P71

KR5

Internal pull-up resistors can be specified in

P72

KR6

4-bit units by software.

P73

KR7

P80-P83

Input/Output

4-bit input/output port (PORT8).

Input

E - B

Internal pull-up resistors can be specified in

4-bit units by software.

P90-P93

Input/Output

4-bit input/output port (PORT9).

Input

E - D

Internal pull-up resistors can be specified in

4-bit units by software.

P100

Input/Output

MAR

N-ch open-drain 4-bit input/output port

Input

M -A

P101

MAI

(PORT10).

P102

MAZ

Withstands up to 10 V in open-drain mode.

P103

MAT

P110

Input

AN0

4-bit input/output port (PORT11).

Input

P111

AN1

P112

AN2

P113

AN3

1.1 Port Pins (2/2)

Note

Circles indicate schmitt-triggerred inputs.

PD75P036

Pin Name Input/Output

Alternate

Function

8-Bit I/O

When Reset

Input/Output

Function

Circuit

Type

Note 1

TI0

Input

P13

External event pulse input pin to timer/event counter

Input

B - C

PTO0

Input/Output

P20

Timer/event counter output pin

Input

E - B

PCL

Input/Output

P22

Clock output pin

Input

E - B

BUZ

Input/Output

P23

Fixed frequency output pin (for buzzer or for trimming

Input

E - B

the system clock)

SCK

Input/Output

P01

Serial clock input/output pin

Input

F - A

SO/SB0

Input/Output

P02

Serial data output pin

Input

F - B

Serial bus input/output pin

SI/SB1

Input/Output

P03

Serial data output pin

Input

M - C

Serial bus input/output pin

INT4

Input

P00

Edge detection vectored interrupt input pin (Either

Input

rising or falling edge detection is effective)

INT0

Input

P10

Edge detection vectored interrupt input pin (Detection

Input

B - C

INT1

P11

edge can be selected)

INT2

Input

P12

Edge detection testable input pin (rising edge detection)

Input

B - C

KR0-KR3

Input/Output

P60-P63

Testable input/output pin (parallel falling edge detection)

Input

F - A

KR4-KR7

Input/Output

P70-P73

Testable input/output pin (parallel falling edge detection)

Input

F - A

MAR

Input/Output

P100

In integral A/D

Reverse integration signal output pin

Input

M - A

MAI

Input/Output

P101

converter mode

Integration signal output pin

Input

M - A

MAZ

Input/Output

P102

of MFT

Auto zero signal output pin

Input

M - A

MAT

Input/Output

P103

Comparator input pin

Input

M - A

PPO

Input/Output

P21

In timer mode

Timer pulse output pin

Input

E - B

of MFT

1.2 Non-Port Pins (1/2)

Note

Circles indicate Schmitt-triggerred inputs.

Remark

MFT: Multifunction timer

PD75P036

1.2 Non-Port Pins (2/2)

Pin Name

Input/Output

Alternate

Function

When Reset

Input/Output

Function

Circuit

Type

Note 1

AN0-AN3

Input

P110-P113

Pins only for A/D

8-bit analog input pin.

AN4-AN7

converter

Y - A

REF+

Input

Reference voltage input

Z - A

pin (AV

side).

REF

Input

Reference voltage input

Z - A

pin (AV

side).

Positive power supply pin. --

GND potential pin.

X1, X2

Input

Crystal or ceramic resonator connection for main

system clock generation. To use external clock, input

the external clock to X1 and its reverse phase to X2.

XT1, XT2

Input

Crystal or ceramic resonator connection for subsystem --

clock generation. To use external clock, input the

external clock to XT1 and its reverse phase to XT2.

XT1 can be used as a 1-bit input (test) pin.

RESET

Input

System reset input pin.

MD0/MD3 Input/Output

P30-P33

Mode selection pins in program memory (PROM)

Input

E - B

write/verify mode.

Note 2

Program voltage application pin in program memory

(PROM) write/verify mode.

At normal operation, connect the pin to V

directly.

In the PROM write/verify mode, apply +12.5 V.

Positive power supply pin.

GND potential pin.

Notes 1. Circles indicate schmitt trigger inputs.

2. If the V

pin is not connected directly to the V

pin at normal operation, the

PD75P036 does not operate

normally.

PD75P036

1.3

Pin Input/Output Circuits

The following shows a simplified input/output circuit diagram for each pin of the

PD75P036.

TYPE A (for TYPE E - B)

TYPE D (for TYPE E - B, F - A)

TYPE B

P-ch

N-ch

CMOS-level input buffer

data

output
disable

OUT

P-ch

N-ch

Push-pull output that can be set in an output
high-impedance state (both P-ch and N-ch are off)

Schmitt-triggerred input with hysteresis characteristics

data

output
disable

Type D

Type A

P.U.R.
enable

P.U.R.

P-ch

IN/OUT

data

output
disable

Type D

IN/OUT

P.U.R. : Pull-Up Resistor

P.D.R. : Pull-Down Resistor

P.D.R.
enable

P.D.R.

N-ch

Type A

P.U.R.
enable

P.U.R.

P-ch

TYPE B - C

TYPE E - B

TYPE E - D

P.U.R. : Pull-Up Resistor

PD75P036

TYPE F - A

TYPE Y

TYPE M - A

TYPE M - C

data

output
disable

Type D

Type B

P.U.R.
enable

P-ch

P.U.R.

IN/OUT

P.U.R. : Pull-Up Resistor

TYPE F - B

data

output
disable

P.U.R.
enable

P.U.R.

N-ch

P-ch

P-ch
N-ch

P-ch

N-ch

output

disable

(P)

output

disable

(N)

IN/OUT

TYPE Y - A

IN/OUT

N-ch
(+10-V
voltage)

data

output
disable

Middle-voltage input buffer
(withstands up to + 10 V)

data

output
disable

P.U.R.
enable

IN/OUT

N-ch

P.U.R. : PullUp Resistor

Sam-

pling

Sam-

pling

input
enable

Reference voltage

(from serial resistor

string voltage tap)

Reference voltage

(from serial resistor

string voltage tap)

Input buffer

IN instruction

PD75P036

Pin Name

Recomended Connecting Method

P00/INT4

Connect to V

P01/SCK

Connect to V

or V

P02/SO/SB0

P03/SI/SB1

P10/INT0-P12/INT2

Connect to V

P13/TI0

P20/PTO0

Input state: Independently connect to V

or V

via a

P21/PPO

resistor.

P22/PCL

Output state: Leave Open.

P23/BUZ

P30/MD0-P33/MD3

P40-P43

P50-P53

P60/KR0-P63/KR3

P70/KR4-P73/KR7

P80-P83

P90-P93

P100/MAR

P101/MAI

P102/MAZ

P103/MAT

P110/AN0-P113/AN3

Connect to V

or V

AN4-AN7

REF+

Connect to V

REF

Connect to V

XT1

Connect to V

or V

XT2

Leave Open.

Connect directly to V

1.4 Recommended Connection of Unused Pins

PD75P036

MEMORY

2.1 Differences between

PD75P036 and

PD75028/75036

The

PD75P036 is a microcontroller provided by replacing the

PD75028's on-chip mask ROM with one-time

PROM or EPROM. Capacity of program memory and data memory are different, but CPU function and internal

hardware are identical. Table 2-1 shows the differences between the

PD75P036 and

PD75028/75036. Users

should fully consider these differences especially when debugging or producing an application system on an

experimental basis by using the PROM version and then mass-producing the system using the mask ROM version.

For details about the CPU function and the internal hardware, refer to

PD75028 User's Manual (IEM-1280).

Table 2-1. Differences between

PD75P036 and

PD75028/75036

Item

PD75P036

PD75028

PD75036

Program memory

One-time PROM/EPROM

Mask ROM

0000H-3F7FH

0000H-1F7FH

0000H-3F7FH

(16256 x 8 bits)

(8064 x 8 bits)

(16256 x 8 bits)

Data memory

000H-3FFH

000H-1FFH

000H-3FFH

(1024 x 4 bits)

(512 x 4 bits)

(1024 x 4 bits)

Pull-up resistor

Ports 0-3, 6-8

Can be specified by software.

Ports 4, 5, 10

Not provided

Can be connected by mask option

Pull-down resistor

Port 9

Can be specified by software.

XT1 feedback resistor

Provided on-chip

Can be disconnected by mask option

Supply voltage

= 2.7 to 6.0 V

Pin connection

Pin 16 (SDIP)

Internally connected

Pin 25 (QFP)

Pins 60-63

P33/MD3-P30/MD0

P33-P30

(SDIP)

Pins 5-8 (QFP)

Electrical specifications

Supply current and operating temperature ranges differ between

PD75P036 and

PD75028/75036. For details, refer to the electrical specifications described in Data Sheet

of each model.

Others

Noise immunity and noise radiation differ because circuit complexity and mask layout are

different.

Caution The noise immunity and noise radiation differ between the PROM and mask ROM versions. To

replace the PROM version with the mask ROM version in the course of experimental production

to mass production, evaluate your system by using the CS version (not ES) of the mask ROM

version.

PD75P036

2.2 Program Memory (ROM) ··· 16256 words x 8 bits

The program memory is a 16256-word x 8-bit PROM and stores programs, table data, etc.

The program memory is accessed by referencing the program counter contents. Table data can be referenced

by executing a table look-up instruction (MOVT).

Figure 2-1 shows the address range in which a branch can be taken by branch instructions and subroutine call

instructions. A relative branch instruction (BR $addr) enables a branch to addresses [PC value 15 to 1, +2 to

+16] regardless of block boundaries.

Program memory addresses are 0000H-3F7FH and the following addresses are assigned to special purposes:

(All areas except 0000H or 0001H can be used as normal program memory.)

· Addresses 0000H-0001H

Vector table into which the program start address and MBE setting value when the RESET signal is generated

are written.

Processing at reset is started at any desired address.

· Addresses 0002H-000DH

Vector table into which the program start address and MBE setting value when each vectored interrupt is

generated are written.

Interrupt servicing can be started at any desired address.

· Addresses 0020H-007FH

Table area referenced by the GETI instruction

Note

Note The GETI instruction is provided to execute any 2-byte or 3-byte instruction or two 1-byte instructions as a 1-

byte instruction; it is used to reduce the number of program steps.

PD75P036

Figure 2-1. Program Memory Map

MBE

Internal reset start address (high-order six bits)

Internal reset start address (low-order eight bits)

INTBT/INT4 start address (high-order six bits)

INTBT/INT4 start address (low-order eight bits)

INT1 start address (high-order six bits)

INT1 start address (low-order eight bits)

INTCSI start address (high-order six bits)

INTCSI start address (low-order eight bits)

INT0 start address (high-order six bits)

INT0 start address (low-order eight bits)

INTMFT start address (high-order six bits)

INTMFT start address (low-order eight bits)

INT0 start address (high-order six bits)

INT0 start address (low-order eight bits)

GETI instruction reference table

0 0 0 2 H

0 0 0 4 H

0 0 0 6 H

0 0 0 8 H

0 0 0 A H

0 0 0 C H

0 7 F F H

0 0 8 0 H

0 0 7 F H

0 0 2 0 H

0 0 0 0 H

0 8 0 0 H

0 F F F H

1 0 0 0 H

1 F F F H

2 0 0 0 H

2 F F F H

3 0 0 0 H

3 F 7 F H

A d d r e s s

CALLF

! faddr

instruction

entry

address

BRCB

! caddr

instruction

branch

address

BRCB ! caddr

instruction

branch addresses

BRCB ! caddr

instruction

branch addresses

BRCB ! caddr

instruction

branch addresses

BR ! addr

Instruction

branch

address

CALL ! addr

instruction

subroutine

entry addres

BR $ addr
instruction

relative

branch Address

(15 to 1 and

+2 to +16)

Branch destination

address and

subroutine entry

address to be set

by GETI instruction

MBE

PD75P036

2.3 Data Memory (RAM)

The data memory consists of a data area and a peripheral hardware area as shown in Figure 2-2.

The data memory consists of banks, each consisting of 256 words x 4 bits, and the following memory banks can

be used:

· Memory banks 0-3 (data area)

· Memory bank 15 (peripheral hardware area)

Figure 2-2. Data Memory Map

(8 x 4)

256 x 4

128 x 4

Not implemented

F 8 0 H

F F F H

2 0 0 H

2 F F H

3 0 0 H

3 F F H

1 F F H

0 F F H

0 0 8 H

0 0 0 H

General purpose

0 0 7 H

Data Memory

Memory Bank

256 x 4

1 0 0 H

Data area
Static RAM
(1024 x 4)

Stack area

Peripheral

hardware area

PD75P036

(1)

Data area

The data area consists of static RAM and is used to store process data and as stack memory when a

(subroutine) or an interrupt is executed. Even when CPU operation is stopped in the standby mode, the memory

contents can be retained for hours with battery backup, etc. The data area is manipulated by executing memory

manipulation instructions.

The static RAM is mapped each 256 x 4 bits in memory banks 0-3. Bank 0 is mapped as a data area; it can

also be used as a general purpose register area (000H-007H) and a stack area (000H-0FFH).

One address of the static RAM consists of four bits; however it can be manipulated in 8-bit units by executing

8-bit memory manipulation instructions and bit-wise by executing bit manipulation instructions. To execute an

8-bit memory manipulation instruction, specify an even address.

(a)

General purpose register area

Can be handled by executing general purpose register and memory manipulation instructions. A maximum

of eight 4-bit registers can be used. The portions of the eight general purpose registers not used by a

program can be used as a data area or stack area.

(b) Stack area

Is set by an instruction and can be used as a save area when a subroutine is executed or interrupt servicing

is performed.

(2)

Peripheral hardware area

The peripheral hardware area is mapped in addresses F80H-FFFH of memory bank 15.

Like the static memory, the peripheral hardware area is handled by executing memory manipulation instructions.

However, the bit units in which the peripheral hardware can be manipulated vary depending on the address.

Addresses in which the peripheral hardware is not mapped do not contain data memory and cannot be

accessed.

PD75P036

WRITING AND VERIFYING PROM (PROGRAM MEMORY)

The program memory incorporated in the

PD75P036 is a 16256 x 8-bit electrically writable PROM. The pins

as listed in the table given below are used for write and verification of the PROM. No address is input; instead, an

address is updated by inputting a clock from the X1 pin.

Pin Name

Function

Applies voltage when program memory is written/verified (normally, at V

potential)

X1, X2

These pins input clock that updates address when program memory is written/verified. To X2 pin,

input X1's signal reverse phase.

MD0-MD3 (P30-P33)

These pins select operation mode when program memory is written/verified.

P40-P43 (Lower 4)

These pins input/output 8-bit data when program memory is written/verified.

P50-P53 (Upper 4)

Power supply voltage application pin.

Apply 2.7 to 6.0 V to this pin during normal operation and 6 V when program memory is written/verified.

Cautions 1. Always cover the erasure window of the

PD75P036KG with an opaque film except when the

contents of the EPROM are erased.

2. The one-time PROM version

PD75P036CW/GC is not equipped with a window, and therefore,

the contents of the program memory of this model cannot be erased by exposing it to ultraviolet

rays.

3.1 Operation Modes For Writing/Verifying Program Memory

When +6V is applied to the V

pin of the

PD75P036 with +12.5V applied to the V

pin, the

PD75P036 is set

in the program memory write/verify mode. In this mode, the following operation modes can be set by using the MD0-

MD3 pins. At this time, all remaining pins are set to the V

potential with pull-down resistors.

Operating Mode Specification

Operating Mode

MD0

MD1

MD2

MD3

+12.5 V

+6 V

Program memory address 0 clear mode

Write mode

Verify mode

Program inhibit mode

x: L or H

PD75P036

3.2 Program Memory Write Procedure

The program memory write procedure is as follows. High-speed program memory write is possible.

(1) Connect the unused pins to V

via pull-down resistors. The X1 pin must be low.

(2) Supply 5 V to the V

and V

pins.

(3) Wait for 10

(4) Set program memory address 0 clear mode.

(5) Supply 6 V to the V

pin and 12.5 V to the V

pin.

(6) Set program inhibit mode.

(7) Write data in 1 ms write mode.

(8) Set program inhibit mode.

(9) Set verify mode. If data has been written connectly, proceed to step (10). If data has not yet been written,

repeat steps (7) to (9).

(10) Write additional data for (the number of times data was written (X) in steps (7) to (9)) times

1 ms.

(11) Set program inhibit mode.

(12) Supply a pulse to the X1 pin four times to update the program memory address by 1.

(13) Repeat steps (7) to (12) to the last address.

(14) Set program memory address 0 clear mode.

(15) Change the voltages of V

and V

pins to 5 V.

(16) Turn off the power supply.

Steps (2) to (12) are illustrated below.

Data input

Data

output

Data input

Write

Verify

Additional
data write

Address

increment

X-time repetition

P40-P43
P50-P53

MD0
(P30)

MD1
(P31)

MD2
(P32)

MD3
(P33)

PD75P036

3.3 Program Memory Read Procedure

The

PD 75P036 program memory contents can be read in the following procedure. Read operation should be

performed in the verify mode.

(1) Connect the unused pins to V

via pull-down resistors. The X1 pin must be low.

(2) Supply 5 V to the V

and V

pins.

(3) Wait for 10

(4) Set program memory address 0 clear mode.

(5) Supply 6 V to the V

pin and 12.5 V to the V

pin.

(6) Set program inhibit mode.

(7) Set verify mode. Data of each address is sequentially output each time a clock pulse is input to the X1 pin

four times.

(8) Set program inhibit mode.

(9) Set program memory address 0 clear mode.

(10) Change the voltages of V

and V

pins to 5 V.

(11) Turn off the power supply.

Steps (2) to (9) are illustrated below.

Data output

"L"

Data output

P40-P43
P50-P53

MD0
(P30)

MD1
(P31)

MD2
(P32)

MD3
(P33)

PD75P036

3.4 Erasure (

PD75P036KG only)

The contents of the data programmed to the

PD75P036 can be erased by exposing the window to ultraviolet

rays.

The wavelength of the ultraviolet rays used to erase the contents is about 250 nm, and the quantity of the

ultraviolet rays necessary for complete erasure is 15 W·s/cm

(= ultraviolet ray intensity x erasure time).

When a commercially available ultraviolet ray lamp (wavelength: 254 nm, intensity: 12 mW/cm

) is used, about

15 to 20 minutes is required.

Cautions 1. The contents of the program memory may be erased if the

PD75P036 is exposed for a long

time to direct sunlight or a fluorescent light. To protect the contents from being erased, mask

the window with the opaque film. NEC attaches quality-tested opaque film to the UV EPROM

products for shipping.

2. To erase the memory contents, the distance between the ultraviolet ray lamp and the

PD75P036

should be 2.5 cm or less.

Remark

The time required for erasure changes depending on the degradation of the ultraviolet ray lamp and the

surface condition (dirt) of the window.

PD75P036

Parameter

Symbol

Test Conditions

Ratings

Unit

Supply voltage

0.3 to +7.0

0.3 to +13.5

Input voltage

Other than ports 4, 5, or 10

0.3 to V

+0.3

Ports 4, 5 and 10

Open-drain

0.3 to +11

Output voltage

0.3 to V

+0.3

Output current, high

Per pin

All pins

Output current, low

Note

Ports 0, 3, 4 and 5

peak value

Per pin

r.m.s. value

Other than ports

peak value

0, 3, 4 and 5

r.m.s. value

Per pin

Total for ports 0, 3-9, 11

peak value

170

r.m.s. value

120

Total for 0, 2, 10

peak value

r.m.s. value

Operating ambient temperature

40 to +70

Storage temperature

stg

65 to +150

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Note r.m.s. values should be calculated as follows: [r.m.s. value] = [peak value] x Duty

Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter,

or even momentarily. In other words, the absolute maximum ratings are rated values at which the

product is on the verge of suffering physical damage, and therefore the product must be used under

conditions which ensure that the absolute maximum ratings are not exceeded.

Capacitance (T

= 25

C, V

= 0 V)

Parameter

Symbol

Test Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

Unmeasured pins returned to 0 V

I/O capacitance

PD75P036

Main System Clock Oscillator Characteristics (T

= 40 to +70

C, V

= 2.7 to 6.0 V)

Resonator

Recommended

Parameter

Test Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation frequency

= Oscillation voltage

2.0

5.0

Note 3

MHz

resonator

)

Note 1

range

Oscillation stabilization

After V

came to MIN.

time

Note 2

of oscillation voltage range

Crystal

Oscilaltion frequency

2.0

4.19

5.0

Note 3

MHz

resonator

)

Note 1

Oscillation stabilization

= 4.5 to 6.0 V

time

Note 2

External clock

X1 input frequency

2.0

5.0

Note 3

MHz

)

Note 1

X1 input high- and

100

250

low-level widths (t

, t

)

Notes 1. The oscillation frequency and X1 input frequency are indicated only to express the characteristics of the

oscillator. For instruction execution time, refer to AC Characteristics.

2. Time required for oscillation to stabilize after V

reaches the minimum value of the oscillation voltage

range or the STOP mode has been released.

3. When the oscillation frequency is 4.19 MHz < fx

5.0 MHz, do not select PCC = 0011 as the instruction

execution time: otherwise, one machine cycle is set to less than 0.95

s, falling short of the rated minimum

value of 0.95

Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted

line in the figures as follows to avoid adverse influences on the wiring capacity:

Keep the wiring length as short as possible.

Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of

lines through which a high alternating current flows.

Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

. Do not connect the power source pattern through which a high current flows.

Do not extract signals from the oscillation circuit.

PD74HCU04

PD75P036

Subsystem Clock Oscillator Characteristics (T

= 40 to +70

C, V

= 2.7 to 6.0 V)

Resonator

Recommended

Parameter

Test Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation frequency

32.768 35

kHz

resonator

)

Note 1

Oscillation stabilization

= 4.5 to 6.0 V

1.0

time

Note 2

External clock

X1 input frequency

100

kHz

)

Note 1

X1 input high-, low-level

widths (t

, t

)

Notes 1. The oscillation frequency and XT1 input frequency are indicated only to express the characteristics of

the oscillator. For instruction execution time, refer to AC Characteristics.

2. Time required for oscillation to stabilize after V

reaches the minimum value of the oscillation voltage

range.

Cautions When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted

line in the figures as follows to avoid adverse influences on the wiring capacity:

· Keep the wiring length as short as possible.

· Do not cross the wiring over the other signal lines. Do not route the wiring in the vicinity of lines

through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

. Do not connect the power source pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce the current

dissipation and therefore, the subsystem clock circuit is influenced by noise more easily than the main

system clock oscillation circuit. When using th subsystem clock, therefore, exercise utmost care in wiring

the circuit.

XT1

XT2

PD75P036

Parameter

Symbol Test Conditions

MIN.

TYP. MAX.

Unit

Input voltage, high

IH1

Ports 2, 3, 8, 9, 11

0.7V

IH2

Ports 0, 1, 6, 7, RESET

0.8V

IH3

Ports 4, 5, 10

Open-drain

0.7V

IH4

X1, X2, XT1, XT2

0.5

Input voltage, low

IL1

Ports 2 to 5, 8 to 11

0.3V

IL2

Ports 0, 1, 6, 7, RESET

0.2V

IL3

X1, X2, XT1, XT2

0.4

Output voltage, high

= 4.5 to 6.0 V, I

= 1 mA

1.0

= 100

0.5

Output voltage, low

Ports 3, 4, 5

= 4.5 to 6.0 V,

0.4

2.0

= 15 mA

= 4.5 to 6.0 V, I

= 1.6 mA

0.4

= 400

0.5

SB0, 1

Open-drain

0.2V

Pull-up Resistor

1 k

Input leakage current, high

LIH1

= V

Other than below

LIH2

X1, X2, XT1, XT2

LIH3

= 9 V

Ports 4, 5, 10

(Open-drain)

Input leakage current, low

LIL1

= 0 V

Other than below

LIL2

X1, X2, XT1, XT2

Input leakage current, high

LOH1

= V

LOH2

= 9 V

Ports 4, 5, 10

(Open-drain)

Input leakage current, low

LOL

= 0 V

Internal pull-up resistor

Ports 0, 1, 2,

= 5.0 V

10 %

3, 6, 7, 8

= 3.0 V

10 %

300

(except P00)

= V

Internal pull-down resistor

Port 9

=5.0 V

10 %

= V

= 3.0 V

10 %

DC Characteristics (T

= 40 to +70

C, V

= 2.7 to 6.0 V)

PD75P036

Parameter

Symbol Test Conditions

MIN.

TYP.

MAX.

Unit

Supply current

Note 1

DD1

4.19 MHz

= 5 V

10%

Note 3

4.5

Crystal

= 3 V

10%

Note 4

0.9

DD2

oscillator

Note 2

HALT

= 5 V

10%

700

2100

C1 = C2 = 22 pF

mode

= 3 V

10%

300

900

DD3

32.768 kHz

Operating

= 3 V

10%

100

300

Crystal

mode

DD4

oscillator

Note 5

HALT

= 3 V

10%

mode

DD5

XT1 = 0 V

= 5 V

10%

0.5

STOP mode

0.1

3 V

10% T

= 25°C

0.1

DD6

32.768 kHz

= 3 V

10%

Note 6

Crystal oscillator

STOP mode

Notes 1. Currents for the internal pull-up resistor are not included.

2. Including when the subsystem clock is operated.

3. High-speed mode operation (when processor clock control register (PCC) is set to 0011).

4. Low-speed mode operation (when PCC is set to 0000).

5. When operated with the subsystem clock by setting the system clock control register (SCC) to SCC3 =

1 and SCC0 = 0 to stop the main system clock operation.

6. When subsystem clock is operated by executing STOP instruction during main system clock operation.

PD75P036

Parameter

Symbol Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle time

Note 1

Operating on

= 4.5 to 6.0 V

0.95

(minimum instruction execution

main system clock

3.8

time = 1 machine cycle)

Operating on

114

122

125

subsystem clock

TI0 input frequency

= 4.5 to 6.0 V

MHz

275

kHz

TI0 input high-, low-level widths t

TIH

= 4.5 to 6.0 V

0.48

TIL

1.8

Interrupt input high-, low-level

INTH

INT0

Note 2

widths

INTL

INT1, 2, 4

KR0 - 7

RESET low-level width

RSL

AC CHARACTERISTICS (T

= 40 to +70

C, V

= 2.7 to 6.0 V)

Notes 1. The CPU clock (

) cycle time is determined

by the oscillation frequency of the connected

oscillator, system clock control register (SCC),

and processor clock control register (PCC).

The figure on the right is cycle time t

vs.

supply voltage V

characteristics at the

main system clock.

2. 2t

or 128/f

depending on the setting of the

interrupt mode register (IM0).

6
5

0.5

Operation Guaranteed
Range

(During Main System Clock Operation)

Power Supply Voltage V

[V]

Cycle Time t

[ s]

PD75P036

SERIAL TRANSFER OPERATION

Two-Wire and Three-Wire Serial I/O Modes (SCK: internal clock output)

Parameter

Symbol Test Conditions

MIN.

TYP. MAX.

Unit

SCK cycle time

KCY1

= 4.5 to 6.0 V

1600

3800

SCK high-, low-level widths

KL1

= 4.5 to 6.0 V

KCY1

/2)50

KH1

KCY1

/2)150

SI setup time (to SCK

)

SIK1

150

SI hold time (from SCK

)

KSI1

400

SO output delay time

KSO1

= 1 k

= 4.5 to 6.0 V

250

from SCK

= 100 pF

Note

1000

Two-Wire and Three-Wire Serial I/O Modes (SCK: external clock input)

Parameter

Symbol Test Conditions

MIN.

TYP. MAX.

Unit

SCK cycle time

KCY2

= 4.5 to 6.0 V

800

3200

SCK high-, low-level widths

KL2

= 4.5 to 6.0 V

400

KH2

1600

SI setup time (to SCK

)

SIK2

100

SI hold time (from SCK

)

KSI2

400

SO output delay time

KSO2

= 1 k

= 4.5 to 6.0 V

300

from SCK

= 100 pF

Note

1000

Note R

and C

are load resistance and load capacitance of the SO output line.

PD75P036

Parameter

Symbol Test Conditions

MIN.

TYP. MAX.

Unit

SCK cycle time

KCY4

= 4.5 to 6.0 V

800

3200

SCK high-/low-level widths

KL4

= 4.5 to 6.0 V

400

KH4

1600

SB0, 1 setup time (to SCK

)

SIK4

100

SB0, 1 hold time (from SCK

)

KSI4

KCY4

SB0, 1 output delay time

KSO4

= 1 k

= 4.5 to 6.0 V

300

from SCK

= 100 pF

Note

1000

SB0, 1

from SCK

KSB

KCY4

SCK

from SB0, 1

SBK

KCY4

SB0, 1 low-level width

SBL

KCY4

SB0, 1 high-level width

SBH

KCY4

Note R

and C

are load resistance and load capacitance of the SO output line.

SBI Mode (SCK: external clock output (master))

SBI Mode (SCK: internal clock output (master))

Parameter

Symbol Test Conditions

MIN.

TYP. MAX.

Unit

SCK cycle time

KCY3

= 4.5 to 6.0 V

1600

3800

SCK high-/low-level widths

KL3

= 4.5 to 6.0 V

KCY3

/2)50

KH3

KCY3

/2)150

SB0, 1 Setup time (to SCK

)

SIK3

150

SB0, 1 hold time (from SCK

)

KSI3

KCY3

SB0, 1 output delay time

KSO3

= 1 k

= 4.5 to 6.0 V

250

from SCK

= 100 pF

Note

1000

SB0, 1

from SCK

KSB

KCY3

SCK

from SB0, 1

SBK

KCY3

SB0, 1 low-level width

SBL

KCY3

SB0, 1 high-level width

SBH

KCY3

PD75P036

Parameter

Symbol Test conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Absolute accuracy

Note 1

2.5 V

REF+

70 °C

1.5

LSB

10 °C

2.0

LSB

Conversion time

Note 2

CONV

168/f

Sampling time

Note 3

SAMP

44/f

Analog input voltage

IAN

REF

REF+

Analog supply voltage

2.5

Reference input voltage

Note 4

REF+

2.5 V

(AV

REF+

) (AV

REF

)

2.5

Reference input voltage

Note 4

REF

2.5 V

(AV

REF+

) (AV

REF

)

1.0

Analog input high impedance

1000

REF

current

REF

0.35

2.0

A/D Converter (T

= 40 to +70°C, V

= 2.7 to 6.0 V, AV

= V

= 0 V)

Notes 1. Absolute accuracy from which quantization error (

1/2 LSB) is removed.

2. Time until conversion end (EOC = 1) after conversion start instruction execution (40.1

s: Operation at

fx = 4.19 MHz).

3. Time until sampling end after conversion start instruction execution (10.5

s: Operation at fx = 4.19 MHz).

4. (AV

REF+

) (AB

REF

) should be 2.5 V or more.

PD75P036

Parameter

Symbol Test Conditions

MIN.

TYP.

MAX.

Unit

Data retention supply voltage

DDDR

2.0

6.0

Data retention supply

DDDR

= 2.0 V

0.1

current

Note 1

Release signal set time

SREL

Oscillation stabilization wait

WAIT

Released by RESET

time

Note 2

Released by interrupt

Note 3

BTM3

BTM2

BTM1

BTM0

WAIT time ( ): f

= 4.19 MHz

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

STOP instruction execution

DDDR

Operating
mode

HALT mode

STOP mode

Data retention mode

WAIT

RESET

SREL

Internal reset operation

STOP instruction execution

DDDR

Standby release signal

(interrupt request)

Operating
mode

HALT mode

STOP mode

Data retention mode

WAIT

SREL

Data Memory STOP Mode: Low-voltage Data Retention Characteristics (T

= 40 to +70

Notes 1. Does not include current in the internal pull-up resistor

2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable

operation when oscillation is started.

3. Depends on the setting of the basic interval timer mode register (BTM) as follows:

Data Retention Timing (releasing STOP mode by RESET)

Data Retention Timing (standby release signal: releasing STOP mode by interrupt)

PD75P036

Parameter

Symbol Test Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, high

IH1

Other than X1 or X2

0.7V

IH2

X1 and X2

0.5

Input voltage, low

IL1

Other than X1 or X2

0.3V

IL2

X1 and X2

0.4

Input leakage current

= V

or V

Output voltage, high

= 1 mA

1.0

Output voltage, low

= 1.6 mA

0.4

supply current

MD0 = V

, MD1 = V

Parameter

Symbol

Note 1

Test Conditions

MIN.

TYP.

MAX.

Unit

Address setup time

Note 2

(to MD0

)

MD1 setup time (to MD0

)

M1S

OES

Data setup time (to MD0

)

Address hold time

Note 2

(from MD0

)

Data hold time (from MD0

)

Data output float delay time from MD0

130

setup time (to MD3

)

VPS

setup time (to MD3

)

VDS

VCS

Initialized program pulse width

0.95

1.0

1.05

Additional program pulse width

OPW

0.95

21.0

MD0 setup time (to MD1

)

MOS

CES

Data output delay time from MD0

MD0 = MD1 = V

MD1 hold time (from MD0

)

M1H

OEH

M1H

+ t

M1R

MD1 recovery time (from MD0

)

M1R

Program counter reset time

PCR

X1 input high-/low-level width

, t

0.125

X1 input frequency

4.19

MHz

Initial mode set time

MD3 setup time (to MD1

)

M3S

MD3 hold time (from MD1

)

M3H

MD3 setup time (from MD0

)

M3SR

When data is read from

program memory

Address

Note 2

to data output delay time

DAD

ACC

When data is read from

program memory

Address

Note 2

to data output hold time

HAD

When data is read from

130

program memory

MD3 hold time (from MD0

)

M3HR

When data is read from

program memory

Data output float delay time from MD3

DFR

When data is read from

program memory

DC Programming Characteristics (T

= 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

Notes 1. These symbols are correspond to

PD27C256A symbols.

2. The internal address signal is incremented by 1 at the rising edge of fourth X1 input. The internal address

is not connected to any pin.

Cautions 1. V

must not exceed +13.5 V, including the overshoot.

2. Apply V

before V

and disconnect it after V

AC Programming Characteristics (T

= 25

C, V

= 6.0

0.25 V, V

= 12.5

0.3 V, V

= 0 V)

PD75P036

vs f

vs V

(Port 0)

vs V

(Ports 2, 6 to 10)

[MHz]

= 5 V, T

= 25 °C)

[mA]

PCC = 0011

PCC = 0010

PCC = 0000

Main system
clock
HALT mode

1.0

1.5

2.0

0.5

[MHz]

= 3 V, T

= 25 °C)

[mA]

PCC = 0010

PCC = 0000

Main system
clock
HALT mode

[mA]

= 25°C)

[V]

= 5 V

= 4 V

= 3 V

= 2.7 V

= 6 V

[mA]

= 5 V

= 6 V

= 4 V

= 2.7 V

= 3 V

= 25°C)

PD75P036

PACKAGE DRAWINGS

F
D

NOTE

Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

P64C-70-750A,C-1

ITEM MILLIMETERS

INCHES

58.68 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

0.25

19.05 (T.P.)

5.08 MAX.

17.0

0~15°

0.50±0.10

0.9 MIN.

2.311 MAX.

0.070 MAX.

0.020

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

0.007

0~15°

+0.004

0.003

0.070 (T.P.)

Item "K" to center of leads when formed parallel.

+0.10

0.05

+0.004

0.005

64 PIN PLASTIC SHRINK DIP (750 mil)

PD75P036

64 PIN PLASTIC QFP ( 14)

detail of lead end

5°±5°

P64GC-80-AB8-3

ITEM

MILLIMETERS

INCHES

17.6±0.4

14.0±0.2

1.0

0.35±0.10

0.15

14.0±0.2

0.693±0.016

0.039

0.006

0.031 (T.P.)

0.551

NOTE

0.10

0.15

1.8±0.2

0.8 (T.P.)

0.004

0.006

+0.004

0.003

Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.

0.071±0.008

0.014

0.551

0.8±0.2

0.031

2.55

0.100

0.693±0.016

17.6±0.4

1.0

+0.009

0.008

0.1±0.1

0.004±0.004

2.85 MAX.

0.112 MAX.

+0.10

0.05

+0.009

0.008

+0.004

0.005

+0.009

0.008

PD75P036

64 PIN CERAMIC WQFN

C D

X64KG-80A-1

ITEM MILLIMETERS

INCHES

13.8±0.25

13.0

12.4

0.543

0.512

0.488

+0.011

0.010

13.8±0.25

0.543

1.94

0.076

2.14

0.084

3.56 MAX.

0.141 MAX.

0.51±0.1

0.020±0.004

0.08

0.003

0.8 (T.P.)

0.031 (T.P.)

1.0±0.15

0.039±0.006

C 0.3

C 0.012

0.9

0.035

0.9

0.035

R 1.5

R 0.059

NOTE

Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.

6.0

0.236

1.0

0.039

0.75±0.15

0.030

0.10

0.004

+0.011

0.010

+0.006

0.007

PD75P036

RECOMMENDED SOLDERING CONDITIONS

It is recommended that the

PD75P036 be soldered under the following conditions.

For details on the recommended soldering conditions, refer to Information Document "Semiconductor Devices

Mounting Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended, please contact your NEC sales

representative.

Table 7-1. Soldering Conditions for Surface Mount Devices

PD75P036GC-AB8: 64-pin plastic QFP (14 x 14 mm)

Soldering Method

Soldering Conditions

Recommended Soldering

Code

Wave soldering

Soldering bath temperature: 260°C max.,

WS60-162-1

Time: 10 seconds max., Number of times: 1,

Maximum number of days: 2 days

Note

, (thereafter, 16 hours of

prebaking is required at 125°C),

Preheating temperature: 120

C max. (package surface

temperature).

Infrared reflow

Package peak temperature: 230°C,

IR30-162-1

Time: 30 seconds max. (210°C min.),

Number of times: 1, Maximum number of days: 2 days

Note

(thereafter, 16 hours of prebaking is required at 125°C)

VPS

Package peak temperature: 215°C,

VP15-162-1

Time: 40 seconds max. (200°C min.),

Number of times: 1, Maximum number of days: 2 days

Note

(thereafter, 16 hours of prebaking is required at 125°C)

Partial heating

Pin temperature: 300°C max.,

Time: 3 seconds max. (per pin row)

Note Number of days after unpacking the dry pack. Storage conditions are 25

C and 65% RH max.

Caution

Do not use different soldering methods together (except the partial heating method).

Table 7-2. Soldering Conditions for Through-hole Devices

PD75P036CW: 64-pin Plastic Shrink DIP (750 mils)

Soldering Method

Soldering Conditions

Wave soldering (pin only)

Soldering bath temperature: 260°C max., Time: 10 seconds max.

Partial heating

Pin temperature: 300°C max., Time: 3 seconds max. (per pin row)

Caution Apply wave soldering only to the lead part and be careful so as not to bring solder into direct

contact with the device body.

PD75P036

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are readily available to support development of systems using

PD75P03s:

Hardware

IE-75000-R

Note 1

In-circuit emulator for 75K series

IE-75001-R

IE-75000-R-EM

Note 2

Emulation board for IE-75000-R and IE-75001-R

EP-75028CW-R

Emulation prove for

PD75P036CW

EP-75028GC-R

Emulation prove for

PD75P036GC. Provided with 64-pin conversion socket.

EV-9200GC-64

EV-9200G-80 used for

PD75P036GC/75P036KG

PG-1500

PROM programmer

PA-75P036CW

PROM programmer adapter used for

PD75P036CW. It is connected to PG-1500.

PA-75P036GC

PROM programmer adapter used for

PD75P036GC. It is connected to PG-1500.

Software

IE control program

Host machine

PG-1500 controller

· PC-9800 series (MS-DOS

Ver. 3.30 to Ver. 5.00A

Note 3

)

RA75X relocatable

· IBM PC/AT

(Refer to document OS for IBM PC)

assembler

Notes 1. For maintenance purpose only

2. Not provided with IE-75001-R

3. Ver.5.00/5.00A has a task swap function, but this function cannot be used with these software.

Remark

Please refer to the 75X SERIES SELECTION GUIDE (IF-1027) for information on third party development

tools.

OS for IBM PC

The following OS are supported for IBM PC.

Version

PC DOS

Ver. 3.1 to Ver. 6.3

J6.1/V

Note

to 16.3/V

Note

MS-DOS

Ver. 5.0 to Ver. 6.2

5.0/V

Note

to J6.2/V

Note

IBM DOS

J5.02/V

Note

Note Supported only English mode.

Caution

Ver. 5.0 or later has a task swap function, but this function cannot be used with these software.

PD75P036

APPENDIX B. RELATED DOCUMENTS

Please use this document in conjunction with the following.

Related document may be "Preliminary." However, in this document, "Preliminary" is not indicated.

Device Document

Title

Document Number

Japanese

English

PD75P036 Data Sheet (This document)

IC-7914

IC-2967

PD75028 User's Manual

IEU-694

IEU-1280

PD75028 Instruction List

IEM-5511

PD75028 Application Note -- Basics

IEA-689

IEA-1277

75X series Selection Guide

IF-151

IF-1027

Title

Document Number

Japanese

English

Hardware

IE-75000-R/IE-75001-R User's Manual

EEU-846

EEU-1416

IE-75000-R-EM User's Manual

EEU-673

EEU-1294

EP-75028CW-R User's Manual

EEU-697

EEU-1314

IE-75028GC-R User's Manual

EEU-692

EEU-1306

PG-1500 User'ss Manual

EEU-651

EEU-1335

Software

RA75X Assembler Package User's Manual

Operation

EEU-731

EEU-1346

Language

EEU-730

EEU-1363

PG-1500 Controller User's Manual

PC-9800 series

EEU-704

Scheduled

(MS-DOS) based

IBM PC series

EEU-5008

EEU-1291

(PC DOS) based

Development Tool Document

PD75P036

Other Document

Caution The contents of the documents listed above are subject to change without prior notice to user's.

Make sure to use the latest edition when starting design.

Title

Number

Japanese

English

Package Manual

IEI-635

IEI-1213

Semiconductor Device Mounting Technology Manual

IEI-616

IEI-1207

Quality Grades on NEC Semiconductor Devices

IEI-620

IEI-1209

NEC Semiconductor Device Reliability/Quality Control System

IEM-5068

Electrostatic Discharge (ESD) Test

MEM-539

Guide to Quality Assurance for Semiconductor Devices

MEI-603

MEI-1202

Microcomputer-Related Product Guide -- Third Party Products

MEI-604

PD75P036

NOTES FOR CMOS DEVICES

(1) PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

(2) HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

lelvel may be generated due to noise, etc., hence causing mulfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry.

Each unused pin should be connected to VDD or GND with a resistor, if it is

considered to have a possibility of being an output pin. All handling related

to the unused pins must be judged device by device and related specifications

governing the devices.

(3) STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immediately

after power-on for devices having reset function.

PD75P036

M4 94.11

No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties b y or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standatd", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computer, office equipment, communication equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical eqiupment (not specifically designed for
life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nucleare reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.

The export of these products from Japan is regulated by the Japanese government. The export of some
or all of these products may prohibited without governmental license. To export or re-export some or all
or these products from a country other than Japan may also be prohibited without a license from that
country. Please call an NEC sales representative.

License not needed:

PD75P036KG

The customer must judge the need for license:

PD75P036CW, 75P036GC-AB8

Document Outline

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Document Outline

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