Printed in Japan

Document No. IC-3239
(O.D. No.

IC-8720)

Date Published August 1994 P

MOS INTEGRATED CIRCUIT

PD75P048

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The

PD75P048 is a One-Time PROM version of the

PD75048. The

PD75P048 is suitable for small-scale

production or experimental production in system development.

Detailed functions are described in the following user's manual. Read this manual when designing your

system.

PD75048 User's Manual: IEU-1278

FEATURES

The

PD75048 compatible

The

PD75P048 for evaluation/pre-production, while the

PD75048 for mass-production

8064

8 bits of one-time programmable ROM

512

4 bits of RAM

1024

4 bits of EEPROM (Data memory area)

Ports 0 to 3 and 6 to 8 with software-selectable pull-up resistors

Port 9 with software-selectable pull-down resistors

12 N-channel open drain input/output ports (ports 4, 5, and 10)

Low-voltage operation possible (V

= 2.7 to 6.0 V)

ORDERING INFORMATION

Part number

Package

Quality grade

PD75P048CW

64-pin plastic shrink DIP (750 mil)

Standard

PD75P048GC-AB8

64-pin plastic QFP ( 14 mm)

Standard

Caution Pull-up/pull-down resistor mask options are not available.

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by

NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

The information in this document is subject to change without notice.

The mark 5 shows major revised points.

1994

DATA SHEET

PD75P048

PIN CONFIGURATION (Top View)

64-pin plastic shrink DIP

64-pin plastic QFP

SB1/SI/P03

SB0/SO/P02

SCK/P01

INT4/P00

BUZ/P23

PCL/P22

PPO/P21

PTO0/P20

MAT/P103
MAZ/P102

MAI/P101

MAR/P100

RESET

X1
X2

XT1
XT2

REF+

REF

AN7
AN6
AN5
AN4

AN3/P113
AN2/P112
AN1/P111
AN0/P110

TI0/P13

PD75P048CW

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P30/MD0
P31/MD1
P32/MD2
P33/MD3
P40
P41
P42
P43
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
P70/KR4
P71/KR5
P72/KR6
P73/KR7
P80
P81
P82
P83
P90
P91
P92
P93
P10/INT0
P11/INT1
P12/INT2

P50

P51

P52

P53

P60/KR0

P61/KR1

P62/KR2

P63/KR3

P70/KR4

P71/KR5

P72/KR6

P73/KR7

P80

P81

P82

P83

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33

P90
P91
P92
P93
P10/INT0
P11/INT1
P12/INT2
TI0/P13
AV

AN0/P110
AN1/P111
AN2/P112
AN3/P113
AN4
AN5
AN6

P43
P42
P41
P40

MD3/P33
MD2/P32
MD1/P31
MD0/P30

SB1/SI/P03

SB0/SO/P02

SCK/P01

INT4/P00

BUZ/P23

PCL/P22

PPO/P21

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PTO0/P20

MAT/P103

MAZ/P102

MAI/P101

MAR/P100

RESET

XT1

XT2

REF+

REF

AN7

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

PD75P048GC-AB8

1
2
3
4
5
6
7
8
9

10
11
12
13
14
15
16

PD75P048

PIN IDENTIFICATION

P00-03

: Port0

P10-13

: Port1

P20-23

: Port2

P30-33

: Port3

P40-43

: Port4

P50-53

: Port5

P60-63

: Port6

P70-73

: Port7

P80-83

: Port8

P90-93

: Port9

P100-103

: Port10

P110-113

: Port11

KR0-7

: Key Return

SCK

: Serial Clock

: Serial Input

: Serial Output

SB0, 1

: Serial Bus 0, 1

RESET

: Reset Input

TI0

: Timer Input 0

PTO0

: Programmable Timer Output 0

BUZ

: Buzzer Clock

PCL

: Programmable Clock

INT0,1,4

: External Vectored Interrupt 0, 1, 4

INT2

: External Test Input 2

X1, 2

: Main System Clock Oscillation 1, 2

XT1, 2

: Subsystem Clock Oscillation 1, 2

MAR

: Reference Integration Control

MAI

: Integration Control

MAZ

: Autozero Control

MAT

: External Comparate Timing Input

PPO

: Programmable Pulse Output ... MFT timer mode

AN0-7

: Analog Input 0-7

REF+

: Analog Reference (+)

REF-

: Analog Reference (-)

: Analog V

: Positive Power Supply

: Ground

: Programming Power Supply

MD0-MD3

: Mode Selection

Remarks MFT: Multi-function timer

MFT
A/D
mode

PD75P048

BLOCK DIAGRAM

BASIC
INTERVAL
TIMER

INTBT

TIMER/
COUNTER
#0

INTT0

TI0/P13

PTO0/P20

SERIAL
INTERFACE

INTCSI

SI/SB1/P03

SO/SB0/P02

SCK/P01

INTERRUPT
CONTROL

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0 - KR3/P60 - P63
KR4 - KR7/P70 - P73

A/D
CONVERTER

REF+

REF

AN0 - AN3/P110 - P113

AN4 - AN7

WATCH
TIMER

INTW

BUZ/P23

MULTI-
FUNCTION
TIMER

MAR/P100

MAI/P101

MAZ/P102

MAT/P103

PPO/P21

INTMFT

PROGRAM
COUNTER

PROM
PROGRAM
MEMORY
8064

8 BITS

DECODE
AND
CONTROL

ALU

RAM

512

4 BITS

GENERAL REG.

EEPROM

1024

4 BITS

BANK

DATA
MEMORY

PORT 0

BIT SEQ.
BUFFER

P00 - P03

PORT 1

P10 - P13

PORT 2

P20 - P23

PORT 3

P30/MD0 - P33/MD3

PORT 4

P40 - P43

PORT 5

P50 - P53

PORT 6

P60 - P63

PORT 7

P70 - P73

PORT 8

P80 - P83

PORT 9

P90 - P93

PORT 10

P100 - P103

PORT 11

P110 - P113

CPU CLOCK

CLOCK
OUTPUT
CONTROL

CLOCK
DIVIDER

PCL/P22

XT1 XT2

SUB

CLOCK GENERATOR

MAIN

STAND BY
CONTROL

RESET

PD75P048

CONTENTS

PIN FUNCTIONS ·························································································································

1.1

PORT PINS ··········································································································································

1.2

NON-PORT PINS ·································································································································

1.3

PIN INPUT/OUTPUT CIRCUITS ········································································································

DIFFERENCES BETWEEN THE

PD75P048 AND THE

PD75048 ······································· 13

PROM (PROGRAM MEMORY) WRITE AND VERIFY ····························································· 14

3.1

PROM WRITE AND VERIFY OPERATION MODE ··········································································

3.2

PROM WRITE PROCEDURE ··············································································································

3.3

PROM READ PROCEDURE ················································································································

SCREENING OF ONE-TIME PROM MODEL ··········································································· 17

ELECTRICAL SPECIFICATIONS ·································································································· 18

PERFORMANCE CURVE (REFERENCE VALUE) ····································································· 32

PACKAGE DRAWINGS ··············································································································· 34

RECOMMENDED SOLDERING CONDITIONS ········································································· 36

APPENDIX A. DEVELOPMENT TOOLS ·························································································· 37

APPENDIX B. RELATED DOCUMENTS ·························································································· 38

PD75P048

1. PIN FUNCTIONS

1.1 PORT PINS (1/2)

Pin Name

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30

Note 2

P31

Note 2

P32

Note 2

P33

Note 2

P40 - P43

Note 2

P50 - P53

Note 2

I/O Circuit

Type

Note 1

-A

-B

-C

E-B

M-A

Input/

Output

Input

I/O

Input

I/O

Shared

INT4

SCK

SO/SB0

SI/SB1

INT0

INT1

INT2

TI0

PTO0

PPO

PCL

BUZ

MD0

MD1

MD2

MD3

When Reset

Input

High

impedance

High

impedance

8-Bit

I/O

Function

4-bit input port (PORT0).

For P01 to P03, pull-up resistors can be

provided by software in units of 3 bits.

With noise elimination function

4-bit input port (PORT1).

Pull-up resistors can be provided by

software in units of 4 bits.

4-bit I/O port (PORT2).

Pull-up resistors can be provided by

software in units of 4 bits.

Programmable 4-bit I/O port (PORT3).

I/O can be specified bit by bit.

Pull-up resistors can be provided by

software in units of 4 bits.

N-ch open-drain 4-bit I/O port (PORT4).

Can withstand 10 V.

Data input/output pins for the PROM

write and verity (Four low-order bits).

N-ch open-drain 4-bit I/O port (PORT5).

Can withstand 10 V.

Data input/output pins for the PROM

write and verify (Four high-order bits).

Note 1. The circle (

) indicates the Schmitt trigger input.

2. Can directly drive LEDs.

PD75P048

1.1 PORT PINS (2/2)

Pin Name

P60

P61

P62

P63

P70

P71

P72

P73

P80 - P83

P90 - P93

P100

P101

P102

P103

P110

P111

P112

P113

I/O Circuit

Type

Note

-A

E-B

E-D

M-A

Input/

Output

I/O

Input

Shared

KR0

KR1

KR2

KR3

KR4

KR5

KR6

KR7

MAR

MAI

MAZ

MAT

AN0

AN1

AN2

AN3

When Reset

Input

High

impedance

Input

8-Bit

I/O

Function

Programmable 4-bit I/O port (PORT 6).

Pull-up resistors can be provided by

software in units of 4 bits.

4-bit I/O port (PORT 7).

A pull-up resistor can be provided by

software in units of 4 bits

4-bit I/O port (PORT 8).

A pull-up resistor can be provided by

software in units of 4 bits.

4-bit I/O port (PORT 9).

A pull-up resistor can be provided by

software in units of 4 bits.

N-ch open drain 4-bit I/O port (PORT 10).

Can withstand 10 V in open-drain

mode.

4-bit input port (PORT 11).

Note

The circle (

) indicates the Schmitt trigger input.

PD75P048

Pin Name

TI0

PTO0

PCL

BUZ

SCK

SO/SB0

SI/SB1

INT4

INT0

INT1

INT2

KR0 - KR3

KR4 - KR7

MAR

MAI

MAZ

MAT

PPO

AN0 - AN3

AN4 - AN7

REF+

REF

I/O Circuit

Type

Note

-C

E-B

-A

-B

-C

-A

M-A

E-B

Y-A

Z-A

Shared

P13

P20

P22

P23

P01

P02

P03

P00

P10

P11

P12

P60 - P63

P70 - P73

P100

P101

P102

P103

P21

P110 - P113

When Reset

Input

High

impedance

High

impedance

High

impedance

High

impedance

Input

Input/

Output

Input

I/O

Input

I/O

Input

Function

Input for receiving external event pulse signal

for timer/event counter

Timer/event counter output

Clock output

Output for arbitrary frequency output (for

buzzer output or system clock trimming)

Serial clock I/O

Serial data output

Serial bus I/O

Serial data input

Serial bus I/O

Edge detection vectored interrupt input (either

rising edge or falling edge detection)

Edge detection vectored interrupt input

(detection edge selectable)

Edge detection testable input (rising edge

detection)

Parallel falling edge detection testable input

In MFT integrat-

ing A/D

converter mode

In MFT timer

mode

For A /D

converter only

1.2 NON-PORT PINS (1/2)

Reverse integration signal

output

Integration signal output

Auto-zero signal output

Comparator input

Timer pulse output

8-bit analog input

Reference voltage input

(AV

side)

Reference voltage input

(AV

side)

Positive power supply

GND potential

Note The circle (

) indicates the Schmitt trigger input.

Remark MFT: Multi-Function Timer

PD75P048

1.2 NON-PORT PINS (2/2)

Pin Name

X1, X2

XT1, XT2

RESET

MD0 - MD3

Note 2

Shared

P30 - P33

When Reset

Input

Input/

Output

Input

I/O

Function

Crystal/ceramic resonator connection for main

system clock generation. When external clock

signal is used, it is applied to X1, and its

reverse phase signal is applied to X2.

Crystal connection for subsystem clock

generation. When external clock signal is

used, it is applied to XT1, and its reverse

phase signal is applied to XT2. XT1 can be

used as a 1-bit input (test).

System reset input

Operation mode selection pins during the

PROM write/verify cycles.

Normally connected to V

directly; +12.5 V is

applied as the programming voltage during the

PROM write/verify cycles.

Positive power supply

GND potential

I/O Circuit

Type

Note 1

E-B

Note 1. The circle (

) indicates the Schmitt trigger input.

2. The V

should be connected to V

directly in normal operation mode. If V

and V

pins are not

connected, the

PD75P048 does not operate correctly.

PD75P048

1.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuit of each

PD75P048 pin is shown below in a simplified manner.

P-ch

Type A (For Type E-B)

N-ch

Type D (For Type E-B, F-A)

P-ch

N-ch

OUT

Data

Output
disable

CMOS input buffer

Push-pull output which can be set to high-impedance output
(off for both P-ch and N-ch)

Type B

Type E-B

P-ch

IN/OUT

Data

Output
disable

P.U.R.

enable

Type D

P.U.R.

Type A

Schmitt trigger input with hysteresis

P.U.R.: Pull-Up Resistor

Type B-C

Type E-D

P-ch

P.U.R.

P.U.R.
enable

N-ch

IN/OUT

P.D.R.

enable

P.D.R.

Data

Output
disable

Type D

Type A

P.U.R.: Pull-Up Resistor

P.D.R.: Pull-Down Resistor

(1/3)

PD75P048

Type F-A

Type M-C

P-ch

N-ch

IN/OUT

Data

Output
disable

P.U.R.: Pull-Up Resistor

Type F-B

Type Y

P-ch

IN/OUT

Data

Output
disable

P.U.R.

enable

Type D

P.U.R.

Type B

P.U.R.: Pull-Up Resistor

Input
enable

Type M-A

Type Y-A

Middle-voltage input buffer
(Can withstand + 10 V)

(2/3)

P-ch

IN/OUT

Data

Output
disable

P.U.R.

enable

P.U.R.

P.U.R.: Pull-Up Resistor

N-ch

P-ch

N-ch

Sampl-
ing C

Reference voltage
(from voltage tap of
series resistor string)

Output
disable

(N)

Output
disable

(P)

P-ch

P.U.R.

enable

P.U.R.

N-ch
(Can with-
stand + 10 V)

Data

Output
disable

IN/OUT

P-ch

N-ch

Sampl-
ing C

Reference voltage
(from voltage tap of
series resistor string)

IN instruction

Input buffer

P.U.R.: Pull-Up Resistor

PD75P048

2. DIFFERENCES BETWEEN THE

PD75P048 AND THE

PD75048

The

PD75P048 is a One-Time PROM version of the

PD75048. The

PD75P048 has the same CPU and

internal hardwares. Table 2-1 shows the differences between the

PD75P048 and the

PD75048. Bear in mind

the differences between these two products when debugging or developing on an experimental basis your

application system by using the one-time PROM model, and then mass-producing the application system by

using the mask ROM model.

Details for the CPU functions and internal hardwares are available in

PD75048 User's Manual (IEU-1278).

Table 2-1 Differences between the

PD75P048 and the

PD75048

Items

Program Memory

Pull-up Resistors

Pull-Down Resistors

XT1 Feedback Resistor

Pin Connection

Electrical Specification

Other

PD75P048

PD75048

One-time PROM

Mask ROM

· 0000H to 1F7FH

· 8064

8 bits

Software-selectable

N/A

Mask-option

Software-selectable

On-chip

Mask-option

P33/MD3 - P30/MD0

P33 - P30

Current dissipation differs. For details,

refer to Data Sheet of each model.

Circuit scale and mask layout differ.

Consequently, noise immunity and noise

radiation differ.

Ports 0 to 3 and 6 to 8

Ports 4, 5 and 10

Port 9

60 - 63 (SDIP)

5 - 8 (QFP)

16 (SDIP)

25 (QFP)

Note The noise immunity and noise radiation of the PROM and mask ROM models differ. To replace the PROM

mode, which has been used for experimental production of your application system with the mask ROM

model for mass production of the application system, be sure to perform thorough evaluation by using

the CS model (not ES model) of the mask ROM model.

PD75P048

3. PROM (PROGRAM MEMORY) WRITE AND VERIFY

The

PD75P048 contains 8064 bytes of PROM. The following table shows the pin functions during the write

and verify cycles. Note that it is not necessary to enter an address, because the address is updated by pulsing

the X1 clock pins.

Pin Name

X1, X2

MD0 - MD3 (P30 - P33)

P40 - P43 (lower 4 bits)

P50 - P53 (higher 4 bits)

Function

Normally 2.7 to 6 V; 12.5 V is applied during write/verify

After a write/verify write, the X1 and X2 clock pins are

pulsed. The inverted signal of the X1 should be input to the

X2.

Note that these pins are also pulsed during a read.

Operation mode selection pins.

8-bit data input/output pins for write and verify

Supply voltage.

Normally 2.7 to 6 V; 6 V is applied during write/verify

Caution The

PD75P048CW/GC do not have a UV erase window, thus the PROM contents cannot be erased

with ultra-violet ray.

3.1 PROM WRITE AND VERIFY OPERATION MODE

When 6 V and 12.5 V are applied to the V

and V

pins, respectively, the PROM is placed in the write/verify

mode. The operation is selected by the MD0 to MD3 pins, as shown in the table.

The other pins should be returned to V

potential via pull-down resistors.

Operation Mode Specification

+12.5 V

+6 V

MD0

MD1

MD2

MD3

Operation Mode

Clear program memory address to 0

Write mode

Verify mode

Program inhibit

: Don't care.

PD75P048

3.2 PROM WRITE PROCEDURE

PROMs can be written at high speed using the following procedure: (see the following figure)

(1) Pull unused pins to V

through resistors. Set the X1 pin low.

(2) Supply 5 volts to the V

and V

pins.

(3) Wait for 10

(4) Select the zero clear program memory address mode.

(5) Supply 6 volts to the V

and 12.5 volts to the V

pins.

(6) Select the program inhibit mode.

(7) Write data in the 1 ms write mode.

(8) Select the program inhibit mode.

(9) Select the verify mode. If the data is correct, proceed to step (10). If not, repeat steps (7), (8) and (9).

(10) Perform one additional write (duration of 1 ms

number of writes at (7) to (9)).

(11) Select the program inhibit mode.

(12) Apply four pulses to the X1 pin to increment the program memory address by one.

(13) Repeat steps (7) to (12) until the end address is reached.

(14) Select the zero clear program memory address mode.

(15) Return the V

and V

pins back to + 5 volts.

(16) Turn off the power.

The following figure shows steps (2) to (12).

MD0

(P30)

Input data

Output
data

Input data

P40-P43
P50-P53

MD1

(P31)

MD2

(P32)

MD3

(P33)

Write

Verify

Additional write

Address
increment

X repetition

PD75P048

3.3 PROM READ PROCEDURE

The PROM contents can be read in the verify mode by using the following procedure: (see the following

figure)

(1) Pull unused pins to V

through resistors. Set the X1 pin low.

(2) Supply 5 volts to the V

and V

pins.

(3) Wait for 10

(4) Select the clear program memory address mode.

(5) Supply 6 volts to the V

and 12.5 volts to the V

pins.

(6) Select the program inhibit mode.

(7) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored

in one address.

(8) Select the program inhibit mode.

(9) Select the clear program memory address mode.

(10) Return the V

and V

pins back to + 5 volts.

(11) Turn off the power.

The following figure shows steps (2) to (9).

MD0

(P30)

Output data

P40-P43
P50-P53

MD1

(P31)

MD2

(P32)

MD3

(P33)

"L"

Output data

PD75P048

5. ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply Voltage

-0.3 to +7.0

Input Voltage

Other than ports 4, 5, 10

-0.3 to V

+0.3

Ports 4, 5, 10

w/pull-up

-0.3 to V

+0.3

resistor

Open drain

-0.3 to +11

Output Voltage

-0.3 to V

+0.3

High-Level Output

1 pin

-10

Current

All pins

-30

Low-Level Output

Note

Ports 0, 3, 4, 5

Peak

Current

1 pin

rms

Other than ports 0, 3, 4, 5

Peak

1 pin

rms

Total of ports 0, 3 - 9, 11

Peak

170

rms

120

Total of ports 0, 2, 10

Peak

rms

Operating Temperature

opt

-10 to +70

Storage Temperature

stg

-65 to +150

Note rms = Peak value x

Duty

Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality

of the product may be degraded. The absolute maximum rating therefore specifies the upper or

lower limit of the value at which the product can be used without physical damages. Be sure not

to exceed or fall below this value when using the product.

EEPROM RATINGS (T

= -10 to +70

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

Ratings

Unit

Write Times

100,000

times

Data Retention Time

years

CAPACITANCE (T

= 25

C, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input Capacitance

f = 1 MHz

Output Capacitance

Pins other than those measured are at 0 V

Input/Output

PD75P048

MAIN SYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -10 to +70

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Ceramic

Oscillation

= oscillation

frequency(f

)

Note 1

voltage range

2.0

5.0

Note 3

MHz

Oscillation stabiliza-

After V

come to

tion time

Note 2

MIN. value of
oscillation voltage

range

Crystal

Oscillation

2.0

4.19

5.0

Note 3

MHz

frequency (f

)

Note 1

Oscillation stabiliza-

= 4.5 to 6.0 V

tion time

Note 2

External Clock

X1 input frequency
(f

)

Note 1

2.0

5.0

Note 3

MHz

X1 input high-,
low-level widths

100

250

, t

)

Note 1. Only to express the characteristics of the oscillator circuit. For instruction execution time, refer to

AC Characteristics.

2. Time required for oscillation to stabilize after V

has reached the minimum volue of the oscillation

voltage range or the STOP mode has been released.

3. When the oscillation frequency is 4.19 MHz < fx

5.0 MHz, do not select PCC = 0011 as the instruction

execution time: otherwise, one machine cycle is set to less than 0.95

s, falling short of the rated

minimum value of 0.95

Caution When using the oscillation circuit of the main system clock, wire the portion enclosed in dotted

line in the figures as follows to avoid adverse influences on the wiring capacity:

Keep the wiring length as short as possible.

Do not cross the wiring over the other signal lines.

Do not route the wiring in the vicinity of lines through which a high alternating current flows.

Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

. Do not connect the ground pattern through which a high curent flows.

Do not extract signals from the oscillation circuit.

PD74HCU04

PD75P048

SUBSYSTEM CLOCK OSCILLATOR CIRCUIT CHARACTERISTICS

= -10 to +70

C, V

= 2.7 to 6.0 V)

Oscillator

Recommended

Item

Conditions

MIN.

TYP.

MAX.

Unit

Constants

Crystal

Oscillation

32.768

kHz

frequency (f

)

Note 1

Oscillation stabiliza-

= 4.5 to 6.0 V

1.0

tion time

Note 2

External Clock

XT1 input frequency
(f

)

Note 1

100

kHz

XT1 input high-,
low-level widths

XTH

, t

XTL

)

Note 1. Indicates only the characteristics of the oscillator circuit. For instruction execution time, refer to AC

Characteristics.

2. Time required for oscillation to stabilize after V

has reached the minimum value of the oscillation

voltage range.

Caution When using the oscillation circuit of the subsystem clock, wire the portion enclosed in dotted line

in the figures as follows to avoid adverse influences on the wiring capacity:

Keep the wiring length as short as possible.

Do not cross the wiring over the other signal lines.

Do not route the wiring in the vicinity of lines through which a high alternating current flows.

Always keep the ground point of the capacitor of the oscillator circuit at the same potential as

. Do not connect the ground pattern through which a high current flows.

Do not extract signals from the oscillation circuit.

The amplification factor of the subsystem clock oscillation circuit is designed to be low to reduce

the current dissipation and therefore, the subsystem clock oscillation circuit is influenced by noise

more easily than the main system clock oscillation circuit. When using the subsystem clock,

therefore, exercise utmost care in wiring the circuit.

XT1

XT2

XT1

XT2

PD75P048

DC CHARACTERISTICS (T

= -10 to +70

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

High-Level Input

IH1

Ports 2,3,8,9,11

0.7V

Voltage

IH2

Ports 0,1,6,7, RESET

0.8V

IH3

Ports 4,5,10

w/pull-up resistor

0.7V

Open-drain

0.7V

IH4

X1, X2, XT1, XT2

-0.5

Low-level Input

IL1

Ports 2-5, 8-11

0.3V

Voltage

IL2

Ports 0, 1, 6, 7, RESET

0.2V

IL3

X1, X2, XT1, XT2

0.4

High-Level Output

= 4.5 to 6.0V, I

= -1 mA

-1.0

Voltage

= -100

-0.5

Low-Level Output

Ports 3,4,5

= 4.5 to 6.0V,

0.4

2.0

Voltage

= 15mA

= 4.5 to 6.0V, I

= 1.6 mA

0.4

= 400

0.5

SB0, 1

Open-drain pull-up

0.2V

resistor

1 k

High-Level Input

LIH1

= V

Other than below

Leakage Current

LIH2

X1,X2,XT1

LIH3

= 9V

Ports 4,5,10

(open-drain)

Low-Level Input

LIL1

= 0V

Other than below

-3

Leakage Current

LIL2

X1,X2,XT1

-20

High-Level Output

LOH1

= V

Other than below

Leakage Current

LOH2

= 9V

Ports 4,5,10

(open-drain)

Low-Level Output

LOL

= 0V

-3

Leakage Current

Internal Pull-Up Resistor

Ports 0,1,2,3,6,7,8

= 5.0V

10%

(except P00) V

= 0V

= 3.0V

10%

300

Ports 4,5,10

= 5.0V

10%

= V

-2.0 V

= 3.0V

10%

Internal Pull-Down

Port 9 V

= V

= 5.0V

10%

Resistor

= 3.0V

10%

PD75P048

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply

DD1

4.19MHz crystal

= 5V

10%

Note 2

5.5

Current

Note 1

oscillator

= 3V

10%

Note 3

1.7

5.1

DD2

C1 = C2 = 22pF

HALT mode

= 5V

10%

900

2700

= 3V

10%

450

1400

DD3

32.768kHz

Note 4

Operation

= 3V

10%

100

300

crystal oscillator

mode

DD4

HALT mode

= 3V

10%

110

DD5

XT1 = 0V

= 5V

10%

0.5

STOP mode

= 3V

10%

0.3

= 25

DD6

32.768kHz oscillator

= 3V

10%

Note 5

STOP mode

Note 1. Current flowing through internal pull-up resistor. Current flowing when EEPROM is accessed is not

included.

2. When

PD75048 operates in high-speed mode with processor clock control register (PCC) set to 0011.

3. When

PD75048 operates in low-speed mode with PCC set to 0000.

4. When the system clock control register (SCC) is set to 1001, the oscillation of the main system clock

is stopped, and the subsystem clock is used.

5. When STOP instruction is executed with SCC set to 0000.

Note Supply current when EEPROM is accessed is shown in EEPROM Characteristics.

PD75P048

AC CHARACTERISTICS (T

= -10 to +70

C, V

= 2.7 to 6.0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU Clock Cycle Time

w/main system clock

= 4.5 to 6.0V

0.95

(Minimum Instruction

3.8

Execution Time

w/subsystem clock

114

122

125

= 1 Machine Cycle)

Note 1

TI0 Input Frequency

= 4.5 to 6.0 V

MHz

275

kHz

TI0 Input High-, Low-

TIH

= 4.5 to 6.0 V

0.48

Level Widths

TIL

1.8

Interrupt Input High-,

INTH

INT0

Note 2

Low-Level Widths

INTL

INT1, 2, 4

KR0-7

RESET Low-Level Width

RSL

Note 1. The CPU clock (

) cycle time is de-

termined by the oscillation frequency

of the connected oscillator, system

clock control register (SCC), and

processor clock control register (PCC).

The figure on the right is cycle time t

vs. supply voltage V

characteristics

at the main system clock.

2. 2

tCY

or 128/f

depending on the set-

ting of the interrupt mode register

(IM0).

0.5

Supply voltage V

[V]

Cycle time t

[ s]

vs V

(with main system clock)

Operation
quaranteed
range

PD75P048

SERIAL TRANSFER OPERATION

Two-Line and Three-Line Serial I/O Modes (SCK: internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY1

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL1

= 4.5 to 6.0 V

KCY1

/2-50

Widths

KH1

KCY1

/2-150

SI Set-Up Time (vs. SCK

) t

SIK1

150

SI Hold Time (vs. SCK

)

KSI1

400

SCK

SO Output

KSO1

= 1k

Note

= 4.5 to 6.0V

250

Delay Time

= 100pF

1000

TWO-LINE AND THREE-LINE SERIAL I/O MODES (SCK: external clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY2

= 4.5 to 6.0V

800

3200

SCK High-, Low-Level

KL2

= 4.5 to 6.0V

400

Widths

KH2

1600

SI Set-Up Time (vs. SCK

) t

SIK2

100

SI Hold Time (vs. SCK

)

KSI2

400

SCK

SO Output

KSO2

= 1k

, C

= 100 pF

Note

= 4.5 to 6.0V

300

Delay Time

1000

Note R

and C

are load resistance and load capacitance of the SO output line.

PD75P048

SBI MODE (SCK: internal clock output (master))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY3

= 4.5 to 6.0 V

1600

3800

SCK High-, Low-Level

KL3

= 4.5 to 6.0 V

KCY3

/2-50

Widths

KH3

KCY3

/2-150

SB0, 1 Set-Up Time

SIK3

150

(vs. SCK

)

SB0, 1 Hold Time

KSI3

KCY3

(vs. SCK

)

SCK

SB0, 1 Output

KSO3

= 1k

Note

= 4.5 to 6.0V

250

Delay Time

= 100pF

1000

SCK

SB0, 1

KSB

KCY3

SB0,1

SCK

SBK

KCY3

SB0, 1 Low-Level Width

SBL

KCY3

SB0, 1 High-Level Width

SBH

KCY3

SBI MODE (SCK: external clock input (slave))

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK Cycle Time

KCY4

= 4.5 to 6.0 V

800

3200

SCK Ligh-, Low-Level

KL4

= 4.5 to 6.0 V

400

Widths

KH4

1600

SB0, 1 Set-Up Time

SIK4

100

(vs. SCK

)

SB0, 1 Hold Time

KSI4

KCY4

(vs. SCK

)

SCK

SB0, 1 Output

KSO4

= 1k

Note

= 4.5 to 6.0V

300

Delay Time

= 100pF

1000

SCK

SB0, 1

KSB

KCY4

SB0,1

SCK

SBK

KCY4

SB0, 1 Low-Level Width

SBL

KCY4

SB0, 1 High-Level Width

SBH

KCY4

Note R

and C

are load resistance and load capacitance of the SB0 and SB1 output lines.

PD75P048

A/D CONVERTER (T

= -10 to +70

C, V

= 2.7 to 6.0V, AV

= V

= 0V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Absolute Accuracy

Note 1

2.5V

REF

1.5

LSB

Conversion Time

Note 2

CONV

168/f

Sampling Time

Note 3

SAMP

44/f

Analog Input Voltage

IAN

REF-

REF+

Analog Supply Voltage

2.5

Reference Input Voltage

REF+

2.5V

(AV

ref+

) (AV

ref-

)

2.5

Reference Input Voltage

REF-

2.5V

(AV

ref+

) (AV

ref-

)

1.0

Analog Input Impedance

1000

REF

Current

REF

0.25

2.0

Note 1. Absolute accuracy excluding quantization error (

LSB)

2. Time since execution of conversion start instruction until end of conversion (EOC = 1) (40.1

s: f

= 4.19

MHz)

3. Time since execution of conversion start instruction until end of sampling (10.5

s: f

= 4.19 MHz)

PD75P048

EEPROM CHARACTERISTICS

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply current for

DD7

4.19MHz crystal oscillator V

= 5V+10%

Note 2

6.5

EEPROM access

Note 1

C1 = C = 22pF

= 3V+10%

Note 3

Note 1. Current flowing through the internal pull-up resistor is not included.

2. When the processor clock control register (PCC) is set to 0011 and the high-speed mode is used.

3. When PCC is set to 0000 and the low-speed mode is used.

EEPROM WRITE TIME

Select the write time of the EEPROM in accordance with the oscillation frequency of the main system clock

as follows:

Oscillation Frequency of Main

Setting of EEPROM Control Register

Write time

System Clock (f

)

EWTC1

EWTC0

= 2.0 to 5.0 MHz

x 18/f

(17.6 ms)

= 2.0 to 4.2 MHz

x 18/f

(8.8 ms)

= 2.0 MHz

x 18/f

Remarks ( ): f

= 4.19 MHz

LOW-VOLTAGE DATA RETENTION CHARACTERISTICS OF DATA MEMORY IN STOP MODE

= 10 to +70

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data Retention Supply

DDDR

2.0

6.0

Voltage

DDDR

= 2.0 V

0.1

Release Signal Set Time

SREL

WAIT

Released by RESET

Released by interrupt request

Note 1. Does not include current flowing through internal pull-up resistor

2. The oscillation stabilization wait time is the time during which the CPU is stopped to prevent unstable

operation when oscillation is started.

3. Depends on the setting of the basic interval timer mode register (BTM) as follows:

BTM3

BTM2

BTM1

BTM0

WAIT time ( ): f

= 4.19 MHz

(approx. 250 ms)

(approx. 31.3 ms)

(approx. 7.82 ms)

(approx. 1.95 ms)

Oscillation Stabilization
Wait Time

Note 2

Data Retention Supply
Current

Note 1

Note 3

PD75P048

6. PERFORMANCE CURVE (REFERENCE VALUE)

Note

Does not include current flowing through EEPROM.

XT1

XT2

Crystal
oscillator

4.19 MHz

32.768 kHz

22 pF

330 k

Supply voltage V

[V]

vs V

(Crystal oscillation)

(T = 25

5.0

1.0

0.5

0.1

0.05

0.01

0.005

0.001

Supply current I

[mA]

High-speed mode PCC = 0011

Main system clock
HALT mode

Subsystem clock HALT mode

Subsystem clock oscillation

Medium-speed mode

PCC = 0010

Low-speed mode PCC = 0000

Main system clock STOP mode

Main system clock stopped

Subsystem clock operation mode

Main system lock stopped

PD75P048

7. PACKAGE DRAWINGS

F
D

NOTE

Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.

P64C-70-750A,C-1

ITEM

MILLIMETERS

INCHES

58.68 MAX.

1.778 (T.P.)

3.2±0.3

0.51 MIN.

4.31 MAX.

1.78 MAX.

0.17

0.25

19.05 (T.P.)

5.08 MAX.

17.0

0~15°

0.50±0.10

0.9 MIN.

2.311 MAX.

0.070 MAX.

0.020

0.035 MIN.

0.126±0.012

0.020 MIN.

0.170 MAX.

0.200 MAX.

0.750 (T.P.)

0.669

0.010

0.007

0~15°

+0.004

0.003

0.070 (T.P.)

Item "K" to center of leads when formed parallel.

+0.10

0.05

+0.004

0.005

64 PIN PLASTIC SHRINK DIP (750 mil)

PD75P048

64 PIN PLASTIC QFP ( 14)

detail of lead end

5°±5°

P64GC-80-AB8-2

ITEM

MILLIMETERS

INCHES

17.6±0.4

14.0±0.2

1.0

0.35±0.10

0.15

14.0±0.2

0.693±0.016

0.039

0.006

0.031 (T.P.)

0.551

NOTE

0.15

1.8±0.2

0.8 (T.P.)

0.006

+0.004

0.003

Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.

0.071±0.008

0.014

0.551

0.8±0.2

0.031

2.55

0.100

0.693±0.016

17.6±0.4

1.0

+0.009

0.008

0.1±0.1

0.004±0.004

2.85 MAX.

0.112 MAX.

+0.10

0.05

+0.009

0.008

+0.004

0.005

+0.009

0.008

PD75P048

8. RECOMMENDED SOLDERING CONDITIONS

It is recommended that

PD75P048 be soldered under the following conditions. For details on the recommended

soldering conditions, refer to Information Document "Semiconductor Devices Mounting Manual" (IEI-1207). For

other soldering methods and conditions, consult NEC.

Table 8-1 Soldering Conditions of Surface-Mount Type

PD75P048GC-AB8: 64-pin plastic QFP (

14 mm)

Soldering Method

Soldering Conditions

Symbol for Recommended
Condition

Infrared Reflow

Package peak temperature: 235

IR35-00-2

time: 30 seconds max. (210

C min.),

number of times: 2 max.
<Caution>
(1) Start second reflow after device temperature
(which has risen because of first reflow) has returned to
room temperature.
(2) Do not clean flux with water after first reflow.

VPS

Package peak temperature: 215

VP15-00-2

time: 40 seconds max. (200

C min.),

number of times: 1 max.
<Caution>
(1) Start second reflow after device temperature
(which has risen because of first reflow) has returned to
room temperature.
(2) Do not clean flux with water after first reflow.

Pin Partial Heating

Pin temperature: 300

C max.,

time: 3 seconds max. (per side)

Caution Do not use two or more soldering methods in combination (except the pin partial heating method).

Table 8-2 Soldering Conditions of Through-Hole Type

PD75P048CW: 64-pin plastic shrink DIP (750 mil)

Soldering Method

Soldering Conditions

Wave soldering

Soldering bath temperature: 260

C max.,

(lead parts only)

time: 10 seconds max.,

Pin Partial Heating

Pin temperature: 260

C max.,

time: 10 seconds max.

Caution The wave soldering must be performed at the lead part only. Note that the soldering must not be

directly contacted to the board.

PD75P048

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are readily available to support development of systems using

PD75P048:

Hardware

IE-75000-R

Note 1

In-circuit emulator for 75X series

IE-75001-R

IE-75000-R-EM

Note 2

Emulation board for IE-75000-R and IE-75001-R

EP-75028CW-R

Common emulation probe commonly used with

PD75028CW

EP-75028GC-R

Emulation probe commonly used with

PD75028GC, provided with

EV-9200GC-64, 64-pin conversion socket

PG-1500

PROM programmer

PA-75P036CW

PROM programmer adapter commonly used with

PD75P036. It is connected

to PG-1500.

PA-75P036GC

PROM programmer adapter commonly used with

PD75P036GC. It is connected

to PG-1500.

Software

IE Control Program

Host machine

PG-1500 Controller

PC-9800 series (MS-DOS

Ver. 3.30 to Ver. 5.00A

Note 3

)

RA75X Relocatable

IBM PC/AT

(Refer to OS for IBM PC.)

Assembler

Note 1. Maintenance product

2. Not provided with IE-75001-R.

3. Ver. 5.00/5.00A has a task swap function, but this function cannot be used with this software.

Remarks For development tools from other companies, refer to 75X Series Selection Guide (IF-1027).

OS for IBM PC

As OS for IBM PC, the followings are supported.

Version

PC DOS

Ver. 5.02 to Ver. 6.1

MS-DOS

Ver. 3.30 to Ver. 5.00A

Note 1

5.0/V

Note 2

IBM DOS

J5.02/V

Note 2

Note 1. Version later than 5.0 have a task swap function, but this function cannot be used with this software.

2. This supports English mode only.

EV-9200GC-64

PD75P048

APPENDIX B. RELATED DOCUMENTS

Documents related to device

Document

Document No.

User's manual

IEU-1278

Instruction list

75X series selection guide

IF-1027

Documents related to development tools

Doument

Document No.

Hardware

IE-75000-R/IE-75001-R user's manual

EEU-1416

IE-75000-R-EM user's manual

EEU-1294

EP-750028CW-R user's manual

EEU-1314

EP-75028GC-R user's manual

EEU-1306

PG-1500 user's manual

EEU-1335

Software

RA75X assembler package user's manual

Operation

EEU-1346

Language

EEU-1343

PG-1500 controller user's manual

EEU1291

Other related documents

Document

Document No.

Package manual

IEI-1213

Semiconductor device - mounting maual

IEI-1207

NEC semiconductor device quality grade

IEI-1209

NEC semiconductor device reliabiliy quality control

Static electricity discharge (ESD) test

Semiconductor device quality guarantee guide

MEI-1202

Product guide related to microcomputer - other manufacturers

Note The documents listed above are subject to change without notice. Be sure to use the latest document

for designing.

PD75P048

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused

pins must be judged device by device and related specifications governing the

devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immedi-

ately after power-on for devices having reset function.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation

Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,

Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.

Special:

Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.

M4 92.6

NEC is manufacturing and selling the products under microcomputer (with

on-chip EEPROM) patent license with the BULL CP8.

This product should not be used for IC cards (SMART CARD).

[MEMO]

MS-DOS is a trademark of Microsoft Corporation.

IBM DOS, PC/AT and PC DOS are trademarks of IBM Corporation.

PD75P048

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75P048CW

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD75P048CW