1994

The µPD75P3018 replaces the µPD753017's internal mask ROM with a one-time PROM, and features expanded ROM

capacity.

Because the µPD75P3018 supports programming by users, it is suitable for use in evaluations of systems in

development stages using the µPD753012, 753016, or 753017, and for use in small-scale production.

The following document describes further details of the functions. Please make sure to read this document

before starting design.

µPD753017 User's Manual : U11282E

FEATURES

Compatible with µPD753017

Memory capacity:

· PROM : 32768 x 8 bits

· RAM

: 1024 x 4 bits

Can operate in same power supply voltage as the mask version µPD753017

· V

= 2.2 to 5.5 V

LCD controller/driver

ORDERING INFORMATION

Part Number

Package

PROM (

8 bits)

µPD75P3018GC-3B9

80-pin plastic QFP (14 x 14 mm, 0.65-mm pitch)

32768

µPD75P3018GK-BE9

80-pin plastic TQFP (fine pitch) (12 x 12 mm, 0.5-mm pitch)

32768

Caution Mask-option pull-up resistors are not provided in this device.

Document No. U10956EJ1V0DS00 (1st edition)
(Previous No. IP-3538)
Date Published August 1996 P
Printed in Japan

The information in this document is subject to change without notice.

PD75P3018

MOS INTEGRATED CIRCUIT

DATA SHEET

4-BIT SINGLE-CHIP MICROCONTROLLER

The mark shows major revised points.

1994

µPD75P3018

FUNCTION OUTLINE

Item

Function

Instruction execution time

· 0.95, 1.91, 3.81, 15.3

µs (main system clock: at 4.19 MHz operation)

· 0.67, 1.33, 2.67, 10.7

µs (main system clock: at 6.0 MHz operation)

· 122

µs (subsystem clock: at 32.768 kHz operation)

Internal memory

PROM

32768 x 8 bits

RAM

1024 x 4 bits

General-purpose register

· 4 bit-operation: 8

4 banks

· 8 bit-operation: 4

4 banks

Input/output port

CMOS input

On-chip pull-up resistor connection can be specified by using software: 23

CMOS input/output

CMOS output

Also used for segment pins

N-ch open drain input/output

13-V breakdown voltage

Total

LCD controller/driver

· Segment number selection : 24/28/32 segments (can be changed to CMOS

output port in 4 time-unit; max. 8)

· Display mode selection

: Static 1/2 duty (1/2 bias)

1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)

Timer

5 channels:
· 8-bit timer/event counter: 3 channels (can be used for 16-bit timer/event counter)
· Basic interval timer/watchdog timer: 1 channel
· Watch timer: 1 channel

Serial interface

· 3-wire serial I/O mode ... MSB or LSB can be selected for transferring top bit
· 2-wire serial I/O mode
· SBI mode

Bit sequential buffer (BSB)

16 bits

Clock output (PCL)

, 524, 262, 65.5 kHz (main system clock: at 4.19 MHz operation)

, 750, 375, 93.8 kHz (main system clock: at 6.0 MHz operation)

Buzzer output (BUZ)

· 2, 4, 32 kHz

(main system clock: at 4.19 MHz operation
or subsystem clock: at 32.768 kHz operation)

· 2.86, 5.72, 45.8 kHz (main system clock: at 6.0 MHz operation)

Vectored interrupts

· External : 3
· Internal : 5

Test input

· External : 1
· Internal : 1

System clock oscillator

· Ceramic or crystal oscillator for main system clock oscillation
· Crystal oscillator for subsystem clock oscillation

Standby function

STOP/HALT mode

Power supply voltage

= 2.2 to 5.5 V

Package

· 80-pin plastic QFP (14 x 14 mm)
· 80-pin plastic TQFP (fine pitch) (12 x 12 mm)

µPD75P3018

CONTENTS

1. PIN CONFIGURATION (Top View) ..................................................................................................

2. BLOCK DIAGRAM ...........................................................................................................................

3. PIN FUNCTIONS ..............................................................................................................................

3.1

Port Pins ....................................................................................................................................................

3.2

Non-port Pins ............................................................................................................................................

3.3

Pin Input/Output Circuits .......................................................................................................................... 10

3.4

Recommended Connection for Unused Pins ......................................................................................... 12

4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE .......................................................... 13

4.1

Difference between Mk I Mode and Mk II Mode ...................................................................................... 13

4.2

Setting of Stack Bank Selection Register (SBS) .................................................................................... 14

5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017 ....................... 15

6. MEMORY CONFIGURATION ........................................................................................................... 16

7. INSTRUCTION SET .......................................................................................................................... 20

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................... 30

8.1

Operation Modes for Program Memory Write/Verify ............................................................................. 30

8.2

Program Memory Write Procedure .......................................................................................................... 31

8.3

Program Memory Read Procedure .......................................................................................................... 32

8.4

One-time PROM Screening ...................................................................................................................... 33

9. ELECTRICAL CHARACTERISTICS ................................................................................................ 34

10. PACKAGE DRAWINGS ................................................................................................................... 48

11. RECOMMENDED SOLDERING CONDITIONS ................................................................................ 50

APPENDIX A µPD75316B, 753017 AND 75P3018 FUNCTION LIST ................................................... 51

APPENDIX B DEVELOPMENT TOOLS ................................................................................................ 53

APPENDIX C RELATED DOCUMENTS ................................................................................................ 57

µPD75P3018

1. PIN CONFIGURATION (Top View)

· 80-pin plastic QFP (14

14 mm)

µPD75P3018GC-3B9

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

µPD75P3018GK-BE9

PIN IDENTIFICATIONS

P00-P03

: Port0

S0-31

: Segment Output 0-31

P10-P13

: Port1

COM0-3

: Common Output 0-3

P20-P23

: Port2

LC0-2

: LCD Power Supply 0-2

P30-P33

: Port3

BIAS

: LCD Power Supply Bias Control

P40-P43

: Port4

LCDCL

: LCD Clock

P50-P53

: Port5

SYNC

: LCD Synchronization

P60-P63

: Port6

TI0-2

: Timer Input 0-2

P70-P73

: Port7

PTO0-2

: Programmable Timer Output 0-2

BP0-BP7

: Bit Port 0-7

BUZ

: Buzzer Clock

KR0-KR7

: Key Return 0-7

PCL

: Programmable Clock

SCK

: Serial Clock

INT0, 1, 4

: External Vectored Interrupt 0, 1, 4

: Serial Input

INT2

: External Test Input 2

: Serial Output

X1, 2

: Main System Clock Oscillation 1, 2

SB0, 1

: Serial Bus 0,1

XT1, 2

: Subsystem Clock Oscillation 1, 2

RESET

: Reset

: Programming Power Supply

MD0-MD3

: Mode Selection 0-3

: Positive Power Supply

D0-D7

: Data Bus 0-7

Vss

: Ground

S11

S10

RESET

P73/KR7

P72/KR6

P71/KR5

P70/KR4

P63/KR3

P62/KR2

P61/KR1

S12
S13
S14
S15

S16

S17

S18

S19

S20

S21

S22

S23

S24/BP0

S25/BP1

S26/BP2

S27/BP3

S28/BP4

S29/BP5

S30/BP6

S31/BP7

COM0

COM1

COM2

COM3

BIAS

LC0

LC1

LC2

P40/D0

P41/D1

P42/D2

P43/D3

Vss

P50/D4

P51/D5

P52/D6

P53/D7

P00/INT4

P01/SCK

P02/SO/SB0

P60/KR0
X2
X1
V

XT2

XT1

P33/MD3

P32/MD2

P31/SYNC/MD1

P30/LCDCL/MD0

P23/BUZ

P22/PCL/PTO2

P21/PTO1

P20/PTO0

P13/TI0

P12/INT2/TI1/TI2

P11/INT1

P10/INT0

P03/SI/SB1

µPD75P3018

PORT0

P00 to P03

PORT1

P10 to P13

PORT2

P20 to P23

PORT3

P30 to P33
/MD0 to MD3

PORT4

P40/D0 to
P43/D3

PORT5

P50/D4 to
P53/D7

PORT6

P60 to P63

PORT7

P70 to P73

LCD

CONTROLLER

/DRIVER

S0 to S23

S24/BP0 to
S31/BP7

COM0 to
COM3

LC0

to V

LC2

BIAS

LCDCL/P30

SYNC/P31

LCD

RESET

CPU CLOCK

STAND BY

CONTROL

XT2

XT1

SYSTEM CLOCK
GENERATOR

MAIN

SUB

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

fx/2

PCL/P22

GENERAL

REG.

RAM

DATA

MEMORY

1024 x 4 BITS

BANK

SBS

SP (8)

ALU

DECODE

AND

CONTROL

TIMER/EVENT

COUNTER

PTO1/P21

INT1

TIMER/EVENT

COUNTER

PTO2/P22/PCL

INT2

BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER

INTBT

TIMER/EVENT

COUNTER

TI0/P13

INT 0

CLOCKED
SERIAL
INTERFACE

SI/SB1/P03

INTCSI

INTERRUPT
CONTROL

INT0/P10

TI1/TI2/

P12/INT2

PTO0/P20

TOUT0

WATCH
TIMER

INTW

BUZ/P23

LCD

SO/SB0/P02

SCK/P01

TOUT0

INT1/P11
INT2/P12
INT4/P00

KR0/P60 to

KR7/P73

BIT SEQ.
BUFFER (16)

PROGRAM

COUNTER

(15)

PROM

PROGRAM

MEMORY

32768 x 8 BITS

TOUT0

2. BLOCK DIAGRAM

µPD75P3018

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin name

I/O

Shared by

Function

8-bit

Status

I/O circuit

I/O

after reset

type

Note 1

P00

Input

INT4

This is a 4-bit input port (PORT0).

Input

P01 to P03 are 3-bit pins for which an internal

P01

I/O

SCK

pull-up resistor connection can be specified

<F>-A

by software.

P02

I/O

SO/SB0

<F>-B

P03

I/O

SI/SB1

<M>-C

P10

Input

INT0

This is a 4-bit input port (PORT1).

Input

-C

These are 4-bit pins for which an internal pull-up

P11

INT1

resistor connection can be specified by software.
INT0 includes noise elimination function.

P12

TI1/TI2/INT2

P13

TI0

P20

I/O

PTO0

This is a 4-bit I/O port (PORT2).

Input

E-B

These are 4-bit pins for which an internal pull-up

P21

PTO1

resistor connection can be specified by software.

P22

PCL/PTO2

P23

BUZ

P30

I/O

LCDCL/MD0

This is a programmable 4-bit I/O port (PORT3).

Input

E-B

Input and output in single-bit units can be specified.

P31

SYNC/MD1

When set for 4-bit units, an internal pull-up resistor
connection can be specified by software.

P32

MD2

P33

MD3

P40

Note 2

I/O

This is an N-ch open-drain 4-bit I/O port (PORT4).

High

M-E

When set to open-drain, voltage is 13 V.

impedance

P41

Note 2

Also functions as data I/O pin (lower 4 bits)
for program memory (PROM) write/verify.

P42

Note 2

P43

Note 2

P50

Note 2

I/O

This is an N-ch open-drain 4-bit I/O port (PORT5).

High

M-E

When set to open-drain, voltage is 13 V.

impedance

P51

Note 2

Also functions as data I/O pin (upper 4 bits)
for program memory (PROM) write/verify.

P52

Note 2

P53

Note 2

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. Low-level input leakage current increases when input instructions or bit manipulation instructions are executed.

µPD75P3018

3.1 Port Pins (2/2)

Pin name

I/O

Shared by

Function

8-bit

Status

I/O circuit

I/O

after reset

type

Note 1

P60

I/O

KR0

This is a programmable 4-bit I/O port (PORT6).

Input

<F>-A

Input and output in single-bit units can be specified.

P61

KR1

When set for 4-bit units, an internal pull-up resistor
connection can be specified by software.

P62

KR2

P63

KR3

P70

I/O

KR4

This is a 4-bit I/O port (PORT7).

Input

<F>-A

When set for 4-bit units, an internal pull-up resistor

P71

KR5

connection can be specified by software.

P72

KR6

P73

KR7

BP0

Output

S24

1-bit I/O port (BIT PORT). These pins are also used

Note 2

H-A

as segment output pin.

BP1

S25

BP2

S26

BP3

S27

BP4

Output

S28

BP5

S29

BP6

S30

BP7

S31

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input.

2. V

LC1

is selected as the input source for BP0 to BP7. The output level varies depending on the external circuit

for BP0 to BP7 and V

LC1

Example: As shown below, BP0 to BP7 are mutually connected via the µPD75P3018, so the output levels of BP0 to BP7

are determined by the sizes of R

, R

, and R

LC1

BP0

BP1

PD75P3018

µPD75P3018

3.2 Non-port Pins (1/2)

Pin name

I/O

Shared by

Function

Status

I/O circuit

after reset

type

Note

TI0

Input

P13

External event pulse input to timer/event counter

Input

-C

TI1, TI2

Input

P12/INT2

PTO0

I/O

P20

Timer/event counter output

Input

E-B

PTO1

P21

PTO2

P22

PCL

Output

P22

Clock output

Input

E-B

BUZ

I/O

P23

Frequency output (for buzzer or system clock trimming)

Input

E-B

SCK

I/O

P01

Serial clock I/O

Input

<F>-A

SO/SB0

I/O

P02

Serial data output

Input

<F>-B

Serial data bus I/O

SI/SB1

I/O

P03

Serial data input

Input

<M>-C

Serial data bus I/O

INT4

Input

P00

Edge detection vectored interrupt input

Input

(valid for detecting both rising and falling edges)

INT0

Input

P10

Edge detection vectored interrupt input Clock synch/asynch

Input

-C

(detected edge is selectable)

is selectable

INT1

P11

Asynch

INT2

Input

P12/TI1/TI2

Rising edge detection test input

Asynch

Input

-C

KR0-KR3

I/O

P60-P63

Parallel falling edge detection test input

Input

<F>-A

KR4-KR7

I/O

P70-P73

Parallel falling edge detection test input

Input

<F>-A

Input

Ceramic/crystal oscillation circuit connection for main system

clock. If using an external clock, input to X1 and input

inverted phase to X2.

XT1

Input

Crystal oscillation circuit connection for subsystem clock.

If using an external clock, input to XT1 and input inverted

XT2

phase to XT2. XT1 can be used as a 1-bit (test) input.

RESET

Input

System reset input

MD0

I/O

P30/LCDCL

Mode selection for program memory (PROM) write/verify

Input

E-B

MD1

P31/SYNC

MD2, MD3

P32, P33

D0-D3

I/O

P40-P43

Data bus for program memory (PROM) write/verify

Input

M-E

D4-D7

P50-P53

Programmable power supply voltage for program memory

(PROM) write/verify.
For normal operation, connect directly to V

Apply +12.5 V for PROM write/verify.

Positive power supply

Vss

Ground

Note

Circuit types enclosed in brackets indicate Schmitt trigger input.

µPD75P3018

3.2 Non-port Pins (2/2)

Pin name

I/O

Shared by

Function

Status

I/O circuit

after reset

type

S0-S23

Output

Segment signal output

Note 1

G-A

S24-S31

Output

BP0-BP7

Segment signal output

Note 1

H-A

COM0-COM3 Output

Common signal output

Note 1

G-B

LC0-

LC2

Power source for LCD driver

BIAS

Output

Output for external split resistor cut

High

impedance

LCDCL

Note 2

I/O

P30

Clock output for driving external expansion driver

Input

E-B

SYNC

Note 2

I/O

P31

Clock output for synchronization of external expansion driver

Input

E-B

Notes 1. The V

LCX

(X = 0, 1, 2) shown below are selected as the input source for the display outputs.

S0-S31: V

LC1

, COM0-COM2: V

LC2

, COM3: V

LC0

2. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

µPD75P3018

1 0

3.3 Pin Input/Output Circuits

The input/output circuits for the µPD75P3018's pins are shown in abbreviated form below.

P-ch

N-ch

P-ch

N-ch

OUT

Data

Output

disable

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type A

P-ch

P.U.R.
enable

P.U.R.

P.U.R. : Pull-Up Resistor

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R. : Pull-Up Resistor

Type B

CMOS standard input buffer

Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).

Schmitt trigger input with hysteresis characteristics.

(Continued)

TYPE A

TYPE D

TYPE E-B

TYPE B

TYPE B-C

TYPE F-A

µPD75P3018

1 1

TYPE F-B

TYPE H-A

TYPE M-C

TYPE G-A

TYPE G-B

TYPE M-E

Output

disable

P-ch

N-ch

IN/OUT

Data

P-ch

P.U.R.

enable

P.U.R.

Output

disable

(N)

Output

disable

(P)

P.U.R. : Pull-Up Resistor

IN/OUT

Type G-A

Voltage

controller

Type E-B

SEG

data

Output

disable

Bit Port

data

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Output

disable

P.U.R. : Pull-Up Resistor

N-ch

P-ch

OUT

N-ch

P-ch

LC0

LC1

COM

data

LC2

N-ch

P-ch

Pull-up resistor operated only when executing input instructions
(when pins are low level, current flows from V

to pins).

Output

disable

Data

N-ch

IN/OUT

(+13-V
breakdown
voltage)

Note

P-ch

Input instruction

Note

P.U.R.

N-ch

LC2

P-ch

N-ch

P-ch

OUT

LC0

LC1

SEG

data

(+13-V
breakdown
voltage)

µPD75P3018

1 2

3.4 Recommended Connection for Unused Pins

Recommended connection

P00/INT4

Connect to V

or V

P01/SCK

Connect to V

or V

P02/SO/SB0

P03/SI/SB1

Connect to V

P10/INT0, P11/INT1

Connect to V

or V

P12/TI1/TI2/INT2

P13/TI0

P20/PTO0

Input status

:connect to Vss or V

through

P21/PTO1

individual resistor

P22/PTO2/PCL

Output status :open

P23/BUZ

P30/LCDCL/MD0

P31/SYNC/MD1

P32/MD2, P33/MD3

P40-P43

P50-P53

P60/KR0-P63/KR3

P70/KR4-P73/KR7

S0-S23

Open

S24/BP0-S31/BP7

COM0-COM3

LC0

-V

LC2

Connect to Vss

BIAS

Connect to Vss only when V

LC0

to V

LC2

are all not used.

In other cases, leave open.

XT1

Note

Connect to Vss

XT2

Note

Open

Note

When subsystem clock is not used, specify SOS.0 = 1 (indicates that

internal feedback resistor is disconnected).

µPD75P3018

1 3

4. SWITCHING FUNCTION BETWEEN Mk I AND Mk II MODE

Setting a stack bank selection (SBS) register for the µPD75P3018 enables the program memory to be switched between

Mk I mode and Mk II mode. This function is applicable when using the µPD75P3018 to evaluate the µPD753012, 753016,

or 753017.

When the SBS bit 3 is set to 1 : sets Mk I mode (supports Mk I mode for µPD753012, 753016, and 753017)

When the SBS bit 3 is set to 0 : sets Mk II mode (supports Mk II mode for µPD753012, 753016, and 753017)

4.1 Difference between Mk I Mode and Mk II Mode

Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the µPD75P3018.

Table 4-1. Difference between Mk I Mode and Mk II Mode

Item

Mk I Mode

Mk II Mode

Program counter

13-0

14-0

is fixed at 0

Program memory (bytes)

16384

32768

Data memory (bits)

1024 x 4

Stack

Stack bank

Selectable via memory banks 0 to 3

No. of stack bytes

2 bytes

3 bytes

Instruction

BRA !addr1 instruction

Use disabled

Use enabled

CALLA !addr1 instruction

Instruction

CALL !addr instruction

3 machine cycles

4 machine cycles

execution time CALLF !faddr instruction

2 machine cycles

3 machine cycles

Supported mask ROMs

When set to Mk I mode:

When set to Mk II mode:

µPD753012, 753016, and 753017

Caution

The Mk II mode supports a program area exceeding 16 Kbytes for the 75X and 75XL series. Therefore,

this mode is effective for enhancing software compatibility with products that have a program area of

more than 16 Kbytes.

With regard to the number of stack bytes during execution of subroutine call instructions, the usable

area increases by 1 byte per stack compared to the Mk I mode when the Mk II mode is selected.

However, when the CALL !addr and CALLF !faddr instructions are used, the machine cycle becomes

longer by 1 machine cycle. Therefore, if more emphasis is placed on RAM use efficiency and

processing performance than on software compatibility, the Mk I mode should be used.

µPD75P3018

1 4

4.2 Setting of Stack Bank Selection Register (SBS)

Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for doing

this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be

sure to initialize the stack bank selection register to 10XXB

Note

at the beginning of the program. When using the Mk II mode,

be sure to initialize it to 00XXB

Note

Set the desired value for XX.

Figure 4-1. Format of Stack Bank Selection Register

Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When using

instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the instructions.

2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after

RESET input and after setting the stack bank selection register.

SBS3

SBS2

SBS1

SBS0

F84H

Address

SBS

Symbol

Stack area specification

Memory bank 0

Memory bank 1

Memory bank 2

Memory bank 3

Be sure to enter "0" for bit 2.

Mk II mode

Mk I mode

Mode selection specification

µPD75P3018

1 5

5. DIFFERENCES BETWEEN µPD75P3018 AND µPD753012, 753016, AND 753017

The µPD75P3018 replaces the internal mask ROM in the µPD753012, 753016, and 753017 with a one-time PROM and

features expanded ROM capacity. The µPD75P3018's Mk I mode supports the Mk I mode in the µPD753012, 753016,

and 753017 and the µPD75P3018's Mk II mode supports the Mk II mode in the µPD753012, 753016, and 753017.

Table 5-1 lists differences among the µPD75P3018 and the µPD753012, 753016, and 753017. Be sure to check the

differences among these products before using them with PROMs for debugging or prototype testing of application

systems or, later, when using them with a mask ROM for full-scale production.

For the CPU functions and internal hardwares, refer to µPD753017 User's Manual (U11282E).

Table 5-1. Differences between µPD75P3018 and µPD753012, 753016, and 753017

Item

µPD753012

µPD753016

µPD753017

µPD75P3018

Program counter

14 bits

15 bits

Program memory (bytes)

Mask ROM

One-time PROM

During

12288

16384

Mk I mode

During

12288

16384

24576

32768

Mk II mode

Data memory (x 4 bits)

1024

Mask options

Pull-up resistor for

Yes (Can be specified whether to incorporate or not)

No (Cannot incorporate)

PORT4 and PORT5

LCD split resistor

Feed back resistor

Yes (Can be specified with the SOS register whether to

No (Cannot incorporate)

for subsystem clock

incorporate or not)

Wait time

Yes (Can be specified either 2

or 2

)

Note

No (Fixed at 2

)

Note

during RESET

Pin configuration

Pin Nos. 29 to 32

P40 to P43

P40/D0 to P43/D3

Pin Nos. 34 to 37

P50 to P53

P50/D4 to P53/D7

Pin No. 50

P30/LCDCL

P30/LCDCL/MD0

Pin No. 51

P31/SYNC

P31/SYNC/MD1

Pin Nos. 52 and 53

P32, P33

P32/MD2, P33/MD3

Pin No. 57

Other

Noise resistance and noise radiation may differ due to the different circuit sizes and mask
layouts.

Note

For 2

, during 6.0 MHz operation is 21.8 ms, and during 4.19 operation is 31.3 ms.

For 2

, during 6.0 MHz operation is 5.46 ms, and during 4.19 operation is 7.81 ms.

Caution

Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask

ROM versions from the PROM version in a processe between prototype development and full

production, be sure to fully evaluate the mask ROM version's CS (not ES).

*
*

µPD75P3018

1 6

6. MEMORY CONFIGURATION

6.1 Program Counter (PC) ... 15 bits

This is a 15-bit binary counter that stores program memory address data.

Bit 15 is valid during Mk II mode. But PC14 is fixed at zero during Mk I mode, and the lower 14 bits are all valid.

Figure 6-1. Configuration of Program Counter

6.2 Program Memory (PROM) ... 32768 x 8 bits

The program memory consists of 32768 x 8-bit one-time PROM. The program memory address can be selected as shown

below by setting the stack bank selection (SBS) register.

Mk I mode

Mk II mode

Usable address

0000H to 3FFFH

0000H to 7FFFH

Figures 6-2 and 6-3 show the addressing ranges for the program memory and branch instruction and the subroutine call

instruction, during Mk I and Mk II modes.

PC14

PC13

PC12

PC11

PC10

PC9

PC8

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

Fixed at zero during
Mk I mode

µPD75P3018

1 7

Figure 6-2. Program Memory Map (Mk I mode)

MBE

RBE

Internal reset start address (upper 6 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 6 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 6 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 6 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 6 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 6 bits)

INTT0 start address (lower 8 bits)

INTT1, INTT2 start address (upper 6 bits)

INTT1, INTT2 start address (lower 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

2000H

2FFFH

3000H

3FFFH

CALLF

!faddr instruction

entry address

· BR BCDE instruction
· BR BCXA instruction
· BR !addr instruction
· CALL !addr instruction
branch address

Branch/call

address

by GETI

BR $addr instruction

relative branch address

(15 to 1,

+2 to +16)

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

0020H

Remark

For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch

to addresses with changes in the PC's lower 8 bits only.

µPD75P3018

1 8

Figure 6-3. Program Memory Map (Mk II mode)

Caution

To allow the vectored interrupt's 14-bit start address (noted above), set the address within a 16-K area

(0000H to 3FFFH).

Remark

For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to branch
to addresses with changes in the PC's lower 8 bits only.

MBE

RBE

Internal reset start address (upper 6 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 6 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 6 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 6 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 6 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 6 bits)

INTT0 start address (lower 8 bits)

INTT1, INTT2 start address (upper 6 bits)

INTT1, INTT2 start address (lower 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

1FFFH

2000H

2FFFH

3000H

3FFFH

4000H

4FFFH

5000H

5FFFH

6000H

6FFFH

7000H

7FFFH

0020H

007FH

0080H

07FFH

0800H

0FFFH

1000H

CALLF

!faddr instruction

entry address

!addr instruction
branch address

CALL

!addr instruction
branch address

Branch/call

address

by GETI

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

Branch addresses for

the following instructions

· BR BCDE
· BR BCXA

· BRA !addr1

· CALLA !addr1

BR $addr1 instruction

relative branch address

(15 to 1,

+2 to +16)

µPD75P3018

1 9

6.3 Data Memory (RAM) ... 1024 x 4 bits

Figure 6-4 shows the data memory configuration.

Data memory consists of a data area and a peripheral hardware area. The data area consists of 1024 x 4-bit static RAM.

Figure 6-4. Data Memory Map

Note

Memory bank 0, 1, 2, or 3 can be selected as the stack area.

(8 x 4)

256 x 4

(248 x 4)

256 x 4

(224 x 4)

(32 x 4)

256 x 4

128 x 4

000H

01FH

020H

0FFH

100H

1DFH

1E0H

1FFH

200H

2FFH

300H

3FFH

F80H

FFFH

General-purpose register area

Display data memory

Data area

static RAM

(1024 x 4)

Stack area

Note

Peripheral hardware area

Data memory

Memory bank

Not incorporated

µPD75P3018

2 0

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction's operand area, use the following coding format to describe operands corresponding to the instruction's

operand representations (for further description, see the RA75X Assembler Package User's Manual Language (EEU-

1363)). When there are several codes, select and use just one. Codes that consist of upper-case letters and + or symbols

are key words that should be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (For details, refer to the User's

Manual). The number of labels that can be entered for fmem and pmem are restricted.

Representation

Coding format

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label

Note

bit

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

pmem

FC0H-FFFH immediate data or label

addr

0000H-3FFFH immediate data or label (Mk I mode and Mk II mode)

addr1

0000H-7FFFH immediate data or label (Mk II mode only)

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H-7FH immediate data (however, bit0 = 0) or label

PORTn

PORT0-PORT7

IEXXX

IEBT, IECSI, IET0, IET1, IET2, IE0-IE2, IE4, IEW

RBn

RB0-RB3

MBn

MB0-MB3, MB15

Note

When processing 8-bit data, only even-numbered addresses can be specified.

µPD75P3018

2 1

(2) Operation legend

: A register; 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

: Register pair (DE)

: Register pair (HL)

XA'

: Expansion register pair (XA')

BC'

: Expansion register pair (BC')

DE'

: Expansion register pair (DE')

HL'

: Expansion register pair (HL')

: Program counter

: Stack pointer

: Carry flag; bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn : Port n (n = 0 to 7)

IME

: Interrupt master enable flag

IPS

: Interrupt priority selection register

IEXXX

: Interrupt enable flag

RBS

: Register bank selection register

MBS

: Memory bank selection register

PCC

: Processor clock control register

: Delimiter for address and bit

(XX)

: Addressed data

XXH

: Hexadecimal data

µPD75P3018

2 2

(3) Description of symbols used in addressing area

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

MB = MBS

MBS = 0-3, 15

MB = MBE · MBS

MBS = 0-3, 15

MB = 0

MBE = 1 :

MBE = 0 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr = 0000H-3FFFH

addr, addr1 =

(Current PC) 15 to (Current PC) 1

(Current PC) +2 to (Current PC) +16

caddr = 0000H-0FFFH (PC

= 000B: Mk I or Mk II mode) or

1000H-1FFFH (PC

= 001B: Mk I or Mk II mode) or

2000H-2FFFH (PC

= 010B: Mk I or Mk II mode) or

3000H-3FFFH (PC

= 011B: Mk I or Mk II mode) or

4000H-4FFFH (PC

= 100B: Mk II mode) or

5000H-5FFFH (PC

= 101B: Mk II mode) or

6000H-6FFFH (PC

= 110B: Mk II mode) or

7000H-7F7FH (PC

= 111B: Mk II mode)

faddr = 0000H-07FFH

taddr = 0020H-007FH

addr1 = 0000H-7FFFH (Mk II mode only)

*10

*11

Program memory

addressing

Data memory

addressing

µPD75P3018

2 3

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies as

shown below.

· No skip ..................................................................... S = 0

· Skipped instruction is 1-byte or 2-byte instruction .... S = 1

· Skipped instruction is 3-byte instruction

Note

.............. S = 2

Note

3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution

The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= t

) of the CPU clock

. Use the PCC setting to select among four cycle times.

µPD75P3018

2 4

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Transfer

MOV

A, #n4

A<-n4

String-effect A

reg1, #n4

reg1<-n4

XA, #n8

XA<-n8

String-effect A

HL, #n8

HL<-n8

String-effect B

rp2, #n8

rp2<-n8

A, @HL

A<-(HL)

A, @HL+

2+S

A<-(HL), then L<-L+1

L=0

A, @HL

2+S

A<-(HL), then L<-L1

L=FH

A, @rpa1

A<-(rpa1)

XA, @HL

XA<-(HL)

@HL, A

(HL)<-A

@HL, XA

(HL)<-XA

A, mem

A<-(mem)

XA, mem

XA<-(mem)

mem, A

(mem)<-A

mem, XA

(mem)<-XA

A, reg1

A<-reg1

XA, rp'

XA<-rp'

reg1, A

reg1<-A

rp'1, XA

rp'1<-XA

XCH

A, @HL

A<->(HL)

A, @HL+

2+S

A<->(HL), then L<-L+1

L=0

A, @HL

2+S

A<->(HL), then L<-L1

L=FH

A, @rpa1

A<->(rpa1)

XA, @HL

XA<->(HL)

A, mem

A<->(mem)

XA, mem

XA<->(mem)

A, reg1

A<->reg1

XA, rp'

XA<->rp'

Table

MOVT

XA, @PCDE

XA<-(PC

13-8

+DE)

ROM

reference

XA, @PCXA

XA<-(PC

13-8

+XA)

ROM

XA, @BCDE

XA<-(BCDE)

ROM

Note

*11

XA, @BCXA

XA<-(BCXA)

ROM

Note

*11

Note

Only the lower 3 bits in the B register are valid.

µPD75P3018

2 5

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Bit transfer

MOV1

CY, fmem.bit

CY<-(fmem.bit)

CY, pmem.@L

CY<-(pmem

7-2

3-2

.bit(L

1-0

))

CY, @H+mem.bit

CY<-(H+mem

3-0

.bit)

fmem.bit, CY

(fmem.bit)<-CY

pmem.@L, CY

(pmem

7-2

3-2

.bit(L

1-0

))<-CY

@H+mem.bit, CY

(H+mem

3-0

.bit)<-CY

Arithmetic

ADDS

A, #n4

1+S

A<-A+n4

carry

XA, #n8

2+S

XA<-XA+n8

carry

A, @HL

1+S

A<-A+(HL)

carry

XA, rp'

2+S

XA<-XA+rp'

carry

rp'1, XA

2+S

rp'1<-rp'1+XA

carry

ADDC

A, @HL

A, CY<-A+(HL)+CY

XA, rp'

XA, CY<-XA+rp'+CY

rp'1, XA

rp'1, CY<-rp'1+XA+CY

SUBS

A, @HL

1+S

A<-A(HL)

borrow

XA, rp'

2+S

XA<-XArp'

borrow

rp'1, XA

2+S

rp'1<-rp'1XA

borrow

SUBC

A, @HL

A, CY<-A(HL)CY

XA, rp'

XA, CY<-XArp'CY

rp'1, XA

rp'1, CY<-rp'1XACY

AND

A, #n4

A<-A

A, @HL

A<-A

(HL)

XA, rp'

XA<-XA

rp'

rp'1, XA

rp'1<-rp'1

A, #n4

A<-Avn4

A, @HL

A<-Av(HL)

XA, rp'

XA<-XAvrp'

rp'1, XA

rp'1<-rp'1vXA

XOR

A, #n4

A<-Avn4

A, @HL

A<-Av(HL)

XA, rp'

XA<-XAvrp'

rp'1, XA

rp'1<-rp'1vXA

Accumulator

RORC

CY<-A

, A

<-CY, A

n-1

<-A

manipulation

NOT

A<-A

Increment/

INCS

reg

1+S

reg<-reg+1

reg=0

decrement

rp1

1+S

rp1<-rp1+1

rp1=00H

@HL

2+S

(HL)<-(HL)+1

(HL)=0

mem

2+S

(mem)<-(mem)+1

(mem)=0

DECS

reg

1+S

reg<-reg1

reg=FH

rp'

2+S

rp'<-rp'1

rp'=FFH

µPD75P3018

2 6

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Comparison

SKE

reg, #n4

2+S

Skip if reg=n4

reg=n4

@HL, #n4

2+S

Skip if (HL)=n4

(HL)=n4

A, @HL

1+S

Skip if A=(HL)

A=(HL)

XA, @HL

2+S

Skip if XA=(HL)

XA=(HL)

A, reg

2+S

Skip if A=reg

A=reg

XA, rp'

2+S

Skip if XA=rp'

XA=rp'

Carry flag

SET1

CY<-1

manipulation

CLR1

CY<-0

SKT

1+S

Skip if CY=1

CY=1

NOT1

CY<-CY

Memory bit

SET1

mem.bit

(mem.bit)<-1

manipulation

fmem.bit

(fmem.bit)<-1

pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

))<-1

@H+mem.bit

(H+mem

3-0

.bit)<-1

CLR1

mem.bit

(mem.bit)<-0

fmem.bit

(fmem.bit)<-0

pmem.@L

(pmem

7-2

3-2

.bit(L

1-0

))<-0

@H+mem.bit

(H+mem

3-0

.bit)<-0

SKT

mem.bit

2+S

Skip if(mem.bit)=1

(mem.bit)=1

fmem.bit

2+S

Skip if(fmem.bit)=1

(fmem.bit)=1

pmem.@L

2+S

Skip if(pmem

7-2

3-2

.bit(L

1-0

))=1

(pmem.@L)=1

@H+mem.bit

2+S

Skip if(H+mem

3-0

.bit)=1

(@H+mem.bit)=1

SKF

mem.bit

2+S

Skip if(mem.bit)=0

(mem.bit)=0

fmem.bit

2+S

Skip if(fmem.bit)=0

(fmem.bit)=0

pmem.@L

2+S

Skip if(pmem

7-2

3-2

.bit(L

1-0

))=0

(pmem.@L)=0

@H+mem.bit

2+S

Skip if(H+mem

3-0

.bit)=0

(@H+mem.bit)=0

SKTCLR

fmem.bit

2+S

Skip if(fmem.bit)=1 and clear

(fmem.bit)=1

pmem.@L

2+S

Skip if(pmem

7-2

3-2

.bit (L

1-0

))=1 and clear

(pmem.@L)=1

@H+mem.bit

2+S

Skip if(H+mem

3-0

.bit)=1 and clear

(@H+mem.bit)=1

AND1

CY, fmem.bit

CY<-CY

(fmem.bit)

CY, pmem.@L

CY<-CY

(pmem

7-2

3-2

.bit(L

1-0

))

CY, @H+mem.bit

CY<-CY

(H+mem

3-0

.bit)

OR1

CY, fmem.bit

CY<-CYv(fmem.bit)

CY, pmem.@L

CY<-CYv(pmem

7-2

3-2

.bit(L

1-0

))

CY, @H+mem.bit

CY<-CYv(H+mem

3-0

.bit)

XOR1

CY, fmem.bit

CY<-CYv (fmem.bit)

CY, pmem.@L

CY<-CYv(pmem

7-2

3-2

.bit(L

1-0

))

CY, @H+mem.bit

CY<-CYv(H+mem

3-0

.bit)

µPD75P3018

2 7

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Branch

Note 1

addr

<-0, PC

13-0

<-addr

Use the assembler to select the
most appropriate instruction
among the following.

· BR !addr
· BRCB !caddr
· BR $addr

addr1

14-0

<-addr1

*11

Use the assembler to select
the most appropriate instruction
among the following.

· BRA !addr1
· BR !addr
· BRCB !caddr
· BR $addr1

!addr

<-0, PC

13-0

<-addr

$addr

<-0, PC

13-0

<-addr

$addr1

<-0, PC

13-0

<-addr1

14-0

<-addr1

PCDE

<-0, PC

13-0

<-PC

13-8

+DE

14-0

<-PC

14-8

+DE

PCXA

<-0, PC

13-0

<-PC

13-8

+XA

14-0

<-PC

14-8

+XA

BCDE

<-0, PC

13-0

<-BCDE

Note 2

*11

14-0

<-BCDE

Note 2

BCXA

<-0, PC

13-0

<-BCXA

Note 2

*11

14-0

<-BCXA

Note 2

BRA

Note 1

!addr1

14-0

<-addr1

*11

BRCB

!caddr

<-0, PC

13-0

<-PC

13, 12

+caddr

11-0

14-0

<-PC

14, 13, 12

+caddr

11-0

Notes 1. Shaded areas indicate support for Mk II mode only.

2. The only following bits are valid in the B register.

For Mk I mode : Lower 2 bits

For Mk II mode : Lower 3 bits

µPD75P3018

2 8

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Subroutine

CALLA

Note

!addr1

(SP5)<-0, PC

14-12

*11

stack control

(SP6)(SP3)(SP4)<-PC

11-0

(SP2)<-X, X, MBE, RBE

140

<-addr1, SP<-SP6

CALL

Note

!addr

(SP4)(SP1)(SP2)<-PC

11-0

(SP3)<-MBE, RBE, PC

13, 12

<-0, PC

130

<-addr, SP<-SP4

(SP5)<-0, PC

14-12

(SP6)(SP3)(SP4)<-PC

11-0

(SP2)<-X, X, MBE, RBE

<-0, PC

13-0

<-addr, SP<-SP6

CALLF

Note

!faddr

(SP4)(SP1)(SP2)<-PC

11-0

(SP3)<-MBE, RBE, PC

13, 12

<-0, PC

13-0

<-000+faddr, SP<-SP4

(SP5)<-0, PC

14-12

(SP6)(SP3)(SP4)<-PC

11-0

(SP2)<-X, X, MBE, RBE

14-0

<-0000+faddr, SP<-SP6

RET

Note

MBE, RBE, PC

13, 12

<-(SP+1)

11-0

<-(SP)(SP+3)(SP+2)

<-0, SP<-SP+4

X, X, MBE, RBE<-(SP+4)

0, PC

14-12

<-(SP+1)

11-0

<-(SP)(SP+3)(SP+2)

SP<-SP+6

RETS

Note

3+S

MBE, RBE, PC

13, 12

<-(SP+1)

Unconditional

11-0

<-(SP)(SP+3)(SP+2)

<-0, SP<-SP+4

then skip unconditionally

X, X, MBE, RBE<-(SP+4)

0, PC

14-12

<-(SP+1)

11-0

<-(SP)(SP+3)(SP+2)

SP<-SP+6

then skip unconditionally

RETI

Note

13, 12

<-(SP+1)

1, 0

, PC

<-0

11-0

<-(SP)(SP+3)(SP+2)

PSW<-(SP+4)(SP+5), SP<-SP+6

0, PC

14-12

<-(SP+1)

11-0

<-(SP)(SP+3)(SP+2)

PSW<-(SP+4)(SP+5), SP<-SP+6

Note

Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

µPD75P3018

2 9

Instruction

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip

group

bytes

cycle

area

condition

Subroutine

PUSH

(SP1)(SP2)<-rp, SP<-SP2

stack control

(SP1)<-MBS, (SP2)<-RBS, SP<-SP2

POP

rp<-(SP+1)(SP), SP<-SP+2

MBS<-(SP+1), RBS<-(SP), SP<-SP+2

Interrupt

IME(IPS.3)<-1

control

IEXXX

IEXXX<-1

IME(IPS.3)<-0

IEXXX

IEXXX<-0

I/O

Note 1

A, PORTn

A<-PORTn

(n=0-7)

XA, PORTn

XA<-PORTn+

, PORTn (n=4, 6)

OUT

Note 1

PORTn, A

PORTn<-A

(n=2-7)

PORTn, XA

PORTn+

, PORTn<-XA (n=4, 6)

CPU control

HALT

Set HALT Mode(PCC.2<-1)

STOP

Set STOP Mode(PCC.3<-1)

NOP

No Operation

Special

SEL

RBn

RBS<-n (n=0-3)

MBn

MBS<-n (n=0-3, 15)

GETI

Note 2, 3

taddr

· When using TBR instruction

*10

13-0

<-(taddr)

5-0

+(taddr+1), PC

<-0

· When using TCALL instruction

(SP4)(SP1)(SP2)<-PC

11-0

(SP3)<-MBE, RBE, PC

13, 12

, PC

<-0

13-0

<-(taddr)

5-0

+(taddr+1)

SP<-SP4

· When using instruction other than

Determined by

TBR or TCALL

referenced

Execute (taddr)(taddr+1) instructions

instruction

· When using TBR instruction

*10

13-0

<-(taddr)

5-0

+(taddr+1), PC

<-0

· When using TCALL instruction

(SP5)<-0, PC

14-12

(SP6)(SP3)(SP4)<-PC

11-0

(SP2)<-X, X, MBE, RBE, PC

<-0

13-0

<-(taddr)

5-0

+(taddr+1)

SP<-SP6

· When using instruction other than

Determined by

TBR or TCALL

referenced

Execute (taddr)(taddr+1) instructions

instruction

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction's table definitions.

3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.

- - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - -

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

- - - - - - - - - - - -

µPD75P3018

3 0

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory contained in the µPD75P3018 is a 32768 x 8-bit one-time PROM that can be electrically written one

time only. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the X1

pin is used instead of address input as a method for updating addresses.

Function

Pin where program voltage is applied during program memory
write/verify (usually V

potential)

X1, X2

Clock input pins for address updating during program memory
write/verify. Input the X1 pin's inverted signal to the
X2 pin.

MD0-MD3

Operation mode selection pin for program memory write/verify

D0/P40 to D3/P43

8-bit data I/O pins for program memory write/verify

(lower 4 bits)
D4/P50 to D7/P53
(upper 4 bits)

Pin where power supply voltage is applied.
Applies V

= 2.2 to 5.5 V in normal operation mode and +6 V

for program memory write/verify.

Caution

Pins not used for program memory write/verify should be connected to Vss.

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the V

pin and +12.5 V to the V

pin, the µPD75P3018 enters the program memory write/verify

mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.

Operation mode specification

Operation mode

MD0

MD1

MD2

MD3

+12.5 V

+6 V

Zero-clear program memory address

Write mode

Verify mode

Program inhibit mode

X: L or H

µPD75P3018

3 1

8.2 Program Memory Write Procedure

Program memory can be written at high speed using the following procedure.

(1)

Pull unused pins to Vss through resistors. Set the X1 pin low.

(2)

Supply 5 V to the V

and V

pins.

(3)

Wait 10 µs.

(4)

Select the zero-clear program memory address mode.

(5)

Supply 6 V to the V

and 12.5 V to the V

pins.

(6)

Select the program inhibit mode.

(7)

Write data in the 1 ms write mode.

(8)

Select the program inhibit mode.

(9)

Select the verify mode. If the data is correct, go to step (10) and if not, repeat steps (7) to (9).

(10) (X : number of write operations from steps (7) to (9)) x 1 ms additional write.

(11) Select the program inhibit mode.

(12) Apply four pulses to the X1 pin to increment the program memory address by one.

(13) Repeat steps (7) to (12) until the end address is reached.

(14) Select the zero-clear program memory address mode.

(15) Return the V

and V

pins back to 5 V.

(16) Turn off the power.

The following figure shows steps (2) to (12).

+ 1

D0/P40 to D3/P43
D4/P50 to D7/P53

MD0

(P30)

MD1

(P31)

MD2

(P32)

MD3

(P33)

Data input

Data

output

Data input

X repetitions

Write

Verify

Additional write

Address

increment

µPD75P3018

3 2

8.3 Program Memory Read Procedure

The µPD75P3018 can read program memory contents using the following procedure.

(1)

Pull unused pins to Vss through resistors. Set the X1 pin low.

(2)

Supply 5 V to the V

and V

pins.

(3)

Wait 10 µs.

(4)

Select the zero-clear program memory address mode.

(5)

Supply 6 V to the V

and 12.5 V to the V

pins.

(6)

Select the program inhibit mode.

(7)

Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one

address.

(8)

Select the program inhibit mode.

(9)

Select the zero-clear program memory address mode.

(10) Return the V

and V

pins back to 5 V.

(11) Turn off the power.

The following figure shows steps (2) to (9).

+ 1

D0/P40 to D3/P43
D4/P50 to D7/P53

MD0

(P30)

MD2

(P32)

MD3

(P33)

MD1

(P31)

"L"

Data output

µPD75P3018

3 4

9. ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings (T

= 25 °C)

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

0.3 to +7.0

PROM supply voltage

0.3 to +13.5

Input voltage

Other than ports 4 and 5

0.3 to V

+ 0.3

Ports 4 and 5 (During N-ch open drain)

0.3 to +14

Output voltage

0.3 to V

+ 0.3

High-level output current

Per pin

Total of all pins

Low-level output current

Per pin

Total of all pins

220

Operating ambient

40 to +85

°C

temperature

Storage temperature

stg

65 to +150

°C

Caution

If the absolute maximum rating of even one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. The absolute maximum ratings are therefore values which,

when exceeded, can cause the product to be damaged. Be sure that these values are never exceeded

when using the product.

Capacitance (T

= 25 °C, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V

I/O capacitance

µPD75P3018

3 5

Main System Clock Oscillation Circuit Characteristics (T

= 40 to +85 °C)

Resonator Recomended Constants Parameter Conditions MIN. TYP. MAX. Unit

Ceramic V

= 2.2 to 5.5 V Oscillation frequency 1.0 6.0

Note 2

MHz

resonator (f

)

Note 1

Oscillation After V

has 4 ms

stabilization time

Note 3

reached MIN. value
of oscillation voltage
range

Crystal V

= 2.2 to 5.5 V Oscillation frequency 1.0 6.0

Note 2

MHz

resonator (f

)

Note 1

Oscillation V

= 4.5 to 5.5 V 10 ms

stabilization time

Note 3

External V

= 1.8 to 5.5 V X1 input frequency 1.0 6.0

Note 2

MHz

clock (f

)

Note 1

X1 input high-/ 83.3 500 ns
low-level widths
(t

, t

)

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation circuit

only. For the instruction execution time, refer to AC Characteristics.

2. When the supply voltage is 1.8 V

< 2.7 V and the oscillation frequency is 4.19 MHz < f

6.0 MHz, do

not select processor clock control register (PCC) = 0011 as the instruction execution time. If PCC = 0011, one

machine cycle is less than 0.95

µs, falling short of the rated value of 0.95 µs.

3. The oscillation stabilization time is the time required for oscillation to be stabilized after V

has been applied

or STOP mode has been released.

Caution

When using the main system clock oscillation circuit, wire the portion enclosed in the broken line in

the above figure as follows to prevent adverse influences due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

X1 X2

C1 C2

X1 X2

C1 C2

X1 X2

µPD75P3018

3 6

Subsystem Clock Oscillation Circuit Characteristics (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Resonator Recomended Constants Parameter Conditions MIN. TYP. MAX. Unit

Crystal Oscillation frequency 32 32.768 35 kHz
resonator (f

)

Note 1

Oscillation V

= 4.5 to 5.5 V 1.0 2 s

stabilization time

Note 2

2.2 V 10

External XT1 input frequency 32 100 kHz
clolck (f

)

Note 1

XT1 input high-/ 5 15

µs

low-level widths
(t

XTH

, t

XTL

)

Notes 1. The oscillation frequency and XT1 input frequency shown above indicate characteristics of the oscillation circuit

only. For the instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is the time required for oscillation to be stabilized after V

has been applied.

Caution

When using the subsystem clock oscillation circuit, wire the portion enclosed in the broken line in the

above figure as follows to prevent adverse influences due to wiring capacitance:

· Keep the wiring length as short as possible.

· Do not cross the wiring with other signal lines.

· Do not route the wiring in the vicinity of a line through which a high alternating current flows.

· Always keep the ground point of the capacitor of the oscillation circuit at the same potential as V

· Do not ground to a power supply pattern through which a high current flows.

· Do not extract signals from the oscillation circuit.

The subsystem clock oscillation circuit has a low amplification factor to reduce current dissipation and

is more susceptible to noise than the main system clock oscillation circuit. Therefore, exercise utmost

care in wiring the subsystem clock oscillation circuit.

XT1 XT2

C3 C4

XT1 XT2

µPD75P3018

3 7

DC Characteristics (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-level output I

Per pin 15 mA

current Total of all pins 150 mA

High-level input V

IH1

Ports 2, 3 2.7 V

5.5 V 0.7 V

voltage 2.2 V

< 2.7 V 0.9 V

IH2

Ports 0, 1, 6, 7, RESET 2.7 V

5.5 V 0.8 V

2.2 V

< 2.7 V 0.9 V

IH3

Ports 4, 5 2.7 V

5.5 V 0.7 V

13 V

(During N-ch open drain) 2.2 V

< 2.7 V 0.9 V

13 V

IH4

X1, XT1 V

0.1 V

Low-level input V

IL1

Ports 2, 3, 4, 5 2.7 V

5.5 V 0 0.3 V

voltage 2.2 V

< 2.7 V 0 0.1 V

IL2

Ports 0, 1, 6, 7, RESET 2.7 V

5.5 V 0 0.2 V

2.2 V

< 2.7 V 0 0.1 V

IL3

X1, XT1 0 0.1 V

High-level output V

SCK, SO/SB0, SB1, Ports 2, 3, 6, 7, BP0 to 7 V

0.5 V

voltage I

= 1 mA

Low-level output V

OL1

SCK, SO, Ports 2, 3, 4, 5, 6, 7, I

= 15 mA 0.2 2.0 V

voltage BP0 to 7 V

= 4.5 to 5.5 V

= 1.6 mA 0.4 V

OL2

SB0, SB1 During N-ch open drain 0.2 V

Pull-up resistor

1 k

High-level input I

LIH1

= V

Pins other than X1, XT1 3

µA

leakage current I

LIH2

X1, XT1 20

µA

LIH3

= 13 V Ports 4, 5 (During N-ch open drain) 20

µA

Low-level input I

LIL1

= 0 V Pins other than X1, XT1, Ports 4, 5 3

µA

leakage current I

LIL2

X1, XT1 20

µA

LIL3

Ports 4, 5 (During N-ch open drain) 30

µA

When input instruction V

= 5.0 V 10 27

µA

is executed V

= 3.0 V 3 8

µA

High-level output I

LOH1

OUT

= V

SCK, SO/SB0, SB1, Ports 2, 3, 6, 7 3

µA

leakage current I

LOH2

OUT

= 13 V Ports 4, 5 (During N-ch open drain) 20

µA

Low-level output I

LOL

OUT

= 0 V 3

µA

leakage current

Internal pull-up R

= 0 V Ports 0, 1, 2, 3, 6, 7 (except P00 pin) 50 100 200 k

resistor

µPD75P3018

3 8

DC Characteristics (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

LCD drive voltage V

LCD

VAC0 = 0

2.2

LCD output voltage V

ODC

= ±5

µA

LCD0

= V

LCD

±0.2

deviation

Note 1

LCD1

= V

LCD

2/3

(common)

LCD2

= V

LCD

1/3

LCD output voltage V

ODS

= ±1

µA

2.2 V - V

LCD

- V

±0.2

deviation

Note 1

(segment)

Supply current

Note 2

DD1

6.0 MHz

Note 3

= 5.0 V ±10 %

Note 4

3.7

11.0

crystal

= 3.0 V ±10 %

Note 5

0.73

2.2

DD2

oscillation

HALT

= 5.0 V ±10 %

0.92

2.6

C1 = C2 = 22 pF mode

= 3.0 V ±10 %

0.30

0.9

DD1

4.19 MHz

Note 3

= 5.0 V ±10 %

Note 4

2.7

8.0

crystal

= 3.0 V ±10 %

Note 5

0.57

1.7

DD2

oscillation

HALT

= 5.0 V ±10 %

0.90

2.5

C1 = C2 = 22 pF mode

= 3.0 V ±10 %

0.28

0.8

DD3

32.768

Low-

= 3.0 V ±10 %

126

µA

kHz

Note 6

voltage V

= 2.5 V ±10 %

110

µA

crystal

mode

Note 7

= 3.0 V, T

= 25 °C

µA

oscillation

Low power

dissipation

mode

Note 8

DD4

HALT

Low-

= 3.0 V ±10 %

8.5

µA

mode

voltage V

= 2.5 V ±10 %

5.8

µA

mode

Note 7

= 3.0 V, T

= 25 °C

8.5

µA

Low power

dissipation

mode

Note 8

DD5

XT1 = 0 V

Note 9

= 5.0 V ±10 %

0.05

µA

STOP mode V

= 3.0 V ±10 %

0.02

µA

= 25 °C

0.02

µA

Notes 1. Voltage deviation is the difference between the ideal values (V

LCDn

; n = 0, 1, 2) of the segment and common

outputs and the output voltage.

2. The current flowing through the internal pull-up resistor is not included.

3. Including the case when the subsystem clock oscillates.

4. When the device operates in high-speed mode with the processor clock control register (PCC) set to 0011.

5. When the device operates in low-speed mode with PCC set to 0000.

6. When the device operates on the subsystem clock, with the system clock control register (SCC) set to 1001

and oscillation of the main system clock stopped.

7. When the sub-oscillation control register (SOS) is set to 0000.

8. When the SOS is set to 0010.

9. When the SOS is set to 0011.

= 3.0 V ±10 %

117

µA

= 3.0 V, T

= 25 °C

µA

= 3.0 V ±10 %

3.5

µA

= 3.0 V, T

= 25 °C

3.5

µA

µPD75P3018

3 9

AC Characteristics (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CPU clock cycle time

Note 1

Operation

When ceramic V

= 2.7 to 5.5 V

0.67

µs

(minimum instruction

with

or crystal is used V

= 2.2 to 5.5 V

0.85

µs

execution time

main system When external V

= 2.7 to 5.5 V

0.67

µs

= 1 machine cycle)

clock

clock is used

0.95

µs

Operation with subsystem

114

122

125

µs

clock

TI0, TI1, TI2 input frequency

= 2.7 to 5.5 V

MHz

275

kHz

TI0, TI1, TI2 high-/low-level

TIH

, t

TIL

= 2.7 to 5.5 V

0.48

µs

widths

1.8

µs

Interrupt input high-/low-level t

INTH

, t

INTL

INT0

Note 2

µs

widths

INT1, 2, 4

µs

KR0-7

µs

RESET low-level width

RSL

µs

Notes 1. The cycle time of the CPU clock

(

) is determined by the

oscillation frequency of the

connected resonator (and

external clock), the system clock

control register (SCC), and

processor clock control register

(PCC).

The figure on the right shows the

supply voltage V

vs. cycle time

characteristics when the

device operates with the main

system clock.

2. 2t

or 128/f

depending on the

setting of the interrupt mode

Remark

The shaded portion indicates the range when

the external clock is used.

Operation
guaranteed range

Supply voltage

[V]

0.5

Cycle time t

[

vs V

(with main system clock)

µPD75P3018

4 0

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ... internal clock output): (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY1

= 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level widths t

KL1

, t

KH1

= 2.7 to 5.5 V t

KCY1

/250 ns

KCY1

/2150 ns

Note 1

setup time (to SCK

) t

SIK1

= 2.7 to 5.5 V 150 ns

500 ns

Note 1

hold time (from SCK

) t

KSI1

= 2.7 to 5.5 V 400 ns

600 ns

SCK

Ø Æ

Note 1

output t

KSO1

= 1 k

Note 2

= 2.7 to 5.5 V 0 250 ns

delay time C

= 100 pF 0 1000 ns

2-wire and 3-wire serial I/O modes (SCK ... external clock input): (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY2

= 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level widths t

KL2

, t

KH2

= 2.7 to 5.5 V 400 ns

1600 ns

Note 1

setup time (to SCK

) t

SIK2

= 2.7 to 5.5 V 100 ns

150 ns

Note 1

hold time (from SCK

) t

KSI2

= 2.7 to 5.5 V 400 ns

600 ns

SCK

Ø Æ

Note 1

output t

KSO2

= 1 k

Note 2

= 2.7 to 5.5 V 0 300 ns

delay time C

= 100 pF 0 1000 ns

Notes 1. In 2-wire serial I/O mode, read SB0 or SB1 instead.

2. R

and C

respectively indicate the load resistance and load capacitance of the SO output line.

µPD75P3018

4 1

SBI mode (SCK ... internal clock output (master)): (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY3

= 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-/low-level widths t

KL3

, t

KH3

= 2.7 to 5.5 V t

KCY3

/250 ns

KCY3

/2150 ns

SB0, 1 setup time t

SIK3

= 2.7 to 5.5 V 150 ns

(to SCK

) 500 ns

SB0, 1 hold time (from SCK

) t

KSI3

KCY3

/2 ns

SCK

Ø Æ

SB0, 1 output t

KSO3

= 1 k

Note

= 2.7 to 5.5 V 0 250 ns

delay time C

= 100 pF 0 1000 ns

SCK

SB0, 1

KSB

KCY3

SB0, 1

Ø Æ

SCK

SBK

KCY3

SB0, 1 low-level width t

SBL

KCY3

SB0, 1 high-level width t

SBH

KCY3

SBI mode (SCK ... external clock input (slave)): (T

= 40 to +85 °C, V

= 2.2 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY4

= 2.7 to 5.5 V 800 ns

3200 ns

SCK high-/low-level widths t

KL4

, t

KH4

= 2.7 to 5.5 V 400 ns

1600 ns

SB0, 1 setup time t

SIK4

= 2.7 to 5.5 V 100 ns

(to SCK

) 150 ns

SB0, 1 hold time (from SCK

) t

KSI4

KCY4

/2 ns

SCK

Ø Æ

SB0, 1 output t

KSO4

= 1 k

Note

= 2.7 to 5.5 V 0 300 ns

delay time C

= 100 pF 0 1000 ns

SCK

SB0, 1

KSB

KCY4

SB0, 1

Ø Æ

SCK

SBK

KCY4

SB0, 1 low-level width t

SBL

KCY4

SB0, 1 high-level width t

SBH

KCY4

Note

and C

respectively indicate the load resistance and load capacitance of the SB0, 1 output line.

µPD75P3018

4 5

Data retention characteristics of data memory in STOP mode and at low supply voltage (T

= 40 to +85 °C)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Release signal setup time

SREL

µs

Oscillation stabilization

WAIT

Released by RESET

wait time

Note 1

Released by interrupt request

Note 2

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent unstable

operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

Wait time

BTM3

BTM2

BTM1

BTM0

= 4.19 MHz

= 6.0 MHz

(approx. 250 ms) 2

(approx. 175 ms)

(approx. 31.3 ms) 2

(approx. 21.8 ms)

(approx. 7.81 ms) 2

(approx. 5.46 ms)

(approx. 1.95 ms) 2

(approx. 1.37 ms)

Data Retention Timing (when STOP mode released by RESET)

Data Retention Timing (standby release signal: when STOP mode released by interrupt signal)

STOP mode

Operation mode

Internal reset operation

Oscillation stabilization wait time

Data retention mode

SREL

WAIT

STOP instruction execution

RESET

DDDR

STOP mode

Operation mode

Oscillation stabilization wait time

Data retention mode

SREL

WAIT

STOP instruction execution

Standby release signal

(interrupt request)

DDDR

µPD75P3018

4 6

DC Programming Characteristics (T

= 25 ± 5 °C, V

= 6.0 ± 0.25 V, V

= 12.5 ± 0.3 V, V

= 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input voltage high V

IH1

Except X1, X2 0.7 V

IH2

X1, X2 V

0.5 V

Input voltage low V

IL1

Except X1, X2 0 0.3 V

IL2

X1, X2 0 0.4 V

Input leakage current I

= V

or V

µA

Output voltage high V

= 1 mA V

1.0 V

Output voltage low V

= 1.6 mA 0.4 V

supply current I

30 mA

supply current I

MD0 = V

, MD1 = V

30 mA

Cautions 1. Ensure that V

does not exceed +13.5 V including overshoot.

2. V

must be applied before V

, and cut after V

AC Programming Characteristics (T

= 25 ± 5 °C, V

= 6.0 ± 0.25 V, V

= 12.5 ± 0.3 V, V

= 0 V)

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit

Address setup time

Note 2

(to MD0

)

µs

MD1 setup time (to MD0

)

M1S

OES

µs

Data setup time (to MD0

)

µs

Address hold time

Note 2

(from MD0

)

µs

Data hold time (from MD0

)

µs

MD0

Data output float delay time t

0 130 ns

setup time (to MD3

)

VPS

µs

setup time (to MD3

)

VDS

VCS

µs

Initial program pulse width t

0.95 1.0 1.05 ms

Additional program pulse width t

OPW

0.95 21.0 ms

MD0 setup time (to MD1

)

M0S

CES

µs

MD0

ØÆ

Data output delay time t

MD0 = MD1 = V

µs

MD1 hold time (from MD0

)

M1H

OEH

µs

MD1 recovery time (from MD0

)

M1R

µs

Program counter reset time t

PCR

µs

X1 input high-/low-level width t

, t

-- 0.125

µs

X1 input frequency f

-- 4.19 MHz

Initial mode setting time t

µs

MD3 setup time (to MD1

)

M3S

µs

MD3 hold time (from MD1

)

M3H

µs

MD3 setup time (to MD0

)

M3SR

-- Program memory read 2

µs

Data output delay time from address

Note 2

DAD

ACC

Program memory read 2

µs

Data output hold time from address

Note 2

HAD

Program memory read 0 130

µs

MD3 hold time (from MD0

)

M3HR

-- Program memory read 2

µs

MD3

ØÆ

Data output float delay time t

DFR

-- Program memory read 2

µs

Notes 1. Symbol of corresponding

µPD27C256A

2. The internal address signal is incremented by 1 on the 4th rise of the X1 input, and is not connected to a pin.

M1H

+ t

M1R

µs

µPD75P3018

4 8

10. PACKAGE DRAWINGS

80 PIN PLASTIC QFP ( 14)

detail of lead end

°±

S80GC-65-3B9-3

ITEM

MILLIMETERS

INCHES

17.2

0.4

14.0

0.2

0.8

0.30

0.10

0.13

14.0

0.2

0.677

0.016

0.031

0.005

0.026 (T.P.)

0.551

NOTE

0.10

0.15

1.6

0.2

0.65 (T.P.)

0.004

0.006

+0.004

0.003

Each lead centerline is located within 0.13
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

0.063

0.008

0.012

0.551

0.8

0.2

0.031

2.7

0.106

0.677

0.016

17.2

0.4

0.8

+0.009

0.008

0.1

0.004

3.0 MAX.

0.119 MAX.

+0.10

0.05

+0.009

0.008

+0.004

0.005

+0.009

0.008

µPD75P3018

4 9

80 PIN PLASTIC TQFP (FINE PITCH) ( 12)

ITEM

MILLIMETERS

INCHES

0.5 (T.P.)

0.10

0.004

0.020 (T.P.)

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

14.0

0.2

0.551+0.009

0.008

12.0

0.2

0.472+0.009

0.008

12.0

0.2

0.472+0.009

0.008

14.0

0.2

0.551+0.009

0.008

1.25

0.049

0.22

0.009

0.002

P80GK-50-BE9-4

1.27 MAX.

0.050 MAX.

1.0

0.2

0.039+0.009

0.008

0.5

0.2

0.020+0.008

0.009

0.145

0.006

0.002

0.10

0.004

1.05

0.041

0.05

0.002

°±

+0.05

0.04

+0.055

0.045

detail of lead end

µPD75P3018

5 0

11. RECOMMENDED SOLDERING CONDITIONS

Solder the µPD75P3018 under the following recommended conditions.

For the details on the recommended soldering conditions, refer to Information Document Semiconductor Device

Mounting Technology Manual (C10535E).

For the soldering methods and conditions other than those recommended, consult NEC.

Table 11-1. Soldering Conditions of Surface Mount Type

(1)

µPD75P3018GC-3B9: 80-pin plastic QFP (14

14 mm)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.),

IR35-00-3

Number of times: 3 max.

VPS

Package peak temperature: 215 °C, Time: 40 seconds max. (200 °C min.),

VP15-00-3

Number of times: 3 max.

Wave soldering

Solder temperature: 260 °C max., Time: 10 seconds max.,

WS60-00-1

Number of times: 1
Preheating temperature: 120 °C max. (package surface temperature)

Pin partial heating

Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device)

Caution

Do not use two or more soldering methods in combination (except the pin partial heating method).

(2)

µPD75P3018GK-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

Soldering Method

Soldering Conditions

Symbol

Infrared reflow

IR35-107-2

VPS

VP15-107-2

Wave soldering

WS60-107-1

Pin partial heating

Note The number of days for storage after the dry pack has been opened. The storage conditions are 25 °C, 65 % RH max.

Caution

Do not use two or more soldering methods in combination (except the pin partial heating method).

Package peak temperature: 235 °C, Time: 30 seconds max. (210 °C min.),
Number of times: 2 max., Exposure limit: 7 days

Note

(After that, prebaking is

necessary at 125 °C for 10 hours.)

Package peak temperature: 215 °C, Time: 40 seconds max. (200 °C min.),
Number of times: 2 max., Exposure limit: 7 days

Note

(After that, prebaking is

necessary at 125 °C for 10 hours.)

Solder temperature: 260 °C max., Time: 10 seconds max.,
Number of times: 1,
Preheating temperature: 120 °C max. (package surface temperature)
Exposure limit: 7 days

Note

(After that, prebaking is necessary at 125 °C for 10

hours.)

Pin temperature: 300 °C max., Time: 3 seconds max. (per side of device)

µPD75P3018

5 1

APPENDIX A

µPD75316B, 753017 AND 75P3018 FUNCTION LIST

Parameter

µPD75316B

µPD753017

µPD75P3018

Program memory

Mask ROM

One-time PROM

0000H-3F7FH

0000H-5FFFH

0000H-7FFFH

(16256

8 bits)

(24576

8 bits)

(32768

8 bits)

Data memory

000H-3FFH (1024

4 bits)

CPU

75X Standard

75XL CPU

Instruction

When main system

0.95, 1.91, or 15.3

µs

· 0.95, 1.91, 3.81, or 15.3

µs (at 4.19 MHz operation)

execution time

clock is selected

(at 4.19 MHz operation)

· 0.67, 1.33, 2.67, or 10.7

µs (at 6.0 MHz operation)

When subsystem

122

µs (at 32.768 kHz operation)

clock is selected

Pin connection

29 to 32

P40 to P43

P40/D0 to P43/D3

34 to 37

P50 to P53

P50/D4 to P53/D7

P12/INT2

P12/INT2/TI1/TI2

P21

P21/PTO1

P22/PCL

P22/PCL/PTO2

50 to 53

P30 to P33

P30/MD0 to P33/MD3

Stack

SBS register

None

SBS.3 = 1; Mk I mode selection
SBS.3 = 0; Mk II mode selection

Stack area

000H-0FFH

n00H-nFFH (n = 0-3)

Subroutine call instruction

2-byte stack

Mk I mode: 2-byte stack

stack operation

Mk II mode: 3-byte stack

Instruction

BRA !addr1

Unavailable

Mk I mode: unavailable

CALLA !addr1

Mk II mode: available

MOVT XA, @BCDE

Available

MOVT XA, @BCXA
BR BCDE
BR BCXA

CALL !addr

3 machine cycles

Mk I mode: 3 machine cycles, Mk II mode: 4 machine cycles

CALLF !faddr

2 machine cycles

Mk I mode: 2 machine cycles, Mk II mode: 3 machine cycles

Mask option

Yes

None

Timer

3 channels:

5 channels:

· Basic interval timer

· Basic interval timer/watchdog timer: 1 channel

: 1 channel

· 8-bit timer/event counter: 3 channels

· 8-bit timer/event counter

(can be used as 16-bit timer/event counter)

: 1 channel

· Watch timer: 1 channel

µPD75P3018

5 2

Parameter

µPD75316B

µPD753017

µPD75P3018

Clock output (PCL)

, 524, 262, 65.5 kHz

(Main system clock:

(Main system clock: at 4.19 MHz operation)

at 4.19 MHz operation)

, 750, 375, 93.8 kHz

(Main system clock: at 6.0 MHz operation)

BUZ output (BUZ)

2 kHz

· 2, 4, 32 kHz

(Main system clock:

(Main system clock: at 4.19 MHz operation or

at 4.19 MHz operation)

subsystem clock: at 32.768 kHz operation)
· 2.86, 5.72, 45.8 kHz
(Main system clock: at 6.0 MHz operation)

Serial interface

3 modes are available
· 3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
· 2-wire serial I/O mode
· SBI mode

SOS register

Feedback resistor cut flag

None

Provided

(SOS.0)

Sub-oscillator current

None

Provided

cut flag (SOS.1)

None

Yes

Standby release by INT0

Yes

Vectored interrupt

External: 3, Internal: 3

External: 3, Internal: 5

Supply voltage

= 2.0 to 6.0 V

= 2.2 to 5.5 V

Operating ambient temperature

= 40 to +85 °C

Package

· 80-pin plastic TQFP (fine pitch) (12 x 12 mm)
· 80-pin plastic QFP (14 x 14 mm)

µPD75P3018

5 3

APPENDIX B DEVELOPMENT TOOLS

The following development tools have been provided for system development using the µPD75P3018. In the 75XL Series,

the relocatable assembler common to series is used in combination with the device file of each type.

RA75X relocatable assembler

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

µS5A13RA75X

Ver.3.30 to

5" 2HD

µS5A10RA75X

Ver.6.2

Note

IBM PC/AT

Refer to "OS for

3.5" 2HC

µS7B13RA75X

or compatible

IBM PCs"

5" 2HC

µS7B10RA75X

Device file

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

µS5A13DF753017

Ver.3.30 to

5" 2HD

µS5A10DF753017

Ver.6.2

Note

IBM PC/AT

Refer to "OS for

3.5" 2HC

µS7B13DF753017

or compatible

IBM PCs"

5" 2HC

µS7B10DF753017

Note

Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark

Operation of the assembler and device file is guaranteed only when using the host machine and OS described

above.

µPD75P3018

5 4

PROM Write Tools

Hardware

PG-1500

This is a PROM programmer that can program single-chip microcontroller with PROM in stand
alone mode or under control of host machine when connected with supplied accessory board
and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.

PA-75P316BGC

This is a PROM programmer adapter for the µPD75P316BGC and µPD75P3018GC.
It can be used when connected to a PG-1500.

PA-75P316BGK

This is a PROM programmer adapter for the µPD75P316BGK and µPD75P3018GK.
It can be used when connected to a PG-1500.

Software

PG-1500 controller

Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500 on
host machine.

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

µS5A13PG1500

Ver.3.30 to

5" 2HD

µS5A10PG1500

Ver.6.2

Note

IBM PC/AT

Refer to "OS for

3.5" 2HD

µS7B13PG1500

or compatible

IBM PCs"

5" 2HC

µS7B10PG1500

Note

Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark

Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described above.

µPD75P3018

5 5

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the µPD75P3018.

Various system configurations using these in-circuit emulators are listed below.

Hardware

IE-75000-R

Note 1

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
For development of the µPD75P3018, the IE-75000-R is used with optional emulation board (IE-
75300-R-EM) and emulation probe (EP-753018GC-R or EP-753018GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).

IE-75001-R

The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging during
development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used with optional emulation board (IE-75300-R-EM) and emulation probe
(EP-753018GC-R or EP-753018GK-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.

IE-75300-R-EM

Note 2

This is an emulation board for evaluating application systems using the µPD75P3018.
It is used in combination with the IE-75000-R or IE-75001-R.

EP-753018GC-R

This is an emulation probe for the µPD75P3018GC.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

EV-9200GC-80

It includes a 80-pin conversion socket (EV-9200GC-80) to facilitate connections
with target system.

EP-753018GK-R

This is an emulation probe for the µPD75P3018GK.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

EV-9500GK-80

It includes a 80-pin conversion adapter (EV-9500GK-80) to facilitate connections with target
system.

Software

IE control program

This program can control the IE-75000-R or IE-75001-R on a host machine when connected to
the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

µS5A13IE75X

Ver.3.30 to

5" 2HD

µS5A10IE75X

Ver.6.2

Note 3

IBM PC/AT

Refer to "OS for

3.5" 2HC

µS7B13IE75X

or compatible

IBM PCs"

5" 2HC

µS7B10IE75X

Notes 1. This is a maintenance product.

2. The IE-75300-R-EM is sold separately.

3. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.

Remark

Operation of the IE control program is guaranteed only when using the host machine and OS described above.

µPD75P3018

5 7

APPENDIX C RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary versions are

not marked as such.

Device Related Documents

Document No.

Document Name

Japanese

English

µPD753012, 753016, 753017 Data Sheet

IC-9016

U10140E

µPD75P3018 Data Sheet

U10956J

U10956E

(This document)

µPD753017 User's Manual

U11282J

IEU-1425

µPD753017 Instruction Table

IEM-5598

75XL Series Selection Guide

U10453J

U10453E

Development Tool Related Documents

Document No.

Document Name

Japanese

English

IE-75000-R/IE-75001-R User's Manual

EEU-846

EEU-1416

Hardware

IE-75300-R-EM User's Manual

U11354J

EEU-1493

EP-753017GC/GK-R User's Manual

EEU-967

IEU-1495

PG-1500 User's Manual

EEU-651

EEU-1335

RA75X Assembler Package

Operation

EEU-731

EEU-1346

User's Manual

Language

EEU-730

EEU-1363

Software

PG-1500 Controller User's Manual

PC-9800 Series

EEU-704

EEU-1291

(MS-DOS) base

IBM PC Series

EEU-5008

U10540E

(PC DOS) base

Other Related Documents

Document No.

Document Name

Japanese

English

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

IEI-620

IEI-1209

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Electrostatic Discharge (ESD) Test

MEM-539

Guide to Quality Assurance for Semiconductor Devices

MEI-603

MEI-1202

Guide for Products Related to Microcomputer: Other Companies

MEI-604

Caution

The above related documents are subject to change without notice. For design purpose, etc., be sure

to use the latest documents.

µPD75P3018

5 8

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken

to stop generation of static electricity as much as possible, and quickly dissipate

it once, when it has occurred. Environmental control must be adequate. When

it is dry, humidifier should be used. It is recommended to avoid using insulators

that easily build static electricity. Semiconductor devices must be stored and

transported in an anti-static container, static shielding bag or conductive

material. All test and measurement tools including work bench and floor should

be grounded. The operator should be grounded using wrist strap. Semiconductor

devices must not be touched with bare hands. Similar precautions need to be

taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level

may be generated due to noise, etc., hence causing malfunction. CMOS devices

behave differently than Bipolar or NMOS devices. Input levels of CMOS devices

must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have

a possibility of being an output pin. All handling related to the unused pins must

be judged device by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function

have not yet been initialized. Hence, power-on does not guarantee out-pin

levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after

power-on for devices having reset function.

µPD75P3018

5 9

NEC Electronics Inc. (U.S.)

Mountain View, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby Sweden
Tel: 8-63 80 820
Fax: 8-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 3

µPD75P3018

6 0

MS-DOS is a trademark of Microsoft Corporation.

IBM DOS, PC DOS, and PC/AT are trademarks of International Business Machines Corporation.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited

without governmental license, the need for which must be judged by the customer. The export or re-export of this product

from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

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