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Электронный компонент: UPD75P3216

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'
1995
DATA SHEET
PD75P3216
MOS INTEGRATED CIRCUIT
The
PD75P3216 replaces the
PD753208's internal mask ROM with a one-time PROM, and features expanded
ROM capacity.
Because the
PD75P3216 supports programming by users, it is suitable for use in prototype testing for system
development using the
PD753204, 753206, or 753208, and for use in small-lot production.
The functions are explained in detail in the following user's manual. Be sure to read this manual when
designing your system.
PD753208 User's Manual: U10158E
FEATURES
Compatible with
PD753208
Memory capacity:
PROM : 16384
8 bits
RAM
: 512
4 bits
Can operate in same power supply voltage range as the mask version
PD753208
V
DD
= 1.8 to 5.5 V
LCD controller/driver
ORDERING INFORMATION
Part Number
Package
PD75P3216GT
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
Caution Mask-option pull-up resistors are not provided in this device.
4-BIT SINGLE-CHIP MICROCONTROLLER
Document No. U10241EJ1V0DS00 (1st edition)
Date Published January 1997 N
Printed in Japan
1997
The information in this document is subject to change without notice.
The mark shows major revised points.
2
PD75P3216
FUNCTION OUTLINE
Parameter
Function
Instruction execution time
0.95, 1.91, 3.81, 15.3
s (@ 4.19-MHz operation with system clock)
0.67, 1.33, 2.67, 10.7
s (@ 6.0-MHz operation with system clock)
Internal memory
PROM
16384
8 bits
RAM
512
4 bits
General-purpose register
4-bit operation: 8
4 banks
8-bit operation: 4
4 banks
Input/
CMOS input
6
Connecting on-chip pull-up resistors can be specified by software: 5
output
CMOS input/output
20
Connecting on-chip pull-up resistors can be specified by software: 20
port
Also used for segment pins: 8
N-ch open-drain I/O
4
13-V withstand
Total
30
LCD controller/driver
Segment selection:
4/8/12 segments (can be changed to CMOS input/
output port in 4-time units; max. 8)
Display mode selection:
Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
Timer
5 channels
8-bit timer/event counter: 1 channel
8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier
generator, timer with gate)
Basic interval timer/watchdog timer: 1 channel
Watch timer: 1 channel
Serial interface
3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
2-wire serial I/O mode
SBI mode
Bit sequential buffer (BSB)
16 bits
Clock output (PCL)
, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)
, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)
Buzzer output (BUZ)
2, 4, 32 kHz (@ 4.19-MHz operation with system clock)
2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)
Vectored interrupts
External: 2, Internal: 5
Test input
External: 1, Internal: 1
System clock oscillator
Ceramic or crystal oscillator for system clock oscillation
Standby function
STOP/HALT mode
Power supply voltage
V
DD
= 1.8 to 5.5 V
Package
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
3
PD75P3216
CONTENTS
1.
PIN CONFIGURATION (Top View) .................................................................................................... 4
2.
BLOCK DIAGRAM .............................................................................................................................. 5
3.
PIN FUNCTIONS ................................................................................................................................. 6
3.1
Port Pins ...................................................................................................................................................... 6
3.2
Non-port Pins .............................................................................................................................................. 7
3.3
Equivalent Circuits for Pins ...................................................................................................................... 8
3.4
Recommended Connection of Unused Pins ........................................................................................ 10
4.
Mk I AND Mk II MODE SELECTION FUNCTION ............................................................................ 11
4.1
Difference between Mk I Mode and Mk II Mode ................................................................................... 11
4.2
Setting of Stack Bank Selection (SBS) Register ................................................................................. 12
5.
Differences between
PD75P3216 and
PD753204, 753206, and 753208 ................................13
6.
MEMORY CONFIGURATION ........................................................................................................... 14
7.
INSTRUCTION SET ........................................................................................................................... 16
8.
ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY ................................................. 25
8.1
Operation Modes for Program Memory Write/Verify ........................................................................... 25
8.2
Program Memory Write Procedure ........................................................................................................ 26
8.3
Program Memory Read Procedure ........................................................................................................ 27
8.4
One-time PROM Screening ..................................................................................................................... 28
9.
ELECTRICAL SPECIFICATIONS ..................................................................................................... 29
10. CHARACTERISTIC CURVE (REFERENCE VALUE) ...................................................................... 42
11. PACKAGE DRAWINGS .................................................................................................................... 44
12. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 45
APPENDIX A.
PD753108, 753208, AND 75P3216 FUNCTIONAL LIST ........................................... 46
APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 48
APPENDIX C. RELATED DOCUMENTS ............................................................................................... 52
4
PD75P3216
1. PIN CONFIGURATION (Top View)
48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
PD75P3216GT
48
S12
47
S13
46
S14
45
S15
44
P93/S16
43
P92/S17
42
P91/S18
41
P90/S19
40
P83/S20
39
P82/S21
38
P81/S22
37
P80/S23
36
P23
35
P22/PCL/PTO2
34
P21/PTO1
33
P20/PTO0
1
COM0
2
3
4
5
P30/LCDCL/MD0
6
P31/SYNC/MD1
7
P32/MD2
8
P33/MD3
9
10
11
12
13
14
15
16
X1
X2
17
18
19
20
21
22
23
24
32
31
30
29
28
27
26
25
P50/D4
P51/D5
P52/D6
P53/D7
P60/KR0/D0
P61/KR1/D1
P62/KR2/D2
V
SS
COM1
COM2
COM3
V
LC0
V
LC1
V
LC2
BIAS
P63/KR3/D3
V
DD
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
V
PP
Note
Note Be sure to connect V
PP
to V
DD
directly in normal operation mode.
PIN IDENTIFICATIONS
BIAS
: LCD Power Supply Bias Control
BUZ
: Buzzer Clock
COM0-COM3 : Common Output 0 to 3
D0-D7
: Data Bus 0 to 7
INT0, INT4
: External Vectored Interrupt 0, 4
KR0-KR3
: Key Return 0 to 3
LCDCL
: LCD Clock
MD0-MD3
: Mode Selection 0 to 3
P00-P03
: Port0
P10, P13
: Port1
P20-P23
: Port2
P30-P33
: Port3
P50-P53
: Port5
P60-P63
: Port6
P80-P83
: Port8
P90-P93
: Port9
PCL
: Programmable Clock
PTO0-PTO2
: Programmable Timer Output 0 to 2
RESET
: Reset Input
S12-S23
: Segment Output 12 to 23
SB0, SB1
: Serial Bus 0, 1
SCK
: Serial Clock
SI
: Serial Input
SO
: Serial Output
SYNC
: LCD Synchronization
TI0
: Timer Input 0
V
DD
: Positive Power Supply
V
LC0
-V
LC2
: LCD Power Supply 0 to 2
V
PP
: Programming Power Supply
V
SS
: Ground
X1, X2
: System Clock Oscillation 1, 2
5
PD75P3216
2. BLOCK DIAGRAM
P20-P23
PORT0
P00-P03
S12-S15
4
COM0-COM3
BIAS
f
LCD
V
SS
V
pp
RESET
V
DD
STANDBY
CONTROL
X2
X1
SYSTEM
CLOCK
GENERATOR
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
fx/2
N
PCL/PTO2/P22
GENERAL
REG.
DATA
MEMORY
(RAM)
512
4 BITS
BANK
SBS
SP (8)
CY
ALU
PROGRAM
COUNTER
PROM
PROGRAM
MEMORY
16384
8 BITS
DECODE
AND
CONTROL
PORT1
P10, P13
PORT2
PORT3
P30/MD0-
P33/MD3
PORT5
P50/D4-
P53/D7
PORT6
P60/D0-
P63/D3
PORT8
P80-P83
PORT9
P90-P93
LCD
CONTROLLER/
DRIVER
4
S16/P93-
S19/P90
4
S20/P83-
S23/P80
V
LC0
V
LC1
V
LC2
LCDCL/P30
SYNC/P31
CLOCKED
SERIAL
INTERFACE
SI/SB1/P03
INTCSI
INTERRUPT
CONTROL
INT0/P10
SO/SB0/P02
SCK/P01
TOUT
INT4/P00
KR0/P60-
KR3/P63
BIT SEQ.
BUFFER (16)
4
8-BIT
TIMER
COUNTER #1
8-BIT
TIMER
COUNTER #2
CASCADED
16-BIT
TIMER
COUNTER
INTT2
INTT1
PTO1/P21
PTO2/
PCL/P22
INTT0
TOUT
8-BIT
TIMER/EVENT
COUNTER #0
TI0/P13
PTO0/P20
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
INTBT
BUZ/P23
WATCH
TIMER
INTW f
LCD
4
2
4
4
4
4
4
4
TOUT
4
CPU CLOCK
6
PD75P3216
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name
I/O
Shared by
Function
8-bit
Status
I/O Circuit
I/O
After Reset
Type
Note 1
P00
Input
INT4
Input
<B>
P01
I/O
SCK
<F>-A
P02
I/O
SO/SB0
<F>-B
P03
I/O
SI/SB1
<M>-C
P10
Input
INT0
Input
<B>-C
P13
TI0
P20
I/O
PTO0
Input
E-B
P21
PTO1
P22
PCL/PTO2
P23
BUZ
P30
I/O
LCDCL/MD0
Input
E-B
P31
SYNC/MD1
P32
MD2
P33
MD3
P50
Note 2
I/O
D4
High
M-E
P51
Note 2
D5
impedance
P52
Note 2
D6
P53
Note 2
D7
P60
I/O
KR0/D0
Input
<F>-A
P61
KR1/D1
P62
KR2/D2
P63
KR3/D3
P80
I/O
S23
Input
H
P81
S22
P82
S21
P83
S20
P90
I/O
S19
Input
H
P91
S18
P92
S17
P93
S16
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.
2. Low level input current leakage increases when input instructions or bit manipulation instructions are
executed.
This is a 4-bit input port (PORT0).
P01 to P03 are 3-bit pins for which an internal
pull-up resistor can be connected by software.
This is a 4-bit I/O port (PORT2).
These are 4-bit pins for which an internal pull-up
resistor can be connected by software.
This is a programmable 4-bit I/O port (PORT3).
Input and output in single-bit units can be specified.
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
This is a 1-bit input port (PORT1).
These are 1-bit pins for which an internal pull-up
resistor can be connected by software.
P10/INT0 can select noise elimination circuit.
This is a programmable 4-bit I/O port (PORT9).
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
This is a 4-bit I/O port (PORT8).
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
This is a programmable 4-bit I/O port (PORT6).
Input and output in single-bit units can be specified.
When set for 4-bit units, an internal pull-up resistor
can be connected by software.
Also functions as data I/O pin (lower 4 bits) for
program memory (PROM) write/verify.
This is an N-ch open-drain 4-bit I/O port (PORT5).
When set to open-drain, voltage is 13 V.
Also functions as data I/O pin (upper 4 bits)
for program memory (PROM) write/verify.
7
PD75P3216
3.2 Non-port Pins
Pin Name
I/O
Shared by
Function
Status
I/O Circuit
After Reset
Type
Note 1
TI0
Input
P13
Input
<B>-C
PTO0
Output P20
Input
E-B
PTO1
P21
PTO2
P22/PCL
PCL
P22/PTO2
BUZ
P23
SCK
I/O
P01
Input
<F>-A
SO/SB0
P02
<F>-B
SI/SB1
P03
<M>-C
INT4
Input
P00
Input
<B>
INT0
Input
P10
Input
<B>-C
KR0 to KR3
Input
P60/D0-P63/D3
Input
<F>-A
X1
Input
--
--
--
X2
--
RESET
Input
--
--
<B>
MD0 to MD3
Input
P30 to P33
Input
<F>-A
D0 to D3
I/O
P60/KR0-P63/KR3
Input
<F>-A
D4 to D7
P50 to P53
M-E
V
PP
--
--
--
--
V
DD
--
--
--
--
V
SS
--
--
--
--
S12 to S15
Output
--
Segment signal output
Note 2
G-A
S16 to S19
Output P93 to P90
Segment signal output
Input
H
S20 to S23
P83 to P80
COM0 to COM3 Output
--
Common signal output
Note 2
G-B
V
LC0
to V
LC2
--
--
Power source for LCD drive
--
--
BIAS
Output
--
Output for external split resistor cut
Note 3
--
LCDCL
Note 4
Output P30/MD0
Clock output for driving external expansion driver
Input
E-B
SYNC
Note 4
P31/MD1
Clock output for synchronization of external expansion driver
Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.
2. The V
LCX
(X = 0, 1, 2) shown below are selected as the input source for the display outputs.
S12 to S15: V
LC1
, COM1 to COM2: V
LC2
, COM3: V
LC0
3. When the split resistor is incorporated
: Low level
When the split resistor is not incorporated : High impedance
4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.
External event pulse input to timer/event counter
Timer/event counter output
Timer counter output
Clock output
Any frequency output (for buzzer or system clock trimming)
Serial clock I/O
Serial data output
Serial data bus I/O
Serial data input
Serial data bus I/O
Edge detection vectored interrupt input
(detecting both rising and falling edges)
Edge detection vectored interrupt input
(detected edge is selectable). INT0/P10
can select noise elimination circuit
Falling edge detection testable input
Ceramic/crystal oscillation circuit connection for system
clock. If using an external clock, input to X1 and input
inverted phase to X2.
System reset input
Mode selection for program memory (PROM) write/verify
Data bus pin for program memory (PROM) write/verify.
Programmable power supply voltage for program memory
(PROM) write/verify.
For normal operation, connect directly to V
DD
.
Apply +12.5 V for PROM write/verify.
Positive power supply
Ground
Noise elimination
circuit/asynch
is selectable
8
PD75P3216
3.3 Equivalent Circuits for Pins
The equivalent circuits for the
PD75P3216's pins are shown in abbreviated form below.
IN
V
DD
P-ch
N-ch
V
DD
P-ch
N-ch
OUT
Data
Output
disable
IN
V
DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type A
V
DD
P-ch
P.U.R.
enable
P.U.R.
P.U.R. : Pull-Up Resistor
IN
V
DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Type D
Output
disable
P.U.R. : Pull-Up Resistor
Type B
CMOS standard input buffer
Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).
Schmitt trigger input with hysteresis characteristics.
(Continued)
TYPE A
TYPE D
TYPE E-B
TYPE B
TYPE B-C
TYPE F-A
9
PD75P3216
(Continued)
TYPE F-B
TYPE H
TYPE M-C
TYPE G-A
TYPE G-B
TYPE M-E
Output
disable
V
DD
P-ch
N-ch
IN/OUT
Data
V
DD
P-ch
P.U.R.
enable
P.U.R.
Output
disable
(N)
Output
disable
(P)
P.U.R. : Pull-Up Resistor
IN/OUT
Type G-A
Type E-B
SEG
data
Output
disable
Data
V
DD
P-ch
IN/OUT
P.U.R.
enable
Data
P.U.R.
Output
disable
P.U.R. : Pull-Up Resistor
N-ch
This pull-up resistor is effective only when an input
instruction is executed (when the pin level is low,
current flows from V
DD
to the pin).
Note
SEG
data
V
LC0
V
LC1
V
LC2
N-ch
P-ch
N-ch
OUT
N-ch
N-ch
P-ch
P-ch
N-ch
OUT
N-ch
V
LC0
V
LC1
V
LC2
COM
data
N-ch
IN/OUT
P-ch
V
DD
P.U.R.
Note
data
output
disable
(+13 V)
(+13 V)
input
instruction
Voltage
control
circuit
10
PD75P3216
3.4 Recommended Connection of Unused Pins
Pin
Recommended Connection
P00/INT4
Connect to Vss or V
DD
P01/SCK
Connect to Vss or V
DD
through a resistor individually
P02/SO/SB0
P03/SI/SB1
Connect to Vss
P10/INT0
Connect to Vss or V
DD
P13/TI0
P20/PTO0
Input status : connect to Vss or V
DD
through a resistor individually
P21/PTO1
Output status: open
P22/PTO2/PCL
P23/BUZ
P30/MD0/LCDCL
P31/MD1/SYNC
P32/MD2
P33/MD3
P50/D4 to P53/D7
Connect to Vss
P60/KR0/D0 to P63/KR3/D3
Input status : connect to Vss or V
DD
through a resistor individually
Output status: open
S12 to S15
Open
COM0 to COM3
S16/P93 to S19/P90
Input status : connect to Vss or V
DD
through a resistor individually
S20/P83 to S23/P80
Output status: open
V
LC0
to V
LC2
Connect to Vss
BIAS
Connect to Vss only when V
LC0
to V
LC2
are all not used.
In other cases, leave open.
V
PP
Be sure to connect V
DD
directly.
11
PD75P3216
4. Mk I AND Mk II MODE SELECTION FUNCTION
Setting a stack bank selection (SBS) register for the
PD75P3216 enables the program memory to be switched
between Mk I mode and Mk II mode. This function is applicable when using the
PD75P3216 to evaluate the
PD753204,
753206, or 753208.
When the SBS bit 3 is set to 1: sets Mk I mode (supports Mk I mode for
PD753204, 753206, and 753208)
When the SBS bit 3 is set to 0: sets Mk II mode (supports Mk II mode for
PD753204, 753206, and 753208)
4.1 Difference between Mk I Mode and Mk II Mode
Table 4-1 lists points of difference between the Mk I mode and the Mk II mode for the
PD75P3216.
Table 4-1. Difference between Mk I Mode and Mk II Mode
Item
Mk I Mode
Mk II Mode
Program counter
PC
13-0
Program memory (bytes)
16384
Data memory (bits)
512
4
Stack
Stack bank
Selectable via memory banks 0, 1
No. of stack bytes
2 bytes
3 bytes
Instruction
BRA !addr1 instruction
None
Provided
CALLA !addr1 instruction
CALL !addr instruction
3 machine cycles
4 machine cycles
CALLF !faddr instruction
2 machine cycles
3 machine cycles
Supported mask ROMs
When set to Mk I mode:
When set to Mk II mode:
PD753204, 753206, and 753208
PD753204, 753206, and 753208
Caution
The Mk II mode supports a program area which exceeds 16K bytes in the 75X and 75XL series. This
mode enhances the software compatibility with products which have more than 16K bytes.
When the Mk II mode is selected, the number of stack bytes used in execution of a subroutine call
instruction increases by 1 per stack for the usable area compared to the Mk I mode. Furthermore,
when a CALL !addr, or CALLF !faddr instruction is used, each instruction takes another machine
cycle. Therefore, when more importance is attached to RAM utilization or throughput than software
compatibility, use the Mk I mode.
Instruction
execution time
12
PD75P3216
4.2 Setting of Stack Bank Selection (SBS) Register
Use the stack bank selection register to switch between Mk I mode and Mk II mode. Figure 4-1 shows the format for
doing this.
The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode, be
sure to initialize the stack bank selection register to 100XB
Note
at the beginning of the program. When using the Mk II
mode, be sure to initialize it to 000XB
Note
.
Note Set the desired value for X.
Figure 4-1. Format of Stack Bank Selection Register
SBS3
SBS2
SBS1
SBS0
F84H
Address
3
2
1
0
SBS
0
0
1
1
0
1
0
1
Symbol
Stack area specification
Memory bank 0
Memory bank 1
Setting prohibited
0
Be sure to enter "0" for bit 2.
0
1
Mk II mode
Mk I mode
Mode selection specification
Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in Mk I mode. When
using instructions for Mk II mode, set SBS3 to "0" and set Mk II mode before using the
instructions.
2. When using Mk II mode, execute a subroutine call instruction and an interrupt instruction after
RESET input and after setting the stack bank selection register.
13
PD75P3216
5. DIFFERENCES BETWEEN
PD75P3216 AND
PD753204, 753206, AND 753208
The
PD75P3216 replaces the internal mask ROM in the
PD753204, 753206, and 753208 with a one-time PROM
and features expanded ROM capacity. The
PD75P3216's Mk I mode supports the Mk I mode in the
PD753204, 753206,
and 753208 and the
PD75P3216's Mk II mode supports the Mk II mode in the
PD753204, 753206, and 753208.
Table 5-1 lists differences among the
PD75P3216 and the
PD753204, 753206, and 753208. Be sure to check the
differences among these products before using them with PROMs for debugging or prototype testing of application
systems or, later, when using them with a mask ROM for full-scale production.
For details on the CPU functions and internal hardware, refer to
PD753208 User's Manual (U10158E).
Table 5-1. Differences between
PD75P3216 and
PD753204, 753206, and 753208
Item
PD753204
PD753206
PD753208
PD75P3216
Program counter
12 bits
13 bits
14 bits
Program memory (bytes)
Mask ROM
Mask ROM
Mask ROM
One-time PROM
4096
6144
8192
16384
Data memory (
4 bits)
512
Mask options
Pull-up resistor for
Yes (specifiable)
No (off chip)
port 5
Waiting time in
Yes (selectable from 2
17
/f
X
and 2
15
/f
X
)
Note
No
RESET
(Fixed to 2
15
/f
X
ms)
Pin configuration
Pin 9 to 12
P30 to P33
P30/MD0-P33/MD3
Pin 14 to 17
P50 to P53
P50/D4-P53/D7
Pin 18 to 20
P60/KR0 to P63/KR3
P60/KR0/D0-
P63/KR3/D3
Pin 25
IC
V
PP
Other
Noise resistance and noise radiation may differ due to the different circuit sizes and
mask layouts.
Note 2
17
/f
X
= 21.8 ms (@6.0 MHz), 31.3 ms (@4.19 MHz)
2
15
/f
X
= 5.46 ms (@6.0 MHz), 7.81 ms (@4.19 MHz)
Caution
Noise resistance and noise radiation are different in PROM and mask ROMs. In transferring to mask
ROM versions from the PROM version in a process between prototype development and full
production, be sure to fully evaluate the mask ROM version's CS (not ES).
14
PD75P3216
6. MEMORY CONFIGURATION
Figure 6-1. Program Memory Map
Note
Can be used only in Mk II mode.
Remark
For instructions other than those noted above, the BR PCDE and BR PCXA instructions can be used to
branch to addresses with changes in the PC's lower 8 bits only.
MBE
MBE
MBE
MBE
MBE
MBE
RBE
RBE
RBE
RBE
RBE
RBE
Internal reset start address (upper 6 bits)
Internal reset start address (lower 8 bits)
INTBT/INT4 start address (upper 6 bits)
INTBT/INT4 start address (lower 8 bits)
INT0 start address (upper 6 bits)
INT0 start address (lower 8 bits)
INTCSI start address (upper 6 bits)
INTCSI start address (lower 8 bits)
INTT0 start address (upper 6 bits)
INTT0 start address (lower 8 bits)
INTT1/INTT2 start address (upper 6 bits)
INTT1/INTT2 start address (lower 8 bits)
Reference table for GETI instruction
0000H
0002H
0004H
0006H
0008H
000AH
000CH
007FH
0080H
07FFH
0800H
0FFFH
1000H
1FFFH
2000H
2FFFH
3000H
3FFFH
CALLF
!faddr instruction
entry address
Branch addresses for
the following instructions
BR !addr
CALL !addr
BRA !addr1
CALLA !addr1
MOVT BCDE
MOVT BCXA
Branch/call
address
by GETI
BR $addr instruction
relative branch address
(15 to 1,
+2 to +16)
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
BRCB
!caddr instruction
branch address
7
6
5
0
Note
Note
0020H
15
PD75P3216
Figure 6-2. Data Memory Map
Note Memory bank 0 or 1 can be selected as the stack area.
(32
4)
256
4
(224
4)
128
4
0
1
15
000H
01FH
020H
0FFH
100H
1ECH
1F7H
1F8H
F80H
FFFH
General-purpose register area
Display data memory (12
4)
Data area
static RAM
(512
4)
Stack area
Note
Peripheral hardware area
Data memory
Memory bank
Not incorporated
1FFH
256
4
(236
4)
(12
4)
(8
4)
1EBH
16
PD75P3216
7. INSTRUCTION SET
(1) Representation and coding formats for operands
In the instruction's operand area, use the following coding format to describe operands corresponding to the
instruction's operand representations (for further description, refer to RA75X Assembler Package User's Manual
Language (EEU-1343)). When there are several codes, select and use just one. Codes that consist of upper-case
letters and + or symbols are key words that should be entered as they are.
For immediate data, enter an appropriate numerical value or label.
Enter register flag symbols as label descriptors instead of mem, fmem, pmem, bit, etc. (for further description, refer
to
PD753208 User's Manual (U10158E)). The number of labels that can be entered for fmem and pmem are
restricted.
Representation
Coding Format
reg
X, A, B, C, D, E, H, L
reg1
X, B, C, D, E, H, L
rp
XA, BC, DE, HL
rp1
BC, DE, HL
rp2
BC, DE
rp'
XA, BC, DE, HL, XA', BC', DE', HL'
rp'1
BC, DE, HL, XA', BC', DE', HL'
rpa
HL, HL+, HL, DE, DL
rpa1
DE, DL
n4
4-bit immediate data or label
n8
8-bit immediate data or label
mem
8-bit immediate data or label
Note
bit
2-bit immediate data or label
fmem
FB0H to FBFH, FF0H to FFFH immediate data or label
pmem
FC0H to FFFH immediate data or label
addr
0000H to 3FFFH immediate data or label
addr1
0000H to 3FFFH immediate data or label (Mk II mode only)
caddr
12-bit immediate data or label
faddr
11-bit immediate data or label
taddr
20H to 7FH immediate data (however, bit0 = 0) or label
PORTn
PORT0 to PORT3, PORT5, PORT6, PORT8, PORT9
IEXXX
IEBT, IECSI, IET0, IET1, IET2, IE0, IE2, IE4, IEW
RBn
RB0 to RB3
MBn
MB0, MB1, MB15
Note
When processing 8-bit data, only even-numbered addresses can be specified.
17
PD75P3216
(2) Operation legend
A
: A register; 4-bit accumulator
B
: B register
C
: C register
D
: D register
E
: E register
H
: H register
L
: L register
X
: X register
XA
: Register pair (XA); 8-bit accumulator
BC
: Register pair (BC)
DE
: Register pair (DE)
HL
: Register pair (HL)
XA'
: Expansion register pair (XA')
BC'
: Expansion register pair (BC')
DE'
: Expansion register pair (DE')
HL'
: Expansion register pair (HL')
PC
: Program counter
SP
: Stack pointer
CY
: Carry flag; bit accumulator
PSW
: Program status word
MBE
: Memory bank enable flag
RBE
: Register bank enable flag
PORTn : Port n (n = 0 to 3, 5, 6, 8, 9)
IME
: Interrupt master enable flag
IPS
: Interrupt priority selection register
IEXXX
: Interrupt enable flag
RBS
: Register bank selection register
MBS
: Memory bank selection register
PCC
: Processor clock control register
.
: Delimiter for address and bit
(XX)
: Addressed data
XXH
: Hexadecimal data
18
PD75P3216
(3) Description of symbols used in addressing area
Remarks 1. MB indicates access-enabled memory banks.
2. In area *2, MB = 0 for both MBE and MBS.
3. In areas *4 and *5, MB = 15 for both MBE and MBS.
4. Areas *6 to *11 indicate corresponding address-enabled areas.
(4) Description of machine cycles
S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies
as shown below.
No skip .................................................................... S = 0
Skipped instruction is 1-byte or 2-byte instruction .. S = 1
Skipped instruction is 3-byte instruction
Note
........... S = 2
Note
3-byte instructions: BR !addr, BRA !addr1, CALL !addr, and CALLA !addr1
Caution The GETI instruction is skipped for one machine cycle.
One machine cycle equals one cycle (= tCY) of the CPU clock F. Use the PCC setting to select among four cycle
times.
MB = 0 (000H to 07FH)
MB = 15 (F80H to FFFH)
MB = MBS
MBS = 0, 1, 15
MB = MBE MBS
MBS = 0, 1, 15
*1
MB = 0
*2
MBE = 1 :
MBE = 0 :
*3
MB = 15, fmem = FB0H to FBFH, FF0H to FFFH
MB = 15, pmem = FC0H to FFFH
addr = 0000H to 3FFFH
*4
*5
*6
addr, addr1 =
*7
(Current PC) 15 to (Current PC) 1
(Current PC) +2 to (Current PC) +16
*8
caddr = 0000H to 0FFFH (PC
13
,
12
= 00B) or
1000H to 1FFFH (PC
13
,
12
= 01B) or
2000H to 2FFFH (PC
13
,
12
= 10B) or
3000H to 3FFFH (PC
13
,
12
= 11B)
faddr = 0000H to 07FFH
taddr = 0020H to 007FH
addr1 = 0000H to 3FFFH (Mk II mode only)
*9
*10
*11
Program memory
addressing
Data memory
addressing
19
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Transfer
MOV
A, #n4
1
1
A
n4
String-effect A
reg1, #n4
2
2
reg1
n4
XA, #n8
2
2
XA
n8
String-effect A
HL, #n8
2
2
HL
n8
String-effect B
rp2, #n8
2
2
rp2
n8
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L=0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L=FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
@HL, A
1
1
(HL)
A
*1
@HL, XA
2
2
(HL)
XA
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
mem, A
2
2
(mem)
A
*3
mem, XA
2
2
(mem)
XA
*3
A, reg
2
2
A
reg
XA, rp'
2
2
XA
rp'
reg1, A
2
2
reg1
A
rp'1, XA
2
2
rp'1
XA
XCH
A, @HL
1
1
A
(HL)
*1
A, @HL+
1
2+S
A
(HL), then L
L+1
*1
L=0
A, @HL
1
2+S
A
(HL), then L
L1
*1
L=FH
A, @rpa1
1
1
A
(rpa1)
*2
XA, @HL
2
2
XA
(HL)
*1
A, mem
2
2
A
(mem)
*3
XA, mem
2
2
XA
(mem)
*3
A, reg1
1
1
A
reg1
XA, rp'
2
2
XA
rp'
MOVT
XA, @PCDE
1
3
XA
(PC
13-8
+DE)
ROM
XA, @PCXA
1
3
XA
(PC
13-8
+XA)
ROM
XA, @BCDE
Note
1
3
XA
(B
2-0
+BCDE)
ROM
*6
XA, @BCXA
Note
1
3
XA
(B
2-0
+BCXA)
ROM
*6
Note
Only the lower 2 bits in the B register are valid.
Table
reference
20
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Bit transfer
MOV1
CY, fmem.bit
2
2
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
(H+mem
3-0
.bit)
*1
fmem.bit, CY
2
2
(fmem.bit)
CY
*4
pmem.@L, CY
2
2
(pmem
7-2
+L
3-2
.bit(L
1-0
))
CY
*5
@H+mem.bit, CY
2
2
(H+mem
3-0
.bit)
CY
*1
Arithmetic
ADDS
A, #n4
1
1+S
A
A+n4
carry
XA, #n8
2
2+S
XA
XA+n8
carry
A, @HL
1
1+S
A
A+(HL)
*1
carry
XA, rp'
2
2+S
XA
XA+rp'
carry
rp'1, XA
2
2+S
rp'1
rp'1+XA
carry
ADDC
A, @HL
1
1
A, CY
A+(HL)+CY
*1
XA, rp'
2
2
XA, CY
XA+rp'+CY
rp'1, XA
2
2
rp'1, CY
rp'1+XA+CY
SUBS
A, @HL
1
1+S
A
A(HL)
*1
borrow
XA, rp'
2
2+S
XA
XArp'
borrow
rp'1, XA
2
2+S
rp'1
rp'1XA
borrow
SUBC
A, @HL
1
1
A, CY
A(HL)CY
*1
XA, rp'
2
2
XA, CY
XArp'CY
rp'1, XA
2
2
rp'1, CY
rp'1XACY
AND
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
OR
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
XOR
A, #n4
2
2
A
A
n4
A, @HL
1
1
A
A
(HL)
*1
XA, rp'
2
2
XA
XA
rp'
rp'1, XA
2
2
rp'1
rp'1
XA
RORC
A
1
1
CY
A
0
, A
3
CY, A
n-1
A
n
NOT
A
2
2
A
A
INCS
reg
1
1+S
reg
reg+1
reg=0
rp1
1
1+S
rp1
rp1+1
rp1=00H
@HL
2
2+S
(HL)
(HL)+1
*1
(HL)=0
mem
2
2+S
(mem)
(mem)+1
*3
(mem)=0
DECS
reg
1
1+S
reg
reg1
reg=FH
rp'
2
2+S
rp'
rp'1
rp'=FFH
Accumulator
manipulation
Increment/
decrement
21
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Comparison
SKE
reg, #n4
2
2+S
Skip if reg=n4
reg=n4
@HL, #n4
2
2+S
Skip if(HL)=n4
*1
(HL)=n4
A, @HL
1
1+S
Skip if A=(HL)
*1
A=(HL)
XA, @HL
2
2+S
Skip if XA=(HL)
*1
XA=(HL)
A, reg
2
2+S
Skip if A=reg
A=reg
XA, rp'
2
2+S
Skip if XA=rp'
XA=rp'
SET1
CY
1
1
CY
1
CLR1
CY
1
1
CY
0
SKT
CY
1
1+S
Skip if CY=1
CY=1
NOT1
CY
1
1
CY
CY
SET1
mem.bit
2
2
(mem.bit)
1
*3
fmem.bit
2
2
(fmem.bit)
1
*4
pmem.@L
2
2
(pmem
7-2
+L
3-2
.bit(L
1-0
))
1
*5
@H+mem.bit
2
2
(H+mem
3-0
.bit)
1
*1
CLR1
mem.bit
2
2
(mem.bit)
0
*3
fmem.bit
2
2
(fmem.bit)
0
*4
pmem.@L
2
2
(pmem
7-2
+L
3-2
.bit(L
1-0
))
0
*5
@H+mem.bit
2
2
(H+mem
3-0
.bit)
0
*1
SKT
mem.bit
2
2+S
Skip if(mem.bit)=1
*3
(mem.bit)=1
fmem.bit
2
2+S
Skip if(fmem.bit)=1
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if(pmem
7-2
+L
3-2
.bit(L
1-0
))=1
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if(H+mem
3-0
.bit)=1
*1
(@H+mem.bit)=1
SKF
mem.bit
2
2+S
Skip if(mem.bit)=0
*3
(mem.bit)=0
fmem.bit
2
2+S
Skip if(fmem.bit)=0
*4
(fmem.bit)=0
pmem.@L
2
2+S
Skip if(pmem
7-2
+L
3-2
.bit(L
1-0
))=0
*5
(pmem.@L)=0
@H+mem.bit
2
2+S
Skip if(H+mem
3-0
.bit)=0
*1
(@H+mem.bit)=0
SKTCLR
fmem.bit
2
2+S
Skip if(fmem.bit)=1 and clear
*4
(fmem.bit)=1
pmem.@L
2
2+S
Skip if(pmem
7-2
+L
3-2
.bit (L
1-0
))=1 and clear
*5
(pmem.@L)=1
@H+mem.bit
2
2+S
Skip if(H+mem
3-0
.bit)=1 and clear
*1
(@H+mem.bit)=1
AND1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
OR1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
XOR1
CY, fmem.bit
2
2
CY
CY
(fmem.bit)
*4
CY, pmem.@L
2
2
CY
CY
(pmem
7-2
+L
3-2
.bit(L
1-0
))
*5
CY, @H+mem.bit
2
2
CY
CY
(H+mem
3-0
.bit)
*1
Memory bit
manipulation
Carry flag
manipulation
22
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Branch
BR
Note
addr
--
--
PC
13-0
addr
*6
Use the assembler to select the
most appropriate instruction
among the following.
BR !addr
BRCB !caddr
BR $addr
addr1
--
--
PC
13-0
addr1
*11
Use the assembler to select
the most appropriate instruction
among the following.
BRA !addr1
BR !addr
BRCB !caddr
BR $addr1
!addr
3
3
PC
13-0
addr
*6
$addr
1
2
PC
13-0
addr
*7
$addr1
1
2
PC
13-0
addr1
PCDE
2
3
PC
13-0
PC
13-8
+DE
PCXA
2
3
PC
13-0
PC
13-8
+XA
BCDE
2
3
PC
13-0
BCDE
*6
BCXA
2
3
PC
13-0
BCXA
*6
BRA
Note
!addr1
3
3
PC
13-0
addr1
*11
BRCB
!caddr
2
2
PC
13-0
PC
13, 12
+caddr
11-0
*8
Note Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
23
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
Subroutine
CALLA
Note
!addr1
3
3
(SP6)(SP3)(SP4)
PC
11-0
stack control
(SP5)
0, 0, PC
13, 12
(SP2)
X, X, MBE, RBE
PC
130
addr1, SP
SP6
CALL
Note
!addr
3
3
(SP4)(SP1)(SP2)
PC
11-0
*6
(SP3)
MBE, RBE, PC
13, 12
PC
130
addr, SP
SP4
4
(SP6)(SP3)(SP4)
PC
11-0
(SP5)
0, 0, PC
13, 12
(SP2)
X, X, MBE, RBE
PC
13-0
addr, SP
SP6
CALLF
Note
!faddr
2
2
(SP4)(SP1)(SP2)
PC
11-0
*9
(SP3)
MBE, RBE, PC
13, 12
PC
13-0
000+faddr, SP
SP4
3
(SP6)(SP3)(SP4)
PC
11-0
(SP5)
0, 0, PC
13, 12
(SP2)
X, X, MBE, RBE
PC
13-0
000+faddr, SP
SP6
RET
Note
1
3
MBE, RBE, PC
13, 12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4
X, X, MBE, RBE
(SP+4)
PC
11-0
(SP)(SP+3)(SP+2)
MBE, 0, PC
13, 12
(SP+1)
SP
SP+6
RETS
Note
1
3+S
MBE, RBE, PC
13, 12
(SP+1)
Unconditional
PC
11-0
(SP)(SP+3)(SP+2)
SP
SP+4
then skip unconditionally
X, X, MBE, RBE
(SP+4)
PC
11-0
(SP)(SP+3)(SP+2)
0, 0, PC
13, 12
(SP+1)
SP
SP+6
then skip unconditionally
RETI
Note
1
3
MBE, RBE, PC
13, 12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
PSW
(SP+4)(SP+5), SP
SP+6
0, 0, PC
13, 12
(SP+1)
PC
11-0
(SP)(SP+3)(SP+2)
PSW
(SP+4)(SP+5), SP
SP+6
PUSH
rp
1
1
(SP1)(SP2)
rp, SP
SP2
BS
2
2
(SP1)
MBS, (SP2)
RBS, SP
SP2
POP
rp
1
1
rp
(SP+1)(SP), SP
SP+2
BS
2
2
MBS
(SP+1), RBS
(SP), SP
SP+2
Note
Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
24
PD75P3216
Instruction
Mnemonic
Operand
No. of Machine
Operation
Addressing
Skip
Group
Bytes
Cycle
Area
Condition
EI
2
2
IME(IPS.3)
1
IEXXX
2
2
IEXXX
1
DI
2
2
IME(IPS.3)
0
IEXXX
2
2
IEXXX
0
I/O
IN
Note 1
A, PORTn
2
2
A
PORTn
(n=0-3, 5, 6, 8, 9)
XA, PORTn
2
2
XA
PORTn+
1
, PORTn(n=8)
OUT
Note 1
PORTn, A
2
2
PORTn
A
(n=2-3, 5, 6, 8, 9)
PORTn, XA
2
2
PORTn+
1
, PORTn
XA(n=8)
CPU control
HALT
2
2
Set HALT Mode(PCC.2
1)
STOP
2
2
Set STOP Mode(PCC.3
1)
NOP
1
1
No Operation
Special
SEL
RBn
2
2
RBS
n (n=0-3)
MBn
2
2
MBS
n (n=0, 1, 15)
GETI
Note 2, 3
taddr
1
3
When using TBR instruction
*10
PC
13-0
(taddr)
5-0
+(taddr+1)
When using TCALL instruction
(SP4)(SP1)(SP2)
PC
11-0
(SP+1)
MBE, RBE, PC
13, 12
PC
13-0
(taddr)
5-0
+(taddr+1)
SP
SP4
When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
1
3
When using TBR instruction
*10
PC
13-0
(taddr)
5-0
+(taddr+1)
4
When using TCALL instruction
(SP6)(SP3)(SP4)
PC
11-0
(SP2)
X, X, MBE, RBE
PC
13-0
(taddr)
5-0
+(taddr+1)
SP
SP6
3
When using instruction other than
Determined by
TBR or TCALL
referenced
Execute (taddr)(taddr+1) instructions
instruction
Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBE to 15.
2. TBR and TCALL instructions are assembler directives for the GETI instruction's table definitions.
3. Shaded areas indicate support for Mk II mode only. Other areas indicate support for Mk I mode only.
Interrupt
control
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
25
PD75P3216
8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY
The program memory contained in the
PD75P3216 is a 16384
8-bit one-time PROM that can be electrically written
one time only. The pins listed in the table below are used for this PROM's write/verify operations. Clock input from the
X1 pin is used instead of address input as a method for updating addresses.
Pin
Function
V
PP
Pin where program voltage is applied during program
memory write/verify (usually V
DD
potential)
X1, X2
Clock input pins for address updating during program
memory write/verify. Input the X1 pin's inverted signal to
the X2 pin.
MD0 to MD3
Operation mode selection pin for program memory write/
verify
D0/P60/KR0-D3/P63/KR3 (lower 4 bits)
8-bit data I/O pins for program memory write/verify
D4/P50-D7/P53 (upper 4 bits)
V
DD
Pin where power supply voltage is applied. Applies 1.8 to
5.5 V in normal operation mode and +6 V for program
memory write/verify.
Caution
Pins not used for program memory write/verify should be connected to Vss.
8.1 Operation Modes for Program Memory Write/Verify
When +6 V is applied to the V
DD
pin and +12.5 V to the V
PP
pin, the
PD75P3216 enters the program memory write/
verify mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below.
Operation Mode Specification
Operation Mode
V
PP
V
DD
MD0
MD1
MD2
MD3
+12.5 V
+6 V
H
L
H
L
Zero-clear program memory address
L
H
H
H
Write mode
L
L
H
H
Verify mode
H
X
H
H
Program inhibit mode
X: L or H
26
PD75P3216
8.2 Program Memory Write Procedure
Program memory can be written at high speed using the following procedure.
(1) Pull down unused pins to Vss through resistors. Set the X1 pin low.
(2) Supply 5 V to the V
DD
and V
PP
pins.
(3) Wait 10
s.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the V
DD
and 12.5 V to the V
PP
pins.
(6) Write data in the 1 ms write mode.
(7) Select the verify mode. If the data is correct, go to step (8) and if not, repeat steps (6) and (7).
(8) (X : number of write operations from steps (6) and (7))
1 ms additional write.
(9) Apply four pulses to the X1 pin to increment the program memory address by one.
(10) Repeat steps (6) to (9) until the end address is reached.
(11) Select the zero-clear program memory address mode.
(12) Return the V
DD
and V
PP
pins back to 5 V.
(13) Turn off the power.
The following figure shows steps (2) to (9).
V
PP
V
DD
V
DD
+ 1
V
DD
V
PP
V
DD
X1
D0/P60/KR0-
D3/P63/KR3
D4/P50-
D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
X repetitions
Write
Verify
Additional
write
Address
increment
Data input
Data
output
Data input
27
PD75P3216
8.3 Program Memory Read Procedure
The
PD75P3216 can read program memory contents using the following procedure.
(1) Pull down unused pins to V
SS
through resistors. Set the X1 pin low.
(2) Supply 5 V to the V
DD
and V
PP
pins.
(3) Wait 10
s.
(4) Select the zero-clear program memory address mode.
(5) Supply 6 V to the V
DD
and 12.5 V to the V
PP
pins.
(6) Select the verify mode. Apply four pulses to the X1 pin. Every four clock pulses will output the data stored in one
address.
(7) Select the zero-clear program memory address mode.
(8) Return the V
DD
and V
PP
pins back to 5 V.
(9) Turn off the power.
The following figure shows steps (2) to (9).
V
PP
V
DD
V
DD
+ 1
V
DD
V
PP
V
DD
X1
D0/P60/KR0-
D3/P63/KR3
D4/P50-
D7/P53
Data output
Data output
MD0/P30
MD2/P32
MD3/P33
MD1/P31
"L"
28
PD75P3216
8.4 One-time PROM Screening
Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends
that after the required data is written and the PROM is stored under the temperature and time conditions shown below,
the PROM should be verified via a screening.
Storage Temperature
Storage Time
125 C
24 hours
29
PD75P3216
9. ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25 C)
Parameter
Symbol
Test Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to +7.0
V
PROM supply voltage
V
PP
0.3 to +13.5
V
Input voltage
V
I1
Except port 5
0.3 to V
DD
+ 0.3
V
V
I2
Port 5
N-ch open-drain
0.3 to +14
V
Output voltage
V
O
0.3 to V
DD
+ 0.3
V
Output current, high
I
OH
Per pin
10
mA
Total for all pins
30
mA
Output current, low
I
OL
Per pin
30
mA
Total for all pins
220
mA
Operating ambient
T
A
40 to +85
Note
C
temperature
Storage temperature
T
stg
65 to +150
C
Note
When LCD is driven in normal mode: T
A
= 10 to +85 C
Caution Exposure to Absolute Maximum Ratings even for instant may affect device reliability; exceeding
the ratings could cause parmanent damage. The parameters apply independently. The device
should be operated within the limits specified under DC and AC Characteristics.
CAPACITANCE (T
A
= 25 C, V
DD
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f = 1 MHz
15
pF
Output capacitance
C
OUT
Unmeasured pins returned to 0 V.
15
pF
I/O capacitance
C
IO
15
pF
30
PD75P3216
SYSTEM CLOCK OSCILLATOR CHARACTERISTICS (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Resonator
Recommended Constant
Parameter
Test Conditions
MIN.
TYP.
MAX.
Unit
Ceramic
Oscillator
1.0
6.0
Note 2
MHz
resonator
frequency (fx)
Note 1
Oscillation
After V
DD
reaches oscil-
4
ms
stabilization time
Note 3
lation voltage range MIN.
Crystal
Oscillator
1.0
6.0
Note 2
MHz
resonator
frequency (fx)
Note 1
Oscillation
V
DD
= 4.5 to 5.5 V
10
ms
stabilization time
Note 3
30
External
X1 input
1.0
6.0
Note 2
MHz
clock
frequency (fx)
Note 1
X1 input
83.3
500
ns
high/low level width
(t
XH
, t
XL
)
Notes 1.
The oscillator frequency and X1 input frequency indicate characteristics of the oscillator only. For the
instruction execution time, refer to the AC characteristics.
2.
When the oscillator frequency is 4.19 MHz < fx
6.0 MHz, setting the processor clock control register
(PCC) to 0011 results in 1 machine cycle being less than the required 0.95
s. Therefore, set PCC
to a value other than 0011.
3.
The oscillation stabilization time is necessary for oscillation to stabilize after applying V
DD
or releasing
the STOP mode.
Caution When using the system clock oscillator, wiring in the area enclosed with the dotted line should be
carried out as follows to avoid an adverse effect from wiring capacitance.
Wiring should be as short as possible.
Wiring should not cross other signal lines.
Wiring should not be placed close to a varying high current.
The potential of the oscillator capacitor ground should be the same as V
SS
.
Do not ground it to the ground pattern in which a high current flows.
Do not fetch a signal from the oscillator.
X2
X1
C1
C2
V
DD
X1
X2
X2
X1
C1
C2
V
DD
31
PD75P3216
DC CHARACTERISTICS (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Output current, low
I
OL
Per pin
15
mA
Total for all pins
150
mA
Input voltage, high
V
IH1
Ports 2, 3, 8, 9
2.7
V
DD
5.5 V
0.7V
DD
V
DD
V
1.8
V
DD
< 2.7 V
0.9V
DD
V
DD
V
V
IH2
Ports 0, 1, 6, RESET
2.7
V
DD
5.5 V
0.8V
DD
V
DD
V
1.8
V
DD
< 2.7 V
0.9V
DD
V
DD
V
V
IH3
Port 5
N-ch open-drain
2.7
V
DD
5.5 V
0.7V
DD
13
V
1.8
V
DD
< 2.7 V
0.9V
DD
13
V
V
I14
X1
V
DD
0.1
V
DD
V
Input voltage, low
V
IL1
Ports 2, 3, 5, 8, 9
2.7
V
DD
5.5 V
0
0.3V
DD
V
1.8
V
DD
< 2.7 V
0
0.1V
DD
V
V
IL2
Ports 0, 1, 6, RESET
2.7
V
DD
5.5 V
0
0.2V
DD
V
1.8
V
DD
< 2.7 V
0
0.1V
DD
V
V
IL3
X1
0
0.1
V
Output voltage, high
V
OH
SCK, SO, ports 2, 3, 6, 8, 9 I
OH
= 1 mA
V
DD
0.5
V
Output voltage, low
V
OL1
SCK, SO, ports 2, 3, 5, 6, 8, 9
I
OL
= 15 mA,
0.2
2.0
V
V
DD
= 4.5 to 5.5 V
I
OL
= 1.6 mA
0.4
V
V
OL2
SB0, SB1
N-ch open-drain pull-up resistor
1 k
0.2V
DD
V
Input leakage
I
LIH1
V
IN
= V
DD
Other pins than X1
3
A
current, high
I
LIH2
X1
20
A
I
LIH3
V
IN
= 13 V
Port 5 (N-ch open-drain)
20
A
Input leakage
I
LIL1
V
IN
= 0 V
Other pins than port 5 and X1
3
A
current, low
I
LIL2
X1
20
A
I
LIL3
Port 5 (N-ch open-drain) When an
3
A
input instruction is not executed
Port 5 (N-ch
30
A
open-drain)
When an input
V
DD
= 5.0 V
10
27
A
instruction
V
DD
= 3.0 V
3
8
A
is executed
Output leakage
I
LOH1
V
OUT
= V
DD
SCK, SO/SB0, SB1, ports 2, 3, 6, 8, 9
3
A
current, high
I
LOH2
V
OUT
= 13 V
Port 5 (N-ch open-drain)
20
A
Output leakage
I
LOL
V
OUT
= 0 V
3
A
current, low
Pull-up resistor
R
L
V
IN
= 0 V
Ports 0, 1, 2, 3, 6, 8, 9
50
100
200
k
(Excluding P00 pin)
32
PD75P3216
DC CHARACTERISTICS (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
LCD drive voltage
V
LCD
VAC0 = 0
T
A
= 40 to +85
C
2.7
V
DD
V
T
A
= 10 to +85
C
2.2
V
DD
V
VAC0 = 1
1.8
V
DD
V
VAC current
I
VAC
VAC0 = 1, V
DD
= 2.0 V
10%
1
4
A
LCD output voltage
V
ODC
lo =
1
A
V
LCD0
= V
LCD
0
0.2
V
deviation
Note 1
(common)
V
LCD1
= V
LCD
2/3
LCD output voltage
V
ODS
lo =
0.5
A
V
LCD2
= V
LCD
1/3
0
0.2
V
deviation
Note 1
(segment)
2.2 V
V
LCD
V
DD
Note 1
Supply current
Note 2
I
DD1
6.0 MHz
V
DD
= 5.0 V
10%
Note 3
2.6
7.8
mA
Crystal oscillation
V
DD
= 3.0 V
10%
Note 4
0.47
1.4
mA
I
DD2
C1 = C2 = 22 pF
HALT mode
V
DD
= 5.0 V
10%
0.72
2.1
mA
V
DD
= 3.0 V
10%
0.27
0.8
mA
I
DD1
4.19 MHz
V
DD
= 5.0 V
10%
Note 3
1.9
5.7
mA
Crystal oscillation
V
DD
= 3.0 V
10%
Note 4
0.36
1.1
mA
I
DD2
C1 = C2 = 22 pF
HALT mode
V
DD
= 5.0 V
10%
0.7
2.0
mA
V
DD
= 3.0 V
10%
0.23
0.7
mA
I
DD5
STOP mode
Note 5
V
DD
= 5.0 V
10%
0.05
10
A
V
DD
= 3.0 V
0.02
5
A
10%
T
A
= 25C
0.02
3
A
Notes 1.
The voltage deviation is the difference from the output voltage corresponding to the ideal value of the
segment and common outputs (V
LCDn
; n = 0, 1, 2).
2.
Not including current flowing in on-chip pull-up resistors.
3.
When the processor clock control register (PCC) is set to 0011 and the device is operated in the high-
speed mode.
4.
When PCC is set to 0000 and the device is operated in the low-speed mode.
5.
Set VAC0 to 0 when setting the STOP mode. If VAC0 is set to 1, the current increases by about 1
A.
33
PD75P3216
AC CHARACTERISTICS (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
CPU clock cycle
t
CY
V
DD
= 2.7 to 5.5 V
0.67
64
s
time
Note 1
0.95
64
s
TI0 input frequency
f
TI
V
DD
= 2.7 to 5.5 V
0
1
MHz
0
275
kHz
TI0 input
t
TIH
, t
TIL
V
DD
= 2.7 to 5.5 V
0.48
s
high/low-level width
1.8
s
Interrupt input high/
t
INTH
, t
INTL
INT0
IM02 = 0
Note 2
s
low-level width
IM02 = 1
10
s
INT4
10
s
KR0 to KR3
10
s
RESET low level width
t
RSL
10
s
Notes 1.
The cycle time (minimum instruction
execution time) of the CPU clock
(
) is determined by the oscillation
frequency of the connected
resonator (and external clock) and
the processor clock control register
(PCC). The figure at the right
indicates the cycle time t
CY
versus
supply voltage V
DD
characteristic.
2.
2t
CY
or 128/fx is set by setting the
interrupt mode register (IM0).
1
0
2
3
4
5
6
0.5
1
3
4
5
6
30
64
Supply Voltage V
DD
[V]
t
CY
vs V
DD
Cycle Time t
CY
[ s]
Guaranteed Operation
Range
34
PD75P3216
SERIAL TRANSFER OPERATION
2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high/low-level
t
KL1
, t
KH1
V
DD
= 2.7 to 5.5 V
t
KCY1
/250
ns
width
t
KCY1
/2150
ns
SI
Note 1
setup time
t
SIK1
V
DD
= 2.7 to 5.5 V
150
ns
(to SCK
)
500
ns
SI
Note 1
hold time
t
KSI1
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
600
ns
SO
Note 1
output delay time
t
KSO1
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
250
ns
from SCK
C
L
= 100 pF
Note 2
0
1000
ns
Notes 1.
In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2.
R
L
and C
L
are the load resistance and load capacitance of the SO output lines.
2-Wire and 3-Wire Serial I/O Mode (SCK...External clock input): (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high/low-level
t
KL2
, t
KH2
V
DD
= 2.7 to 5.5 V
400
ns
width
1600
ns
SI
Note 1
setup time
t
SIK2
V
DD
= 2.7 to 5.5 V
100
ns
(to SCK
)
150
ns
SI
Note 1
hold time
t
KSI2
V
DD
= 2.7 to 5.5 V
400
ns
(from SCK
)
600
ns
SO
Note 1
output delay time
t
KSO2
R
L
= 1 k
,
V
DD
= 2.7 to 5.5 V
0
300
ns
from SCK
C
L
= 100 pF
Note 2
0
1000
ns
Notes 1.
In the 2-wire serial I/O mode, read SB0 or SB1 instead.
2.
R
L
and C
L
are the load resistance and load capacitance of the SO output lines.
35
PD75P3216
SBI Mode (SCK...Internal clock output (master)): (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY3
V
DD
= 2.7 to 5.5 V
1300
ns
3800
ns
SCK high/low-level
t
KL3
, t
KH3
V
DD
= 2.7 to 5.5 V
t
KCY3
/250
ns
width
t
KCY3
/2150
ns
SB0, 1 setup time
t
SIK3
V
DD
= 2.7 to 5.5 V
150
ns
(to SCK
)
500
ns
SB0, 1 hold time (from SCK
)
t
KSI3
V
DD
= 2.7 to 5.5 V
t
KCY3
/2
ns
SB0, 1 output delay
t
KSO3
R
L
= 1 k
,
Note
V
DD
= 2.7 to 5.5 V
0
250
ns
time from SCK
C
L
= 100 pF
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY3
ns
SCK
from SB0, 1
t
SBK
t
KCY3
ns
SB0, 1 low-level width
t
SBL
t
KCY3
ns
SB0, 1 high-level width
t
SBH
t
KCY3
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines.
SBI Mode (SCK...External clock input (slave)): (T
A
= 40 to +85 C, V
DD
= 1.8 to 5.5 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY4
V
DD
= 2.7 to 5.5 V
800
ns
3200
ns
SCK high/low-level
t
KL4
, t
KH4
V
DD
= 2.7 to 5.5 V
400
ns
width
1600
ns
SB0, 1 setup time
t
SIK4
V
DD
= 2.7 to 5.5 V
100
ns
(to SCK
)
150
ns
SB0, 1 hold time (from SCK
)
t
KSI4
V
DD
= 2.7 to 5.5 V
t
KCY4
/2
ns
SB0, 1 output delay
t
KSO4
R
L
= 1 k
,
Note
V
DD
= 2.7 to 5.5 V
0
300
ns
time from SCK
C
L
= 100 pF
0
1000
ns
SB0, 1
from SCK
t
KSB
t
KCY4
ns
SCK
from SB0, 1
t
SBK
t
KCY4
ns
SB0, 1 low-level width
t
SBL
t
KCY4
ns
SB0, 1 high-level width
t
SBH
t
KCY4
ns
Note
R
L
and C
L
are the load resistance and load capacitance of the SB0 and SB1 output lines.
36
PD75P3216
AC Timing Test Point (Excluding X1 Input)
Clock Timing
TI0 Timing
X1 Input
1/f
X
t
XL
t
XH
0.1 V
V
DD
0.1 V
V
IH
(MIN.)
V
IL
(MAX.)
V
IH
(MIN.)
V
IL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
V
OH
(MIN.)
V
OL
(MAX.)
TI0
1/f
TI
t
TIL
t
TIH
37
PD75P3216
Serial Transfer Timing
3-wire serial I/O mode
t
KCY1, 2
t
KL1, 2
t
KH1, 2
SCK
SI
SO
t
SIK1, 2
t
KSI1, 2
t
KSO1, 2
Input Data
Output Data
2-wire serial I/O mode
t
KSO1, 2
t
SIK1, 2
t
KL1, 2
t
KH1, 2
SCK
t
KSI1, 2
SB0, 1
t
KCY1, 2
38
PD75P3216
Serial Transfer Timing
Bus release signal transfer
Command signal transfer
t
KCY3, 4
t
KH3, 4
t
KSI3, 4
t
SIK3, 4
t
KSO3, 4
SCK
SB0, 1
t
KL3, 4
t
SBK
t
SBH
t
SBL
t
KSB
t
KCY3, 4
t
KH3, 4
t
KSI3, 4
t
SIK3, 4
t
KSO3, 4
SCK
SB0, 1
t
KL3, 4
t
SBK
t
KSB
Interrupt input timing
t
INTL
t
INTH
INTP0, 4
KR0 to 3
RESET input timing
t
RSL
RESET
39
PD75P3216
DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS
(T
A
= 40 to +85 C)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Release signal set time
t
SREL
0
s
Oscillation stabilization
t
WAIT
Release by RESET
2
15
/f
X
ms
wait time
Note 1
Release by interrupt
Note 2
ms
Notes 1.
The oscillation stabillization wait time is the time during which the CPU operation is stopped to prevent
unstable operation at the oscillation start.
2.
Depends on the basic interval timer mode register (BTM) settings (See the table below).
BTM3
BTM2
BTM1
BTM0
Wait Time
When fx = 4.19-MHz operation
When fx = 6.0-MHz operation
--
0
0
0
2
20
/fx (approx. 250 ms)
2
20
/fx (approx. 175 ms)
--
0
1
1
2
17
/fx (approx. 31.3 ms)
2
17
/fx (approx. 21.8 ms)
--
1
0
1
2
15
/fx (approx. 7.81 ms)
2
15
/fx (approx. 5.46 ms)
--
1
1
1
2
13
/fx (approx. 1.95 ms)
2
13
/fx (approx. 1.37 ms)
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
V
DD
RESET
STOP Instruction Execution
STOP Mode
Data Retention Mode
Internal Reset Operation
HALT Mode
Operating Mode
V
DDDR
t
SREL
t
WAIT
t
SREL
t
WAIT
V
DD
STOP Instruction Execution
STOP Mode
Data Retention Mode
HALT Mode
Operating Mode
Standby Release Signal
(Interrupt Request)
V
DDDR
40
PD75P3216
DC Programming Characteristics (T
A
= 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
= 0V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, high
V
IH1
Other than X1, X2 pins
0.7 V
DD
V
DD
V
V
IH2
X1, X2
V
DD
0.5
V
DD
V
Input voltage, low
V
IL1
Other than X1, X2 pins
0
0.3 V
DD
V
V
IL2
X1, X2
0
0.4
V
Input leakage current
I
LI
V
IN
= V
IL
or V
IH
10
A
Output voltage, high
V
OH
I
OH
= 1 mA
V
DD
1.0
V
Output voltage, low
V
OL
I
OL
= 1.6 mA
0.4
V
V
DD
supply current
I
DD
30
mA
V
PP
supply current
I
PP
MD0 = V
IL
, MD1 = V
IH
30
mA
Cautions 1. Keep V
PP
to within +13.5 V, including overshoot.
2. Apply V
DD
before V
PP
and turn it off after V
PP
.
AC Programming Characteristics (T
A
= 25
5
C, V
DD
= 6.0
0.25 V, V
PP
= 12.5
0.3 V, V
SS
= 0 V)
Parameter
Symbol
Note 1
Test Conditions
MIN.
TYP.
MAX.
Unit
Address setup time
Note 2
t
AS
t
AS
2
s
(vs. MD0
)
MD1 setup time (vs. MD0
)
t
M1S
t
OES
2
s
Data setup time (vs. MD0
)
t
DS
t
DS
2
s
Address hold time
Note 2
t
AH
t
AH
2
s
(vs. MD0
)
Data hold time (vs. MD0
)
t
DH
t
DH
2
s
MD0
data output float
t
DF
t
DF
0
130
ns
delay time
V
PP
setup time (vs. MD3
)
t
VPS
t
VPS
2
s
V
DD
setup time (vs. MD3
)
t
VDS
t
VCS
2
s
Initial program pulse width
t
PW
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
OPW
t
OPW
0.95
21.0
ms
MD0 setup time (vs. MD1
)
t
M0S
t
CES
2
s
MD0
data output delay time
t
DV
t
DV
MD0 = MD1 = V
IL
1
s
MD1 hold time (vs. MD0
)
t
M1H
t
OEH
t
M1H
+ t
M1R
50
s
2
s
MD1 recovery time (vs. MD0
)
t
M1R
t
OR
2
s
Program counter reset time
t
PCR
--
10
s
X1 input high-, low-level width
t
XH
, t
XL
--
0.125
s
X1 input frequency
f
X
--
4.19
MHz
Initial mode set time
t
1
--
2
s
MD3 setup time (vs. MD1
)
t
M3S
--
2
s
MD3 hold time (vs. MD1
)
t
M3H
--
2
s
MD3 setup time (vs. MD0
)
t
M3SR
--
When program memory is read
2
s
Address
Note 2
data output
t
DAD
t
ACC
When program memory is read
2
s
delay time
Address
Note 2
data output
t
HAD
t
OH
When program memory is read
0
130
ns
hold time
MD3 hold time (vs. MD0
)
t
M3HR
--
When program memory is read
2
s
MD3
data output float
t
DFR
--
When program memory is read
2
s
delay time
Notes 1.
Symbol of corresponding
PD27C256A
2.
The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not
connected to a pin.
41
PD75P3216
Program Memory Write Timing
Program Memory Read Timing
V
PP
V
DD
V
DD
+1
V
DD
X1
D0/P60/KR0-
D3/P63/KR3
D4/P50-
D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
V
PP
V
DD
Data input
t
VPS
t
VDS
t
XH
t
XL
t
I
t
DS
t
DH
t
PW
t
DV
t
DF
t
M1R
t
M0S
t
DS
t
DH
t
OPW
t
AH
t
AS
t
M1S
t
M1H
t
PCR
t
M3S
t
M3H
Data input
Data input
Data output
V
PP
V
DD
V
DD
+1
V
DD
X1
D0/P60/KR0-
D3/P63/KR3
D4/P50-
D7/P53
MD0/P30
MD1/P31
MD2/P32
MD3/P33
V
DD
V
PP
Data output
t
VPS
t
VDS
t
XH
t
XL
t
DAD
t
HAD
t
DV
t
DFR
t
M3HR
t
I
t
PCR
t
M3SR
Data output
42
PD75P3216
10. CHARACTERISTIC CURVE (REFERENCE VALUE)
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
Supply Current I
DD
(mA)
0
1
2
3
4
5
6
7
8
Supply Voltage V
DD
(V)
(T
A
= 25
C)
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
HALT mode
X1
X2
Crystal
resonator
6.0 MHz
22 pF
V
DD
22 pF
I
DD
vs V
DD
(System clock : 6.0 MHz Crystal resonator)
43
PD75P3216
0.001
0.005
0.01
0.05
0.1
0.5
1.0
5.0
10
0
1
2
3
4
5
6
7
8
PCC = 0011
PCC = 0010
PCC = 0001
PCC = 0000
X1
X2
22 pF
V
DD
22 pF
Supply Current I
DD
(mA)
Supply Voltage V
DD
(V)
(T
A
= 25
C)
HALT mode
Crystal
resonator
4.19 MHz
I
DD
vs V
DD
(System clock : 4.19 MHz Crystal resonator)
44
PD75P3216
11. PACKAGE DRAWINGS
48 PIN PLASTIC SHRINK SOP (375 mil)
C
B
D
E
F
G
A
1
24
48
25
L
I
H
J
K
detail of lead end
3
M
M
N
+7 3
P48GT-65-375B-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
16.21 MAX.
0.65 (T.P.)
2.0 MAX.
1.70.1
10.00.3
0.63 MAX.
0.639 MAX.
0.0050.003
0.079 MAX.
0.394
0.3150.008
0.025 MAX.
NOTE
L
M
0.50.2
0.15
1.00.2
8.00.2
0.004
0.020
+0.008
0.009
Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.
0.0670.004
0.026 (T.P.)
0.006
N
0.10
0.004
0.012
0.300.10
0.1250.075
+0.004
0.002
0.10
+0.10
0.05
+0.004
0.005
+0.012
0.013
0.039
+0.009
0.008
45
PD75P3216
12. RECOMMENDED SOLDERING CONDITIONS
The
PD75P3216 should be soldered and mounted under the conditions recommended in the table below.
For details of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual" (C10535E).
For soldering methods and conditions other than those recommended below, contact an NEC Sales representative.
Table 12-1. Surface Mounting Type Soldering Conditions
PD75P3216GT: 48-pin plastic shrink SOP (375 mil, 0.65-mm pitch)
Soldering
Soldering Conditions
Symbol
Method
Infrared rays
Peak package's surface temperature: 235 C, Reflow time: 30 seconds or less
IR35-107-2
reflow
(at 210 C or higher), Number of reflow processes: Twice max.
Number of days: 7
Note
(after that, prebaking is necessary at 125
C for 10 hours)
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping, and non-
thermal-resistant tray) cannot be baked in their packs.
VPS
Peak package's surface temperature: 215 C, Reflow time: 40 seconds or less
VP15-107-2
(at 200 C or higher), Number of reflow processes: Twice max.
Number of days: 7
Note
(after that, prebaking is necessary at 125
C for 10 hours)
<Precaution>
Products other than those supplied in thermal-resistant tray (magazine, taping, and non-
thermal-resistant tray) cannot be baked in their packs.
Wave soldering
Solder temperature: 260 C or below, Flow time: 10 seconds or less, Number of
WS60-107-1
flow process: 1, Preheating temperature: 120 C or below (Package surface temperature)
Number of days: 7
Note
(after that, prebaking is necessary at 125
C for 10 hours)
Partial heating
Pin temperature: 300 C or below, Time: 3 seconds or less (per device side)
--
Note
The number of days during which the product can be stored at 25
C, 65 % RH max. after the dry pack
has been opened.
Caution
Use of more than one soldering method should be avoided (except for partial heating).
46
PD75P3216
APPENDIX A.
PD753108, 753208, AND 75P3216 FUNCTIONAL LIST
Parameter
PD753108
PD753208
PD75P3216
Program memory
Mask ROM
One-time PROM
0000H-1FFFH
0000H-3FFFH
(8192
8 bits)
(16384
8 bits)
Data memory
000H-1FFH
(512
4 bits)
CPU
75XL CPU
Instruction
When main system
0.95, 1.91, 3.81, 15.3
s (@ 4.19-MHz operation)
execution
clock is selected
0.67, 1.33, 2.67, 10.7
s (@ 6.0-MHz operation)
time
When subsystem
122
s (@ 32.768-kHz
None
clock is selected
operation)
I/O port
CMOS input
8 (on-chip pull-up resistors can
6 (on-chip pull-up resistors can be specified by software: 5)
be specified by software: 7)
CMOS input/output
20 (on-chip pull-up resistors can be specified by software)
N-ch open drain
4 (on-chip pull-up resistors can be specified by software,
4 (no mask option, withstand
input/output
withstand voltage is 13 V)
voltage is 13 V)
Total
32
30
LCD controller/driver
Segment selection: 16/20/24
Segment selection: 4/8/12 segments
(can be changed to CMOS
(can be changed to CMOS input/output port in 4 time-unit;
input/output port in 4 time-
max. 8)
unit; max. 8)
Display mode selection: static, 1/2 duty (1/2 bias), 1/3 duty (1/2 bias), 1/3 duty (1/3 bias),
1/4 duty (1/3 bias)
On-chip split resistor for LCD driver can be specified by
No on-chip split resistor for
using mask option.
LCD driver
Timer
5 channels
5 channels
8-bit timer/event
8-bit timer counter: 2 channels
counter: 3 channels
(Can be used as 16-bit timer counter, carrier generator,
(Can be used as 16-bit
timer with gate)
timer/event counter, carrier
8-bit timer/event counter: 1 channel
generator, timer with gate)
Basic interval timer/watchdog timer: 1 channel
Basic interval timer/
Watch timer: 1 channel
watchdog timer: 1 channel
Watch timer: 1 channel
Clock output (PCL)
, 524, 262, 65.5 kHz
(Main system clock: @ 4.19-MHz operation)
, 750, 375, 93.8 kHz
(Main system clock: @ 6.0-MHz operation)
Buzzer output (BUZ)
2, 4, 32 kHz
2, 4, 32 kHz
(Main system clock: @
(Main system clock: @ 4.19-MHz operation)
4.19-MHz operation or sub-
2.93, 5.86, 46.9 kHz
system clock: @ 32.768-kHz
(Main system clock: @ 6.0-MHz operation)
operation)
2.86, 5.72, 45.8 kHz
(Main system clock: @
6.0-MHz operation)
Serial interface
3 modes are available
3-wire serial I/O mode ... MSB/LSB can be selected for transfer top bit
2-wire serial I/O mode
SBI mode
SCC register
Contained
None
SOS register
Vectored interrupt
External: 3, internal: 5
External: 2, internal: 5
47
PD75P3216
Parameter
PD753108
PD753208
PD75P3216
Test input
External: 1, internal: 1
Operation supply voltage
V
DD
= 1.8 to 5.5 V
Operating ambient temperature
T
A
= 40 to +85
C
Package
64-pin plastic QFP
48-pin plastic shrink SOP
(14
14 mm)
(375 mil, 0.65-mm pitch)
64-pin plastic QFP
(12
12 mm)
48
PD75P3216
APPENDIX B. DEVELOPMENT TOOLS
The following development tools have been provided for system development using the
PD75P3216.
In the 75XL series, relocatable assemblers common to the series can be used in combination with the device files for
each product type.
RA75X relocatable assembler
Host machine
Part No. (name)
OS
Supply medium
PC-9800 Series
MS-DOS
TM
3.5" 2HD
S5A13RA75X
Ver.3.30 to
5" 2HD
S5A10RA75X
Ver.6.2
Note
IBM PC/AT
TM
Refer to "OS for
3.5" 2HC
S7B13RA75X
or compatible
IBM PCs"
5" 2HC
S7B10RA75X
Device file
Host machine
Part No. (name)
OS
Supply medium
PC-9800 Series
MS-DOS
TM
3.5" 2HD
S5A13DF753208
Ver.3.30 to
5" 2HD
S5A10DF753208
Ver.6.2
Note
IBM PC/AT
Refer to "OS for
3.5" 2HC
S7B13DF753208
or compatible
IBM PCs"
5" 2HC
S7B10DF753208
Note Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described
above.
49
PD75P3216
PROM Write Tools
Hardware
PG-1500
This is a PROM programmer that can program single-chip microcomputer with PROM in
stand alone mode or under control of host machine when connected with supplied
accessory board and optional programmer adapter.
It can also program typical PROMs in capacities ranging from 256 K to 4 M bits.
PA-75P3216GT
This is a PROM programmer adapter for the
PD75P3216GT.
It can be used when connected to a PG-1500.
Software
PG-1500 controller
Connects PG-1500 to host machine with serial and parallel interface and controls PG-1500
on host machine.
Host machine
Part No. (name)
OS
Supply medium
PC-9800 Series
MS-DOS
3.5" 2HD
S5A13PG1500
Ver.3.30 to
5" 2HD
S5A10PG1500
Ver.6.2
Note
IBM PC/AT
Refer to "OS for
3.5" 2HD
S7B13PG1500
or compatible
IBM PCs"
5" 2HC
S7B10PG1500
Note
Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remark
Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described
above.
50
PD75P3216
Debugging Tools
In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the
PD75P3216.
Various system configurations using these in-circuit emulators are listed below.
Hardware
IE-75000-R
Note 1
The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging
during development of application systems using the 75X or 75XL Series products.
For development of the
PD753208 subseries, the IE-75000-R is used with optional
emulation board (IE-75300-R-EM) and emulation probe (EP-753208GT-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
The IE-75000-R includes a connected emulation board (IE-75000-R-EM).
IE-75001-R
The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging
during development of application systems using the 75X or 75XL Series products.
The IE-75001-R is used in combination with optional emulation board (IE-75300-R-EM) and
emulation probe (EP-753208GT-R).
Highly efficient debugging can be performed when connected to host machine and PROM
programmer.
IE-75300-R-EM
This is an emulation board for evaluating application systems using the
PD75P3216.
It is used in combination with the IE-75000-R or IE-75001-R.
EP-753208GT-R
This is an emulation probe for the
PD75P3216GK.
When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-
EM.
EV-9500GT-48
It includes a flexible board (EV-9500GT-48) to facilitate connections with target system.
Software
IE control program
This program can control the IE-75000-R or IE-75001-R on a host machine when connected
to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.
Host machine
Part No. (name)
OS
Supply medium
PC-9800 Series
MS-DOS
3.5" 2HD
S5A13IE75X
Ver.3.30 to
5" 2HD
S5A10IE75X
Ver.6.2
Note 2
IBM PC/AT
Refer to "OS for
3.5" 2HC
S7B13IE75X
or compatible
IBM PCs"
5" 2HC
S7B10IE75X
Notes 1. This is a maintenance product.
2. Ver. 5.00 or later includes a task swapping function, but this software is not able to use that function.
Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS described
above.
2. The generic name for the
PD753204, 753206, 753208, and 75P3216 is the
PD753208 subseries.
51
PD75P3216
OS for IBM PCs
The following operating systems for the IBM PC are supported.
OS
Version
PC DOS
TM
Ver.5.02 to Ver.6.3
J6.1/V
Note
to J6.3/V
Note
MS-DOS
Ver.5.0 to Ver.6.22
5.0/V
Note
to 6.2/V
Note
IBM DOS
TM
J5.02/V
Note
Note
Only English version is supported.
Caution Ver. 5.0 or later include a task swapping function, but this software is not able to use that function.
52
PD75P3216
APPENDIX C. RELATED DOCUMENTS
Some of the related documents are preliminary but are not marked as such.
Device related documents
Document Name
Document Number
Japanese
English
PD753204, 753206, 753208 preliminary product information
U10166J
U10166E
PD75P3216 data sheet
U10241J
This document
PD753208 user's manual
U10158J
U10158E
75XL series selection guide
U10453J
U10453E
Development tool related documents
Document Name
Document Number
Japanese
English
Hardware
IE-75000-R/IE-75001-R user's manual
EEU-846
EEU-1416
IE-75300-R-EM user's manual
U11354J
U11354E
EP-753208GT-R user's manual
U10739J
U10739E
PG-1500 user's manual
EEU-651
EEU-1335
Software
RA75X assembler package user's manual
Operation
EEU-731
EEU-1346
Language
EEU-730
EEU-1363
PG-1500 controller user's manual
PC-9800 series
EEU-704
EEU-1291
(MS-DOS) base
IBM PC series
EEU-5008
U10540E
(PC DOS) base
Other related documents
Document Name
Document Number
Japanese
English
IC package manual
C10943X
Semiconductor device mounting technology manual
C10535J
C10535E
Quality grade on NEC semiconductor devices
C11531J
C11531E
NEC semiconductor device reliability/quality control system
C10983J
C10983E
Static electricity discharge (ESD) test
MEM-539
Semiconductor device quality guarantee guide
MEI-603
MEI-1202
Microcomputer related product guide - other manufacturers
U11416J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
documents for designing, etc.
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NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconductor
devices must not be touched with bare hands. Similar precautions need to be
taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS devices
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
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NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.1.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951
NEC do Brasil S.A.
Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J96. 8
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[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
MS-DOS is a trademark of Microsoft Corporation.
IBM DOS, PC/AT, and PC DOS are trademarks of IBM Corporation.