ChipFind - документация

Электронный компонент: UPD77019GC

Скачать:  PDF   ZIP

Document Outline

PD77018A, 77019 are 16 bits fixed-point DSPs (Digital Signal Processors) developed for digital signal processing
with its demand for high speed and precision.
Maximum operating speed of the
PD77018A, 77019 is improved compared with the
PD77015, 77017, 77018.
And the
PD77019 internal instruction RAM (4K
32 bits) is suitable for program code replacement.
FEATURES
FUNCTIONS
Instruction cycle: 16.6 ns (MIN.)
Operation clock: 60 MHz
External clock: 60, 30, 20, 15, 7.5 MHz
Crystal: 60 MHz
On-chip PLL to provide higher operation clock than the external clock
Dual load/store
Hardware loop function
Conditional execution
Executes product-sum operation in one instruction cycle
PROGRAMMING
16 bits
16 bits + 40 bits
40 bits multiply accumulator
8 general registers (40 bits each)
8 ROM/RAM data pointer: each data memory area has 4 registers
10 source interrupts (external: 4, internal: 6)
3 operand instructions (example: R0 = R0 +R1L
R2L)
Nonpipeline on execution stage
MEMORY AREAS
Instruction memory area : 64K words
32 bits
Data memory areas : 64K words
16 bits
2
(X memory, Y memory)
In this document, all descriptions of the
PD77018A also apply to the
PD77019, unless otherwise
specified.
MOS INTEGRATED CIRCUIT
16 bits, Fixed-point Digital Signal Processor
PD77018A, 77019
The mark
shows major revised points.
Document No. U11849EJ2V0DS00 (2nd edition)
Date Published October 1997 N
Printed in Japan
The information in this document is subject to change without notice.
1996
DATA SHEET
PD77018A, 77019
2
CLOCK GENERATOR
Mask option for CLKOUT pin:
Fixed to the low level.
Does not output the internal system clock.
Selectable source clock: external clock input and crystal resonator
[External clock]
On-chip PLL to provide higher operation clock (60 MHz max.) than the external clock.
Variable multiple rates (1, 2, 3, 4, 8) by mask option.
[Crystal resonator]
Oscillation frequency corresponds directly to the system clock frequency (Sure to specify the mask option
frequency multiple as "1").
ON-CHIP PERIPHERAL
I/O port: 4 bits
Serial I/O (16 bits): 2 channels
Host I/O (8 bits): 1 channel
CMOS
+3 V single power supply
ORDERING INFORMATION
Part Number
Package
PD77018AGC-
-9EU
100-pin plastic TQFP (FINE PITCH) (14
14 mm)
PD77019GC-
-9EU
100-pin plastic TQFP (FINE PITCH) (14
14 mm)
Remark
indicates a code suffix.
3
PD77018A, 77019
BLOCK DIAGRAM
Serial
I/O #1
Serial
I/O #2
Ports
Host I/O
X Memory
Data
Pointers
X Memory
Y Memory
Data
Pointers
Y Memory
Interrupt
Control
Loop
Control
Stack
PC Stack
Instruction
Memory
CPU Control
MPY
16
16+40
40
ALU (40)
R0R7
XBus
YBus
External
Memory
INT1 INT4
RESET CLKOUT
X1
Main Bus
X2
Wait
Controller
IE I/O
WAIT
PD77018A, 77019
4
FUNCTIONAL PIN GROUPS
SO1
SORQ1
SOEN1
SCK1
SI1
SIEN1
SIAK1
SO2
SOEN2
SCK2
SI2
SIEN2
P0 - P3
HCS
HA0, HA1
HRD
HRE
HWR
HWE
HD0 - HD7
(8)
(2)
(4)
Serial Interface #1
Serial Interface #2
Host Interface
Ports
RESET
INT1
INT2
INT3
INT4
X / Y
DA0 - DA13
D0 - D15
WAIT
MRD
MWR
External
Data
Memory
Data Bus
Control
Interrupts
(14)
(16)
+3 V
V
DD
GND
X1
X2
CLKOUT
HOLDRQ
BSTB
HOLDAK
TDO, TICE
TCK, TDI, TMS
Debugging
Interface
(2)
(3)
5
PD77018A, 77019
Item
PD77016
PD77015
PD77017
PD77018
PD77018A
PD77019
Internal instruction RAM
1.5K words
256 words
4K words
Internal instruction ROM
None
4K words
12K words
24K words
External instruction memory
48K words
None
Data RAM (X/Y memory)
2K words each
1K words each
2K words each
3K words each
Data ROM (X/Y memory)
None
2K words each
4K words each
12K words each
External data memory
48K words each
16K words each
Instruction cycle
(Maximum operation speed)
External clock
(at maximum operation speed)
Crystal
(at maximum operation speed)
Instruction
STOP instruction is added.
Serial interface (2 Channels)
Power supply
5V
3 V
Package
160-pin plastic QFP
100-pin plastic TQFP
Functional Differences among the
PD7701
Family
Channel 1 has the
same functions
as channel 2.
Channel 1 has the same functions as that of the
PD77016.
Channel 2 has no SORQ2 or SIAK2 pin (Channel 2 is used for CODEC connection).
33/16.5/8.25/4.125 MHz
Variable multiple rate (1, 2, 4, 8 ) by mask option.
66 MHz
60/30/20/15/7.5 MHz
Variable multiple rate (1, 2, 3, 4, 8 ) by
mask option.
60 MHz
30 ns (33 MHz)
16.6 ns (60 MHz)
33 MHz
PD77018A, 77019
6
PIN CONFIGURATION
100-pin plastic TQFP (FINE PITCH) (14
14 mm ) (Top View)
100
WAIT
99
BSTB
98
MRD
97
V
DD
96
GND
95 94 93
MWR
HOLDAK
HOLDRQ
92
TMS
91
TDI
90
TCK
89
TICE
88
TDO
87
CLKOUT
86
V
DD
85 84 83
X1
X2
GND
82
HA1
81
HA0
80
HWR
79
HRD
78
HCS
77
HD0
76
HD1
HD2
75
HD3
74
HD4
73
HD5
72
HD6
71
HD7
70
V
DD
69
GND
68
HWE
67
HRE
66
P0
65
P1
64
P2
63
P3
62
SI2
61
SIEN2
60
SCK2
59
SO2
58
SOEN2
57
V
DD
56
GND
55
SOEN1
54
SORQ1
53
SO1
52
SIAK1
51
RESET
INT4
INT3
INT2
INT1
I.C.
X/Y
DA13
DA12
GND
V
DD
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
GND
V
DD
DA3
DA2
DA1
DA0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
D15
D14
D13
D12
GND
V
DD
D11
D10
D9
D8
GND
V
DD
D7
D6
D5
D4
GND
V
DD
D3
D2
D1
D0
SI1
SIEN1
SCK1
7
PD77018A, 77019
BSTB:
Bus Strobe
CLKOUT:
Clock Output
D0-D15:
16 Bits Data Bus
DA0-DA13:
External Data Memory Address Bus
GND:
Ground
HA0,HA1:
Host Data Access
HCS:
Host Chip Select
HD0-HD7:
Host Data Bus
HOLDAK:
Hold Acknowledge
HOLDRQ:
Hold Request
HRD:
Host Read
HRE:
Host Read Enable
HWE:
Host Write Enable
HWR:
Host Write
I.C.:
Internally connection
INT1-INT4:
Interrupt
MRD:
Memory Read Output
MWR:
Memory Write Output
P0-P3:
Port
RESET:
Reset
SCK1,SCK2:
Serial Clock Input
SI1,SI2:
Serial Data Input
SIAK1:
Serial Input Acknowledge
SIEN1,SIEN2:
Serial Input Enable
SO1,SO2:
Serial Data Output
SOEN1,SOEN2: Serial Output Enable
SORQ1:
Serial Output Request
TCK:
Test Clock Input
TDI:
Test Data Input
TDO:
Test Data Output
TICE:
Test In-Circuit Emulator
TMS:
Test Mode Select
V
DD
:
Power Supply
WAIT:
Wait Input
X1:
Clock input/crystal connection
X2:
Crystal connection
X/Y:
X/Y Memory Select
PIN IDENTIFICATION
PD77018A, 77019
8
PIN NAME
Pin No.
Symbol
1
RESET
2
INT4
3
INT3
4
INT2
5
INT1
6
I.C.
Note
7
X/Y
8
DA13
9
DA12
10
GND
11
V
DD
12
DA11
13
DA10
14
DA9
15
DA8
16
DA7
17
DA6
18
DA5
19
DA4
20
GND
21
V
DD
22
DA3
23
DA2
24
DA1
25
DA0
Pin No.
Symbol
26
D15
27
D14
28
D13
29
D12
30
GND
31
V
DD
32
D11
33
D10
34
D9
35
D8
36
GND
37
V
DD
38
D7
39
D6
40
D5
41
D4
42
GND
43
V
DD
44
D3
45
D2
46
D1
47
D0
48
SI1
49
SIEN1
50
SCK1
Pin No.
Symbol
51
SIAK1
52
SO1
53
SORQ1
54
SOEN1
55
GND
56
V
DD
57
SOEN2
58
SO2
59
SCK2
60
SIEN2
61
SI2
62
P3
63
P2
64
P1
65
P0
66
HRE
67
HWE
68
GND
69
V
DD
70
HD7
71
HD6
72
HD5
73
HD4
74
HD3
75
HD2
Pin No.
Symbol
76
HD1
77
HD0
78
HCS
79
HRD
80
HWR
81
HA0
82
HA1
83
GND
84
X2
85
X1
86
V
DD
87
CLKOUT
88
TDO
89
TICE
90
TCK
91
TDI
92
TMS
93
HOLDRQ
94
HOLDAK
95
MWR
96
GND
97
V
DD
98
MRD
99
BSTB
100
WAIT
Note I.C. (Internally Connected): Leave this pin open.
9
PD77018A, 77019
CONTENTS
1.
PIN FUNCTIONS ............................................................................................................................... 10
1.1
Pin Functions ........................................................................................................................................... 10
1.2
Recommended Connection for Unused Pins ....................................................................................... 15
2.
FUNCTIONS ...................................................................................................................................... 16
2.1
Pipeline Processing ................................................................................................................................ 16
2.1.1
Outline ........................................................................................................................................... 16
2.1.2
Instructions with Delay .................................................................................................................. 16
2.2
Program Control Unit .............................................................................................................................. 17
2.3
Operation Unit ......................................................................................................................................... 17
2.3.1
General register (R0 to R7) ........................................................................................................... 17
2.3.2
MAC: Multiply ACcumulator ......................................................................................................... 18
2.3.3
ALU: Arithmetic Logic Unit ........................................................................................................... 18
2.3.4
BSFT: Barrel ShiFTer ................................................................................................................... 18
2.3.5
SAC: Shifter And Count Circuit .................................................................................................... 18
2.3.6
CJC: Condition Judge Circuit ....................................................................................................... 19
2.4
Memory ..................................................................................................................................................... 19
2.4.1
Instruction RAM Outline ................................................................................................................ 20
2.4.2
Data Memory Outline .................................................................................................................... 21
2.4.3
Data Memory Addressing .............................................................................................................. 22
2.5
On-chip Peripheral Circuit ...................................................................................................................... 22
2.5.1
Serial Interface Outline .................................................................................................................. 22
2.5.2
Host Interface Outline ................................................................................................................... 22
2.5.3
General Input/output Ports Outline ................................................................................................ 22
2.5.4
Wait Cycle Register ....................................................................................................................... 22
3.
INSTRUCTIONS ................................................................................................................................ 23
3.1
Outline ...................................................................................................................................................... 23
3.2
Instruction Set and Operation ................................................................................................................ 24
4.
ELECTRICAL SPECIFICATIONS ..................................................................................................... 32
5.
PACKAGE DRAWING ...................................................................................................................... 53
6.
RECOMMENDED SOLDERING CONDITIONS ................................................................................ 54
PD77018A, 77019
10
1. PIN FUNCTIONS
1.1 Pin Functions
Power supply
V
DD
+3V power supply
GND
Ground
System control
Symbol
Pin No.
I/O
Function
X1
85
I
Clock input / crystal connection pin
The clock signal is connected to X1, when using external
clock for system clock.
X2
84
_
Crystal connection pin
X2 should be left open when using external clock for
system clock.
CLKOUT
87
O
Internal system clock output
RESET
1
I
Internal system reset signal input
Symbol
Pin No.
I/O
Function
11, 21, 31, 37, 43, 56, 69,
86, 97
10, 20, 30, 36, 42, 55, 68,
83, 96
Interrupt
Symbol
Pin No.
I/O
Function
INT4 - INT1
2 - 5
I
Maskable external interrupt input
Falling edge detection
11
PD77018A, 77019
Remark
The state of the pins added 3S becomes high impedance when bus release signal (HOLDAK = 0) is output.
External data memory interface
Symbol
Pin No.
I/O
Function
X/Y
7
O
Memory select signal output
(3S)
0: X memory is used.
1: Y memory is used.
DA13 - DA0
8, 9, 12 -19, 22 - 25
O
Address bus to external data memory
(3S)
External data memory is accessed.
During the external memory is not accessed, these pins
keep the previous level.
These pins are set to low level; 0000H, by reset.
They continue outputting low level until the first external
memory access.
D15 - D0
26 -29, 32 - 35, 38 - 41,
I/O
16 bits data bus to external data memory
44 - 47
(3S)
External data memory is accessed.
MRD
98
O
Read output
(3S)
Reads external memory
MWR
95
O
Write output
(3S)
Writes external memory
WAIT
100
I
Wait signal input
Wait cycle is input when external memory is read.
1: No wait
0: Wait
HOLDRQ
93
I
Hold request signal input
Input low level when external data memory bus is
expected to use.
BSTB
99
O
Bus strobe signal output
Outputs low level while the
PD77018A is occupying
external memory bus.
HOLDAK
94
O
Hold acknowledge signal output
Outputs low level when the
PD77018A permits external
device to use external data memory bus.
PD77018A, 77019
12
Serial interface
Symbol
Pin No.
I/O
Function
SCK1
50
I
Clock input for serial 1
SORQ1
53
O
Serial output 1 request
SOEN1
54
I
Serial output 1 enable
SO1
52
O (3S)
Serial data output 1
SIEN1
49
I
Serial input 1 enable
SI1
48
I
Serial data input 1
SCK2
59
I
Clock input for serial 2
SOEN2
57
I
Serial output 2 enable
SO2
58
O (3S)
Serial data output 2
SIEN2
60
I
Serial input 2 enable
SI2
61
I
Serial data input 2
SIAK1
51
O
Serial input 1 acknowledge
Remark
The state of the pins added 3S becomes high impedance, when data output have been finished or RESET is input.
13
PD77018A, 77019
Symbol
Pin No.
I/O
Function
HA1
82
I
Specifies register which HD7 to HD0 access
1:
Accesses HST:
Host interface status register
when HA1 = 0
0:
Accesses HDT(in): Host transmit data register when
HWR = 0
0:
Accesses HDT(out): Host receive data register when
HRD = 0
HA0
81
I
Specifies bits of registers which HD7 to HD0 access
1: Accesses bits 15-8 of HST, HDT(in) or HDT(out)
0: Accesses bits 7-0 of HST, HDT(in) or HDT(out)
HCS
78
I
Chip select input
HRD
79
I
Host read input
HWR
80
I
Host write input
HRE
66
O
Host read enable output
HWE
67
O
Host write enable output
HD7 - HD0
70 - 77
I/O (3S)
8 bits host data bus
Host interface
Remark
The state of the pins added 3S becomes high impedance when the host does not access host interface.
I/O port
Symbol
Pin No.
I/O
Function
P3 - P0
62 - 65
I/O
I/O port
PD77018A, 77019
14
Symbol
Pin No.
I/O
Function
I.C.
6
_
Internal connected pin. Leave this pin open.
Caution When any signal is applied to or read
out from this pin, normal operation of
the
PD77018A is not assured.
Symbol
Pin No.
I/O
Function
TDO
88
O
For debugging
TICE
89
O
For debugging
TCK
90
I
For debugging
TDI
91
I
For debugging
TMS
92
I
For debugging
Debugging interface
Other
15
PD77018A, 77019
Recommended connection
connect to V
DD
open
connect to V
DD
or GND, via a resistor
open
connect to V
DD
open
connect to V
DD
or GND
connect to GND
open
connect to V
DD
or GND
connect to V
DD
open
connect to V
DD
or GND, via a resistor
connect to GND, via a resistor
open
open(pull-up internally)
open
Pin I/O
INT1 - INT4
I
X/Y
O
DA0 - DA13
O
D0 - D15
Note1
I/O
MRD
O
MWR
O
WAIT
I
HOLDRQ
I
BSTB
O
HOLDAK
O
SCK1, SCK2
I
SI1, SI2
I
SOEN1, SOEN2
I
SIEN1, SIEN2
I
SORQ1
O
SO1, SO2
O
SIAK1
O
HA0, HA1
I
HCS
I
HRD
I
HWR
I
HRE
O
HWE
O
HD0 - HD7
Note2
I/O
P0 - P3
I/O
TCK
I
TDO, TICE
O
TMS, TDI
I
CLKOUT
O
1.2 Recommended Connection for Unused Pins
Notes 1. Can leave open, if no access to external data memory is
executed in the whole of program.
2. Can leave open, if HCS, HRD, HWR are fixed to high level.
Remark I:
Input pin
O:
Output pin
I/O: Input/Output pin
PD77018A, 77019
16
2. FUNCTIONS
2.1 Pipeline Processing
This section describes the
PD77018A pipeline processing.
2.1.1 Outline
The
PD77018A basic operations are executed in following 3-stage pipeline.
(1) instruction fetch; if
(2) Instruction decoding; id
(3) execution; ex
When the
PD77018A operates a result of a instruction just executed before, the data is input to ALU in parallel
with written back to general registers. Pipeline processing actualizes programming without delay time to execute
instructions and write back data. Three successive instructions and their processing timing are shown below.
Pipeline Processing Timing
2.1.2 Instructions with Delay
The following instructions have delay time in execution.
(1) Instructions to control interrupt
2 instruction cycles have been taken between instruction fetch and execution.
(2) Inter-register transfer instructions and immediate data set instructions
When data is set in data pointer, it needs 2 instruction cycles before the data is valid.
if1
id1
ex1
if2
id2
ex2
if3
id3
ex3
1 instruction cycle
17
PD77018A, 77019
2.2 Program Control Unit
Program control unit controls not only count up of program counter in normal operation, but loop, repeat,
branch, halt and interrupt.
In addition to loop stack of loop 4 level and program stack of 15 level, software stack can be used for multi-
loop and multi-interrupt/subroutine call.
The
PD77018A has external 4 interruptions and internal 6 interruptions from peripheral, and specifies
interrupt enable or disable independently.
The HALT and STOP instructions cause the
PD77018A to place in low power standby mode.
When the HALT instruction is executed, power consumption decreases. HALT mode is released by interrupt
input or hardware reset input. It takes several system clock to recover.
When the STOP instruction is executed, power consumption decreases. STOP mode is released by hardware
reset input. It takes a few ms to recover.
2.3 Operation Unit
Operation unit consists of the following five parts.
40 bits general register
8 for data load/store and input/output of operation data
16 bits
16 bits + 40 bits
40 bits multiply accumulator
40 bits Data ALU
40 bits barrel shifter
SAC: shifter and count circuit.
Standard word length is 40 bits to make overflow check and adjustment easy, and to accumulate the result
of 16 bits
16 bits multiplication correctly.
2.3.1 General register (R0 to R7)
The
PD77018A has eight 40 bits registers for operation input/output and load/store with memory. General
register consists of the following three parts.
R0L to R7L (bit 15 to bit 0)
R0H to R7H (bit 31 to bit 16)
R0E to R7E (bit 39 to bit 32)
But each of RnL, RnH and RnE are treated as a register in the following conditions.
(1) General register used as 40 bits register
General registers are treated as 40 bits register, when they are used for the following aims.
(a) Operand for triminal operation (except for multiplier input)
(b) Operand for dyadic operation (except for multiplier and shift value)
(c) Operand for monadic operation (except for exponent instructions)
(d) Operand for operation
(e) Operand for conditional judge
(f)
Destination for load instruction (with sign extension and 0 clear)
Head room
0
0
1
31
32
39
S S S S S S S S
Result of multiplication among two's complement data
PD77018A, 77019
18
(2) General register used as 32 bits register
Bit 31 to bit 0 of general register are treated as 32 bits register, when it is used for a operand of exponent
instruction.
(3) General register used as 24 bits register
Bit 39 to bit 16 of general register are treated as 24 bits register, when it is used for destination with extended
sign for a load/store instruction.
(4) General register used as 16 bits register
Bit 31 to bit 16 of general register are treated as 16 bits register, when it is used for the following aims.
(a) Signed operand for multiplier
(b) Source/destination for load/store instruction
Bit 15 to bit 0 of general register are treated as 16 bits register, when it is used for the following aims.
(c) Unsigned operand for multiplier
(d) Shift value for shift instruction
(e) Source/destination for load/store instruction
(f)
Source/destination for inter-register transfer instruction
(g) Destination for immediate data set instruction
(f)
Hardware loop times
(5) General register used as 8 bits register
Bit 39 to bit 32 of general register are treated as 8 bits register, when it is used for source/destination of load/
store instruction.
2.3.2 MAC: Multiply ACcumulator
MAC multiplies a pair of 16 bits data, and adds or subtract the result and 40 bits data. MAC outputs 40 bits
data.
MAC operates three types of multiplication: signed data
signed data, signed data
unsigned data and
unsigned data
unsigned data.
Result of multiplication and 40 bits data for addition can be added after 1 or 16 bits arithmetic shift right.
2.3.3 ALU: Arithmetic Logic Unit
ALU performs arithmetic operation and logic operation. Both input/output data are 40 bits.
2.3.4 BSFT: Barrel ShiFTer
BSFT performs shift right/left operation. Both input/output data are 40 bits. There are two types of shift right
operations; arithmetic shift right which sign is extended, and logic shift right which is input 0 in MSB first.
2.3.5 SAC: Shifter And Count Circuit
SAC calculates and outputs shift value for normalization. SAC is input 32 bits data and outputs the 40 bits
data. Then, bit 39 to bit 5 of output data is always 0.
19
PD77018A, 77019
2.3.6 CJC: Condition Judge Circuit
CJC judges whether condition is true or false with 40 bits input data. A conditional instruction is executed
when the result is true, and not executed when the result is false.
2.4 Memory
The
PD77018A has one instruction memory area (64K words
32 bits) and two data memory areas (64K
words
16 bits each). It adopts Harvard-type architecture, with instruction memory area and data memory areas
separated.
The
PD77018A has 2 sets of data addressing units, which are dedicated for addressing data memory area.
Each addressing unit consists of four data pointers, four index registers, a modulo register and addressing ALU.
X memory area addresses are specified by DP0 to DP3, and Y memory area addresses are specified by DP4
to DP7. After memory access, DPn (with the same subscript), can be modified by DNn value. Modulo operation
is performed with DMX for DP0 to DP3, with DMY for DP4 to DP7.
PD77018A, 77019
20
2.4.1 Instruction RAM Outline
The
PD77018A has an instruction ROM (24K words
32 bits) and instruction RAM (256 words
32 bits).
The
PD77019 has an instruction ROM (24K words
32 bits) and instruction RAM (4K words
32 bits).
A system vector area is assigned to 64 words of the instruction RAM. Internal instruction RAM is initialized
and rewritten by boot program.
Boot up ROM contains the program loading instruction code to internal instruction RAM.
Caution
When any data is accessed or stored to system address, normal operation of the device is
not assured.
0300H
02FFH
0240H
023FH
0000H
Internal Instruction ROM
(24K words)
PD77019
System (24K words)
PD77018A
4000H
3FFFH
System (24K words)
A000H
9FFFH
0200H
01FFH
System (256 words)
Bootup ROM (256 words)
Vector (64 words)
System (11.5K words)
Internal Instruction RAM
(4K words)
System (256 words)
Bootup ROM (256 words)
Vector (64 words)
System (15.25K words)
Internal Instruction RAM
(256 words)
Internal Instruction ROM
(24K words)
0100H
00FFH
1200H
11FFH
FFFFH
21
PD77018A, 77019
2.4.2 Data Memory Outline
The
PD77018A and the
PD77019 each has two data memory areas (64K words
16 bits each) in X and
Y memory areas.
Every memory areas consists of 3K words
16 bits data RAM and 12K words
16 bits data ROM . As the
PD77018A and the
PD77019 each has interface with the external data memory, 16 K words
16 bits external
data memory space can be added to X/Y memories.
Each data memory area includes on-chip peripheral area which consists of 64 words.
When the external data memory area is accessed, instruction cycle can be 2 or more by wait function.
Caution
When any data is accessed or stored to system address, normal operation of the device is
not assured.
3840H
383FH
0000H
System (1984 words)
System (11K words)
Data RAM (3K words)
External Data Memory
(16K words)
PD77018A, 77019
Peripheral (64 words)
4000H
3FFFH
FFFFH
System (20K words)
0C00H
0BFFH
7000H
6FFFH
C000H
BFFFH
Data ROM (12K words)
3800H
37FFH
PD77018A, 77019
22
2.4.3 Data Memory Addressing
There are following two types of data memory addressing.
Direct addressing
The address is specified in the instruction field.
Indirect addressing
The address is specified by the data pointer (DP). DP can get a bit reverse before addressing. It can
update the DP value after accessing data memory.
2.5 On-chip Peripheral Circuit
The
PD77018A includes serial interface, host interface, general input/output ports and wait cycle registers.
They are mapped in both X and Y memory areas, and are accessed as memory mapped I/O by the
PD77018A
CPU.
2.5.1 Serial Interface Outline
The
PD77018A has 2 channel serial interfaces. Serial I/O clock must be provided from external. Frame
length can be programmed independently to be 8 bits or 16 bits. MSB first or LSB first can also be selected.
Data is input/output by hand shaking for an external device, and by interrupts, polling or wait function in internal.
2.5.2 Host Interface Outline
The
PD77018A has 8 bits parallel ports as host interface to input/output data to and from host CPU and DMA
controller. When an external device accesses host interface, HA0 and HA1 pins; which are host address input
pins; specifies bit 15 to bit 8 and bit 7 to bit 0. The
PD77018A includes 3 registers consisting of 16 bits, which
are dedicated for input data, output data and status. The
PD77018A has three types of interface method for
internal and external data; interrupts, polling and wait function.
2.5.3 General Input/output Ports Outline
General input/output ports consist of 4 bits. User can set each port as input or output. The
PD77018A
includes two registers. One is 4 bits register for input/output data, and the other is 16 bits for control.
2.5.4 Wait Cycle Register
The wait cycle registers consist of 16 bits. It is used to set wait cycle number when external memory is
accessed. When external data memory area (C000H - FFFFH) is accessed, 0, 1, 3, or 7 wait cycle can be set.
When external data memory area is accessed, wait cycle can be also set by WAIT pin.
23
PD77018A, 77019
3. INSTRUCTIONS
3.1 Outline
All
PD77018A instructions are one-word instructions, consisting of 32 bits. And they are executed in 16.6 ns (min.)
per instruction. There are following 9 instruction types.
(1) Trinomial instructions
: specify the Acc operation. 3 of general registers are specified optionally as the operation object.
(2) Dyadic operation instructions
: specify the Acc, ALU or shifter operation. 2 of general registers are specified optionally as the operation
object. Some instructions can specify a general register and immediate data.
(3) Monadic operation instructions
: specify operations by ALU. 1 general register is specified optionally as the operation object.
(4) Load/store instructions
: transfer 16 bits data from memory to general registers, from general registers to memory and between
general registers.
(5) Inter-register transfer instructions
: transfer data between general register and other registers.
(6) Immediate data set instructions
: set immediate data at general registers or each registers of address operation unit.
(7) Branch instructions
: specify the direction of the program flow.
(8) Hardware loop instructions
: specify times of instruction repeating.
(9) Control Instructions
: specify the control program.
PD77018A, 77019
24
Expression
Selectable registers
ro, ro', ro"
R0 - R7
rl, rl'
R0L - R7L
rh, rh'
R0H - R7H
re
R0E - R7E
reh
R0EH - R7EH
dp
DP0 - DP7
dn
DN0 - DN7
dm
DMX, DMY
dpx
DP0 - DP3
dpy
DP4 - DP7
dpx_mod
DPn, DPn++, DPn , DPn##, DPn%%, !DPn## (n = 0 - 3)
dpy_mod
DPn, DPn++, DPn , DPn##, DPn%%, !DPn## (n = 4 - 7)
dp_imm
DPn##imm (n = 0 - 7)
content of memory address
Example
When the content of DP0 register is 1000,
DP0 shows the content of memory
address 1000.
3.2 Instruction Set and Operation
An operation is written according to the rules for expressing. An expression of instructions having two or more
descriptions can have only one selected.
(a) Expressions and selectable registers
Expression and selectable registers are shown as follows.
25
PD77018A, 77019
(b) Modifying data pointers
Data pointers are modified after memory access. The results are valid immediately after instruction execution.
It is impossible to modify without memory access.
Description
Operation
DPn
No operation: DPn value does not change.
DPn++
DPn
DPn+1
DPn
DPn
DPn1
DPn##
DPn
DPn + DNn: Adds DN0-DN7 corresponding to DP0-DP7
Example DP0
DP0 + DN0
DPn%%
(n = 0 - 3) DPn = ((DP
L
+ DNn )mod (DMX + 1)) + DP
H
(n = 4 - 7) DPn = ((DP
L
+ DNn )mod (DMY + 1)) + DP
H
!DPn##
Access memory after DPn value is bit-reversed
After memory access, DPn
DPn + DNn
DPn##imm
DPn
DPn + imm
(c) Concurrent processing instructions
shows concurrent processing instruction.
Instruction names are shown in abbreviation.
TRI
: Trinomial
DYAD
: Dyadic
MONAD : Monadic
TRANS
: Inter-register transfer
IMM
: Immediate data set
BR
: Branch
LOOP
: Hardware loop
CTR
: Control
(d) State of Overflow flag (OV)
The following marks show the
PD77018A overflow flag state.
: Not affected
: 1 is set when the result of operation is overflow.
Caution
If overflow does not occur after operation, OV is not reset, and keeps the state before
operation.
PD77018A, 77019
26
Concurrent Writing Processing
Flag
TRI.
DYAD. MONAD.
Load/
TRANS.
IMM.
BR. LOOP.
CTL. OV
store
Trinomial
Dyadic
Multiply add
ro = ro + rh
rh'
ro
ro+rh
rh'
Multiply sub
ro = rorh
rh'
ro
rorh
rh'
Sign unsign
ro = ro + rh
rl
ro
ro+rh
rl
Multiply add
(rl should be a plus
integral number.)
Unsign unsign
ro=ro+rl
rl'
ro
ro+rl
rl'
Multiply add
(rl and rl' should be a plus
integral number.)
1 bit shift Multiply add
ro=(ro>>1)+rh
rh'
ro
+rh
rh'
16 bits shift Multiply add
ro = (ro>>16)+rh
rh'
ro
+rh
rh'
Multiply
ro=rh
rh'
ro
rh
rh'
Add
ro"=ro+ro'
ro"
ro+ro'
Immediate add
ro'=ro+imm
ro'
ro+imm (imm
1)
Sub
ro"=roro'
ro"
roro'
Immediate sub
ro'=roimm
ro'
roimm (imm
1)
Arithmetic right shift
ro'=ro SRA rl
ro'
ro >> rl
Immediate arithmetic
ro'=ro SRA imm
ro'
ro >> imm
right shift
Logic right shift
ro'=ro SRL rl
ro'
ro >> rl
Immediate Logic right shift
ro'=ro SRL imm
ro'
ro >> imm
Logic left shift
ro'=ro SLL rl
ro'
ro << rl
Immediate logic left shift
ro'=ro SLL imm
ro'
ro << imm
ro
2
ro
2
16

Name
Mnemonic
Operation
PD77018A INSTRUCTION SET
27
PD77018A, 77019
Dyadic
Monadic
Concurrent Writing Processing
Flag
TRI.
DYAD. MONAD.
Load/
TRANS.
IMM.
BR. LOOP.
CTL. OV
store
Name
Mnemonic
Operation
And
ro" = ro & ro'
ro"
ro & ro'
Immediate and
ro' = ro & imm
ro'
ro & imm
Or
ro" = ro | ro'
ro"
ro | ro'
Immediate or
ro' = ro | imm
ro'
ro | imm
Exclusive or
ro" = ro ^ ro'
ro"
ro ^ ro'
Immediate exclusive or
ro = ro ^ imm
ro
ro ^ imm
Less than
ro" = LT(ro, ro')
if(ro<ro')
{ro"
0000000001H}
else {ro"
0000000000H}
Clear
CLR(ro)
ro
0H
Increment
ro' = ro + 1
ro'
ro + 1
Decrement
ro' = ro 1
ro'
ro 1
Absolute
ro' = ABS (ro)
if (ro<0)
{ro'
ro}
else {ro'
ro}
One's complement
ro' =
~
ro
ro'
~
ro
Two's complement
ro' = ro
ro'
ro
Clip
ro' = CLIP (ro)
if (ro>007FFFFFFFH)
{ro'
007FFFFFFFH]
else if, (ro<FF80000000H)
{ro'
FF80000000H}
else {ro'
ro}
Round
ro' = ROUND (ro)
if (ro>007FFF0000H)
{ro'
007FFF0000H}
else if, (ro>FF80000000H)
{ro'
FF80000000H}
else {ro'
(ro + 8000H) & FFFFFF0000H}
Exponent
ro' = EXP (ro)
ro'
log
2
Substitution
ro' = ro
ro'
ro
1
ro
( )
PD77018A, 77019
28
Monadic
Cumulation
ro'+ = ro
ro'
ro'+ro
Degression
ro' = ro
ro'
ro'ro
Division
ro'/ = ro
if (sign(ro')==sign(ro))
{ro'
(ro'ro)<<1}
else
{ro'
(ro'+ro)<
if (sign(ro')==0
{ro'
ro'+1}
Parallel load/store
ro=
dpx_mod ro'=
dpy_mod
ro
dpx, ro'
dpy
Note 1, Note 2
ro=
dpx_mod
dpy_mod=rh
ro
dpx,
dpy
rh
dpx_mod=rh ro=
dpy_mod
dpx
rh, ro
dpy
dpx_mod=rh
dpy_mod=rh'
dpx
rh,
dpy
rh'
Section load/store
dest=
dpx_mod dest'=
dpy_mod
dest
dpx, dest'
dpy
Note 1, Note 2, Note 3
dest=
dpx_mod
dpy_mod=source
dest
dpx,
dpy
source
dpx_mod=source dest=
dpy_mod
dpx
source, dest
dpy
dpx_mod=source
dpy_mod=source'
dpx
source,
dpy
source'
Concurrent Writing Processing
Flag
TRI.
DYAD. MONAD.
Load/
TRANS.
IMM.
BR. LOOP.
CTL. OV
store
Name
Mnemonic
Operation
Notes 1.
One or both of a mnemonic pair can be written.
2.
After execution of load/store, data is modified by mod.
3.
One of following mnemonic should be selected: dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}.
Load/store
29
PD77018A, 77019
Load/store
Inter-register
transfer
Immediate
data set
Direct addressing
dest =
addr
dest
addr
load/store Note 1
addr = source
addr
source
Immediate index
dest =
dp_imm
dest
dp
load/store Note 2
dp_imm = source
dp
source
Inter-register transfer
dest = rl
dest
rl
Note 3
rl = source
rl
source
Immediate data set
rl = imm
rl
imm
(provided imm = 0-0xFFFF)
dp = imm
dp
imm
(provided imm = 0-0xFFFF)
dn = imm
dn
imm
(provided imm = 0-0xFFFF)
dm = imm
dm
imm
(provided imm = 1-0xFFFF)
Name
Mnemonic
Operation
Concurrent Writing Processing
Flag
TRI.
DYAD. MONAD.
Load/
TRANS.
IMM.
BR. LOOP.
CTL. OV
store
Notes 1.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, add = .
2.
One of following mnemonic should be selected: dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}.
3.
Any register except general registers should be selected as dest or source.
0: X-0xFFFF:X memory
0: Y-0xFFFF:Y memory
PD77018A, 77019
30
Concurrent Writing Processing
Flag
TRI.
DYAD. MONAD.
Load/
TRANS.
IMM.
BR. LOOP.
CTL. OV
store
Name
Mnemonic
Operation
Branch
Jump
JMP imm
PC
imm
Inter-register indirect jump
JMP dp
PC
dp
Subroutine call
CALL imm
SP
SP + 1
STK
PC + 1
PC
imm
Inter-register indirect
CALL dp
SP
SP + 1
subroutine call
STK
PC + 1
PC
dp
Return
RET
PC
STK
SP
SP 1
Return from interrupt
RETI
PC
STK
STK
SP 1 Restore the
interrupt enable flag
Repeat
REP count
start
RC
count
RF
0
repeat
PC
PC
RC
RC 1
end
PC
PC + 1
RF
1
Loop
LOOP count
start
RC
count
(Mnemonics more than two lines)
RF
0
repeat
PC
PC
RC
RC 1
end
PC
PC + 1
RF
1
Loop pop
LPOP
LC
LSR3
LE
LSR2
LS
LSR1
LSP
LSP1
No operation
NOP
PC
PC + 1
Halt
HALT
CPU stop
Note1
Stop
STOP
CPU, PLL, OSC Stop
Note2
If
IF (ro cond)
Conditional judge
Forget interrupt
FINT
Forget interrupt requests
Control
Hardware
loop

31
PD77018A, 77019
Notes 1.
The HALT instruction causes all function except for clock and PLL to halt. The system is placed in much
less power consumption mode.
The contents of internal registers and memories are maintained.
HALT is released by interrupt input. It takes several system clock to recover.
2.
The STOP instruction causes all function including clock and PLL to stop. The system is placed in a
minimum-power consumption mode.
The contents of internal registers and memories are not maintained.
After the STOP instruction is executed, pin status is maintained.
STOP is released by hardware reset. It takes a few ms to recover.
PD77018A, 77019
32
4. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= +25 C)
Parameters
Symbol
Conditions
Ratings
Unit
Power supply voltage
V
DD
0.5 to +4.6
V
Input voltage
V
I
2.7 V
V
DD
3.6 V
0.5 to +4.1
V
V
I
< V
DD
+0.5 V
Output voltage
V
O
0.5 to +4.6
V
Storage temperature
T
stg
65 to +150
C
Operating ambient temperature
T
A
40 to +85
C
Caution
Exposure to Absolute Maximum Ratings for extended periods may affect device reliability;
exceeding the ratings could cause permanent damage. The parameters apply independently.
The device should be operated within the limits specified under DC and AC Characteristics.
Recommended Operating Conditions
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Operating voltage
V
DD
PD77018A
t
cC
19.0 ns
2.7
3.0
3.6
V
t
cC
16.6 ns
3.0
3.3
3.6
V
PD77019
t
cC
20.0 ns
2.7
3.0
3.6
V
t
cC
16.6 ns
3.0
3.3
3.6
V
Input voltage
V
I
0
V
DD
V
Capacitance (T
A
= +25 C, V
DD
= 0 V)
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
10
pF
Output capacitance
C
O
10
pF
Input/output capacitance
C
IO
10
pF
f = 1 MHz
Unmeasured pins returned to
0 V.
33
PD77018A, 77019
DC Characteristics (T
A
= 40 to +85 C, V
DD
= 2.7 to 3.6 V)
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
High level input voltage
V
IH
Except for X1
0.7V
DD
V
DD
V
High level X1 input voltage
V
IHC
X1 input
0.8V
DD
V
DD
V
Low level input voltage
V
IL
0
0.2V
DD
V
High level output voltage
V
OH
I
OH
= 2.0 mA
0.7V
DD
V
I
OH
= 100
A
0.8V
DD
V
Low level output voltage
V
OL
I
OL
= 2.0 mA
0.2V
DD
V
High level input leak current
I
LIH
Except for TDI, TMS, V
I
= V
DD
10
A
Low level input leak current
I
LIL
Except for TDI, TMS, V
I
= 0 V
10
A
Pull-up pin current
I
PI
TDI, TMS, 0 V
V
I
V
DD
250
A
Power supply current
I
DD
PD77018A
Active mode, t
cC
= 25 ns,
TBD
125
Note 1
mA
V
IH
= V
DD
, V
IL
= 0 V, no load
PD77019
Active mode, t
cC
= 25 ns,
TBD
150
Note 1
mA
V
IH
= V
DD
, V
IL
= 0 V, no load
I
DDH
PD77018A
HALT mode, t
cC
= 200 ns,
13.5
Note2
mA
V
IH
= V
DD
, V
IL
= 0 V, no load
PD77019
HALT mode, t
cC
= 200 ns,
15
Note 2
mA
V
IH
= V
DD
, V
IL
= 0 V, no load
I
DDS
STOP mode, T
A
= +60C, V
IH
= V
DD
, V
IL
= 0 V,
100
A
no load
Notes 1. The MAX. value is measured when a special program that MAX. switching required is executed, and V
DD
= 3.6 V condition.
You can convert by each operation frequency f[MHz] on by each power supply V
DD
[V].
[
PD77018A] Max. current value (T
A
= +25C) = (1.15
V
DD
1.21)
f + 8 [mA]
[
PD77019]
Max. current value (T
A
= +25C) = (1.40
V
DD
1.74)
f + 18 [mA]
2. This value is measured when V
DD
= 3.6 V condition.
You can convert by each operation frequency f[MHz] on by each power supply V
DD
[V].
[
PD77018A] HALT current value (T
A
= +25C) = (0.15
V
DD
0.25)
f + 2 [mA]
[
PD77019]
HALT current value (T
A
= +25C) = (0.17
V
DD
0.38)
f + 5.9 [mA]
AC Timing Test Points
Input (except for X1)
0.7V
DD
0.45V
DD
0.2V
DD
0.7V
DD
0.45V
DD
0.2V
DD
Test points
X1
0.8V
DD
0.5V
DD
0.2V
DD
0.8V
DD
0.5V
DD
0.2V
DD
Test points
Output
0.7V
DD
0.45V
DD
0.2V
DD
0.7V
DD
0.45V
DD
0.2V
DD
Test points
PD77018A, 77019
34
AC Characteristics (T
A
= 40 to +85 C, V
DD
= 2.7 to 3.6 V)
Clock
Required Timing Condition (V
DD
= 2.7 V to 3.6 V)
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CLKIN cycle time
t
cCX
PD77018A
PLL multiple rate: 1
19
40
ns
PLL multiple rate: 2
38
80
ns
PLL multiple rate: 3
57
120
ns
PLL multiple rate: 4
76
160
ns
PLL multiple rate: 8
152
320
ns
PD77019
PLL multiple rate: 1
20
40
ns
PLL multiple rate: 2
40
80
ns
PLL multiple rate: 3
60
120
ns
PLL multiple rate: 4
80
160
ns
PLL multiple rate: 8
160
320
ns
CLKIN high level width
t
wCXH
8
t
cCX
8
ns
2t
rfCX
Note
CLKIN low level width
t
wCXL
8
t
cCX
8
ns
2t
rfCX
Note
CLKIN rise/fall time
t
rfCX
15
ns
Note 0.5t
cCX
t
rfCX
8 (MIN.)
Required Timing Condition (V
DD
= 3.0 V to 3.6 V)
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
CLKIN cycle time
t
cCX
PLL multiple rate: 1
16.6
40
ns
PLL multiple rate: 2
33.3
80
ns
PLL multiple rate: 3
50
120
ns
PLL multiple rate: 4
66.6
160
ns
PLL multiple rate: 8
133
320
ns
CLKIN high level width
t
wCXH
6.5
t
cCX
6.5
ns
2t
rfCX
Note
CLKIN low level width
t
wCXL
6.5
t
cCX
6.5
ns
2t
rfCX
Note
CLKIN rise/fall time
t
rfCX
15
ns
Note 0.5t
cCX
t
rfCX
6.5 (MIN.)
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Internal clock cycle time
t
cC
Active mode
t
cCX
/N
Note
ns
HALT mode
8t
cCX
/N
Note
ns
CLKOUT cycle time
t
cCO
t
cC
ns
CLKOUT level width
t
wCO
0.5t
cCO
5
ns
CLKOUT rise/fall time
t
rfCO
5
ns
Note N: PLL multiple rate (N = 1, 2, 3, 4, 8)
35
PD77018A, 77019
X1
X2
C1
C2
X1
X2
External Clock
Supply
NU
NU: Not Use. Leave Open.
Oscillator Circuit
Resonator
Recommended Circuit
Ceramic or crystal resonator
External clock
Cautions 1. When using system clock oscillator, wire the portion enclosed in broken lines in the figure
as follows to avoid adverse influences on the wiring capacitance:
Keep the wiring length as short as possible.
Do not cross the wiring over the other signal lines.
Do not route the wiring in the vicinity of lines through which a high fluctuating current
flows.
Always keep the ground point of the capacitor of the oscillator circuit at the same
potential as GND.
Do not connect the power source pattern through which a high current flows.
Do not extract signals from the oscillator.
2. When using ceramic resonator or crystal resonator, frequency multiple rate should be
specified to as 1 by mask option. The device does not operate in other frequency multiple
rate.
Recommended Oscillator Circuit Constants
TBD
PD77018A, 77019
36
Reset, Interrupt
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
RESET low level width
t
W(RL)
Crystal resonator is input,
3
Note 1
ms
at power on or STOP mode
External clock is input,
100
Note 1
s
at power on or STOP mode
Active mode or HALT mode
4t
cC
Note 2
ns
RESET recovery time
t
rec(R)
4t
cC
ns
INT1-INT4 low level width
t
W(INTL)
3t
cC
Note 2
ns
INT1-INT4 recovery time
t
rec(INT)
3t
cC
ns
Notes 1.
The t
w(RL)
indicates a time between crystal resonator or oscillator starts to provide clock and PLL
becomes stable. The t
w(RL)
depends on the rating of crystal resonator or oscillator. At power on, the
t
w(RL)
is measured after the point that power supply voltage reaches to 2.7V.
2.
Note that, during HALT mode, t
cC
is extended to 8 times as long as that of Active mode.
37
PD77018A, 77019
Clock Input/Output Timing
Internal clock
X1
CLKOUT
t
cCX
t
wCXH
t
wCXL
t
rfCX
t
rfCX
t
cC
t
cCO
t
wCO
t
rfCO
t
rfCO
t
wCO
Reset Timing
Interrupt Timing
RESET
t
w(RL)
t
rec(R)
INT1 - INT4
t
w(INTL)
t
rec(INT)
38
PD77018A, 77019
External Data Memory Access
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Read data setup time
t
suDDRD
15
ns
Read data hold time
t
hDDRD
0
ns
WAIT setup time
t
suWA
12
ns
WAIT hold time
t
hWA
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Address output delay time
t
dDA
8
ns
Address output hold time
t
hDA
0
ns
MRD output delay time
t
dDR
8
ns
MRD hold time
t
hDR
0
ns
Write data output valid time
t
vDDWD
16
ns
Write data output hold time
t
hDDWD
0
ns
MWR output delay time
t
dDW
0.25t
cC
5
ns
MWR setup time
t
suDW
0
ns
MWR low level width
t
wDWL
0.5t
cC
3
ns
+ t
cDW
Note
MWR high level width
t
wDWH
0.5t
cC
5
ns
Note t
cDW
: Data wait cycle
External Data Memory Access Timing (Read)
t
suDDRD
t
hDR
t
hWA
CLKOUT
DA0 -
DA13,
X/Y
D0 - D15
MRD
WAIT
t
dDA
t
dDR
t
suWA
t
suWA
t
hWA
t
hDDRD
t
hDA
PD77018A, 77019
39
External Data Memory Access Timing (Write)
t
hWA
CLKOUT
DA0 - DA13,
X/Y
D0 - D15
MWR
WAIT
t
dDA
t
suWA
t
suWA
t
hWA
t
wDWH
t
wDWL
t
hDDWD
t
dDW
t
suDW
Hi-Z
Hi-Z
t
vDDWD
t
vDDWD
t
hDA
40
PD77018A, 77019
Bus Arbitration
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HOLDRQ setup time
t
suHRQ
12
ns
HOLDRQ hold time
t
hHRQ
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
BSTB hold time
t
hBS
0
ns
BSTB output delay time
t
dBS
12
ns
HOLDAK output delay time
t
dHAK
12
ns
Data hold time when bus arbitration
t
h(BS-D)
30
ns
Data valid time after bus arbitration
t
v(BS-D)
15
ns
PD77018A, 77019
41
Bus Arbitration Timing (Bus idle)
CLKOUT
t
suHRQ
BSTB
HOLDRQ
HOLDAK
X/Y, DA0 - DA13,
MRD, MWR
t
hBS
(Bus busy)
Bus idle
t
dBS
t
dHAK
t
h(BS-D)
t
hHRQ
t
suHRQ
Bus release
Bus idle
(Bus busy)
t
hHRQ
t
v(BS-D)
t
dHAK
Hi-Z
42
PD77018A, 77019
Bus Arbitration Timing (Bus busy)
CLKOUT
t
suHRQ
BSTB
HOLDRQ
HOLDAK
X/Y, DA0 - DA13,
MRD, MWR
(Bus busy)
Bus busy
t
hBS
t
dHAK
t
suHRQ
Bus idle
Bus idle
(Bus busy)
t
hHRQ
t
v(BS-D)
t
dHAK
Bus release
t
hHRQ
t
dBS
t
h(BS-D)
Hi-Z
PD77018A, 77019
43
Serial Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK input cycle time
t
cSC
2t
cC
ns
SCK input high/low level width
t
wSC
25
ns
SCK input rise/fall time
t
rfSC
20
ns
SOEN recovery time
t
recSOE
20
ns
SOEN hold time
t
hSOE
0
ns
SIEN recovery time
t
recSIE
20
ns
SIEN hold time
t
hSIE
0
ns
SI setup time
t
suSI
20
ns
SI hold time
t
hSI
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SORQ output delay time
t
dSOR
30
ns
SORQ hold time
t
hSOR
0
ns
SO valid time
t
vSO
30
ns
SO hold time
t
hSO
0
ns
SIAK output delay time
t
dSIA
30
ns
SIAK hold time
t
hSIA
0
ns
Notes for Serial Clock
Serial clock inputs SCK1 and SCK2 are sensitive to any kind of interfering signals (noise on power supply,
induced voltage, etc.). Spurious signals can cause malfunction of the device. Special care for the serial clock
design should be taken. Careful grounding, decoupling and short wiring of SCK1 and SCK2 are recommended.
Intersection of SCK1 and SCK2 with other serial interface lines or close wiring to lines carrying high frequency
signals or large changing currents should be avoided.
It considers for the serial clock to make a waveform stable especially about the rising and falling.
Example 1. good example
Straight rising form and falling
form
Example 2. no good example
It doesn't bound. It doesn't make
noise one above another.
Example 3. no good example
It doesn't make a stair stepping.
44
PD77018A, 77019
Serial Output Timing 1
SCK1,
SCK2
t
rfSC
SORQ1
SOEN1,
SOEN2
SO1,
SO2
1st
Last
t
hSO
t
vSO
t
vSO
t
hSOE
t
recSOE
t
recSOE
t
hSOE
t
dSOR
t
wSC
t
wSC
t
cSC
t
hSOR
t
rfSC
Hi-Z
Hi-Z
PD77018A, 77019
45
Serial Output Timing 2 (Continual output)
SCK1,
SCK2
t
rfSC
SORQ1
SOEN1,
SOEN2
SO1,
SO2
1st
Last
t
vSO
t
hSOE
t
recSOE
t
dSOR
t
wSC
t
wSC
t
cSC
t
hSOR
t
rfSC
Last
Hi-Z
t
hSO
46
PD77018A, 77019
Serial Input Timing 1
SCK1,
SCK2
SIAK1
SIEN1,
SIEN2
SI1,
SI2
t
cSC
t
wSC
t
wSC
t
dSIA
t
recSIE
t
hSIE
t
recSIE
t
hSIE
t
hSIA
t
suSI
t
hSI
1st
2nd
t
rfSC
t
rfSC
3rd
PD77018A, 77019
47
Serial Input Timing 2 (Continual input)
SCK1,
SCK2
SIEN1,
SIEN2
SI1,
SI2
t
cSC
t
wSC
t
wSC
t
dSIA
t
recSIE
t
hSIE
t
hSIA
t
suSI
t
hSI
1st
3rd
t
rfSC
t
rfSC
Last
Last1
2nd
SIAK1
48
PD77018A, 77019
Host Interface
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRD delay time
t
dHR
0
ns
HRD width
t
wHR
2t
cC
ns
HCS, HA0, HA1 read hold time
t
hHCAR
0
ns
HCS, HA0, HA1 write hold time
t
hHCAW
0
ns
HRD, HWR recovery time
t
recHS
2t
cC
ns
HWR delay time
t
dHW
0
ns
HWR width
t
wHW
2t
cC
ns
HWR hold time
t
hHDW
0
ns
HWR setup time
t
suHDW
20
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
HRE, HWE output delay time
t
dHE
30
ns
HRE, HWE hold time
t
hHE
30
ns
HRD valid time
t
vHDR
30
ns
HRD hold time
t
hHDR
0
ns
PD77018A, 77019
49
Host Interface Timing (Read)
CLKOUT
HRD
t
dHE
t
hHDR
t
hHCAR
t
recHS
t
vHDR
t
wHR
t
dHR
t
hHE
HCS, HA0, HA1
HD0 - HD7
HRE
Hi-Z
Hi-Z
50
PD77018A, 77019
Host Interface Timing (Write)
CLKOUT
HWR
t
dHE
t
hHDW
t
hHCAW
t
recHS
t
wHW
t
dHW
t
hHE
HCS, HA0, HA1
HD0 - HD7
HWE
t
suHDW
PD77018A, 77019
51
General Input/Output Ports
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Port input setup time
t
suPI
20
ns
Port input hold time
t
hPI
10
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Port output delay time
t
dPO
0
30
ns
General Input/Output Ports Timing
CLKOUT
P0 - P3
(Output)
P0 - P3
(Input)
t
dPO
t
suPI
t
hPI
52
PD77018A, 77019
Debugging Interface (JTAG)
Required Timing Condition
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
TCK cycle time
t
cTCK
4t
cC
ns
TCK high/low level width
t
wTCK
50
ns
TCK rise/fall time
t
rfTCK
20
ns
TMS, TDI setup time
t
suDI
10
ns
TMS, TDI hold time
t
hDI
0
ns
Input pin setup time
t
suJIN
10
ns
Input pin hold time
t
hJIN
0
ns
Switching Characteristics
Parameters
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
TDO output delay time
t
dDO
30
ns
Output pin output delay time
t
dJOUT
30
ns
Debugging Interface Timing
Remark For the details of JTAG, refer to "IEEE1149.1."
t
cTCK
t
wTCK
t
wTCK
t
suDI
t
hDI
Valid
Valid
Valid
t
dDO
t
suJIN
t
hJIN
Valid
t
dJOUT
t
rfTCK
t
rfTCK
TCK
TMS,
TDI
TDO
Capture
state
Update
state
PD77018A, 77019
53
5. PACKAGE DRAWING
100 PIN PLASTIC TQFP (FINE PITCH) ( 14)
ITEM
MILLIMETERS
INCHES
A
NOTE
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
S
A
16.00.2
0.6300.008
B
14.00.2
0.551+0.009
0.008
C
14.00.2
0.551+0.009
0.008
S100GC-50-9EU-1
S
1.27 MAX.
0.050 MAX.
K
1.00.2
0.039+0.009
0.008
L
0.50.2
0.020+0.008
0.009
M
0.145
0.0060.002
N
0.10
0.004
P
1.00.1
0.039+0.005
0.004
Q
0.10.05
0.0040.002
+0.055
0.045
B
C
D
J
H
I
G
F
P
N
L
K
M
Q
R
R
3
3
+7
3
+7
3
detail of lead end
M
75
76
50
26
25
51
100
1
D
F
1.0
16.00.2
0.6300.008
0.039
G
1.0
0.039
H
0.22
0.0090.002
I
J
0.5 (T.P.)
0.10
0.004
0.020 (T.P.)
+0.05
0.04
54
PD77018A, 77019
6. RECOMMENDED SOLDERING CONDITIONS
When soldering these products, it is highly recommended to observe the conditions as shown below. If other
soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL"
(C10535E).
Surface Mount Device
PD77018AGC-
-9EU: 100-pin plastic TQFP (FINE PITCH) (14
14mm)
PD77019GC-
-9EU: 100-pin plastic TQFP (FINE PITCH) (14
14mm)
Peak temperature: 235 C or below (Package surface temperature),
Reflow time: 30 seconds or less (at 210 C or higher),
Maximum number of reflow processes : 2 times,
Exposure limit
Note
: 3 days (10 hours pre-baking is required at 125 C
afterwards).
Peak temperature: 215 C or below (Package surface temperature),
Reflow time: 40 seconds or less (at 200 C or higher),
Maximum number of reflow processes : 2 times,
Exposure limit
Note
: 3 days (10 hours pre-baking is required at 125 C
afterwards).
Pin temperature : 300 C or below,
Heat time : 3 seconds or less (Per each side of the device)
Process
Conditions
Symbol
I
nfrared ray reflow
IR35-103-2
Vapor Phase Soldering
Partial heating method
VP15-103-2
Note
Maximum allowable time from taking the soldering package out of dry pack to soldering.
Storage conditions: 25 C and relative humidity of 65 % or less.
Caution
Apply only one kind of soldering condition to a device, except for "partial heating method",
or the device will be damaged by heat stress.
PD77018A, 77019
55
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD77018A, 77019
[MEMO]
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific:
Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96.5
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.