Document Outline

COVER
ORDERING INFORMATION
BLOCK DIAGRAM
FUNCTIONAL PIN BLOCK
DSP FUNCTION LIST
PIN CONFIGURATIONS
1. PIN FUNCTIONS
- 1.1 Description of Pin Functions
- 1.2 Connection of Unused Pins
  - 1.2.1 Connection of functional pins
  - 1.2.2 Connection of non-functional pin
2. FUNCTIONAL OUTLINE
- 2.1 Program Control Unit
  - 2.1.1 CPU control
  - 2.1.2 Interrupt control
  - 2.1.3 Loop control stack
  - 2.1.4 PC stack
  - 2.1.5 Clock control
  - 2.1.6 Instruction memory
- 2.2 Operation Unit
  - 2.2.1 General-purpose registers (R0 to R7)
  - 2.2.2 Multiply accumulator (MAC)
  - 2.2.3 Arithmetic logic unit (ALU)
  - 2.2.4 Barrel shifter (BSFT)
- 2.3 Data Memory Unit
  - 2.3.1 Data memory
  - 2.3.2 Data addressing unit
- 2.4 Peripheral Unit
  - 2.4.1 Serial interface (SIO)
  - 2.4.2 Host interface (HIO)
  - 2.4.3 General-purpose I/O port (PIO)
  - 2.4.4 External memory interface (MIO)
  - 2.4.5 Timers (TIM1 and TIM2)
  - 2.4.6 Interrupt controller (INTC)
  - 2.4.7 DMA controller (PMT)
  - 2.4.8 SD card interface (SDCIF)
  - 2.4.9 Debug interface (IEIO)
3. CLOCK GENERATOR
4. RESET FUNCTION
- 4.1 Hardware Reset
5. FUNCTION OF BOOT-UP ROM
- 5.1 Boot at Reset
  - 5.1.1 Memory boot
  - 5.1.2 Host boot
  - 5.1.3 Serial boot
- 5.2 Reboot
  - 5.2.1 Memory reboot
  - 5.2.2 Host reboot
  - 5.2.3 Serial reboot
6. STANDBY MODE
- 6.1 Halt Mode
- 6.2 Stop Mode
7. MEMORY MAP
- 7.1 Instruction Memory
  - 7.1.1 Instruction memory map
  - 7.1.2 Interrupt vector table
- 7.2 Data Memory
  - 7.2.1 Data memory map
  - 7.2.2 Internal peripherals
8. GENERAL-PURPOSE PORT AND INTERRUPT
- 8.1 General-purpose Port Pins
- 8.2 Interrupt Pin
9. INSTRUCTION
- 9.1 Outline of Instruction
- 9.2 Instruction Set and Its Operation
10. ELECTRICAL SPECIFICATIONS
11. PACKAGE DRAWINGS
12. RECOMMENDED SOLDERING CONDITIONS

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD77210, 77213

16-BIT FIXED-POINT DIGITAL SIGNAL PROCESSOR

Document No. U15203EJ3V0DS00 (3rd edition)
Date Published November 2001 NS CP(K)
Printed in Japan

DATA SHEET

2001

The mark shows major revised points.

The

µPD77210 and 77213 are 16-bit fixed-point digital signal processors (DSP).

Compared with the existing members of the

µPD77111 Family, the µPD77210 Family consumes less power and is

ideal for battery-driven mobile terminal applications such as PDAs and cellular telephones. The

µP77210 Family is

DSP is also compatible with the

µPD77111 Family at the binary level.

The

µPD77210 Family consists of the µPD77210 and 77213. Unless otherwise specified, the µPD77210 Family

refers to the entire family. If there are some differences in function or operation among family products, they are

described under their respective names.

The functions of the

µPD77210 Family are described in detail in the following user's manuals. Refer to these

manuals when designing your system.

µPD77210 Family User's Manual - Architecture:

In preparation

µPD77016 Family User's Manual - Instructions:

U13116E

FEATURES

· Instruction cycle (operating clock):

µPD77210 6.25 ns MIN. (160 MHz MAX.)
µPD77213 8.33 ns MIN. (120 MHz MAX.)

· Memory

-Internal instruction memory:

µPD77210 :RAM 31.5 Kwords x 32 bits
µPD77213 :RAM 15.5 Kwords x 32 bits

ROM 64 Kwords x 32 bits

-Data memory:

µPD77210 :RAM 30 Kwords x 16 bits x 2 planes (X and Y data memories)

External memory space 1 Mwords x 16 bits (common to X and Y data memories)

µPD77213 :RAM 18 Kwords x 16 bits x 2 planes (X and Y data memories)

ROM 32 Kwords x 16 bits x 2 planes (X and Y data memories)

External memory space 1 Mwords x 16 bits (common to X and Y data memories)

· Peripheral

-Audio serial interface: 1 channel

-Time-division serial interface: 1 channel

-16-bit host interface: 1 channel

-16-bit general-purpose port

-16-bit timer: 2 channels

-Peripheral-memory DMA transfer function

-SD (Secure Digital) card interface

µPD77213 only

ta S

heet U

15203E

J3V

µ
µ
µ
µ

77210, 77213

µPD77213

15.5 K

× 32

64K

× 32

18 K

× 16 each

32 K

× 16 each

1 M

× 16 (8 K ×

16, using SD I/F)

8.33 ns

(120 MHz)

SD card I/F

µPD77210

31.5 K

× 32

30 K

× 16 each

1 M

× 16

6.25 ns

(160 MHz)

Integer multiple of

×10 to 64

(external pin)

2 channels (time-division, audio)

16 bits (some are alternative with host)

2 channels

(16-bit resolution)

DSP core: 1.5 V

I/O pins: 3.3 V

161-pin FBGA

144-pin LQFP

µPD77115

11.5 K

× 32

None

16 K

× 16 each

None

Integer multiple

×1 to 16

(external pin)

1 channel

(audio CODEC)

16-bit bus

8 bits

1 channel

(16-bit resolution)

SD card I/F

80-pin TQFP

80-pin FBGA

µPD77114

8 K

× 16 each

100-pin TQFP

µPD77113A

3.5 K

× 32

48 K

× 32

16 K

× 16 each

32 K

× 16 each

None

80-pin FBGA

µPD77112

16 K

× 16 each

100-pin TQFP

µPD77111

1 K

× 32

31.75 K

× 32

3 K

× 16 each

16 K

× 16 each

None

13.3 ns

(75 MHz)

Integer multiple of

×1 to 16

(mask option)

80-pin TQFP

80-pin FBGA

µPD77110

35.5 K

× 32

None

24 K

× 16 each

None

32 K

× 16 each

15.3 ns

(65 MHz)

Integer multiple

×1 to 8

(external pin)

2 channels

(speech CODEC)

8-bit bus

4 bits

None

DSP core: 2.5 V

I/O pins: 3 V

100-pin TQFP

Int. instruction RAM

Int. instruction ROM

Data RAM

(X/Y memory)

Data ROM

(X/Y memory)

Ext. instruction memory

Ext. data memory (X/Y

memory)

Serial interface

Host interface

General-purpose

port (I/O

programmable)

Timer

Others

DSP FUNCTION LIST

Item

Memory

space

(words

bits)

Instruction cycle (at maximum

operating speed)

Multiple

Peripheral

Supply voltage

Package

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

C14

HD7

TSORQ

P10/HD10/INT22

HD6

MA0

P5/INT11

P11/HD11/INT32

GND

MA4

P2/INT20

P12/HD12/INT03

H11

MD5

MA5

GND

H12

MD4

MA10

GND

H13

MD1

M10

MA12

P1/INT10

H14

MD3

M11

MA15/Reserved

Note

GND

M12

MA19/SDCLK

Note

PLL0

GND

HCS

M13

MA18/SDCR

Note

A10

STOPS

GND

HA1

M14

A11

D10

GND

HWR

A12

TRST

D11

TMS

J11

GND

A13

D12

TICE

J12

MD0

ASIEN/MCLK

A14

D13

MD12

J13

MBSTB

TSCK

D14

MD15

J14

TSIAK

P14/HD14/INT23

HA0

MA1

P7/INT31

P15/HD15/INT33

HRD

MA2

P6/INT21

P13/HD13/INT13

TIMOUT

MA7

P3/INT30

GND

ASO

MA9

CLKOUT

K11

GND

N10

MA11

E11

GND

K12

MWR

N11

MA16/Reserved

Note

PLL3

E12

MD14

K13

MWAIT

N12

MA17/Reserved

Note

PLL1

E13

MD9

K14

N13

B10

CSTOP

E14

MD11

HWE

N14

B11

I.C.

HRE

B12

TCK

HD1

GND

B13

HD2

GND

ASI

B14

HD0

TSIEN

TSO

F11

MD10

GND

TSI

P8/HD8/INT02

F12

MD13

GND

P9/HD9/INT12

F13

MD7

MA8

P4/INT01

F14

GND

MA3

P0/INT00

HD3

L10

MA14/SDDAT0

Note

MA6

CLKIN

HD5

L11

GND

P10

PLL2

HD4

L12

MHOLDRQ

P11

MA13/SDMON

Note

HALTS

GND

L13

MRD

P12

RESET

G11

GND

L14

MHOLDAK

P13

C10

I.C.

G12

MD8

P14

C11

TDI

G13

MD2

ASCK/BCLK

C12

TDO

G14

MD6

ASOEN/LRCLK

C13

GND

TSOEN

Note MA13 to MA19 pins of the

µPD77213 are alternate function pins.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

144-pin plastic LQFP (fine pitch) (20 x 20) (Top View)
·

µ
µ
µ
µPD77210GJ-8EN

µ
µ
µ
µPD77213GJ-xxx-8EN

144

120

121

122

123

124

125

126

127

128

129

130

131

GND

132

133

GND

134

135

136

137

138

139

140

141

142

143

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

HALTS

GND

CLKIN

CLKOUT

PLL0

PLL2

PLL1

PLL3

GND

HD7

HD6

HD5

HD4

HD3

HD2

HD1

HD0

GND

MHOLDAK

GND

MRD

MWR

MHOLDRQ

26
27
28
29
30
31
32
33
34
35
36

109

110

111

112

113

114

115

116

117

118

119

GND

STOPS

CSTOP

ASO

MD14

MD15

MD13

MD10

MD8

MD9

MD12

MD11

MD6

MD7

MD4

MD5

MD2

MD3

MD0

MD1

MBSTB

MWAIT

RESET

GND

TCK

TDI

TMS

I.C.
I.C.

TRST

P8/HD8/INT02

P9/HD9/INT12

P10/HD10/INT22

P11/HD11/INT32

P12/HD12/INT03

P13/HD13/INT13

P14/HD14/INT23

P15/HD15/INT33

GND

MA18/SDCR

Note

MA19/SDCLK

Note

GND

HA1

HA0

TIMOUT

HCS

HRD

HRE

HWR

HWE

GND

TDO

TICE

GND

P0/INT00

P2/INT20

P1/INT10

P3/INT30
P4/INT01
P5/INT11
P6/INT21
P7/INT31

ASOEN/LRCLK

108
107
106
105
104
103
102
101
100

99
98
97

MA9

MA8

MA7

94
93
92
91
90
89
88
87
86
85
84

MA12
MA11
MA10

GND

MA13/SDMON

Note

MA5
MA4
MA3
MA2

MA1

GND

TSIAK
TSORQ

83
82
81
80
79
78
77

GND

76
75
74
73

MA0

MA6

MA15/Reserved

Note

ASIEN/MCLK
ASCK/BCLK

ASI

TSOEN

TSO

TSIEN

TSI

TSCK

MA16/Reserved

Note

MA17/Reserved

Note

MA14/SDDAT0

Note

Note MA13 to MA19 pins of the

µPD77213 are alternate function pins.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

Pin No.

Pin Name

GND

109

GND

TCK

GND

ASCK/BCLK

110

TDI

P8/HD8/INT02

ASIEN/MCLK

111

MA18/SDCR

Note

TMS

P9/HD9/INT12

ASI

112

MA19/SDCLK

Note

TRST

P10/HD10/INT22

TSOEN

113

MHOLDRQ

I.C.

P11/HD11/INT32

TSO

114

MHOLDAK

I.C.

P12/HD12/INT03

TSCK

115

MRD

P13/HD13/INT13

TSIEN

116

MWR

GND

P14/HD14/INT23

TSI

117

MWAIT

RESET

P15/HD15/INT33

TSORQ

118

MBSTB

STOPS

TSIAK

119

MD0

CSTOP

GND

MA0

120

MD1

HALTS

HD0

MA1

121

PLL0

HD1

122

GND

PLL1

HD2

GND

123

PLL2

HD3

124

GND

PLL3

HD4

GND

125

MD2

HD5

MA2

126

MD3

GND

HD6

MA3

127

MD4

CLKIN

HD7

MA4

128

MD5

MA5

129

MD6

GND

MA6

130

MD7

MA7

131

MD8

GND

MA8

132

MD9

CLKOUT

HCS

MA9

133

HA0

134

GND

HA1

GND

135

MD10

P0/INT00

HRD

100

MA10

136

MD11

P1/INT10

HRE

101

MA11

137

MD12

P2/INT20

HWR

102

MA12

138

MD13

P3/INT30

HWE

103

MA13/SDMON

Note

139

MD14

P4/INT01

TIMOUT

104

MA14/SDDAT0

Note

140

MD15

P5/INT11

ASOEN/LRCLK

105

MA15/Reserved

Note

141

TDO

P6/INT21

ASO

106

MA16/Reserved

Note

142

TICE

P7/INT31

107

MA17/Reserved

Note

143

GND

108

144

Note MA13 to MA19 pins of the

µPD77213 are alternate function pins.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Pin Name

ASCK

:Audio Serial Clock Input/Output

ASI

:Audio Serial Data Input

ASIEN

:Audio Serial Input Enable

ASO

:Audio Serial Data Output

ASOEN

:Audio Serial Output Enable

BCLK

:Bit Clock Input/Output

CLKIN

:Clock Input

CLKOUT

:Clock Output

CSTOP

:Clear Stop Mode

:Power Supply for I/O Pins

GND

:Ground

HALTS

:Halt Status Signal Output

HD0 to HD15

:Host Data Bus

HCS

:Host Chip Select

HA0, HA1

:Host Data Access

HRD

:Host Read

HRE

:Host Read Enable

HWE

:Host Write Enable

HWR

:Host Write

I.C.

:Internal Connection

:Power Supply for DSP Core

INTmn

:Interrupt (m,n=0 to 3)

LRCLK

:Left Right Clock Input/Output

MA0 to MA19

:External Data Memory Address Bus

MBSTB

:External Data Memory Bus Strobe

MCLK

:Master Clock Input

MD0 to MD15 :External Data Memory Bus

MHOLDAK

:External Data Memory Bus Hold

Acknowledge

MHOLDRQ

:External Data Memory Bus Hold

Request

MRD

:External Data Memory Read Output

MWR

:External Data Memory Write Output

MWAIT

:External Data Memory Access Wait

Input

:Non-Connection

P0 to P15

:Port

PLL0-PLL3

:PLL Multiple Rate Set

Reserved

:Reserved

RESET

:Reset

SDCLK

:SD Card Clock Output

SDCR

:SD Card Command Output/Response

Input

SDDAT0

:SD Card Data Input/Output

SDMON

:SD Card Access Monitor

STOPS

:Stop Status Signal Output

TCK

:Test Clock Input

TDI

:Test Data Input

TDO

:Test Data Output

TICE

:Test In-Circuit Emulator

TIMOUT

:Timer Time Out Monitor Output

TMS

:Test Mode Select

TRST

:Test Reset

TSCK

:Time Division Multiplex Serial Clock

Input

TSI

:Time Division Multiplex Serial Data Input

TSIAK

:Time Division Multiplex Serial Input

Acknowledge

TSIEN

:Time Division Multiplex Serial Input

Enable

TSO

:Time Division Multiplex Serial Data

Output

TSOEN

:Time Division Multiplex Serial Output

Enable

TSORQ

:Time Division Multiplex Serial Output

Request

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

CONTENTS

1. PIN FUNCTIONS....................................................................................................................................13

1.1 Description of Pin Functions ........................................................................................................................13

1.2 Connection of Unused Pins ..........................................................................................................................21

1.2.1 Connection of functional pins ..................................................................................................................21

1.2.2 Connection of non-functional pin .............................................................................................................22

2. FUNCTIONAL OUTLINE .......................................................................................................................23

2.1 Program Control Unit.....................................................................................................................................23

2.1.1 CPU control .............................................................................................................................................23

2.1.2 Interrupt control .......................................................................................................................................23

2.1.3 Loop control stack ...................................................................................................................................23

2.1.4 PC stack ..................................................................................................................................................23

2.1.5 Clock control............................................................................................................................................23

2.1.6 Instruction memory ..................................................................................................................................24

2.2 Operation Unit ................................................................................................................................................24

2.2.1 General-purpose registers (R0 to R7) .....................................................................................................24

2.2.2 Multiply accumulator (MAC) ....................................................................................................................24

2.2.3 Arithmetic logic unit (ALU) .......................................................................................................................24

2.2.4 Barrel shifter (BSFT)................................................................................................................................24

2.3 Data Memory Unit...........................................................................................................................................24

2.3.1 Data memory ...........................................................................................................................................24

2.3.2 Data addressing unit................................................................................................................................25

2.4 Peripheral Unit................................................................................................................................................25

2.4.1 Serial interface (SIO) ...............................................................................................................................25

2.4.2 Host interface (HIO).................................................................................................................................25

2.4.3 General-purpose I/O port (PIO) ...............................................................................................................26

2.4.4 External memory interface (MIO).............................................................................................................26

2.4.5 Timers (TIM1 and TIM2) ..........................................................................................................................26

2.4.6 Interrupt controller (INTC)........................................................................................................................26

2.4.7 DMA controller (PMT) ..............................................................................................................................26

2.4.8 SD card interface (SDCIF).......................................................................................................................26

2.4.9 Debug interface (IEIO).............................................................................................................................26

3. CLOCK GENERATOR...........................................................................................................................27

4. RESET FUNCTION ................................................................................................................................28

4.1 Hardware Reset ..............................................................................................................................................28

5. FUNCTION OF BOOT-UP ROM...........................................................................................................28

5.1 Boot at Reset ..................................................................................................................................................28

5.1.1 Memory boot............................................................................................................................................28

5.1.2 Host boot .................................................................................................................................................29

5.1.3 Serial boot ...............................................................................................................................................29

5.2 Reboot.............................................................................................................................................................29

5.2.1 Memory reboot ........................................................................................................................................29

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

5.2.2 Host reboot ............................................................................................................................................. 30

5.2.3 Serial reboot ........................................................................................................................................... 30

6. STANDBY MODE.................................................................................................................................. 31

6.1 Halt Mode ....................................................................................................................................................... 31

6.2 Stop Mode ...................................................................................................................................................... 31

7. MEMORY MAP...................................................................................................................................... 32

7.1 Instruction Memory ....................................................................................................................................... 32

7.1.1 Instruction memory map ......................................................................................................................... 32

7.1.2 Interrupt vector table............................................................................................................................... 33

7.2 Data Memory .................................................................................................................................................. 34

7.2.1 Data memory map .................................................................................................................................. 34

7.2.2 Internal peripherals ................................................................................................................................. 35

8. GENERAL-PURPOSE PORT AND INTERRUPT ............................................................................... 38

8.1 General-purpose Port Pins ........................................................................................................................... 38

8.2 Interrupt Pin ................................................................................................................................................... 38

9. INSTRUCTION ....................................................................................................................................... 39

9.1 Outline of Instruction .................................................................................................................................... 39

9.2 Instruction Set and Its Operation................................................................................................................. 40

10. ELECTRICAL SPECIFICATIONS....................................................................................................... 46

11. PACKAGE DRAWINGS...................................................................................................................... 69

12. RECOMMENDED SOLDERING CONDITIONS................................................................................. 71

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

·
·
·
· External data memory interface

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

MA0 to

MA19

Note

84, 85,

90 to 97,

100 to 107,

111, 112

M6,N6,N7,P8,

M7,M8,P9,N8,

L8,N9,M9,N10,

M10,P11,L10,

M11,N11,N12,

M13,M12

Output

(3S)

Address bus of external data memory

These pins output an address when the external data

memory is accessed.

SDCLK,

SDCR,

SDDAT0,

SDMON

MD0 to

MD15

119,120,

125 to 132,

135 to 140

J12,H13,G13,

H14,H12,H11,

G14,F13,G12,

E13,F11,E14,

D13,F12,E12,

D14

I/O

(3S)

16-bit data bus

These pins input/output data when the external data

memory is accessed.

MWR

116

K12

Output

(3S)

Write output

This pin outputs a write strobe signal for the external

data memory.

MRD

115

L13

Output

(3S)

Read output

This pin outputs a read strobe signal for the external

data memory.

MHOLDAK

114

L14

Output

Hold acknowledge signal

This pin goes low when the external device is

granted use of the external data memory bus of the

µPD77210 Family.

MHOLDRQ

113

L12

Input

Hold request signal

The external device inputs a low level to this pin

when it uses the external data memory bus of the

µPD77210 Family.

MWAIT

117

K13

Input

Wait signal input

This pin inserts wait cycles when the

µPD77210

Family accesses the external data memory.

· 0: Inserts wait cycles.
· 1: Does not insert wait cycles.

MBSTB

118

J13

Output

Bus strobe signal

This pin goes low while the

µPD77210 Family uses

the external data memory bus.

Note MA13 to MA19 pins of the

µPD77213 are alternate function pins.

Remark Those pins marked "3S" in the above table enter the high-impedance state under the following

conditions:

MA0 to MA19, MRD, and MWR: When the bus is released (MHOLDAK = low level)

MD0 to MD15: When the external data memory is not accessed and when the bus is released

(MHOLDAK = low level)

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

·
·
·
· Timer

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

TIMOUT

Output

Time out monitor

This pin is asserted active when the timer times out.

·
·
·
· Serial interface

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

ASCK/

BCLK

I/O

Audio serial clock input/output

ASCK:Audio serial clock input

BCLK:Serial clock I/O

ASO

Output

(3S)

Audio serial data output

ASI

Input

Audio serial data input

ASOEN/

LRCLK

I/O

Audio serial output enable/left right clock input output

ASOEN:Audio serial output enable input

LRCLK:Left right clock I/O

ASIEN/

MCLK

Input

Audio serial input enable/master clock input output

ASIEN:Audio serial input enable input

MCLK:Master clock input (in master mode)

TSCK

Input

Clock input for time division serial

TSO

Output

(3S)

Time-division serial data output

TSI

Input

Time-division serial data input

TSORQ

Output

Time-division serial output request

TSOEN

Input

Time-division serial output enable

TSIEN

Input

Time-division serial input enable

TSIAK

Output

Time-division serial input acknowledge

Remark Those pins marked "3S" in the above table enter the high-impedance state when data transmission is

completed and when the hardware reset (RESET) signal is input.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

·
·
·
· Host interface

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

HA1

Input

Host address 1

This pin specifies a register that is accessed by the

host interface pins (HD7 to HD0, or HD15 to HD0).

· 1: The host interface status register (HST) is

accessed.

· 0: The host transmit data register (HDT (out)) is

accessed for read (HRD = 0) and the host receive

data register (HDT (in)) is accessed for write (HWR

= 0).

HA0

Input

Host address 0

This pin specifies a register that is accessed by HD7

to HD0 in 8-bit mode. This pin is invalid in 16-bit

mode.

· 1: Bits 15 to 8 of HST, HDT (in), and HDT (out) are

accessed.

· 0: Bits 7 to 0 of HST, HDT (in), and HDT (out)

are accessed.

HCS

Input

Chip select input

HRD

Input

Host read input

HWR

Input

Host write input

HRE

Output

Host read enable output

HWE

Output

Host write enable output

HD0 to

HD7

49 to 56

F4,F2,F3,G1,

G3,G2,H3,H2

I/O

(3S)

8-bit host data bus

These pins constitute a host data bus in 8-bit host

mode. Access to 16-bit data for input/output is

controlled by the HA0 pin, and the data is accessed

two times such that it is divided into two blocks of 8-

bit data.

In 16-bit mode, the lower 8 bits of the data are

input/output.

HD8 to

HD15

39 to 46

C2,C3,D1,D2,

D3,E3,E1,E2

I/O

(3S)

Host data bus

These pins constitute a host data bus in 16-bit host

mode. They input/output 16-bit data with HD0 to

HD7.

P8 to P15/

INT02,

INT12,

INT22,

INT32,

INT03,

INT13,

INT23,

INT33

Remark Those pins marked "3S" in the above table enter the high-impedance state while the host interface is not

being accessed.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

·
·
·
·SD card interface (

µ
µ
µ
µPD77213 only)

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

SDCLK

112

M12

Output

SD card clock output

· Leave this pin open.

MA19

SDCR

111

M13

I/O

(3S)

SD cord command/response

Input

: Response

Output

: Command

· Leave pull-up.

MA18

SDDAT0

104

L10

I/O

(3S)

SD card data input/output

Input

: Read data

Output

: Write data

· Leave pull-up.

MA14

SDMON

103

P11

Output

SD card interface access monitor

This pin outputs a high level when the SD card

interface is being accessed.

1: SD card interface being accessed

0: SD card interface not being accessed

MA13

Reserved

105 to 107

M11, N11, N12

Reserved for future function expansion.

This pin becomes high impedance when the SD card

interface is being used.

MA15 to

MA17

Remark Those pins marked "3S" in the above table enter the high-impedance state when the SD card interface is

not being accessed.

·
·
·
· Others

Pin No.

Pin Name

144-pin LQFP

161-pin FBGA

I/O

Function

Alternate

I.C.

6, 7

B11, C10

Internally connected.

Leave these pins open.

A1,A2,A13,

A14,B1,B2,

B13,B14,E5,

N1,N2,N13,

N14,P1,P2,

P13,P14

No connection.

Leave these pins open.

Caution If any signal is input to these pins or if these pins are read, the correct operation of the

µ
µ
µ
µPD77210

Family is not guaranteed.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

1.2 Connection of Unused Pins

1.2.1 Connection of functional pins

Connect the unused pins as shown in the table below.

Pin Name

I/O

Recommended Connection

STOPS, HALTS

Output

Leave open.

CSTOP

Input

Connect to GND via a pull-down resistor.

CLKOUT

Output

Leave open.

P0 to P15

I/O

Connect to EV

via a pull-up resistor or to GND via a pull-down resistor.

HD0 to HD7

Note 1

I/O

Connect to EV

via a pull-up resistor or to GND via a pull-down resistor.

HA0, HA1

Input

Connect to EV

via a pull-up resistor or to GND via a pull-down resistor.

HCS, HRD, HWR

Input

Connect to EV

via a pull-up resistor.

HRE, HWE

Output

Leave open.

TIMOUT

Output

Leave open.

ASCK, TSCK

Input

ASI, TSI

Input

Connect to EV

via a pull-up resistor or to GND via a pull-down resistor.

ASIEN, TSIEN

Input

ASOEN, TSOEN,

LRCLK

Input

Connect to GND via a pull-down resistor.

ASO, TSO

Output

TSORQ

Output

TSIAK

Output

Leave open.

MA0 to MA19

Output

Leave open.

MD0 to MD15

Note 2

I/O

Connect to EV

via a pull-up resistor or to GND via a pull-down resistor.

MRD, MWR

Output

Leave open.

MHOLDRQ

Input

Connect to EV

via a pull-up resistor.

MBSTB, MHOLDAK

Output

Leave open.

MWAIT

Input

Connect to EV

via a pull-up resistor.

TCK

Input

Connect to GND via a pull-down resistor.

TDO, TICE

Output

Leave open.

TMS, TDI

Input

Leave open (this pin is internally pulled up).

TRST

Input

Leave open (this pin is internally pulled down).

Notes 1. These pins may left opened if the HCS, HRD,and HWR are fixed to the high level.

However, connect these pins as recommended in the HALT and STOP modes when the power

consumption must be lowered.

2. These pins may leave opened if the external data memory is not accessed in the program.

However, connect these pins as recommended in the HALT and STOP modes when the power

consumption must be lowered.

Caution Unused alternate-function pins should be handled in accordance with the processing specified

for the pin function of the initial setting.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

2. FUNCTIONAL OUTLINE

2.1 Program Control Unit

This unit controls the execution of

µPD77210 Family by executing instructions and controlling branching, loop,

interrupts, clock, and standby mode.

2.1.1 CPU control

A three-stage pipeline architecture is employed so that all instructions, except branch instructions and some

others, can be executed with one system clock.

2.1.2 Interrupt control

The interrupt control circuit services the interrupt requests input to the interrupt controller by an external pin

(INTmn) or internal peripherals (such as the serial interface, host interface, timer, and DMA controller). The interrupt

of each interrupt source can be individually enabled or disabled. In addition, multiple interrupts are also supported.

2.1.3 Loop control stack

A loop function without any hardware overhead is realized. A 4-level loop stack is provided to support multiple

loops.

2.1.4 PC stack

A 15-level PC stack that stacks the program counter supports multiple interrupts/subroutine calls.

2.1.5 Clock control

A PLL and a divider are internally provided as a clock generator so that an externally input clock is multiplied or

divided and supplied as the operating clock to the

µPD77210 Family. The multiple of the PLL can be set by using

external pins (PLL0 to PLL3) within a range of

×10 to 64. The division ratio can be set by using a register in a range

÷1 to 16.

The clock control register (CLKC) controls the power (ON/OFF) to the PLL, selects a clock source, controls the

output divider, and controls the output of the CLKOUT pin.

Two types of standby modes are available so that the power consumption can be reduced when the

µPD77210

Family is standing by.

·HALT mode: Current consumption falls to several mA upon execution of the HALT instruction.

This mode is released by an interrupt or hardware reset.

·STOP mode: Current consumption falls to hundreds of

µA

Note

upon execution of the STOP instruction.

This mode is released by hardware reset or inputting a signal to CSTOP pin.

Note When the PLL is stopped

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

2.1.6 Instruction memory

Of the instruction RAM, 64 words are allocated as interrupt vectors.

The

µPD77210 is provided with an instruction RAM of 31.5 Kwords. The µPD77213 is provided with an instruction

RAM of 15.5 Kwords and instruction ROM of 64 Kwords.

A boot-up ROM that boots up the instruction RAM is also provided, and the instruction RAM can be initialized or

rewritten by means of a memory boot (booting from an internal or external data space), host boot (booting via a host

interface), or serial boot (booting via a serial interface).

2.2 Operation Unit

This unit performs multiplication, addition, logic, and shift operations, and consists of a 40-bit multiply

accumulator, a 40-bit data ALU, a 40-bit barrel shifter, and eight 40-bit general-purpose registers.

2.2.1 General-purpose registers (R0 to R7)

These eight 40-bit registers input/output operands and load/store data to/from data memory.

Each register consists of three parts: R0L to R7L (bits 15 to 0), R0H to R7H (bits 31 to 16), and R0E to R7E (bits

39 to 32). Depending on the type of the operation, RnL, RnH, and RnE are used either as one register or in

combination.

2.2.2 Multiply accumulator (MAC)

The multiply accumulator performs multiplication of two 16-bit data items and addition or subtraction between the

result of the multiplication and one 40-bit data item, and then outputs 40-bit data.

A shifter (MSFT: MAC shifter) is provided at the preceding stage of the MAC, so that the 40-bit data that is to be

added to or subtracted from the multiplication result can be arithmetically shifted 1 bit or 16 bits to the right before

addition or subtraction.

2.2.3 Arithmetic logic unit (ALU)

The ALU accepts one or two 40-bit data items as input, performs an arithmetic or logical operation, and then

outputs 40-bit data.

2.2.4 Barrel shifter (BSFT)

The BFST accepts 40-bit data items as input, shifts the data to the left or right by an arbitrary number of bits, and

then outputs 40-bit data. The data can be shifted to the right arithmetically, in which case the sign of the data is

extended, or logically in which case 0 is inserted starting from the MSB.

2.3 Data Memory Unit

The data memory unit consists of two planes of data memory spaces and two pairs of data addressing units.

2.3.1 Data memory

Two data memory planes (X data memory and Y data memory) are provided. The data memory space includes a

64-word peripheral area.

The

µPD77210 has a data RAM consisting of 30 Kwords × 2 planes. The µPD77213 has a data RAM consisting

of 18 Kwords

× 2 planes, and has a data ROM consisting of 32 Kwords × 2 planes.

In addition, They also have an external data memory interface that is used to connect an external 1 Mword data

memory to the device.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

2.3.2 Data addressing unit

An independent data addressing unit is provided for each of the X and Y data memory spaces.

Each data addressing unit has four data pointers (DPn), four index registers (DNn), one module register (DMX or

DMY), and an address ALU.

2.4 Peripheral Unit

The peripheral unit has serial interfaces, a host interface, general-purpose I/O ports, timers, an external memory

interface, and SD card interface (

µPD77213 only). All these internal peripherals are mapped to the X and Y data

memory spaces and are accessed as memory-mapped I/Os by the program.

2.4.1 Serial interface (SIO)

Two serial interface channels, an audio serial interface (ASIO) and a time-division serial interface (TDMSIO), are

provided.

The audio serial interface can be used in either of two modes: audio mode and standard mode. The standard

mode is compatible with the existing

µPD77111 Family. The audio mode is compatible with the µPD77115.

The features of the audio mode are as follows:

· Mode: Master mode and slave mode

Master mode: Supports master clock input (MCLK), bit clock output (BCLK), LR clock output (LRCLK), 256 fs,

384 fs, and 512 fs.

Slave mode: Bit clock input (BCLK) and LR clock input (LRCLK)

· Frame format: 32- or 64-bit audio formats (LRCLK format)
· Handshake: Handshaking with external devices by a dedicated frame signal (LRCLK) and with the internal

circuitry by polling, wait, or interrupt

The standard mode has the following features:

·Serial clock:

Supplied from an external source to each channel. The clock is shared for input and output by

each channel.

·Frame length: 8 or 16 bits, with MSB or LSB first selected for each channel.
·Handshake:

Handshaking with the external device by using a dedicated status signal and with the internal

circuitry by polling, wait, or interrupt.

The time-division serial interface divides the serial input/output signal into 1 to 32 time slots and allows several

devices to share the serial bus. Because the T1 and E1 frame signals are considered. The time slot can be extended

from 1 to 128.

2.4.2 Host interface (HIO)

This is a parallel port that inputs/outputs data from/to an external host CPU and DMA controller. It can be used in

either 8-bit parallel mode or 16-bit parallel mode. In the

µPD77210 Family, 16-bit registers are mapped to memory

for input data, output data, and status. Handshaking with an external device is performed by using a dedicated

status signal, and the internal circuitry handshaking is done by means of polling, wait, or interrupts.

The 8-bit parallel mode is compatible with the existing members of the

µPD77111 Family.

In 16-bit parallel mode, some port pins are used as host interface pins.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

2.4.3 General-purpose I/O port (PIO)

This is a 16-bit I/O port that can be set to either input or output mode in 1-bit units.

The external pins alternate between interrupt pins and host interface pins. By setting the mode of 8 bits of the

port to host interface pin mode, the host interface can be set in the 16-bit parallel mode.

2.4.4 External memory interface (MIO)

This interface accesses an external 1 Mwords data memory area in either of two modes: direct access and DMA

access modes. In DMA access mode, access is made via a memory-mapped register.

In direct access mode, the data paging register (DPR) is set to 0x3F and a page area is accessed as an access

window. An address of the external memory consists of 20 bits with the 8-bit value of the index register added as bits

12 to 19.

In DMA access mode, the address is automatically updated when a memory-mapped register is accessed. The

address is updated in an increment addressing mode in which the address is simply incremented, or in two-

dimensional addressing mode in which an offset is added to each line length.

The number of wait cycles to be inserted when the external memory is accessed can be specified by a register

(MWAIT), within a range of 1 to 15. In addition, wait cycles can also be inserted by using the MWAIT pin.

2.4.5 Timers (TIM1 and TIM2)

The

µPD77210 Family has two timer channels.

These timers can be used as interval timers, event counters, watchdog timers, and free-run timers.

The clock input to the timers is selected from the system clock, serial clock (ASCK or TSCK), external interrupt

(INT00, INT10, INT20, or INT30), or output of each timer.

The count value is 16 bits and the clock input by the prescaler can be divided by 1, 2, 4, 8, 16, 32, 64, or 128.

2.4.6 Interrupt controller (INTC)

The interrupt controller has functions for selecting and masking interrupt signals. It controls the interrupt signal to

be input to the DSP core.

2.4.7 DMA controller (PMT)

The DMA controller realizes data transfer between the peripherals and memory (peripheral-memory transfer) in

the background. It mitigates the software overhead generated by interrupt processing of the data input/output via

SIO, HIO, MIO, and SDCIF (

µPD77213 only).

Data of 14 Kwords at addresses 0x0000 to 0x37FF of the internal data RAM can be transferred by means of

DMA.

2.4.8 SD card interface (SDCIF)

The

µPD77213 supports SD Card interface. This interface is for access of SD card. It supports the DMA transfer

for input data to internal data RAM. The SD card is accessed by using a dedicated routine of system ROM.

2.4.9 Debug interface (IEIO)

The

µPD77210 Family has the following functions that conform to the JTAG (Joint Test Action Group) interface as

a debug interface.

A device conforming to JTAG has an access port dedicated to testing and can be tested independently of the

internal logic.

The

µPD77210 Family has registers and a control circuit for in-circuit emulation, in addition to the instruction

registers, bypass registers, and boundary scan registers that are required by the JTAG Recommendation.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

3. CLOCK GENERATOR

The clock generator generates an internal system clock based on the external clock input from the CLKIN pin and

supplies the clock to the

µPD77210 Family. The configuration of the clock generator is as illustrated below.

Stop

PLL controller

Output divider

Halt

Internal
system
clock

x m (m:10 to 64)

CLKOUT

CLKIN

÷ n (n:1 to 16)

PLL0 to PLL3

CLKC register

Peripheral bus

Standby mode

The PLL is stopped immediately after reset. The clock input from the CLKIN pin is directly supplied to the

µPD77210 Family internal circuitry and bootup commences. The PLL is started up in the boot routine and booting is
carried out via the PLL output clock (except in the case of non-boot or external memory boot). In the case of non-

boot or external memory boot, when booting has finished, after the PLL is started up by setting the CLKC register

from the user program, the clock source must be switched to the PLL, in which case the PLL must be locked. Note

that 300

µs are required between when the PLL is started up and when it is locked.

The PLL multiplication rate is specified by the external pins PLL0 to PLL3. The PLL also has two lock range

modes: 80 to 120 MHz and 120 to 160 MHz. The mode to be used is specified by the P3 pin during booting. The

CLKC register is used to control turning on/off the PLL, select the clock source (external clock/multiplied

clock/divided or non-divided output), control resetting the output divider, set the division ratio, and enable/disable

CLKOUT pin output.

When the output divider is selected, the high-level width of the clock output by the CLKOUT pin is equivalent to 1

cycle of the normal operation (which means that the clock does not have a duty factor of 50%).

In halt mode, output of the divider circuit is automatically selected as the clock source. When the divider circuit is

selected, the clock is not changed even if halt mode is set.

In stop mode, the system clock supplied to the internal circuitry is masked. Because the PLL is not stopped

automatically, it can recover from stop mode without PLL lock time. It is necessary to set the CLKC register by the

program to stop the PLL.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

4. RESET FUNCTION

The device is initialized when a low level of the specified width is input to the RESET pin.

4.1 Hardware Reset

The internal circuitry of the

µPD77210 Family is initialized when the RESET pin is asserted active (low level) for a

specific period. When the RESET pin is then deasserted inactive (high level), booting of the instruction RAM is

performed in accordance with the status of the port pins (P0, P1, P2, and P3), and then processing is executed

starting from the instruction at address 0x200 (reset entry) of the instruction memory.

5. FUNCTION OF BOOT-UP ROM

The instruction RAM is booted up by using the internal boot-up ROM when power is applied or when the contents

of the instruction memory are to be rewritten by the program.

5.1 Boot at Reset

Immediately after release of a hardware reset, the boot program first reads general-purpose I/O port pins P0 to

P3, and a boot mode (memory boot/host boot/serial boot) is determined by the bit patterns of these port pins. Once

the booting processing has been completed, processing is executed starting from the instruction at address 0x200

(reset entry) of the instruction memory.

Boot Mode

Non-boot

Note

X memory initial boot

Y memory initial boot

XY memory initial boot

External memory initial boot

Host boot

Serial boot

Note This setting is used when the

µPD77210 Family must be reset upon restoration from standby mode after a

reset boot has been executed once.

PLL lock range

120 to 160 MHz

80 to 120 MHz

5.1.1 Memory boot

The instruction code stored in data memory is transferred to the instruction RAM. Depending on the data memory

from which the instruction code is to be transferred, X memory boot (booting from the X data memory), Y memory

boot (booting from the Y data memory), XY memory boot (booting from the X and Y data memories), or external

memory boot (booting from the external data memory space) may be performed.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

5.1.2 Host boot

The boot parameter and instruction code are obtained via the host interface and transferred to the instruction

RAM.

5.1.3 Serial boot

The boot parameter and instruction code are obtained via the serial interface and transferred to the instruction

RAM.

5.2 Reboot

The contents of the instruction RAM can be rewritten by calling the following reboot entries by the program.

Parameter

Reboot Mode

Entry

Address

Number of

Instruction

Steps

Transfer

Source Start

Address

Transfer

Destination

Transfer

Destination

Start

Address

Transfer

Destination

Page

(DPR)

X memory

0x1

R7L

DP3

R6L

DP2

R5L

Y memory

0x2

R7L

DP7

R6L

DP6

R5L

XY memories

0x3

R7L

DP3, DP7

R6L

DP2

R5L

Memory

reboot

External memory

0x4

R7L

DP3

R6L

DP2

R5L

Host reboot

0x5

R7L

R6L

DP2

R5L

Serial reboot

0x6

R7L

R6L

DP2

R5L

5.2.1 Memory reboot

The instruction code stored into data memory is transferred to the instruction RAM. Depending on the data

memory from which the instruction code is to be transferred, X memory reboot (rebooting from the X data memory), Y

memory reboot (rebooting from the Y data memory), XY memory reboot (rebooting from the X and Y data memories),

or external memory reboot (rebooting from the external data memory space) may be performed.

Perform memory rebooting by setting the following parameters and calling the entry address by the corresponding

rebooting method.

· R7L: Number of instruction steps to be rebooted
· DP3: First address of X memory storing instruction code (to reboot from X, XY or external memories)
· DP7: First address of X memory storing instruction code (to reboot from Y or XY memories)
· R6L: Transfer source data page register (DPR) (Specify 0x00 in the case of the internal data RAM area.)

Index register (for external memory rebooting)

· DP2: Transfer destination address of the instruction to be rebooted (to reboot from X, XY or external memories)
· DP6: Transfer destination address of the instruction to be rebooted (to reboot from Y memories)
· R5L: Transfer destination page register (DPR) (Specify 0x80 in the case of the internal instruction RAM area.)

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

6. STANDBY MODE

The

µPD77210 Family can be set to either of two standby modes. Each mode can be set by executing the

corresponding instruction. The power consumption can be reduced in these modes.

6.1 Halt Mode

The halt mode can be set by executing the HALT instruction. In this mode, all the functions except the clock

circuit and PLL are stopped and, therefore, the current consumption can be reduced.

The device can be released from this mode by an interrupt or hardware reset. To release the device from halt

mode by issuing an interrupt, the contents of the internal registers and memories are retained. It takes 10 to 20

system clocks to release the

µPD77210 Family from halt mode (if it is released by an interrupt).

When releasing the device from halt mode by using hardware reset, the external clock must be selected as the

clock source in advance that the contents of memories are retain.

In halt mode, the clock circuit of the

µPD77210 Family supplies the clock divided by the ratio specified by the

CLKC register as the internal system clock. The same applies to the clock output by the CLKOUT pin.

6.2 Stop Mode

Stop mode is set when a STOP instruction is executed. In this mode, supply of the clock to the internal system is

stopped.

If the PLL is stopped before stop mode is set, all the functions, including the clock circuit and PLL, are stopped.

As a result, only a leakage current flows and, therefore, the current consumption can be minimized. In this case, the

external clock must be selected as the clock source in advance.

The device is released from stop mode by a hardware reset or the CSTOP pin.

To release the device from stop mode by using the CSTOP pin, the contents of the internal registers and

memories are retained. When releasing the device from stop mode by using hardware reset, the external clock must

be selected as the clock source in advance that the contents of memories are retain.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

7. MEMORY MAP

The

µPD77210 Family employs a Harvard architecture that separates the instruction memory space from the data

memory space.

7.1 Instruction Memory

7.1.1 Instruction memory map

The instruction memory space consists of 64 Kwords

× 32 bits. The area at addresses 0x8000 to 0xFFFF is a

paging area that supports a memory space of 64 Kwords or more by specifying a page by using the instruction

paging register (IPR).

The instruction ROM of the

µPD77213 exists in the paging area and is accessed as IPR=0x0 or 0x1.

The paging area of the

µPD77210 is reserved for future expansion.

Instruction RAM

(15.5 Kwords)

0xFFFF

0x8000

0x7FFF

0x0200

0x01FF

0x0000

System area

0x4000

0x3FFF

Instruction ROM

Note

(32 Kwords)

(IPR=0x0)

(IPR=0x1)

Paging area

Instruction RAM

(31.5 Kwords)

Boot-up ROM

(512 words)

0x0200

0x01FF

0x0000

0xFFFF

0x8000

0x7FFF

PD77210

PD77213

Paging area
(32 Kwords)

Boot-up ROM

(512 words)

Note The higher 8 words of the instruction ROM (0xFFF8 to 0xFFFF) constitute system area.

Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If

these addresses are accessed, correct operation of the device is not guaranteed.

A paging area in which no IPR page exists cannot be accessed. If this kind of paging area is

accessed, correct operation of the device is not guaranteed.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

7.1.2 Interrupt vector table

Addresses 0x200 to 0x23F of the instruction memory are assigned to entry points (vectors) of interrupts. Four

instruction addresses are assigned to each interrupt source.

Four interrupt sources are assigned to each interrupt vector. There are 12 vectors. By identifying the source in

the vector, the

µPD77210 can use 38 interrupt sources and µPD77213 can use 42 interrupt sources.

Each of these interrupt sources can be masked by using the interrupt control register (ICR0 to ICR11).

Interrupt Source

Vector

0x200

Reset

Reserved

0x204

Reserved

0x208

Reserved

0x20C

Reserved

0x210

INT00

INT01

INT02

INT03

0x214

INT10

INT11

INT12

INT13

0x218

INT20

INT21

INT22

INT23

0x21C

INT30

INT31

INT32

INT33

0x220

TSI input

TSIEN

PMT ch0

(TSI input)

SDCR input

Note

0x224

TSO output

TSOEN

PMT ch1

(TSO output)

SDCR output

Note

0x228

ASI input

ASIEN

PMT ch2

(ASI input)

SDDAT input

Note

(busy release)

0x22C

ASO output

ASOEN

PMT ch3

(ASO output)

SDDAT output

Note

0x230

HI input

HWR

PMT ch4

(HI input)

Reserved

0x234

HO output

HRD

PMT ch5

(HO output)

Reserved

0x238

TIMER ch0

TIMER ch1

PMT ch6

(MI input)

Reserved

0x23C

TIMER ch1

TIMER ch0

PMT ch7

(MO output)

Reserved

Note These interrupt sources are for the

µPD77213 only. When using the µPD77210, they are reserved.

Cautions 1. Reset is not an interrupt but is used as an entry of a vector.

2. It is recommended that the vector of an interrupt source that is not used branch to an

abnormality processing routine.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

7.2 Data Memory

7.2.1 Data memory map

The data memory space consists of two planes: the X and Y memory spaces, each of which consists of 64

Kwords

× 16 bits. The area of 0x8000 to 0xFFFF is a paging area that supports a memory space of 64 Kwords or

more by specifying a page by using the data paging register (DPR). The DPR can be set in the same manner

regardless of whether the X or Y memory space is accessed.

Page 0x3F of DPR is a window to the external data memory. The Data ROM of the

µPD77213 exists in the

paging area and is accessed as DPR

=0x0.

Page 0x80 of the DPR is shared by 0x0000 to 0x7FFF of the internal instruction RAM. The lower 16 bits of the

32-bit instruction RAM constitute the X data memory, while the higher 16 bits are the Y data memory.

Because some pins of the

µPD77213 are shared with the SD card interface, the area that can be accessed when

the SD card interface is being used is restricted. The address pins MA13 to MA19 are shared with the SD card

interface. When the SD card interface is being used, therefore, only the 13-bit address area of MA0 to MA12 (8

Kwords) can be accessed.

0xFFFF

0x8000

0x7FFF

0x3800

0x37FF

0x0000

System

0x4000

0x3FFF

(DPR=0x0)

(DPR=0x3F)

Paging area

0x5000

0x4FFF

Data RAM

(14 Kwords)

Paging area

Note 1

(32 Kwords)

0xFFFF

0x8000

0x7FFF

0x3800

0x37FF

0x0000

0x4000

0x3FFF

External data

memory window

(32 Kwords)

(DPR=0x3F)

Peripheral

(2 Kwords)

Data RAM

(16 Kwords)

PD77210

PD77213

Paging area
(32 Kwords)

Data RAM

(14 Kwords)

Peripheral

(2 Kwords)

Data RAM

(4 Kwords)

Data ROM

Note 2

(32 Kwords)

External data

memory window

(32 Kwords)

Paging area

Notes 1. If the paging register is set to a value other than 0x3F (external data memory window) or 0x80 (internal

instruction RAM area), programs and data cannot be stored to the addresses of the paging area, nor

can these addresses be accessed.

2. The higher 8 words of the data ROM (0xFFF8 to 0xFFFF) constitute system area.

Caution Programs and data cannot be allocated to the system area, and neither can it be accessed. If

these addresses are accessed, correct operation of the device is not guaranteed.

A paging area in which no DPR page exists cannot be accessed. If this kind of paging area is

accessed, correct operation of the device is not guaranteed.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

7.2.2 Internal peripherals

The internal peripherals are mapped to the internal data memory space.

Cautions 1. The register names shown in the above table are not reserved words in either assembler or

C. To use these names in assembler or C, therefore, the user must define them.

2. The same register is accessed regardless of whether the X memory space or Y memory

space is accessed, provided that the address is the same.

3. Different registers cannot be accessed simultaneously from the X and Y memory spaces.

Memory-Mapped Peripherals (1/3)

X/Y Memory Address

Function

Peripheral

Name

0x3800

TSDT/SDT1

TDM serial data register/Serial data register 1

0x3801

SST1

Serial status register 1

0x3802

TSST

TDM serial status register

0x3803

TFMT

TDM frame format register

0x3804

TTXL

TDM transfer slot register (low)

0x3805

TTXH

TDM transfer slot register (high)

0x3806

TRXL

TDM receive slot register (low)

0x3807

TRXH

TDM receive slot register (high)

TSIO(SIO1)

0x3808 to 0x380F

Reserved area

Caution Do not access this area.

0x3810

ASDT/SDT2

Audio serial data register/Serial data register 2

0x3811

SST2

Serial status register 2

0x3812

ASST

Audio serial status register

ASIO(SIO2)

0x3813 to 0x381F

Reserved area

Caution Do not access this area.

0x3820

HDT

Host interface data register

0x3821

HST

Host interface status register

HIO

0x3822 to 0x383F

Reserved area

Caution Do not access this area.

0x3840

MDT

Memory data register

0x3841

MSHW

Memory I/F setup/hold width setting register

0x3842

MCST

Memory I/F control/status register

0x3843

MWAIT

Memory I/F wait register

0x3844

MIDX

Direct access index register

0x3845

MADRLI

Memory I/F input start address register (low)

0x3846

MADRHI

Memory I/F input start address register (high)

0x3847

MOFSI

Memory I/F input line offset register

0x3848

MLENI

Memory I/F input line length register

0x3849

MADRLO

Memory I/F output start address register (low)

0x384A

MADRHO

Memory I/F output start address register (high)

0x384B

MOFSO

Memory I/F output line offset register

0x384C

MLENO

Memory I/F output line length register

MIO

0x384D to 0x384F

Reserved area

Caution Do not access this area.

0x3850

PMSA0

PMT start address register 0

PMT ch0

0x3851

PMS0

PMT size register 0

0x3852

PMC0

PMT control register 0

0x3853

PMP0

PMT address pointer 0

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Memory-Mapped Peripherals (2/3)

X/Y Memory Address

Function

Peripheral

Name

0x3854

PMSA1

PMT start address register 1

0x3855

PMS1

PMT size register 1

0x3856

PMC1

PMT control register 1

0x3857

PMP1

PMT address pointer 1

PMT ch1

0x3858

PMSA2

PMT start address register 2

0x3859

PMS2

PMT size register 2

0x385A

PMC2

PMT control register 2

0x385B

PMP2

PMT address pointer 2

PMT ch2

0x385C

PMSA3

PMT start address register 3

0x385D

PMS3

PMT size register 3

0x385E

PMC3

PMT control register 3

0x385F

PMP3

PMT address pointer 3

PMT ch3

0x3860

PMSA4

PMT start address register 4

0x3861

PMS4

PMT size register 4

0x3862

PMC4

PMT control register 4

0x3863

PMP4

PMT address pointer 4

PMT ch4

0x3864

PMSA5

PMT start address register 5

0x3865

PMS5

PMT size register 5

0x3866

PMC5

PMT control register 5

0x3867

PMP5

PMT address pointer 5

PMT ch5

0x3868

PMSA6

PMT start address register 6

0x3869

PMS6

PMT size register 6

0x386A

PMC6

PMT control register 6

0x386B

PMP6

PMT address pointer 6

PMT ch6

0x386C

PMSA7

PMT start address register 7

0x386D

PMS7

PMT size register 7

0x386E

PMC7

PMT control register 7

0x386F

PMP7

PMT address pointer 7

PMT ch7

0x3870

PDT0

Port data register 0

0x3871

PCD0

Port command register 0

0x3872

PDT1

Port data register 1

0x3873

PCD1

Port command register 1

0x3874

PDT2

Port data register 2

PIO

0x3875

PCD2

Port command register 2

0x3876

PDT3

Port data register 3

0x3877

PCD3

Port command register 3

0x3878, 0x3879

Reserved area

Caution Do not access this area.

0x387A, 0x387B

POWC

Power control register

Peripheral

STOP mode

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Memory-Mapped Peripherals (3/3)

X/Y Memory Address

Function

Peripheral

Name

0x387C to 0x387F

Reserved area

Caution Do not access this area.

0x3880

ICR0

Interrupt control register 0

0x3881

ICR1

Interrupt control register 1

0x3882

ICR2

Interrupt control register 2

0x3883

ICR3

Interrupt control register 3

0x3884

ICR4

Interrupt control register 4

0x3885

ICR5

Interrupt control register 5

0x3886

ICR6

Interrupt control register 6

0x3887

ICR7

Interrupt control register 7

0x3888

ICR8

Interrupt control register 8

0x3889

ICR9

Interrupt control register 9

0x388A

ICR10

Interrupt control register 10

0x388B

ICR11

Interrupt control register 11

INTC

0x388C to 0x388F

Reserved area

Caution Do not access this area.

0x3890

TIR0

Timer initial register 0

0x3891

TCR0

Timer count register 0

0x3892

TCSR0

Timer control/status register 0

TIM0

0x3893

Reserved area

Caution Do not access this area.

0x3894

TIR1

Timer initial register 1

0x3895

TCR1

Timer count register 1

0x3896

TCSR1

Timer control/status register 1

TIM1

0x3897 to 0x389F

Reserved area

Caution Do not access this area.

0x38A0

CEFR

Collect enable flag register

0x38A1

CPR0

Collect page register 0

0x38A2

CAR0

Collect address register 0

0x38A3

CLIR0

Collect instruction data register (high) 0

0x38A4

CUIR0

Collect instruction data register (low) 0

0x38A5

CPR1

Collect page register 1

0x38A6

CAR1

Collect address register 1

0x38A7

CLIR1

Collect instruction data register (high) 1

0x38A8

CUIR1

Collection instruction data register (low) 1

IMC

0x38A9 to 0x38AF

Reserved area

Caution Do not access this area.

0x38B0

CLKC

Clock control register

CLKC

0x38B1 to 0x38BF

Reserved area

Caution Do not access this area.

0x38C0

IPR

Instruction paging register

0x38C1

DPR

Data paging register

Page register

0x38C2 to 0x38CF

Reserved area

Caution Do not access this area.

0x38D0

ADCR

Note

Additional I/F control register

Additional IO

0x38D1-0x3FFF

Reserved area

Caution Do not access this area.

Note

µPD77213 only. Do not access 0x38D0 of the µPD77210.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

9. INSTRUCTION

9.1 Outline of Instruction

One instruction consists of 32 bits. All the instructions, with some exceptions such as branch instructions, are

executed with one system clock. The instruction cycle of the

µPD77210 is up to 6.25 ns. The instruction cycle of the

µPD77213 is up to 8.33 ns. The following nine types of instructions are available.

(1) Trinomial instructions

These instructions specify an operation by the MAC. As the operands, three general-purpose registers can

be specified.

(2) Binomial instructions

These instructions specify an operation by the MAC, ALU, or BSFT. As the operands, two general-purpose

registers can be specified. Some of these instructions allow one immediate value to be specified instead of a

general-purpose register.

(3) Monomial instructions

These instructions specify an operation by the ALU. As the operand, a general-purpose register can be

specified.

(4) Load/store instructions

These instructions specify 16-bit data transfer between memory and a general-purpose register. As the

operand, any general-purpose register can be specified.

(5) Register-to-register transfer instructions

These instructions specify transfer between a general-purpose register and another register.

(6) Immediate value setting instructions

These instructions set an immediate value in the general-purpose registers and each register of the address

operation unit.

(7) Branch instructions

These instructions specify branching of the program.

(8) Hardware loop instructions

These instructions specify the repetitive execution of an instruction.

(9) Control instructions

These instructions specify program control.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Instruction Set

Instructions That Can Be

Described Simultaneously

Flag

I
n

t
ruc

t
i
on Group

Instruction Name

Mnemonic

Operation

Tri

nom

i
a

i
nom

i
a

onom

i
a

Load/

t
ore

Trans

f
e

Immedi

ate V

l
u

r
anc

Loop

Cont

rol

Multiply add

ro = ro + rh*rh'

ro + rh*rh'

Multiply sub

ro = ro

- rh*rh'

ro - rh*rh'

Signed/unsigned

multiply add

ro = ro + rh*rl

(rl is in positive integer format.)

ro + rh*rl

Unsigned/unsigned

multiply add

ro = ro + rl*rl'

(rl and rl' are in positive integer

format.)

ro + rl*rl'

1-bit shift multiply add

ro = (ro >> 1) + rh*rh'

ro/2 + rh*rh'

Tri

nom

i
a

l
operat

i
o

16-bit shift multiply

add

ro = (ro >> 16) + rh*rh'

ro/2 + rh*rh'

Multiply

ro = rh*rh'

rh*rh'

Add

ro" = ro + ro'

ro"

ro + ro'

Immediate add

ro' = ro + imm

ro'

ro + imm

(where imm

Sub

ro" = ro

- ro'

ro"

ro - ro'

Immediate sub

ro' = ro

- imm

ro'

ro - imm

(where imm

Arithmetic right shift

ro' = ro SRA rl

ro'

ro >> rl

Immediate arithmetic

right shift

ro' = ro SRA imm

ro'

ro >> imm

Logical right shift

ro' = ro SRL rl

ro'

ro >> rl

Immediate logical right

shift

ro' = ro SRL imm

ro'

ro >> imm

Logical left shift

ro' = ro SLL rl

ro'

ro << rl

Immediate logical left

shift

ro' = ro SLL imm

ro'

ro << imm

And

ro" = ro & ro'

ro"

ro & ro'

Immediate and

ro' = ro & imm

ro'

ro & imm

ro" = ro | ro'

ro"

ro | ro'

Immediate or

ro' = ro | imm

ro'

ro | imm

Exclusive or

ro" = ro^ro'

ro"

ro^ro'

Immediate exclusive

ro` = ro^imm

ro'

ro^imm

i
nom

i
a

l
operat

i
o

Less than

ro" = LT (ro, ro')

if (ro < ro')

{ro"

0x0000000001}

else {ro"

0x0000000000}

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Instructions That Can Be

Described Simultaneously

Flag

I
n

t
ruc

t
i
on Group

Instruction Name

Mnemonic

Operation

Tri

nom

i
a

i
nom

i
a

onom

i
a

Load/

t
ore

Trans

f
e

Immedi

ate V

l
u

r
anc

Loop

Cont

rol

ro = *dpx_mod ro' = *dpy_mod

*dpx, ro' *dpy

ro = *dpx_mod *dpy_mod = rh

*dpx, *dpy rh

*dpx_mod = rh ro = *dpy_mod

*dpx

rh, ro *dpy

Parallel load/store

Notes 1, 2

*dpx_mod = rh *dpy_mod = rh'

*dpx

rh, *dpy rh'

dest = *dpx_mod

dest' = *dpy_mod

dest

*dpx,

dest'

*dpy

dest = *dpx_mod

*dpy_mod = source

dest

*dpx,

*dpy

source

*dpx_mod = source

dest = *dpy_mod

*dpx

source,

dest

*dpy

Partial load/store

Notes 1, 2, 3

*dpx_mod = source

*dpy_mod = source'

*dpx

source,

*dpy

source'

dest = *addr

dest

*addr

Direct addressing

load/store

Note 4

*addr = source

*addr

source

dest = *dp_imm

dest

*dp

Load/

t
ore

Immediate index

load/store

Note 5

*dp_imm = source

*dp

source

dest = rl

dest

Regis

t
er

t
o

-
r
egis

t
er

transfer

Note 6

rl = source

source

rl = imm

(where imm = 0 to 0xFFFF)

dp = imm

(where imm = 0 to 0xFFFF)

imm

dn = imm

(where imm = 0 to 0xFFFF)

imm

I
m

edi

e v

l
ue s

t
t
i
ng

Immediate value setting

dm = imm

(where imm = 1 to 0xFFFF)

imm

Notes 1. Of the two mnemonics, either or both can be described.

2. After transfer, modification specified by mod is performed.

3. dest, dest' = {ro, reh, re, rh, rl}, source, source' = {re, rh, rl}

4. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}, addr = {0: X-0xFFFF: X (X memory), or 0: Y-0xFFFF: Y

(Y memory)}

5. dest = {ro, reh, re, rh, rl}, source = {re, rh, rl}

6. Select any of the registers (except the general-purpose registers) as dest and source.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

10. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= +25

°
°
°
°C)

Parameter

Symbol

Condition

Rating

Unit

For DSP core

- 0.5 to + 2.0

Supply voltage

For I/O pins

- 0.5 to + 4.6

Input voltage

- 0.5 to + 4.6

Output voltage

< EV

+ 0.5 V

- 0.5 to + 4.6

Storage temperature

stg

- 65 to + 150

°C

Operating ambient

temperature

- 20 to + 70

°C

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions

that ensure that the absolute maximum ratings are not exceeded.

Recommended Operating Conditions

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Operating voltage

For DSP core (operating

speed 120 MHz Max.)

1.425

1.50

1.65

For DSP core (operating

speed 160 MHz Max.)

Note

1.55

1.60

1.65

For I/O pins

2.7

3.3

3.6

Input voltage

Note

µPD77210 only

Capacitance (T

= +25

°
°
°
°C, IV

= 0 V, EV

= 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input capacitance

Output capacitance

I/O capacitance

f = 1 MHz,

Pins other than those

tested: 0 V

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

DC Characteristics (Unless otherwise specified, T

-
-
-
- 20 to + 70°°°°C, with IV

and EV

within recommended

operating condition range)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

High level input voltage

IHN

Pins other than below

0.7 EV

IHC

CLKIN

0.7 EV

IHS

RESET, P0 to P15, TSCK,

TSIEN,TSOEN, ASCK, ASIEN,

ASOEN

0.8 EV

Low level input voltage

ILN

Pins other than below

0.2 EV

ILC

CLKIN

0.2 EV

ILS

RESET, P0 to P15, TSCK,

TSIEN,TSOEN, ASCK, ASIEN,

ASOEN

0.2 EV

High level output voltage

-100

µA

0.8 EV

Low level output voltage

= 2.0 mA

0.2 EV

High level input leakage

current

LHN

= EV

µA

Low level input leakage

current

LLN

= 0 V

-10

µA

High impedance leakage

current

0 V

-10

µA

Pull-up pin current

PUI

TDI, TMS, 0 V

200

µA

Pull-down pin current

PDI

TRST, 0 V

-20

-70

-200

µA

During operating,

fclk = 100 MHz,

PLL multiple rate x10

Note 1

Note 2

DDH

In halt mode,

fclk = 100 MHz,

PLL multiple rate x 10,

division rate 1/1

Note 3

Internal supply current

[fclkin = 10 MHz,

= 1.5 V,

IHN

= V

IHC

= V

IHS

= EV

= 0 V, no load,

= 25°C]

DDS

In stop mode

Note 4

µPD77210

240

µA

fclk = 0 Hz,

PLL stop

µPD77213

120

Notes 1. The value is when MAC with Dual Load instruction 50% + nop instruction 50% are executed. It is

roughly estimated at 0.35 mA/MHz.

2. The value is when a special program that brings about frequent switching inside the device is

executed.

It is roughly estimated at 0.7 mA/MHz.

3. The value is when the division rate is 1/1. It is roughly estimated at 0.2 mA/MHz + I

DDS

using the

divided clock.

4. The value in stop mode is the value when PLL is stopped.

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

AC Characteristics (T

-
-
-
- 20 to + 70°°°°C, with IV

and EV

within recommended operating condition range)

Clock

Timing requirements

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

CLKIN cycle time

Note 1

cCX

62.5

CLKIN high level width

wCXH

12.5

CLKIN low level width

wCXL

12.5

CLKIN rise/fall time

rfCX

Internal clock cycle time

Over 120 MHz(

µPD77210

only)

6.25

requirements

Under 120 MHz

8.33

PLL lock-up time

LPLL

300

µs

PLL lock frequency

Note 1

cPLL

When boot:P3

= 0

Note 2

120

160

MHz

When boot:P3

= 1

120

MHz

Notes 1. The CLKIN cycle time must accord with the PLL lock frequency. It is therefore necessary to satisfy both

the CLKIN cycle time condition of 62.5 ns (MIN.) and the PLL lock frequency condition of a multiplied

frequency in the range of 80 to 160 MHz.

2. In the

µPD77213, it can be set only when an external memory boot is being used.

Switching characteristics

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Internal clock cycle

Note

cCX

÷ m × n

CLKOUT cycle time

cCO

CLKOUT width

wCO

n = 1

÷ 2

High level width

÷ n

Low level width

÷ n

CLKOUT rise/fall time

rfCO

CLKOUT delay time

dCO

6.25

Note m: Multiple ratio, n: Division ratio (PLL, divider)

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

12. RECOMMENDED SOLDERING CONDITIONS

The

µPD77210 Family should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Surface Mounting Type Soldering Conditions

µ
µ
µ
µPD77210F1-DA2::::161-pin plastic fine pitch BGA (10 x 10)
µ
µ
µ
µPD77213F1-xxx-DA2::::161-pin plastic fine pitch BGA (10 x 10)

Soldering method

Soldering conditions

Recommended

condition symbol

Infrared reflow

Package peak temperature

: 235 °C, Time: 30 sec. Max. (at 210 °C or higher).

Count

: two times or less

Exposure limit

: 7 days

Note

(after that prebaking is necessary at 125

°C for 10 to 72

hours)

IR35-107-2

µ
µ
µ
µPD77210GJ-8EN::::144-pin plastic LQFP (fine pitch) (20 x 20)
µ
µ
µ
µPD77213GJ-xxx-8EN::::144-pin plastic LQFP (fine pitch) (20 x 20)

Soldering method

Soldering conditions

Recommended

condition symbol

Infrared reflow

Package peak temperature

: 235 °C, Time: 30 sec. Max. (at 210 °C or higher).

Count

: two times or less

Exposure limit

: 3 days

Note

(after that prebaking is necessary at 125

°C for 10 to 72

hours)

IR35-103-2

Partial heating

Pin temperature

: 300 °C Max. , Time: 3 sec. Max. (per pin row)

Note After opening the dry pack, store it at 25

°C or less and 65 % RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for the partial heating).

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829

J01.2

Data Sheet U15203EJ3V0DS

µ
µ
µ
µ

PD77210, 77213

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

µ
µ
µ
µ

PD77210,77213

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

License not needed

µPD77210F1-DA2, µPD77210GJ-8EN

The customer must judge the

µPD77213F1-xxx-DA2, µPD77213GJ-xxx-8EN

M8E 00. 4

The information in this document is current as of November, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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