Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATION FIELDS
ORDERING INFORMATION
78K/II Product Development
FUNCTION LIST
PIN CONFIGURATION (TOP VIEW)
PIN IDENTIFICATION
EXAMPLE OF SYSTEM CONFIGURATION (INVERTER AIR-CONDITIONER IN-DOOR UNIT)
INTERNAL BLOCK DIAGRAM
1. DIFFERENCES BETWEEN uPD78218A AND uPD78214 SUBSERIES
2. PIN FUNCTIONS
- 2.1 PORTS
- 2.2 NON-PORT PINS
- 2.3 PIN I/O CIRCUITS AND UNUSED PIN CONNECTION
3. INTERNAL BLOCK FUNCTIONS
- 3.1 MEMORY SPACE
- 3.2 PORTS
- 3.3 REAL-TIME OUTPUT PORT
- 3.4 TIMER/COUNTER UNIT
- 3.5 A/D CONVERTER
- 3.6 SERIAL INTERFACE
  - 3.6.1 Asynchronous Serial Interface
  - 3.6.2 Clock Synchronous Serial Interface
4. INTERNAL/EXTERNAL CONTROL FUNCTION
- 4.1 INTERRUPTS
  - 4.1.1 Interrupt Sources
  - 4.1.2 Vectored Interrupt
  - 4.1.3 Macro Service
  - 4.1.4 Macro Service Application Examples
- 4.2 LOCAL BUS INTERFACE
  - 4.2.1 Memory Expansion
  - 4.2.2 Programmable Wait
  - 4.2.3 Pseudo-Static RAM Refresh Function
- 4.3 STANDBY
- 4.4 RESET
5. INSTRUCTION SET
6. ELECTRICAL SPECIFICATIONS
7. PACKAGE DRAWINGS
8. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. DEVELOPMENT TOOLS
APPENDIX B. RELATED DOCUMENTS

The mark 5 shows revised points.

The information in this document is subject to change without notice.

Document No. IC-2748E

(O. D. No. IC-8131E)

Date Published April 1995 P
Printed in Japan

DESCRIPTION

The

PD78217A and 78218A are members of the 78K/II series of microcontrollers featuring a high-speed high-

performance CPU. The

PD78217A and 78218A are based on the

PD78213 and 78214, and feature increased memory

capacity and added functions, such as a timer/counter and macro servicing.

Functions are described in detail in the following User's Manuals, which should be read when carrying out design

work.

PD78218A Subseries User's Manual: Hardware (IEU-1313)

78K/II Series User's Manual: Instruction (IEU-1311)

FEATURES

Upper compatibility with

PD78214 subseries (pin-compatible)

High-speed instruction execution (at 12 MHz): 333 ns (

PD78218A), 500 ns (

PD78217A)

On-chip high-performance interrupt controller

On-chip A/D converter: 8 bits

8 channels

Number of I/O pins: 54 (

PD78218A), 36 (

PD78217A)

Real-time output ports: 8 bits

1 channel or 4 bits

2 channels

Serial interface: 2 channels

Timer/counter: 16 bits

1 channel and 8 bits

3 channels

APPLICATION FIELDS

Printers, typewriters, OA equipment such as plain paper copiers (PPCs) and faxes, electronic music instruments,

inverters, cameras, etc.

ORDERING INFORMATION

Part Number

Package

On-Chip ROM

On-Chip RAM

PD78217ACW

64-pin plastic shrink DIP (750 mil)

None

1024

PD78217AGC-AB8

64-pin plastic QFP (14 x 14 mm)

None

1024

PD78218ACW-

×××

64-pin plastic shrink DIP (750 mil)

32K

1024

PD78218AGC-

×××

-AB8

64-pin plastic QFP (14 x 14 mm)

32K

1024

Remark

×××

is the ROM code suffix.

8-BIT SINGLE-CHIP MICROCONTROLLER

DATA SHEET

MOS INTEGRATED CIRCUIT

PD78217A,78218A

1992

1991

PD78217A, 78218A

333 ns (at 12-MHz)

16-bit operation

Multiply and divide (8 bits

8 bits, 16 bits

8 bits)

Bit manipulate

BCD adjust, etc.

None

32 Kbytes

1024 bytes

Program memory: 64 Kbytes, data memory: 1 Mbytes

ROM-less version

EA pin = low level

8 bits

4 banks (memory mapping)

16-bit timer/counter

Timer register

Pulse output capability

Capture register

Toggle output, PWM/PPG

Compare register

One-shot pulse output

8-bit timer/counter 1

Timer register

Pulse output capability

Capture/compare register

(Real-time outputs, 4 bits

Compare register

8-bit timer/counter 2

Timer register

Pulse output capability

Capture register

Toggle output

Compare register

PWM/PPG

8-bit timer/counter 3

Timer register

Compare register

Output port linked 8-bit timer/counter 1

4 bits

2 channels

UART

: 1 channel (on-chip dedicated baud rate generator)

CSI (3-wire serial I/O, SBI) : 1 channel

8-bit resolution

8 channels

19 sources (external 7, internal 12) + BRK instruction

2-level priority order (programmable)

2 servicing modes (vectored interrupt, macro service)

64-pin plastic shrink DIP (750 mil)

64-pin plastic QFP (14 x 14 mm)

Additional

function pins

FUNCTION LIST

Basic instructions

(mnemonic)

Minimum instruction

execution time

Instruction set

On-chip memory

capacity

Address space

I/O

pins

ROM-less mode setting

General registers

Timer/counter

Real-time output port

Serial interface

A/D converter

Interrupt

Package

PD78218A

Item

PD78217A

ROM

RAM

Input

Output

Input/Output

Total

Pins with pull-up resistor

LED direct drive outputs

Transistor direct drive
outputs

Note Additional function pins are included in I/O pins.

Note

PD78217A, 78218A

INTERNAL BLOCK DIAGRAM

Caution

Inernal ROM/RAM capacity varies depending on the product.

Note

In case of the

PD78217A, P40 to P47, P50 to P57, P64 and P65 cannot be used as ports.

P70
-P75

INTP5

PROGRAMMABLE

INTERRUPT

CONTROLLER

BAUD RATE

GENERATOR

UART

CLOCKED

SERIAL

INTERFACE

TIMER/COUNTER

(16 BITS)

REAL-TIME

OUTPUT PORT

(4 BITS

TIMER/COUNTER

CHANNEL-1

(PS + 8 BITS)

TIMER/COUNTER

CHANNEL-2

(PS + 8 BITS)

TIMER/COUNTER

CHANNEL-3

(PS + 8 BITS)

A/D CONVERTER

SFR ADDRESS/DATA BUS

REF

AN0-AN7

P04-P07

P00-P03

TO3

TO2

INTP2

INTP1

INTP0

TO1

TO0

INTP3

SO/SB0

SCK

ASCK

NMI

INTP0-INTP5

BUS CONTROL

ADDRESS BUS

ALU

ROM

TEMPORARY

REGISTERS

PSW

BOOLEAN

PROCESSOR

· RAM (256 Bytes)
· GR
· MACRO
SERVICE
CHANNEL

DATA BUS (8)

· MICRO ROM
· MICRO
SEQUENCER

BUS I/F

SYSTEM CONTROL

DATA BUS

PORT

RAM

A16-A19
(Expansion)
A8-A15

AD0-AD7

WAIT

REFRQ

ASTB

RESET

P64
-P67

P60
-P63

P50
-P57

P40
-P47

P30
-P37

P20
-P27

P00
-P07

Note

PD78217A, 78218A

CONTENTS

DIFFERENCES BETWEEN

PD78218A AND

PD78214 SUBSERIES .................................................. 10

PIN FUNCTIONS ........................................................................................................................................11

2.1

PORTS .................................................................................................................................................................11

2.2

NON-PORT PINS ................................................................................................................................................12

2.3

PIN I/O CIRCUITS AND UNUSED PIN CONNECTION ................................................................................... 13

INTERNAL BLOCK FUNCTIONS ..............................................................................................................15

3.1

MEMORY SPACE ...............................................................................................................................................15

3.2

PORTS .................................................................................................................................................................17

3.3

REAL-TIME OUTPUT PORT .............................................................................................................................. 19

3.4

TIMER/COUNTER UNIT ....................................................................................................................................20

3.5

A/D CONVERTER ...............................................................................................................................................22

3.6

SERIAL INTERFACE ...........................................................................................................................................24

3.6.1

Asynchronous Serial Interface ........................................................................................................ 25

3.6.2

Clock Synchronous Serial Interface ................................................................................................26

INTERNAL/EXTERNAL CONTROL FUNCTION ...................................................................................... 27

4.1

INTERRUPTS ..................................................................................................................................................... 27

4.1.1

Interrupt Sources .............................................................................................................................. 28

4.1.2

Vectored Interrupt .............................................................................................................................30

4.1.3

Macro Service ....................................................................................................................................30

4.1.4

Macro Service Application Examples ............................................................................................. 31

4.2

LOCAL BUS INTERFACE ...................................................................................................................................33

4.2.1

Memory Expansion ...........................................................................................................................33

4.2.2

Programmable Wait ..........................................................................................................................33

4.2.3

Pseudo-Static RAM Refresh Function ............................................................................................ 33

4.3

STANDBY ...........................................................................................................................................................34

4.4

RESET ..................................................................................................................................................................35

INSTRUCTION SET ...................................................................................................................................36

ELECTRICAL SPECIFICATIONS ................................................................................................................40

PACKAGE DRAWINGS .............................................................................................................................57

RECOMMENDED SOLDERING CONDITIONS ........................................................................................59

APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 60

APPENDIX B. RELATED DOCUMENTS ......................................................................................................... 62

PD78217A, 78218A

Part Number

Minimum instruction execution

time (at 12-MHz)

PUSH PSW instruction execution

time (number of clocks)

Power voltage range

On-chip memory

I/O pins

16-bit timer/counter one-shot

pulse output

Macro service counter bit width

Macro service type C MPD, MPT

increments

Macro service execution time

Restrictions when data is

transferred from macro service

type A memory to SFR

A/D converter

Stabilization time for oscillation

in STOP mode release

Package

PD78214 Subseries

PD78212

PD78213

PD78214

PD78P214

333 ns

500 ns

333 ns

When stack area is an internal dual port RAM

: 5 or 7

Other than above

: 7 or 9

=+5V

10%

8 Kbytes

ROM-less

16 Kbytes

(mask ROM)

(PROM)

384 bytes

512 bytes

Not available

NMI active pulse width + dedicated counter 16 bits

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic QUIP: Except

PD78212

· 68-pin plastic QFJ: Except

PD78212

· 64-pin plastic QFP (14 x 14 mm)

· 74-pin plastic QFP (20 x 20 mm)

· 64-pin ceramic shrink DIP

(CERDIP, with window, 750 mil):

PD78P214 only

8/16 bits select capability (except type A)

16-bit increment

Input voltage

restrictions

REF

voltage

restrictions

DIFFERENCES BETWEEN

PD78218A AND

PD78214 SUBSERIES

Macro service depends on mode. Compare with user's manual of products.

Generated when transfer source buffer (memory) address is

0FED0H to 0FEDFH.

Only pins involved in A/D conversion

3.6 V to V

Dedicated counter 15 bits or NMI active pulse width + dedi-

cated counter 16 bits

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic QFP (14 x 14 mm)

· 64-pin ceramic shrink DIP

(CERDIP, with window, 750 mil):

PD78P218A only

Only 8 bits

Only low-order 8 bits increment

(high-order 8 bits are unchanged)

Generated when transfer data is in D0H to DFH.

Pins involved in A/D conversion and pins selected by ADM

REF

pin voltage

3.4 V to V

Series Name

Available

PD78218A Subseries

PD78217A

PD78218A

PD78P218A

500 ns

333 ns

When stack area is an internal dual port RAM

: 6

Other than above

: 8

=+5V

10%

=+5V

0.3V

ROM-less

32 Kbytes

(mask ROM)

(PROM)

1024 bytes

ROM

RAM

PD78217A, 78218A

NMI

INTP0

INTP1

INTP2/CI

INTP3

INTP4/ASCK

INTP5

RxD

TxD

SCK

SO/SB0

TO0 to TO3

AD0 to AD7

A8 to A15

A16 to A19

WAIT/AN6

REFRQ/AN7

AN0 to AN5

PIN FUNCTIONS

2.1

PORTS

Pin Name

I/O

Function

Alternate

Function

Port 0 (P0):

Established as a real-time output port (4 bits

Direct drive of transistors capability

Port 2 (P2):

P20 cannot be used as a general-purpose port. (Non-maskable interrupt)

However, the input level can be confirmed in the interrupt routine.

The connection of the on-chip pull-up resistor can be specified as a 6-bit unit for P22

to P27 by software.

Port 3 (P3):

The input/output specifiable bit-wise.

Input mode pins specifiable for on-chip pull-up resistor connection as a batch by

software.

Port 4 (P4):

The input/output specifiable as an 8-bit batch.

The connection of the on-chip pull-up resistor specifiable as an 8-bit batch by

software.

LED direct drive capability.

Port 5 (P5):

The input/output specifiable bit-wise.

Input mode pins specifiable for on-chip pull-up resistor connection as a batch by

software.

LED direct drive capability.

Port 6 (P6):

P64 to P67 enables to specify the input/output bit-wise.

The connection of the on-chip pull-up resistor to input mode pins can be specified

as a batch for P64 to P67 by software.

Port 7 (P7)

Output

Input

Input/

output

Input/

output

Input/

output

Output

Input/

output

Input

P00 to P07

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34 to P37

P40 to

P47

Note

P50 to

P57

Note

P60 to P63

P64

Note

P65

Note

P66

P67

P70 to P75

Note

In case of the

PD78217A, these cannot be used as ports.

PD78217A, 78218A

P34 to P37

P23 /INTP2

P30

P31

P25/INTP4

P33/SO

P27

P33/SB0

P32

P20

P21

P22

P23/CI

P24

P25/ASCK

P26

P40 to P47

Note

P50 to P57

Note

P60 to P63

P64

Note

P65

Note

P66/AN6

P67/AN7

P70 to P75

TO0 to TO3

ASCK

SB0

SCK

NMI

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

AD0 to AD7

A8 to A15

A16 to A19

WAIT

ASTB

REFRQ

RESET

AN0 to AN5

AN6, AN7

REF

Pin Name

I/O

Output

Input

Output

Input

Output

Input/output

Input

Input/output

Output

Input

Output

Input

Output

Input

Note

In case of the

PD78217A, these cannot be used as ports.

P66/WAIT,

P67/REFRQ

Alternate

Function

2.2

NON-PORT PINS

Function

Timer output

Count clock input to 8-bit timer/counter 2

Serial data input (UART)

Serial data output (UART)

Baud rate clock input (UART)

Serial data input/output (SBI)

Serial data input (3-wire serial I/O)

Serial data output (3-wire serial I/O)

Serial clock input/output (SBI, 3-wire serial I/O)

External interrupt request

Time multiplexing address/data bus (external memory connection)

Upper address bus (external memory connection)

Upper address when extending address (external memory connection)

Read strobe into external memory

Write strobe into external memory

Wait insertion

Address (A0 to A7) latch timing output (during external memory access)

Refresh pulse output into external pseudo-static memory

Chip reset

Crystal connection for system clock oscillation (external clock input to X1

enabled)

ROM-less operating specification (external access of the same space as internal

ROM). Used high for the

PD78218A and used low for the

PD78217A.

Analog voltage input for A/D converter

Reference voltage apply for A/D converter

GND for A/D converter

Positive power supply

GND

PD78217A, 78218A

2.3

PIN I/O CIRCUITS AND UNUSED PIN CONNECTION

The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.

For the input/output circuit configuration of each type, see Fig. 2-1.

Table 2-1 Input/Output Circuit Type of Each Pin

2-A

5-A

8-A

10-A

5-A

Leave open.

Connected to V

or V

Connected to V

Input

: Connected to V

Output

: Leave open.

Leave open.

Input

: Connected to V

Output

: Leave open.

Input

: Connected to V

Note

Output

: Leave open.

Connected to V

Leave open.

Connected to V

or V

Note

Connected to V

Input/Output

Circuit Type

Output

Input

Input/output

Output

Input/output

Input

Output

Input

P00 to P07

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK

P26/INTP5

P27/SI

P30/R

P31/T

P32/SCK

P33/SB0/SO

P34/TO0 to P37/TO3

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT/AN6

P67/REFRQ/AN7

P70/AN0 to P75/AN5

ASTB

RESET

REF

Unused Pin Connection

Pin Name

I/O

Caution

If the input/output mode is undefined for the input/output dual-function pins, connect these pins to

via a resistor of several ten k

(Especially if the reset input pin exceeds the low-level input voltage at power-on or in case of input/

output switching by software.)

Remark

The type numbers are standardized for 78K series, therefore they are not always consecutive numbers

for each product (some circuits are not incorporated).

Note

A voltage outside the range AV

to AV

REF

should not be applied, as this may damage the

PD78217A/78218A.

PD78217A, 78218A

INTERNAL BLOCK FUNCTIONS

3.1

MEMORY SPACE

A memory space of 1 Mbytes can be accessed. Fig. 3-1 shows that memory space. The program memory mapping

differs depending on the EA pin status.

(1)

PD78217A (EA = L)

The program memory is mapped onto external memory (64256 bytes: 00000H to 0FAFFH). This area can also

be used as data memory.

The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion

mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory.

(2)

PD78218A (EA = H)

The program memory is mapped onto internal ROM (32 Kbytes: 00000H to 07FFFH) and external memory (31488

bytes: 08000H to 0FAFFH). The external memory is accessed in the external memory expansion mode. The area

mapped onto the external memory can also be used as data memory.

The data memory is mapped onto internal RAM (1024 bytes: 0FB00H to 0FEFFH). In the 1-Mbyte expansion

mode, external memory (960 Kbytes: 10000H to FFFFFH) is mapped as expanded data memory.

PD78217A, 78218A

Fig. 3-1 Memory Map

Notes 1. Accessed by 1-Mbyte expansion mode. Shaded areas denote internal memory.

2. Accessed by external memory expansion mode.

3. The

PD78217A applies only when EA = L.

FFFFFH

0FFFFH
0FFDFH
0FFD0H
0FF00H

0FEFFH

0FB00H

0FAFFH

00000H

External Memory

(960 Kbytes)

Internal ROM

(32 Kbytes)

10000H

External Memory

(31488 bytes)

Internal RAM

(1024 bytes)

08000H

07FFFH

External Memory

(64256 bytes)

0FEFFH

0FEE0H
0FEDFH

0FB00H

General Register

(32 bytes)

07FFFH

01000H
00FFFH

00800H
007FFH

00080H
0007FH

00040H
0003FH

00000H

Program Area

(28 Kbytes)

CALLF Entry Area

(2 Kbytes)

Program Area

(1920 bytes)

CALLT Table Area

(64 bytes)

Vector Table Area

(64 bytes)

Data Area

(1024 bytes)

Macro Service Control

Word (30 bytes)

0FEC2H

Extended Address

Data Memory

Program Memory/

Data Memory

Program

Memory/

Data

Memory

EA = H

EA = L (ROM-Less Mode)

Normal Address (64 Kbytes)

Data

Memory

Memory Space (1 Mbytes)

Note2

(256 bytes)

00FFFH

Program Memory / Data Memory

Note2

Note1

Special Function Register (SFR)

Note3

PD78217A, 78218A

3.5

A/D CONVERTER

The

PD78217A/78218A incorporate the analog/digital (A/D) converter with 8-channel multiplexed analog input

(AN0 to AN7).

The conversion method used is successive approximation. After the A/D conversion results are generated, they

are held in the 8-bit A/D conversion result register (ADCR), which may allow high-speed and high-precision

conversion (conversion time: Approx. 30

s; at 12-MHz operation).

The following two modes are available for starting A/D conversion:

Hardware start : Starts conversion by trigger input (INTP5)

Software start

: Starts conversion by the A/D converter mode register (ADM) bit setting

The following two modes of operation after starting are available:

Scan mode

: Multiple analog input are selected sequentially and conversion data is obtained from all pins.

Select mode : The analog input is fixed at one pin and a continuous conversion value is obtained.

The above modes and the conversion operation are all stopped by ADM.

If the conversion result is transferred to the ADCR, an interrupt request INTAD is generated, (except in software

start select mode). Therefore, the conversion value can be transferred to memory continuously using macro service

(See section 4.1.3 "Macro Service").

Table 3-3 INTAD Generation Mode

Scan Mode

Select Mode

Hardware start

Software start

PD78217A, 78218A

3.6.1

Asynchronous Serial Interface

The

PD78217A/78218A incorporates UART (Universal Asynchronous Receiver Transmitter) as the asynchronous

serial interface. UART is used to send/receive one byte of data following a start bit.

The UART incorporates a dedicated baud rate generator which can generate a wide range of desired baud rates

and also determine baud rates by scaling the ASCK pin input clocks or 8-bit timer/counter 3 output (TM3 output),

allowing transmission/reception with a variety of baud rates.

If the UART dedicated baud rate generator is used, the MIDI standard baud rate (31.25 kbps) can also be obtained.

Fig. 3-7 Asynchronous Serial Interface (UART) Block Diagram

CLK

: Internal system clock frequency (System Clock Frequency/2)

ASCK

Receive Buffer

Receive Shift

Receive Control

Parity Check

1/16

Internal Bus

Transmit Shift

Transmit Control

Parity Addition

1/16

INTSR

INTSER

INTST

TXS

RXB

Selector

1/N

CLK

1/2

TM3 Output

UART Dedicated Baud Rate Generator

PD78217A, 78218A

3.6.2

Clock Synchronous Serial Interface

The master device starts transmission by activating the serial clock and transfers one-byte data in synchronization

with this clock.

Fig. 3-8 Clock Synchronous Serial Interface Block Diagram

CLK

: Internal System Clock Frequency (System Clock Frequency/2)

(1)

3-wire serial I/O

This is an interface for communicating with devices incorporating a conventional clock synchronous serial

interface.

Basically, communication is performed with three lines, one serial clock line (SCK) and two serial data lines

(SI, SO). When connecting to multiple devices, a handshake line is necessary.

(2)

SBI

Communication with multiple devices is performed with one serial clock line (SCK) and one serial bus line (SB0).

This is NEC's standard serial interface.

The master device selects the slave device to be communicated with by outputting its "address" from the SB0

pin. Therefore, "commands" and "data" perform transfer and receive between the master and slave.

SCK

Shift Register

Internal Bus

INTCSI

SIO

Selector

SO/SB0

Output

Latch

Set Clear

Busy/
Acknowledge
Generator

Selector

Interrupt
Generator

TM3 Output/2

CLK

/32

Bus Release

Command/

Acknowledge

Detector

Serial Clock

Controller

Serial Clock

Counter

N-ch Open-drain output
also possible (SB0: SBI)

PD78217A, 78218A

4.1.1

Interrupt Sources

There are 19 types of interrupt sources and a BRK instruction execution, as shown in Table 4-2.

The priority of the interrupt servicing can be set to 2 levels (high and low priority levels). Therefore, the levels

of nest control when the interrupt is in progress and when interrupt requests occur simultaneously (see Fig. 4-1,

Fig. 4-2) can be separated. Nesting will always take place in the macro service (It won't be put on hold).

The default priority is the priority level (fixed) to service the interrupt requests which occur at the same level

simultaneously (see Fig. 4-2).

Table 4-2 Interrupt Sources

Trigger

Type

Default

Priority

Source

0 (highest)

15 (lowest)

Name

Instruction execution

Pin input edge detection

Pin input edge detection (TM1 capture trigger)

Pin input edge detection (TM2 capture trigger)

Pin input edge detection (TM2 event counter input)

Pin input edge detection (TM0 capture trigger)

TM0 to CR00 match signal generation

TM0 to CR01 match signal generation

TM1 to CR10 match signal generation

TM1 to CR11 match signal generation

TM2 to CR21 match signal generation

Pin input edge detection

TM3 to CR30 match signal generation

Pin input edge detection

A/D converter conversion termination (transfer to ADCR)

TM2 to CR20 match signal generation

ASI receive error generation

ASI receive termination

ASI transmit termination

CSI transfer termination

BRK

NMI

INTP0

INTP1

INTP2

INTP3

INTC00

INTC01

INTC10

INTC11

INTC21

INTP4

INTC30

INTP5

INTAD

INTC20

INTSER

INTSR

INTST

INTCSI

Software

External

Internal

External

Non-

maskable

Maskable

External

Internal

TM0

16-bit timer

TM1 to TM3 :

8-bit timer

ASI

Asynchronous serial interface

CSI

Clock synchronous serial interface

Macro

Service

Internal/

External

PD78217A, 78218A

Fig. 4-1 Servicing Example when an Interrupt Request Occurrence is Issued while an Interrupt is Serviced

Fig. 4-2 Servicing Example of Simultaneous Interrupt Requests

Main Routine

Vectored Interrupt Request a

(Low-Priority Level)

Vectored Interrupt Request e

(High-Priority Level)

Servicing of b

Servicing of c

Servicing of d

Servicing of a

Macro Service
Request b

Vectored
Interrupt
Request c

(High-Priority
Level)

Macro Service
Request d

Servicing of e

Macro Service
Request f

Servicing of f

Macro Service
Request h

Vectored Interrupt Request g (Low-Priority

Level: Pending)

Servicing
of g

Servicing of h

[Nesting 1]

[Nesting 2]

[Nesting 3]

Main Routine

[Nesting 1]

[Nesting 2]

Servicing of b

Servicing of d

Servicing of c

Servicing of a

· Vectored Interrupt Request a

(Low-Priority Level)
· Macro Service Request b
(High-Priority Level)
· Macro Service Request c
(Low-Priority Level)
· Vectored Interrupt Request d

(High-Priority Level)
Default Priority: a > b > c > d

PD78217A, 78218A

4.1.2

Vectored Interrupt

The memory contents of the vector table address, which corresponds to the interrupt source, is branched into

the service routine as a destination address.

As the CPU executes the interrupt servicing, the following operations occur.

When branch :

Saving the CPU status (PC, PSW contents) to the stack.

When return

Returning the CPU status (PC, PSW contents) from the stack.

The RETI instruction executes returning to the main routine from the service routine.

Table 4-3 Vector Table Address

Interrupt Source

INTC21

INTP4

INTC30

INTP5

INTAD

INTC20

INTSER

INTSR

INTST

INTCSI

BRK

NMI

INTP0

INTP1

INTP2

INTP3

INTC00

INTC01

INTC10

INTC11

4.1.3

Macro Service

This is a function to transfer data between the memory and special function registers (SFR) without going through

the CPU. The macro service controller accesses the memory and SFR, and transfers data directly without fetching

it.

High-speed data transfer is enabled because no data is saved, restored or fetched.

Fig. 4-3 Macro Service

003EH

0002H

0006H

0008H

000AH

000CH

0014H

0016H

0018H

001AH

Vector Table

Address

Interrupt Source

Vector Table

Address

001CH

000EH

0010H

0012H

0020H

0022H

0024H

0026H

CPU

Memory

SFR

Macro Service

Controller

Internal Bus

Read

Write

Read

Write

PD78217A, 78218A

4.1.4

Macro Service Application Examples

(1)

Transmit operation of serial interface

Whenever the macro service request INTSR is generated, the receive data is transferred to the memory

from RXB. When the data n (last byte) is transferred to the memory (the receive data storage buffer becomes

empty), the vectored interrupt request INTSR is generated.

Whenever the macro service request INTST is generated, the next transmit data is transferred to TXS from

the memory. When the data n (last byte) is transferred to TXS (the transmit data storage buffer becomes

empty), a vectored interrupt request INTST is generated.

(2)

Receive operation of serial interface

Data n

Data n1

Data 2

Data 1

Transmit Shift Register

Transmission Control

INTST

TXS (SFR)

Internal Bus

Transmit Data Storage Buffer (Memory)

Data n

Data n1

Data 2

Data 1

Internal Bus

Receive Shift Register

Receive Control

INTSR

RXB (SFR)

Receive Buffer

Receive Data Storage Buffer (Memory)

PD78217A, 78218A

(3)

Real-time output port

The INTC10 and INTC11 become output triggers of the real-time output port. In the macro service for them, the

next output pattern and interval can be set simultaneously. Therefore, the INTC10 and INTC11 can control 2

system stepping motor independently. Also, they can be applied to control a PWM or DC motor, etc.

Whenever the macro service request INTC10 is generated, the pattern and timing are transferred to P0L and

CR10, respectively. When the contents of the TM1 match with the contents of the CR10, the next INTC10 is

generated and the contents of the P0L are sent to the output latch. If T

(last byte) is sent to CR10, a vectored

interrupt request INTC10 is generated.

The same operation is available for INTC11 (differences: CR10

CR11, P0L

P0H, P00-P03

P04-P07).

(SFR)

INTC10

Match

n-1

P0L

Internal Bus

Output Latch

Output Pattern Profile (Memory)

n-1

CR10

Internal Bus

TM1

Output Timing Profile (Memory)

(SFR)

P00-P03

PD78217A, 78218A

4.2.1

Memory Expansion

The following modes have been prepared as a memory expansion function.

External memory expansion mode

: Expands the program memory and data memory to 31488 bytes (64256

bytes for the

PD78217A) externally. However, this area can be used

unconditionally under the ROM-less mode (EA = L).

1-Mbyte expansion mode

: Expands the data memory by 960 Kbytes and become a 1-Mbyte

memory space.

4.2.2

Programmable Wait

A wait can be independently inserted to the memory mapped on both a normal address (00000H to 0FFFFH) and

an expanded address (10000H to FFFFFH). Therefore, the efficiency of the entire system is not decreased.

4.2.3

Pseudo-Static RAM Refresh Function

The refresh operations are as follows.

Pulse refresh

Outputs the refresh pulse to REFRQ pin in synchronization with a bus cycle.

Power-down self refresh :

Outputs a low-level to the REFRQ pin in the standby mode and holds the contents

of the pseudo-static RAM.

4.2

LOCAL BUS INTERFACE

The

PD78217A/78218A can be connected to an external memory and I/O (memory mapped I/O), and supports

the 1M-byte memory space (see Fig.3-1).

Fig. 4-4 Local Bus Interface Example

PD78218A

Latch

A16-A19

REFRQ

AD0-AD7

ASTB

A8-A15

Decoder

Pseudo SRAM

PROM

PD27C256A

PD24C1000

Data Bus

Address Bus

Gate Array
I/O Expansion
Centronics I/F, etc.

Kanji-Character
Generator

PD78217A, 78218A

4.3

STANDBY

This is a function to reduce the power consumption of the chip. The following modes are available.

HALT mode : Stops the operation clock of the CPU. The average power consumption is reduced by switching

from normal mode to HALT mode and vice-versa.

STOP mode : Stops the oscillator. This stops all operation in the chip and enables minute power consumption

consisting only of leakage current.

These modes are programmable.

The macro service is started from the HALT mode.

Fig. 4-5 Standby Status Flow

Notes 1. In case a vectored interrupt request is a low-priority level (status to disable interrupt of a low-priority

sequence under the HALT setting).

2. In case a vectored interrupt request is a high-priority level or in case of the status to enable interrupt of

a low-priority sequence under the HALT setting.

3. In case a macro service is a high-priority level (status to disable interrupt of a low-priority sequence under

the HALT setting).

4. In case a macro service is a high-priority level or in case of the status to enable interrupt of a low-priority

sequence under the HALT setting.

HALT Set

RESET Input NMI Input

Vectored Interrupt Request

Program

Operation

HALT

(Standby)

STOP

(Standby)

Macro

Service

STOP Set

RESET Input

NMI Input

Macro Service Request

1-Byte Transfer

Termination

Data Transfer

Interrupt Request
at Interrupt Disable

Macro Service Request

1-Byte Transfer

Termination

Data Transfer

Vectored Interrupt Request

Note 2

Note 3

Note 4

Note 1

PD78217A, 78218A

Set the RESET signal active in the reset operation at power-on until the oscillation stabilization time (approx. 40

ms) elapses.

Fig. 4-7 Reset Operation at Power-On

4.4

RESET

When a low level is input to the RESET pin, the internal hardware is initialized (reset state).

When the RESET input changes from low level to high level, the following data is set in the program counter (PC).

Lower 8 bits of PC :

Contents of 0000H address

Upper 8 bits of PC :

Contents of 0001H address

The contents of the PC set the destination address and the program starts to be executed from the address.

Therefore, it can start from any address by reset start.

Please set the program for the contents of each register as required.

A noise eliminator has been incorporated in the RESET input circuit to prevent any error from noise. This noise

eliminator is a sampling circuit based on analog delay.

Fig. 4-6 Reset Acknowledge

Delay

Reset Start

Delay

Reset End

PC Initialization

Instruction Execution
of Reset Start Address

RESET
(Input)

Internal
Reset Signal

RESET
(Input)

Internal
Reset Signal

Oscillation Stabilization Time

Delay

PC Initialization

Instruction Execution of Reset Start Address

Reset End

PD78217A, 78218A

PARAMETER

SYMBOL

TEST CONDITIONS

RATING

UNIT

0.5 to +7.0

REF

0.5 to V

+0.5

0.5 to +0.5

0.5 to V

+0.5

Note

0.5 to AV

REF

+0.5

0.5 to V

+0.5

Per pin

All output pins

100

Per pin

All output pins

40 to +85

stg

65 to +150

Supply voltage

Input voltage

Output voltage

Output current, low

Output current, high

Operating ambient
temperature

Storage temperature

ELECTRICAL SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Note

P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins.

However, V

absolute maximum ratings should also be satisfied.

Caution

Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter

even momentarily. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under conditions

which ensure that the absolute maximum ratings are not exceeded.

CAPACITANCE (T

= 25

C, V

= V

= 0 V)

OPERATING CONDITIONS

Input capacitance

Output capacitance

I/O capacitance

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

CLOCK FREQUENCY

OPERATING AMBIENT TEMPERATURE (T

)

SUPPLY VOLTAGE (V

)

4 MHz

12 MHz

40 to +85

+5 V

10 %

f = 1 MHz

unmeasured pins

returned to 0 V.

PD78217A, 78218A

OSCILLATOR CHARACTERISTICS (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

RESONATOR

Ceramic

resonator

crystal

resonator

External

clock

RECOMMENDED

CIRCUIT

PARAMETER

Oscillator frequency (f

)

X1 input frequency (f

)

X1 input rising/falling time

, t

)

X1 input high/low level width

WXH

, t

WXL

)

UNIT

MHz

MIN.

MAX.

130

Caution

When using the clock oscillator, wiring in the area enclosed with the dotted line should be carried

out as follows to avoid an adverse effect from wiring capacitance.

Wiring should be as short as possible.

Wiring should not cross other signal lines.

Wiring should not be placed close to a varying high current.

The potential of the oscillator capacitor ground should be the same as V

. Do not ground it to

a ground pattern in which a high current flows.

Do not fetch a signal from the oscillator.

HCMOS
Inverter

PD78217A, 78218A

Input voltage, low

Input voltage, high

Output voltage, high

X1 input current, low

X1 input current, high

Input leakage current

Output leakage current

REF

current

Data retention voltage

Pull-up resistor

0.8

IH1

Pins except for Note 1 and Note 2

2.2

IH2

Pin of Note 1

2.2

REF

IH3

Pin of Note 2

0.8 V

OL1

= 2.0 mA

0.45

OL2

= 8.0 mA

Note3

1.0

OH1

= 1.0 mA

1.0

OH2

= 100

0.5

OH3

= 5.0 mA

Note4

2.0

0 V

100

IH3

100

0 V

REF

Operating mode f

= 12 MHz

1.5

5.0

DD1

Operating mode f

= 12 MHz

DD2

HALT mode f

= 12 MHz

DDDR

STOP mode

2.5

5.5

DDDR

= 2.5 V

DDDR

= 5 V

10 %

= 0 V

DC CHARACTERISTICS (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

DDDR

STOP

mode

Output voltage, low

supply current

Data retention current

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Notes 1. P70/AN0 to P75/AN5, P66/WAIT/AN6, P67/REFRQ/AN7 pins are used as A/D converter input pins.

2. X1, X2, RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK, P26/

INTP5, P27/SI, P32/SCK, P33/SO/SB0, EA pins

3. P40/AD0 to P47/AD7, P50/A8 to P57/A15 pins

4. P00 to P07 pins

PD78217A, 78218A

X1 input clock cycle time

CYX

250

Address setup time (to ASTB

)

SAST

Address hold time (from ASTB

)

Note

HSTA

Address hold time (from RD

)

HRA

Address hold time (from WR

)

HWA

delay time from address

DAR

129

Address float time (from RD

)

FAR

Data input time from address

DAID

No. of waits = 0

228

Data input time from ASTB

DSTID

No. of waits = 0

181

Data input time from RD

DRID

No. of waits = 0

100

delay time from ASTB

DSTR

Data hold time (from RD

)

HRID

Address active time from RD

DRA

124

ASTB

delay time from RD

DRST

124

RD low-level width

WRL

No. of waits = 0

124

ASTB high-level width

WSTH

delay time from address

DAW

129

Data output time from ASTB

DSTOD

142

Data output time from WR

DWOD

DSTW1

Refreshing disabled

DSTW2

Refreshing enabled

129

Data setup time (to WR

)

SODWR

No. of waits = 0

146

Data setup time (to WR

)

SODWF

Refreshing enabled

Data hold time (from WR

)

Note

HWOD

ASTB

delay time from WR

DWST

Refreshing disabled

No. of waits = 0

Refreshing enabled

No. of waits = 0

WAIT

input time from address

DAWT

146

WAIT

input time from ASTB

DSTWT

AC CHARACTERISTICS (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

READ/WRITE OPERATION (1/2)

delay time from ASTB

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

WR low-level width

WWL1

WWL2

114

Note

The hold time includes the time to hold the V

and V

under the load conditions of C

= 100 pF and

= 2 k

Remarks 1.

The values in the above table are based on "f

= 12 MHz and C

= 100 pF".

For a parameter with a dot (·) in the SYMBOL column, refer to "t

CYX

DEPENDENT BUS TIMING

DEFINITION" as well.

196

PD78217A, 78218A

WAIT hold time from ASTB

HSTWT

No. of external waits = 1

174

WAIT

delay time from ASTB

DSTWTH

No. of external waits = 1

273

WAIT

input time from RD

DRWTL

WAIT hold time from RD

HRWT

No. of external waits = 1

WAIT

delay time from RD

DRWTH

No. of external waits = 1

186

Data input time from WAIT

DWTID

delay time from WAIT

DWTW

154

delay time from WAIT

DWTR

WAIT input time from WR

WAIT hold time

HWWT1

No. of external waits = 1

from WR

HWWT2

No. of external waits = 1

WAIT

delay

DWWTH1

No. of external waits = 1

186

time from WR

DWWTH2

No. of external waits = 1

104

REFRQ

delay time from RD

DRRFQ

154

REFRQ

delay time from WR

DWRFQ

REFRQ low-level width

WRFQL

120

ASTB

delay time from REFRQ

DRFQST

280

READ/WRITE OPERATION (2/2)

(At refresh disabled)

Refresh disabled

Refresh enabled

Refresh disabled

Refresh enabled

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

DWWTL

22 ns

Remarks 1.

The values in the above table are based on "f

= 12 MHz and C

= 100 pF".

For a parameter with a dot (·) in the SYMBOL column, refer to "t

CYX

DEPENDENT BUS TIMING

DEFINITION" as well.

PD78217A, 78218A

Input

External clock

1.0

Serial clock cycle time

CYSK

Internal divided by 16

1.3

Internal divided by 64

5.3

Input

External clock

420

Serial clock low-level width

WSKL

Internal divided by 16

556

Internal divided by 64

2.5

Input

External clock

420

Serial clock high-level width

WSKH

Internal divided by 16

556

Internal divided by 64

2.5

SI, SB0 setup time (to SCK

)

SSSK

150

SI, SB0 hold time (from SCK

)

HSSK

400

CMOS push-pull output

SO/SB0 output delay time

(3-wire serial I/O mode)

(from SCK

)

Open-drain output (SBI mode),

= 1 k

SB0 high hold time (from SCK

)

HSBSK

CYX

SB0 low setup time (to SCK

)

SSBSK

CYX

SB0 low-level width

WSBL

CYX

SB0 high-level width

WSBH

CYX

SERIAL OPERATION

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

Output

SBI mode

DSBSK1

300

DSBSK2

800

Remark

The values in the above table are based on "f

= 12 MHz and C

= 100 pF".

PD78217A, 78218A

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

bit

0.4

0.8

1/2

LSB

CONV

SAMP

REF

+0.3

Resolution

Overall error

Note1

Quantization error

Conversion time

Sampling time

Analog input voltage

Analog input

impedance

Reference voltage

REF

current

REF

3.6

= 12 MHz

1.5

5.0

Note 2

0.2

1.5

OTHER OPERATIONS

NMI low-level width

WNIL

NMI high-level width

WNIH

INTP0 to INTP5 low-level width

WITL

CYX

INTP0 to INTP5 high-level width

WITH

CYX

RESET low-level width

WRSL

RESET high-level width

WRSH

EXTERNAL CLOCK TIMING

X1 input low-level width

WXL

130

X1 input high-level width

WXH

130

X1 input rise time

X1 input fall time

X1 input clock cycle time

CYX

250

A/D CONVERTER CHRACTERISTICS (T

= 40 to +85

C, V

= +5 V

10 %, V

= AV

= 0 V)

82 ns

CYX

< 125 ns

(The FR bit of ADM is to be "0")

125 ns

CYX

< 250 ns

(The FR bit of ADM is to be "1")

82 ns

CYX

< 125 ns

(The FR bit of ADM is to be "0")

125 ns

CYX

< 250 ns

(The FR bit of ADM is to be "1")

1000

IAN

0.3 V

REF

Notes 1.

Quantization error is not included. Represented by the ratio to full-scale value.

When ADM register's CS bit = 0, in STOP mode.

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

4.0 V

REF

= 10 to +70

3.6 V

REF

= 10 to +70

4.0 V

REF

360

CYX

240

CYX

PD78217A, 78218A

PARAMETER

SYMBOL

FORMULA

MIN./MAX.

12 MHz

UNIT

X1 input clock cycle time

CYX

MIN.

Address setup time (to ASTB

)

SAST

CYX

MIN.

delay time from address

DAR

CYX

MIN.

129

Address float time (from RD

)

FAR

CYX

/2 30

MIN.

Data input time from address

DAID

(4 + 2n) t

CYX

100

MAX.

228

Note

Data input time from ASTB

DSTID

(3 + 2n) t

CYX

MAX.

181

Note

Data input time from RD

DRID

(2 + 2n) t

CYX

MAX.

100

Note

delay time from ASTB

DSTR

CYX

MIN.

Address active time from RD

DRA

CYX

MIN.

124

ASTB

delay time from RD

DRST

CYX

MIN.

124

RD low-level width

WRL

(2 + 2n) t

CYX

MIN.

124

Note

ASTB high-level width

WSTH

CYX

MIN.

delay time from address

DAW

CYX

MIN.

129

Data output time from ASTB

DSTOD

CYX

+ 60

MAX.

142

CYX

(Refreshing disabled)

CYX

(Refreshing enabled)

Data setup time (to WR

)

SODWR

(3 + 2n) t

CYX

100

MIN.

146

Note

CYX

(Refreshing enabled)

ASTB

delay time from WR

DWST

CYX

MIN.

(3 + 2n) t

CYX

(Refreshing disabled)

(2 + 2n) t

CYX

(Refreshing enabled)

WAIT

input time from address

DAWT

CYX

100

MAX.

146

WAIT

input time from ASTB

DSTWT

CYX

MAX.

WWL1

MIN.

196

Note

WWL2

MIN.

114

Note

WR low-level width

CYX

DEPENDENT BUS TIMING DEFINITION (1/2)

Data setup time (to WR

)

SODWF

MIN.

delay time from ASTB

DSTW1

MIN.

DSTW2

MIN.

129

Remark

"n" indicates the number of waits.

Note

When n = 0

PD78217A, 78218A

PARAMETER

SYMBOL

FORMULA

MIN./MAX.

12 MHz

UNIT

WAIT hold time from ASTB

HSTWT

2Xt

CYX

+ 10

MIN.

174

Note

WAIT

delay time from ASTB

DSTWTH

2(1 + X)t

CYX

MAX.

273

Note

WAIT

input time from RD

DRWTL

CYX

MAX.

WAIT hold time from RD

HRWT

(2X 1)t

CYX

+ 5

MIN.

Note

WAIT

delay time from RD

DRWTH

(2X + 1)t

CYX

MAX.

186

Note

Data input time from WAIT

DWTID

CYX

MAX.

delay time from WAIT

DWTW

CYX

MIN.

154

delay time from WAIT

DWTR

CYX

MIN.

WAIT input time from WR

WAIT hold time

HWWT1

(2X 1)t

CYX

+ 5

MIN.

Note

from WR

HWWT2

2(X 1)t

CYX

+ 5

MIN.

Note

WAIT

delay

DWWTH1

(2X + 1)t

CYX

MAX.

186

Note

time from WR

DWWTH2

2Xt

CYX

MAX.

104

Note

REFRQ

delay time from RD

DRRFQ

CYX

MIN.

154

REFRQ

delay time from WR

DWRFQ

CYX

MIN.

REFRQ low-level width

WRFQL

CYX

MIN.

120

ASTB

delay time from REFRQ

DRFQST

CYX

MIN.

280

CYX

DEPENDENT BUS TIMING DEFINITION (2/2)

(At refresh disabled)

Refresh disabled

Refresh enabled

Refresh disabled

Refresh enabled

DWWTL

CYX

MAX.

Remarks 1.

X: The number of the external waits (1, 2, ...)

CYX

82 ns (f

= 12 MHz)

"n" indicates the number of waits.

Note

When X = 1

PD78217A, 78218A

RECOMMENDED SOLDERING CONDITIONS

The

PD78217A/78218A should be soldered and mounted under the conditions recommended in the table below.

For detail of recommended soldering conditions, refer to the information document "Semiconductor Device Mounting

Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended below, contact an NEC sales represen-

tative.

Table 8-1 Surface Mounting Type Soldering Conditions

Soldering Method

Soldering Conditions

Infrared ray reflow

IR35-00-2

Package peak temperature: 235

C, Reflow time: 30 seconds or less (at 210

C or

higher), Maximum number of reflow processes: 2 times

(1) After the first reflow process, cool the package down to room temperature , then

start the second reflow process.

(2) After the first reflow process, do not use water to remove residual flux.

Package peak temperature: 215

C, Reflow time: 40 seconds or less (at 200

C or

higher), Maximum number of reflow processes: 2 times

(1) After the first reflow process, cool the package down to room temperature , then

start the second reflow process.

(2) After the first reflow process, do not use water to remove residual flux.

Pin temperature: 300

C or below, Heat time: 3 seconds or less (per each side of

the device)

VPS

Partial heating

VP15-00-2

Caution

Apply only one kind of soldering method to a device, except for partial heating method.

PD78217AGC-AB8/78218AGC-

×××

-AB8 : 64-pin plastic QFP (14 x 14 mm)

Symbol

Table 8-2 Insertion Type Soldering Conditions

Solder temperature: 260

C or below, Flow time: 10 seconds or less

Pin temperature: 300

C or below, Heat time: 3 seconds or less (per pin)

Partial heating

Caution

The wave soldering process must be applied only to pins, and make sure that the package body does

not get jet soldered.

Soldering Method

Soldering Conditions

Wave soldering

(pin only)

PD78217ACW/78218ACW-

×××

: 64-pin plastic shrink DIP (750 mil)

PD78217A, 78218A

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78217A/78218A.

Language Processing Software

RA78K/II

Notes1, 2, 3

CC78K/II

Notes1, 2, 3

CC78K/II-L

Notes1, 2, 3

PROM Writing Tools

PG-1500

PA-78P214CW
PA-78P214GC

PG-1500 controller

Notes

1, 2

Debugging Tools

IE-78240-R-A
IE-78240-R

Note

IE-78200-R-BK

IE-78240-R-EM
IE-78200-R-EM

Note

EP-78210CW

Note

EP-78240CW-R
EP-78210GC

Note

EP-78240GC-R

EV-9200GC-64

SD78K/II

Notes

1, 2

DF78210

Notes

1, 2

Fuzzy Inference Development Support System

FE9000

Note

, FE9200

Note

FT9080

Note

, FT9085

Note

FI78K/II

Notes

1, 2

FD78K/II

Notes

1, 2

78K/II series common assembler package

78K/II series common C compiler package

78K/II series common C compiler library source file

PD78218A subseries common in-circuit emulators

78K/II series common break board

PD78218A subseries evaluation emulation boards

PD78218A subseries common emulation probes

Socket to be mounted on a user system board made for 64-pin plastic QFP

IE-78240-R-A screen debugger

PD78218A subseries device file

Fuzzy knowledge data creation tool

Translator

Fuzzy inference module

Fuzzy inference debugger

PROM programmer

Programmer adapters connected to PG-1500

PG-1500 control program

PD78217A, 78218A

APPENDIX B. RELATED DOCUMENTS

Device Related Documents

Document Name

RA78K Series Assembler Package

RA78K Series Structured Assembler Preprocessor

CC78K Series C Compiler

CC78K Series Library Source File

PG-1500 PROM Programmer

PG-1500 Controller

IE-78240-R-A In-Circuit Emulator

IE-78240-R In-Circuit Emulator

SD78K/II Screen Debugger

MS-DOS Based

SD78K/II Screen Debugger

PC DOS Based

78K/II Series Development Tool Selection Guide

Development Tool Related Documents (User`s Manuals)

Operation

Language

Operation

Language

Document No. (Japanese)

EEU-809

EEU-815

EEU-817

EEU-656

EEU-655

EEU-777

EEU-651

EEU-704

EEU-796

EEU-705

EEU-706

EEU-841

EEU-813

EEU-956

EF-231

Document No. (English)

EEU-1399

EEU-1404

EEU-1402

EEU-1280

EEU-1284

EEU-1335

EEU-1291

EEU-1395

EEU-1322

EEU-1331

EEU-1447

Document Name

PD78218A Subseries User's Manual: Hardware

78K/II Series User's Manual: Instruction

78K/II Series Application Note

78K/II Series Selection Guide

78K/II Series Instruction Table

78K/II Series Instruction Set

PD78218A Series Special Function Register Table

Document No. (English)

IEU-1313

IEU-1311

IEA-1220

IEA-1282

IEA-1273

IF-1160

Document No. (Japanese)

IEU-755

IEU-754

IEA-607

IEA-700

IEA-686

IF-304

IEM-5101

IEM-5102

IEM-5532

Fundamentals

Application

Floating Point Operation Program

Hardware

Software

Introduction

Reference

Introduction

Reference

Caution

The contents of the above related documents are subject to change without notice. The latest documents

should be used for design, etc.

PD78217A, 78218A

Document No. (English)

EEU-1438

EEU-1444

EEU-1440

EEU-1459

Document Name

RX78K/II Real-Time OS

Fuzzy Knowledge Data Creation Tool

78K/0, 78K/II, 87AD Series
Fuzzy Inference Development Support System

78K/II Series
Fuzzy Inference Development Support System

78K/II Series Fuzzy Inference Debugger

Document No. (Japanese)

EEU-910

EEU-884

EEU-895

EEU-885

EEU-829

EEU-862

EEU-860

EEU-917

Basic

Installation

Debugger

Technical

Translator

Fuzzy Inference
Module

Document Name

QTOP Microcomputer Pamphlet

Semiconductor Device Package Manual

Semiconductor Device Mounting Technology Manual

Quality Grades on NEC Semiconductor Devices

NEC Semiconductor Device Reliability & Quality Control System

Electrostatic Discharge (ESD) Test

Guide to Quality Assurance for Semiconductor Devices

Microcomputer-Related Products Guide Third Party Products

Embedded Software Related Documents (User's Manuals)

Other Related Documents

Document No. (English)

IEI-1213

IEI-1207

IEI-1209

MEI-1202

Document No. (Japanese)

IB-5040

IEI-635

IEI-616

IEI-620

IEM-5068

MEM-539

MEI-603

MEI-604

Caution

The contents of the above related documents are subject to change without notice. The latest documents

should be used for design, etc.

PD78217A, 78218A

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused

pins must be judged device by device and related specifications governing the

devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immedi-

ately after power-on for devices having reset function.

PD78217A, 78218A

MS-DOS and Windows are trademarks of Microsoft Corporation.

PC/AT and PC DOS

are trademarks of IBM Corporation.

SPARCstation is a trademark of SPARC International, Inc.

Sun OS

is a trademark of Sun Microsystems, Inc.

HP9000 series 300 and HP-UX are

trademarks of Hewlett-Packard Company.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11

The export of these products from Japan is regulated by the Japanese government. The export of some or all of

these products may be prohibited without governmental license. To export or re-export some or all of these

products from a country other than Japan may also be prohibited without a license from that country. Please call

an NEC sales representative.

License not needed:

PD78217ACW, 78217AGC-AB8

The customer must

judge the need for license:

PD78218ACW-xxx, 78218AGC-xxx-AB8

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Document Outline

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