Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATION EXAMPLES
ORDERING INFORMATION
78K/III Series Product Development
PIN CONFIGURATION (TOP VIEW)
FUNCTIONAL OUTLINE
DIFFERENCES BETWEEN uPD78362A AND uPD78366A
BLOCK DIAGRAM
1. PIN FUNCTIONS
- 1.1 PORT PINS
- 1.2 PINS OTHER THAN PORT PINS
- 1.3 PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS
2. CPU ARCHITECTURE
- 2.1 MEMORY SPACE
- 2.2 DATA MEMORY ADDRESSING
- 2.3 PROCESSOR REGISTERS
  - 2.3.1 Control Registers
  - 2.3.2 General-Purpose Registers
  - 2.3.3 Special Function Registers (SFR)
3. FUNCTIONAL BLOCKS
- 3.1 EXECUTION UNIT (EXU)
- 3.2 BUS CONTROL UNIT (BCU)
- 3.3 ROM/RAM
- 3.4 PORT FUNCTIONS
- 3.5 CLOCK GENERATOR CIRCUIT
- 3.6 REAL-TIME PULSE UNIT (RPU)
- 3.7 REAL-TIME OUTPUT PORT (RTP)
- 3.8 A/D CONVERTER
- 3.9 SERIAL INTERFACE
- 3.10 PWM UNIT
- 3.11 WATCHDOG TIMER (WDT)
4. INTERRUPT FUNCTIONS
- 4.1 OUTLINE
- 4.2 MACRO SERVICE
- 4.3 CONTEXT SWITCHING
  - 4.3.1 Context Switching Function by Interrupt Request
  - 4.3.2 Context Switching Function by BRKCS Instruction
  - 4.3.3 Restoration from Context Switching
5. STANDBY FUNCTIONS
6. RESET FUNCTION
7. INSTRUCTION SET
8. EXAMPLE OF SYSTEM CONFIGURATION
9. ELECTRICAL SPECIFICATIONS
10. PACKAGE DRAWING
11. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. DIFFERENCES BETWEEN uPD78362A AND uPD78328
APPENDIX B. TOOLS
- B.1 DEVELOPMENT TOOLS
- B.2 EMBEDDED SOFTWARE

MOS INTEGRATED CIRCUIT

PD78361A, 78362A

16/8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

PD78362A is provided with a high-speed, high-performance CPU and powerful operation functions. Unlike the

existing

PD78328,

PD78362A is also provided with a high-resolution PWM signal output function which

substantially contributes to improving the performance of the inverter control.

A PROM model,

PD78P364A, is also available.

Detailed functions, etc. are described in the following user's manual. Be sure to read the manual to design

systems.

PD78362A User's Manual Hardware : U10745E

PD78356 User's Manual Instruction

: U12117E

FEATURES

Internal 16-bit architecture, external 8-bit data bus

High-speed processing by pipeline control method and high- speed operating clock

Minimum instruction execution time: 125 ns (internal clock: at 16 MHz, external clock: 8MHz)

Real-time pulse unit for inverter control

10-bit resolution A/D converter: 8 channels

8-/9-/10-/12-bit resolution variable PWM signal output function: 2 channels

Powerful serial interface: 2 channels

Internal memory : ROM

32K bytes (

PD78361A)

24K bytes (

PD78362A)

RAM

2K bytes

(

PD78361A)

768 bytes (

PD78362A)

APPLICATION EXAMPLES

Inverter air conditioner

Factory automation fields, such as industrial robots and machine tools.

ORDERING INFORMATION

Part Number

Package

Internal ROM

PD78361ACW-

×××

64-pin plastic shrink DIP (750 mil)

Mask ROM

PD78362ACW-

×××

64-pin plastic shrink DIP (750 mil)

Mask ROM

Remark

×××

indicates a ROM code suffix.

Unless otherwise specified, the

PD78362A is treated as the representative model throughout this document.

The mark

shows major revised points.

Document No. U10098EJ2V0DS00 (2nd edition)
Date Published August 1997 N
Printed in Japan

1996

DATA SHEET

The information in this document is subject to change without notice.

PD78361A, 78362A

125 ns (internal clock: 16 MHz, external clock: 8 MHz)

32K bytes

24K bytes

2K bytes

768 bytes

64K bytes

8 bits

8 banks

115

· 16-bit transfer/operation
· Multiplication/division (16 bits

16 bits, 32 bits

16 bits)

· Bit manipulation
· String
· Sum-of-products operation (16 bits

16 bits + 32 bits)

· Relative operation

14 (of which 8 are shared with analog input)

· 16-bit timer

10-bit dead time timer

16-bit compare register

2 kinds of output mode can be selected

Mode 0, set-reset output: 6 channels
Mode 1, buffer output: 6 channels

· 16-bit timer

16-bit compare register

· 16-bit timer

16-bit capture register

16-bit capture/compare register

· 16-bit timer

16-bit capture register

16-bit capture/compare register

· 16-bit timer

16-bit compare register

16-bit resolution PWM output: 1 channel

Pulse outputs associated with real-time pulse unit: 4 lines

8-/9-/10-/12-bit resolution variable PWM output: 2 channels

10-bit resolution, 8 channels

Dedicated baud rate generator

UART:

1 channel

Clocked serial interface/SBI: 1 channel

· External: 6, internal: 14 (of which 2 are multiplexed with external)
· 4 priority levels can be specified through software
· 3 types of interrupt service modes selectable

(vectored interrupt, macro service, and context switching)

64-pin plastic shrink DIP (750 mil)

· Watchdog timer
· Standby function (HALT and STOP modes)
· PLL control circuit

FUNCTIONAL OUTLINE

Minimum instruction execution
time

Internal memory

ROM

RAM

Memory space

General-purpose registers

Number of basic instructions

Instruction set

I/O lines

Input

I/O

Real-time pulse unit

Real-time output port

PWM unit

A/D converter

Serial interface

Interrupt function

Package

Others

PD78361A

Item

PD78362A

PD78361A, 78362A

TABLE OF CONTENTS

PIN FUNCTIONS ......................................................................................................................

1.1

PORT PINS ..................................................................................................................................... 10

1.2

PINS OTHER THAN PORT PINS .................................................................................................. 11

1.3

PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS ....................................................... 12

CPU ARCHITECTURE .............................................................................................................

2.1

MEMORY SPACE ........................................................................................................................... 14

2.2

DATA MEMORY ADDRESSING .................................................................................................... 16

2.3

PROCESSOR REGISTERS ........................................................................................................... 18

2.3.1

Control Registers ................................................................................................................. 18

2.3.2

General-Purpose Registers .................................................................................................. 19

2.3.3

Special Function Registers (SFR) ........................................................................................ 20

FUNCTIONAL BLOCKS ...........................................................................................................

3.1

EXECUTION UNIT (EXU) ............................................................................................................... 26

3.2

BUS CONTROL UNIT (BCU) ......................................................................................................... 26

3.3

ROM/RAM ....................................................................................................................................... 26

3.4

PORT FUNCTIONS ........................................................................................................................ 26

3.5

CLOCK GENERATOR CIRCUIT ................................................................................................... 28

3.6

REAL-TIME PULSE UNIT (RPU) .................................................................................................. 30

3.7

REAL-TIME OUTPUT PORT (RTP) .............................................................................................. 37

3.8

A/D CONVERTER .......................................................................................................................... 38

3.9

SERIAL INTERFACE ..................................................................................................................... 39

3.10 PWM UNIT ...................................................................................................................................... 41

3.11 WATCHDOG TIMER (WDT) .......................................................................................................... 42

INTERRUPT FUNCTIONS .......................................................................................................

4.1

OUTLINE ......................................................................................................................................... 43

4.2

MACRO SERVICE .......................................................................................................................... 44

4.3

CONTEXT SWITCHING ................................................................................................................. 47

4.3.1

Context Switching Function by Interrupt Request ................................................................ 47

4.3.2

Context Switching Function by BRKCS Instruction .............................................................. 48

4.3.3

Restoration from Context Switching ..................................................................................... 48

STANDBY FUNCTIONS

...................................................................................................................... 49

RESET FUNCTION ...................................................................................................................

INSTRUCTION SET ..................................................................................................................

EXAMPLE OF SYSTEM CONFIGURATION ...........................................................................

ELECTRICAL SPECIFICATIONS ............................................................................................

10. PACKAGE DRAWING ..............................................................................................................

PD78361A, 78362A

P00-P03

P20

P21

P22

P23

P24/TI

P25

P24/INTP3

P05/PWM1

P06/TO40

P07

P80-P85

P06/TIUD

P70-P77

P30

P31

P34

P33/SB1

P32/SB0

P32/SO

P33/SI

P04

P05/TCUD

Real-time output port that outputs pulses in synchronization with trigger

signal from real-time pulse unit.

Non-maskable interrupt request input.

External interrupt request input.

External count clock input to timer 1.

Count operation selection control signal input to up/down counter (timer

4).

External count clock input to up/down counter (timer 4).

Clear signal input to up/down counter (timer 4).

Pulse output from real-time pulse unit.

Analog input to A/D converter.

Serial data output of asynchronous serial interface.

Serial data input of asynchronous serial interface.

Serial clock input/output of clocked serial interface.

Serial data input of clocked serial interface in 3-line mode.

Serial data output of clocked serial interface in 3-line mode.

Serial data input/output of clocked serial interface in SBI mode.

PWM signal output.

Output

Input

Output

Input

Output

Input

I/O

Input

Ouput

I/O

Output

RTP0-RTP3

NMI

INTP0

INTP1

INTP2

INTP3

INTP4

TCUD

TIUD

TCLRUD

TO00-TO05

TO40

ANI0-ANI7

SCK

SB0

SB1

PWM0

PWM1

1.2

PINS OTHER THAN PORT PINS

Pin name

I/O

Function

Shared by:

MODE

RESET

REF

Input

Control signal input to set operation mode. Connected to V

System reset input

Crystal oscillator connecting pins for system clock. If a clock is externally

supplied, input it to pin X1. Leave pin X2 open.

A/D converter reference voltage input.

A/D converter analog power supply.

A/D converter GND.

Positive power supply

GND

PD78361A, 78362A

Input

: Independently connect to V

or V

through resistor

Output : Open

Connect to V

Input

: Independently connect to V

or V

through resistor

Output : Open

Connect to V

Input

: Independently connect to V

or V

through resistor

Output : Open

Connect to V

1.3

PIN I/O CIRCUITS AND PROCESSING OF UNUSED PINS

Table 1-1 shows the I/O circuit types of the respective pins, and recommended connections of the unused

pins. Figure 1-1 shows the circuits of the respective pins.

Table 1-1. Pin I/O Circuit Type and Recommended Connections of Unused Pins

I/O circuit type

Recommended connections

P00/RTP0-P03/RTP3

P04/PWM0

P05/TCUD/PWM1

P06/TIUD/TO40

P07/TCLRUD

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2

P24/INTP3/TI

P25/INTP4

P30/T

P31/R

P32/SO/SB0

P33/SI/SB1

P34/SCK

P40-P47

P50-P57

P70/ANI0-P77/ANI7

P80/TO00-P85/TO05

P90-P92

MODE

RESET

REF

, AV

5-A

2-A

5-A

8-A

5-A

PD78361A, 78362A

CPU ARCHITECTURE

2.1

MEMORY SPACE

The

PD78362A can access a memory space of 64K bytes. Figure 2-1 and 2-2 show the memory map.

Figure 2-1. Memory Map (

PD78361A)

Caution

For word access (including stack operations) to the main RAM area (FE00H-FEFFH), the

address that specifies the operand must be an even value.

Memory space

(64 K

Data memory

Program memory

Data memory

FEFFH

FFFFH

FF00H

FDFFH

FF00H

F6FFH

F700H

0000H

Special function register

(SFR)

(256

Main RAM

(256

Cannot be used

Internal ROM

(32768

FEFFH

FE80H

FE25H
FE06H

F700H

7FFFH

1000H

0FFFH

0800H

07FFH

0080H

007FH

0040H

003FH

0000H

Program area

CALLT instruction table area

(64

Vector table area

(64

General-purpose

MODE = L

Macro service

control (32

Data area

(768

7FFFH

8000H

CALLF instruction entry area

(2048

Peripheral RAM

(1792

PD78361A, 78362A

2.2

DATA MEMORY ADDRESSING

The

PD78362A is provided with many addressing modes that improve the operability of the memory and

can be used with high-level languages. Especially, an area of addresses FC00H-FFFFH (F700H-FFFFH

in the

PD78361A) to which the data memory is mapped can be addressed in a mode peculiar to the functions

provided in this area, including special function registers (SFR) and general-purpose registers.

Figure 2-3. Data Memory Addressing (

PD78361A)

Caution

For word access (including stack oprations) to the main RAM area (FE00H-FEFFH), the

address that specifies the operand must be an even value.

FF20H
FF1FH

FE20H
FE1FH

F700H
F6FFH

FF00H
FEFFH

FE80H
FE7FH

FE00H
FDFFH

8000H
7FFFH

0000H

Special function

(SFR)

General-purpose

Main RAM

Peripheral RAM

Internal ROM

Cannot be used

SFR addressing

Short direct addressing

Direct addressing
Register indirect addressing
Based addressing
Based indexed addressing
Based indexed addressing
(with displacement)

FFFFH

PD78361A, 78362A

2.3

PROCESSOR REGISTERS

The

PD78362A is provided with the following three types of processor registers:

· Control registers

· General-purpose registers

· Special function registers (SFRs)

2.3.1

Control Registers

(1) Program counter (PC)

This is a 16-bit register that holds an address of the instruction to be executed next.

(2) Program status word (PSW)

This 16-bit register indicates the status of the CPU as a result of instruction execution.

(3) Stack pointer (SP)

This 16-bit register indicates the first address of the stack area (LIFO) of the memory.

Figure 2-5. Configuration of Control Registers

PSW

Figure 2-6. Configuration of PSW

PSW

RBS2

RBS1

RBS0

RSS

P/V

: User flag

RBS0-RBS2: Register bank select flag

: Sign flag (MSB of execution result)

: Zero flag

RSS

: Register set select flag

: Auxiliary carry flag

: Interrupt request enable flag

P/V

: Parity/overflow flag

: Carry flag

PD78361A, 78362A

2.3.2

General-Purpose Registers

The

PD78362A is provided with eight banks of general-purpose registers with one bank consisting of 8

words

16 bits. Figure 2-7 shows the configuration of the general-purpose register banks. The general-purpose

registers are mapped to an area of addresses FE80H-FEFFH. Each of these registers can be used as an 8-

bit register. In addition, two registers can be used as one 16-bit register pair (refer to Figure 2-8 ). These

general-purpose registers facilitate complicated multitask processing.

Figure 2-8. Processing Bits of General-Purpose Registers

Figure 2-7. Configuration of General-Purpose Register Banks

RP0

RP1

RP2

RP3

RP4

RP5

RP6

RP7

Bank 7

Bank 1

Bank 0

RBNK0

RBNK1

RBNK2

RBNK3

RBNK4

RBNK5

RBNK7

RBNK6

R15

R13

R11

R14

R12

R10

RP7

RP6

RP5

RP4

RP3

RP2

RP1

RP0

(FH)

(DH)

(BH)

(9H)

(7H)

(5H)

(3H)

(1H)

(EH)

(CH)

(AH)

(8H)

(6H)

(4H)

(2H)

(0H)

FEFFH

FE80H

8-bit processing

16-bit processing

PD78361A, 78362A

2.3.3

Special Function Registers (SFR)

Special function registers (SFRs) are registers assigned special functions such as mode registers and control

registers for internal peripheral hardware, and are mapped to a 256-byte address space at FF00H through

FFFFH.

Table 2-1 lists the SFRs. The meanings of the symbols in this table are as follows:

Symbol ................................... Indicates the mnemonic symbol for an SFR.

This mnemonic can be coded in the operand field of an instruction.

R/W ........................................ Indicates whether the SFR can be read or written.

R/W : Read/write

: Read only

: Write only

Bit units for manipulation ...... Indicates bit units in which the SFR can be manipulated. The SFRs that

can be manipulated in 16-bit units can be coded as an sfrp operand.

Specify an even address for these SFRs.

The SFRs that can be manipulated in 1-bit units can be coded as the

operand of bit manipulation instructions.

On reset ................................. Indicates the status of the register at RESET input.

Cautions 1. Do not access the addresses in the range FF00H-FFFFH to which no special function

register is allocated. If these addresses are accessed, malfunctio ning may occur.

2. Do not write data to the read-only registers. Otherwise, the internal circuit may not

operate normally.

3. When using read data as byte data, process undefined bit(s) first.

4. TOUT and TXS are write-only registers. Do no read these registers.

5. Bits 0, 1, and 4 of SBIC are write-only bits. When these bits are read, they are always

"0".

PD78361A, 78362A

Table 2-1. List of Special Function Registers (1/5)

Bit units for

manipulation

1 bit

8 bits

16 bits

On reset

Address

Special function register (SFR)

Symbol

R/W

FF00H

FF02H

FF03H

FF04H

FF05H

FF07H

FF08H

FF09H

FF10H

FF11H

FF12H

FF13H

FF14H

FF15H

FF16H

FF17H

FF18H

FF19H

FF1AH

FF1BH

FF1CH

FF1DH

FF1EH

FF1FH

FF20H

FF23H

FF25H

FF28H

FF29H

FF2CH

FF2DH

FF2EH

FF2FH

FF30H

FF31H

FF32H

FF33H

Port 0

Port 2

Port 3

Port 4

Port 5

Port 7

Port 8

Port 9

Compare register 00

Compare register 01

Compare register 02

Compare register 03

Buffer register CM00

Buffer register CM01

Buffer register CM02

Timer register 0

Port 0 mode register

Port 3 mode register

Port 5 mode register

Port 8 mode register

Port 9 mode register

Reload register

Timer unit mode register 0

Timer unit mode register 1

Compare register 10

Timer register 1

R/W

0000H

FFH

×××

1 1111B

FFH

××

11 1111B

×××× ×

111B

Undefined

00H

Undefined

0000H

CM00

CM01

CM02

CM03

BFCM00

BFCM01

BFCM02

TM0

PM0

PM3

PM5

PM8

PM9

DTIME

TUM0

TUM1

CM10

TM1

Undefined

PD78361A, 78362A

Table 2-1. List of Special Function Registers (2/5)

Bit units for

manipulation

1 bit

8 bits

16 bits

On reset

Address

Special function register (SFR)

Symbol

R/W

FF34H

FF35H

FF36H

FF37H

FF38H

FF39H

FF3AH

FF3BH

FF3CH

FF3DH

FF40H

FF43H

FF44H

FF45H

FF48H

FF4EH

FF4FH

FF50H

FF51H

FF52H

FF53H

FF54H

FF55H

FF56H

FF57H

FF58H

FF59H

FF5AH

FF5BH

FF5CH

FF5DH

FF5EH

FF5FH

FF60H

FF61H

FF62H

FF68H

Capture/compare register 20

Capture register 20

Timer register 2

Buffer register CM03

External interrupt mode register 0

External interrupt mode register 1

Port 0 mode control register

Port 3 mode control register

Pull-up resistor option register L

Pull-up resistor option register H

Port 8 mode control register

Sampling control register 0

Sampling control register 1

Capture/compare register 30

Capture register 30

Capture register 31

Timer register 3

Compare register 40

Compare register 41

Timer register 4

Timer control register 4

Timer out register

Real-time output port register

Real-time output port mode register

Port read control register

A/D converter mode register

CC20

CT20

TM2

BFCM03

INTM0

INTM1

PMC0

PMC3

PUOL

PUOH

PMC8

SMPC0

SMPC1

CC30

CT30

CT31

TM3

CM40

CM41

TM4

TMC4

TOUT

RTP

RTPM

PRDC

ADM

R/W

Undefined

0000H

Underfined

00H

×××

0 0000B

00H

××

00 0000B

00H

Undefined

0000H

Undefined

0000H

00H

××

01 0101B

Undefined

00H

PD78361A, 78362A

Table 2-1. List of Special Function Registers (3/5)

Bit units for

manipulation

1 bit

8 bits

16 bits

On reset

Address

Special function register (SFR)

Symbol

R/W

FF70H

FF71H

FF72H

FF73H

FF74H

FF75H

FF76H

FF77H

FF78H

FF79H

FF7AH

FF7BH

FF7CH

FF7DH

FF7EH

FF7FH

FF80H

FF82H

FF84H

FF85H

FF86H

FF88H

FF8AH

FF8CH

FF8EH

FFA0H

FFA1H

FFA2H

FFA3H

Slave buffer register 0

Slave buffer register 1

Slave buffer register 2

Slave buffer register 3

Slave buffer register 4

Slave buffer register 5

Master buffer register 0

Master buffer register 1

Master buffer register 2

Master buffer register 3

Master buffer register 4

Master buffer register 5

Timer control register 0

Timer control register 1

Timer control register 2

Timer control register 3

Clocked serial interface mode register

Serial bus interface control register

Baud rate generator control register

Baud rate generator compare register

Serial I/O shift register

Asynchronous serial interface mode register

Asynchronous serial interface status register

Serial receive buffer: UART

Serial transfer shift register: UART

PWM control register 0

PWM control register 1

PWM register 0L

PWM register 0

SBUF0

SBUF1

SBUF2

SBUF3

SBUF4

SBUF5

MBUF0

MBUF1

MBUF2

MBUF3

MBUF4

MBUF5

TMC0

TMC1

TMC2

TMC3

CSIM

SBIC

BRGC

BRG

SIO

ASIM

ASIS

RXB

TXS

PWMC0

PWMC1

PWM0L

PWM0

Undefined

00H

Undefined

80H

00H

Undefined

00H

Undefined

Note

Bits 7 and 5

: read/write

Bits 6, 3, and 2 : read-only

Bits 4, 1, and 0 : write-only

R/W

Note

R/W

PD78361A, 78362A

Table 2-1. List of Special Function Registers (4/5)

Bit units for

manipulation

1 bit

8 bits

16 bits

On reset

Address

Special function register (SFR)

Symbol

R/W

PWM1L

PWM1

ISPR

IMC

MK0L

MK0

MK0H

ADCR0

ADCR0H

ADCR1

ADCR1H

ADCR2

ADCR2H

ADCR3

ADCR3H

ADCR4

ADCR4H

ADCR5

ADCR5H

ADCR6

ADCR6H

ADCR7

ADCR7H

STBC

Note

WDM

Note

R/W

Undefined

00H

80H

FFH

FFFFH

FFH

Undefined

0000

000B

00H

FFA4H

FFA5H

FFA8H

FFAAH

FFACH

FFADH

FFB0H

FFB1H

FFB2H

FFB3H

FFB4H

FFB5H

FFB6H

FFB7H

FFB8H

FFB9H

FFBAH

FFBBH

FFBCH

FFBDH

FFBEH

FFBFH

FFC0H

FFC2H

PWM register 1L

PWM register 1

In-service priority register

Interrupt mode control register

Interrupt mask register 0L

Interrupt mask register 0

Interrupt mask register 0H

A/D conversion result register 0

A/D conversion result register 0H

A/D conversion result register 1

A/D conversion result register 1H

A/D conversion result register 2

A/D conversion result register 2H

A/D conversion result register 3

A/D conversion result register 3H

A/D conversion result register 4

A/D conversion result register 4H

A/D conversion result register 5

A/D conversion result register 5H

A/D conversion result register 6

A/D conversion result register 6H

A/D conversion result register 7

A/D conversion result register 7H

Standby control register

Watchdog timer mode register

Note

Can be written when a special instruction is executed.

PD78361A, 78362A

Table 2-1. List of Special Function Registers (5/5)

Bit units for

manipulation

1 bit

8 bits

16 bits

On reset

Address

Special function register (SFR)

Symbol

R/W

Note

C0AAH

43H

Memory expansion mode register

Programmable wait control register

Interrupt control register (INTOV3)

Interrupt control register (INTP0/INTCC30)

Interrupt control register (INTP1)

Interrupt control register (INTP2)

Interrupt control register (INTP3/INTCC20)

Interrupt control register (INTP4)

Interrupt control register (INTTM0)

Interrupt control register (INTCM03)

Interrupt control register (INTCM10)

Interrupt control register (INTCM40)

Interrupt control register (INTCM41)

Interrupt control register (INTSER)

Interrupt control register (INTSR)

Interrupt control register (INTST)

Interrupt control register (INTCSI)

Interrupt control register (INTAD)

FFC4H

FFC6H

FFC7H

FFE0H

FFE1H

FFE2H

FFE3H

FFE4H

FFE5H

FFE6H

FFE7H

FFE8H

FFE9H

FFEAH

FFEBH

FFECH

FFEDH

FFEEH

FFEFH

PWC

OVIC3

PIC0

PIC1

PIC2

PIC3

PIC4

TMIC0

CMIC03

CMIC10

CMIC40

CMIC41

SERIC

SRIC

STIC

CSIIC

ADIC

R/W

Note

The value of the MM register on reset differs depending on the product.

PD78361A ···· 20H

PD78362A ···· 60H

PD78361A, 78362A

FUNCTIONAL BLOCKS

3.1

EXECUTION UNIT (EXU)

EXU controls address computation, arithmetic and logical operations, and data transfer through microprogram.

EXU has an internal main RAM. This RAM can be accessed by instructions faster than the peripheral RAM.

3.2

BUS CONTROL UNIT (BCU)

BCU starts necessary bus cycles according to the physical address obtained by the execution unit (EXU).If

EXU does not request start of the bus cycle, an address is generated to prefetch an instruction. The prefetched

op code is stored in an instruction queue.

3.3

ROM/RAM

Internal ROM and RAM capacities differ depending on the product.

The

PD78361A has a 32K-byte ROM and a 1792-byte peripheral RAM.

The

PD78362A has a 24K-byte ROM and a 512-byte peripheral RAM.

3.4

PORT FUNCTIONS

The

PD78362A is provided with the ports shown in Figure 3-1 for various control operations.

The functions of each port are listed in Table 3-1. These ports function not only as digital ports but also as

input/output lines of the internal hardware.

Figure 3-1. Port Configuration

P00

P07

P20

P25

P30

P34

P50

P57

P70-P77

P80

P85

P90

P92

P40-P47

Port 0

Port 2

Port 3

Port 4

Port 5

Port 8

Port 7

Port 9

PD78361A, 78362A

Table 3-1. Functions of Each Port

8-bit I/O port. Can be set in input or

output mode in 1-bit units.

6-bit input port.

5-bit I/O port. Can be set in input or

output in 1-bit units.

8-bit I/O port. Can be set in input or

output mode in 8-bit units.

8-bit I/O port. Can be set in input or

output mode in 1-bit units.

8-bit input port.

6-bit I/O port. Can be set in input or

output mode in 1-bit units.

3-bit I/O port. Can be set in input or

output mode in 1-bit units.

In control mode, serves as real-time output port (RTP), or

input operation control signal of real-time pulse unit (RPU)

and output PWM signal.

Inputs external interrupt and count pulse of real-time pulse

unit (RPU) (fixed to the control mode).

In control mode, inputs/outputs signals of serial interfaces

(UART, CSI).

Input analog signals to A/D converter (fixed to the control

mode).

In control mode, outputs timer of real-time pulse unit (RPU).

Port

Port function

Multiplexed function

Port 0

Port 2

Port 3

Port 4

Port 5

Port 7

Port 8

Port 9

PD78361A, 78362A

3.6

REAL-TIME PULSE UNIT (RPU)

The real-time pulse unit (RPU) can measure pulse intervals and frequencies, and output programmable

pulses (six channels of PWM control signals).

The RPU consists of five 16-bit timers (timers 0 through 4), of which one is provided with a 10-bit dead time

timer, which is ideal for inverter control. In addition, a function to turn off the output by the software or an external

interrupt is also provided.

Each timer has the following features:

Timer 0 : Controls the PWM period of the TO00 through TO05 pins. In addition, operates as a

general-purpose interval timer. Timer 0 has the following five operation modes:

General-purpose interval timer mode

PWM mode 0 (symmetrical triangular wave)

PWM mode 0 (asymmetrical triangular wave)

PWM mode 0 (saw-tooth wave)

PWM mode 1

Timer 1 : Operates as a general-purpose interval timer.

Timers 2 & 3 : Has a programmable input sampling circuit that rejects the noise of an input signal,

and a capture function.

Timer 4 : Operates as a general-purpose timer or an up-down counter. When operating as a general-

purpose timer, controls the PWM cycle of the TO40 output pin. Timer 4 has the following

two operation modes:

General-purpose timer mode

Up/down counter mode (UDC mode)

The RPU consists of the hardware shown in Table 3-2. Figures 3-4 through 3-12 show the block diagrams

of the respective timers.

Table 3-2. Configuration of Real-Time Pulse Unit (RPU)

16-bit compare register (CM00)

16-bit compare register (CM01)

16-bit compare register (CM02)

16-bit compare register (CM03)

INTCM03

16-bit compare register (CM10)

INTCM10

16-bit capture/compare register (CC20)

INTCC20

16-bit capture register (CT20)

16-bit capture/compare register (CC30)

INTCC30

16-bit capture register (CT30)

16-bit capture register (CT31)

16-bit compare register (CM40)

INTCM40

16-bit compare register (CM41)

INTCM41

Timer 0 16-bit timer (TM0)

Timer 1 16-bit timer (TM1)

Timer 2 16-bit timer (TM2)

Timer 3 16-bit timer (TM3)

Timer 4 16-bit timer (TM4)

Compare
register
coincidence
interrupt

Capture
trigger

Timer
output

Timer
clear

INTCM03

INTCM10

INTP3

INTCC20

INTP0

INTP1

INTCC30

INTP4

TCLRUD

INTCM40

Timer register

PD78361A, 78362A

Figure 3-9. Block Diagram of Timer 2

Remark f

CLK

: internal system clock

Figure 3-10. Block Diagram of Timer 3

Remark f

CLK

: internal system clock

4-point sampling

noise rejection

circuit

Timer register TM2

Capture/compare

Capture register CT20

CLK

CLR2

INTP3/INTCC20

INTP3

Clear

4-point sampling

noise rejection

circuit

Timer register TM3

Capture/compare

CLK

CLR3

INTP0/INTCC30

INTP0

4-point sampling

noise rejection

circuit

Capture register CT30

CLK

INTP1

4-point sampling

noise rejection

circuit

CLK

INTP4

INTOV3

Clear

Capture register CT31

PD78361A, 78362A

3.9

SERIAL INTERFACE

The

PD78362A is provided with the following two independent serial interfaces:

Asynchronous serial interface (UART)

Clocked serial interface

· 3-line serial I/O mode

· Serial bus interface mode (SBI mode)

Since the

PD78362A contains a baud rate generator (BRG), any serial transfer rate can be set regardless

of the operating clock frequency. The baud rate generator is a block to generate the shift clock for the transmit/

receive serial interface, and is used commonly with the two channels of the serial interfaces.

The serial transfer rate can be selected in a range of 110 bps to 38.4 Kbps by the mode register.

Figure 3-15. Block Diagram of Asynchronous Serial Interface

RXB

PE FE OVE

RXE PS1 PS0 CL SL SCK

ASIM

TXS

ASIS

INTSR

INTSER

INTST

CLK

Internal bus

Receive

buffer

Receive

shift

Receive

control

parity

check

Transfer

shift

Transfer

control

parity

append

Transfer/
receive
baud rate
generator
output

Selector

PD78361A, 78362A

INTERRUPT FUNCTIONS

4.1

OUTLINE

The

PD78362A is provided with powerful interrupt functions that can service interrupt requests from the

internal hardware peripherals and external sources. In addition, the following three interrupt service modes are

available. In addition, four levels of interrupt priority can be specified.

· Vectored interrupt service

· Macro service

· Context switching

Table 4-1. Interrupt Sources

Note

Interrupt source

Name

Trigger

NMI

NMI pin input

INTWDT

Watchdog timer

INTOV3

Overflow of timer 3

INTP0/INTCC30 INTP0 pin input/CC30 coincidence signal

INTP1

INTP1 pin input

INTP2

INTP2 pin input

INTP3/INTCC20 INTP3 pin input/CC20 coincidence signal

INTP4

INTP4 pin input

INTTM0

Underflow of timer 0

INTCM03

CM03 coincidence signal

INTCM10

CM10 coincidence signal

INTCM40

CM40 coincidence signal

INTCM41

CM41 coincidence signal

INTSER

Receive error of UART

INTSR

End of UART reception

INTST

End of UART transfer

INTCSI

End of CSI transfer/reception

INTAD

End of A/D conversion

BRK

BRK instruction

BRKCS

BRKCS instruction

TRAP

Illegal op code trap

RESET

Reset input

Source unit

External

WDT

RPU

External/RPU

External

External/RPU

External

RPU

UART

CSI

A/D

Vector

table

address

0002H

0004H

0006H

0008H

000AH

000CH

000EH

0010H

0012H

0014H

0016H

0018H

001AH

001CH

001EH

0020H

0022H

0024H

003EH

003CH

0000H

Macro

service

None

Provided

None

Context

switching

None

Provided

None

Provided

None

Type

Non-

maskable

Maskable

Software

Exception

Reset

Note Default priority : Priority that takes precedence when two or more maskable interrupts occur at the

same time. 0 is the highest priority, and 15 is the lowest.

PD78361A, 78362A

4.2

MACRO SERVICE

The

PD78362A has a total of five macro services. Each macro service is described below.

(1) Counter mode: EVTCNT

· Operation

(a) Increments or decrements an 8-bit macro service counter (MSC).

(b) A vectored interrupt request is generated when MSC reaches 0.

· Application example: As event counter, or to measure number of times a value is captured

(2) Block transfer mode: BLKTRS

· Operation

(a) Transfers data block between a buffer and a SFR specified by SFR pointer (SFRP).

(b) The transfer source and destination can be in SFR or buffer area. The length of the transfer data

can be specified to be byte or word.

(d) MSC is auto decremented by one each time the macro service has been executed.

(e) When MSC reaches 0, a vectored interrupt request is generated.

· Application example: To transfer/receive data through serial interface

MSC

+1/1

SFRP

MSC

SFR

Buffer N

Buffer 1

Internal bus

PD78361A, 78362A

(3) Block transfer mode (with memory pointer): BLKTRS-P

· Operation

This is the block transfer mode in (2) above with a memory pointer (MEMP). The appended buffer

area of MEMP can be freely set on the memory space.

Remark

Each time the macro service is executed, MEMP is auto incremented (by one for byte

data transfer and by two for word data transfer).

· Application example: Same as (2)

(4) Data differential mode: DTADIF

· Operation

(a) Calculates the difference between the contents of SFR (current value) specified by SFRP and the

contents of SFR saved to the last data buffer (LDB).

(b) Stores the result of the calculation in a predetermined buffer area.

(d) The number of times the data is to be transferred (block size) is specified by MSC. Each time the

macro service is executed, MSC is auto decremented by one.

(e) When MSC reaches 0, a vector interrupt request is generated.

Remark

The differential calculation can be carried out only with 16-bit SFRs.

· Application example : To measure cycle and pulse width by the capture register of the real-time

pulse unit (RPU)

SFR

LDB

Buffer N

Buffer 1

Differential calculation

Internal bus

SFRP

MSC

SFRP

MSC

SFR

MEMP

+1/+2

Buffer N

Buffer 1

Internal bus

PD78361A, 78362A

4.3

CONTEXT SWITCHING

This function is to select a specific register bank through the hardware, and to branch execution to a vector

address predetermined in the register bank. At the same time, it saves the present contents of the PC and PSW

to the register bank when an interrupt occurs, or when the BRKCS instruction is executed.

4.3.1

Context Switching Function by Interrupt Request

When a context switching enable flag corresponding to each maskable interrupt request is set to 1 in the EI

(interrupt enable) status, the context switching function can be started.

The context switching operation by an interrupt request is performed as follows:

(1) When an interrupt request is generated, a register bank to which the context is to be switched is specified

by the contents of the lower 3 bits of the row address (even address) of the corresponding vector table.

(2) A predetermined vector address is transferred to the PC in the register bank to which the context is to

be switched, and the contents of the PC and PSW immediately before the switching takes place are saved

to the register bank.

(3) Execution branches to an address indicated by the contents of the PC newly set.

Figure 4-1. Operation of Context Switching

PSW

RP0

RP1

RP2

RP3

RP4

RP5

RP6

RP7

Registor Bank

(0-7)

Exchange

Save

PD78361A, 78362A

4.3.2

Context Switching Function by BRKCS Instruction

The context switching function can be started by the BRKCS instruction.

The operation of context switching by an interrupt request is as follows:

(1) An 8-bit register is specified by the operand of the BRKCS instruction, and the register bank to which

the context is to be switched is specified by the contents of this register (only the lower 3 bits of 8 bits are

valid).

(2) The vector address predetermined in the register bank to which the context is to be switched is transferred

to the PC, and at the same time, the contents of the PC and PSW immediately before the switching takes

place are saved to the register bank.

(3) Execution branches to the contents of the PC newly set.

4.3.3

Restoration from Context Switching

To restore from the switched context, one of the following two instructions are used. Which instruction is

to be executed is determined by the source that has started the context switching.

Table 4-2. Instructions to Restore from Context Switching

Restore instruction

Context switching starting source

RETCS

Occurrence of interrupt

RETCSB

Execution of BRKCS instruction

PD78361A, 78362A

RESET FUNCTION

When a low level is input to the RESET pin, the system is reset, and each hardware enters the initial status

(reset status). When the RESET pin goes high, the reset status is released, and program execution is started.

Initialize the contents of each register through program as necessary.

Especially, change the number of cycles of the programmable wait control register as necessary.

The RESET pin is equipped with a noise rejecter circuit of analog delay to prevent malfunctioning due to noise.

Caution While the RESET pin is active (low level), all the pins go into a high-impedance state (except

REF

, AV

, V

, X1, and X2 pins).

Figure 6-1. Accepting Reset Signal

To effect reset on when power is applied, make sure that sufficient time elapses to stabilize the oscillation

after the power is applied until the reset signal is accepted, as shown in Figure 6-2.

Figure 6-2. Reset on Power Application

RESET input

Analog

delay

Analog

delay

Analog

delay

Rejected

as noise

Reset

accepted

Reset

released

RESET

Oscillation

stabilization

time

Analog

delay

Reset

released

PD78361A, 78362A

INSTRUCTION SET

Describe an operand in the operand field of each instruction according to the description method of the

instruction (for details, refer to the Assembler Specifications). Some instructions have two or more

operands. Select one of them. Uppercase characters, +, , #, $, !, [, and ] are keywords and must be

described as is.

Describe an appropriate numeric value or label as immediate data. To describe a label, be sure to

describe #, $, !, [, or ].

Table 7-1. Operand Representation and Description

Description

R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15

R0, R1, R2, R3, R4, R5, R6, R7

C, B

RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7

DE, HL, VP, UP

Special function register symbol (Refer to Table 2-1.)

Special function register symbol (register that can be manipulated in 16-bit units. Refer to Table

2-1.)

RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7

(More than one symbol can be described. However, RP5 can be described only for PUSH and

POP instructions, and PSW can be described only for PUSHU and POPU instructions.)

[DE], [HL], [DE +], [HL +], [DE ], [HL ], [VP], [UP]

; register indirect mode

[DE + A], [HL + A], [DE + B], [HL + B], [VP + DE], [VP + HL]

; based indexed mode

[DE + byte], [HL + byte], [VP + byte], [UP + byte], [SP + byte] ; based mode

word[A], word[B], word[DE], word[HL]

; indexed mode

FE20H-FF1FH immediate data or label

FE20H-FF1EH immediate data (however, bit0 = 0) or label (manipulated in 16-bit units)

0000H-FDFFH immediate data or label; relative addressing

0000H-FDFFH immediate data or label; immediate addressing

(However, up to FFFFH can be described for MOV instruction. Only FE00H-FEFFH can be

described for MOVTBLW instruction.)

800H-FFFH immediate data or label

40H-7EH immediate data (however, bit0 = 0)

Note

or label

16-bit immediate data or label

8-bit immediate data or label

3-bit immediate data or label

3-bit immediate data (0-7)

Representation

rp1

rp2

sfr

sfrp

post

mem

saddr

saddrp

$ addr16

! addr16

addr11

addr5

word

byte

bit

Note Do not access bit0 = 1 (odd address) in word units.

Remarks

rp and rp1 are the same in terms of register name that can be described but are different in code

to be generated.

r, r1, rp, rp1, and post can be described in absolute name (R0-R15, RP0-RP7) and function name

(X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, and UP).

Immediate addressing can address the entire space. Relative addressing can address only a

range of 128 to +127 from the first address of the next instruction.

PD78361A, 78362A

Mnemonic

Operand

Byte

Operation

Flag

AC P/V CY

MOV

XCH

Instructions

8-bit data transfer

r1, #byte

saddr, #byte

sfr

Note

, #byte

r, r1

A, r1

A, saddr

saddr, A

saddr, saddr

A, sfr

sfr, A

A, mem

1-4

mem, A

1-4

A, [saddrp]

[saddrp], A

A, !addr16

!addri16, A

PSWL, #byte

PSWH, #byte

PSWL, A

PSWH, A

A, PSWL

A, PSWH

A, r1

r, r1

A, mem

2-4

A, saddr

A, sfr

A, [saddrp]

saddr, saddr

byte

(saddr)

byte

sfr

byte

(saddr)

sfr

(mem)

((saddrp))

(addr16)

PSW

byte

PSW

byte

PSW

(mem)

(saddr)

sfr

((saddrp))

(saddr)

Note When STBC or WDM is described as sfr, this instruction is treated as a dedicated instruction whose

number of bytes is different from that of this instruction.

Remark

For symbols in flag, refer to the table below.

Symbol

Remarks

(Blank)

No change

Cleared to 0

Set to 1

Set/cleared according to result

P/V flag functions as parity flag

P/V flag operates as overflow flag

Value previously saved is restored

PD78361A, 78362A

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

16-bit data transfer

8-bit operation

rp1, #word

saddrp, #word

sfrp, #word

rp, rp1

AX, saddrp

saddrp, AX

saddrp, saddrp

AX, sfrp

sfrp, AX

rp1, !addr16

!addr16, rp1

AX, mem

2-4

mem, AX

2-4

AX, saddrp

AX, sfrp

saddrp, saddrp

rp, rp1

AX, mem

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

rp1

word

(saddrp)

word

sfrp

word

rp1

(saddrp)

sfrp

rp1

(addr16)

rp1

(mem)

(saddrp)

sfrp

(saddrp)

rp1

(mem)

A, CY

A + byte

(saddr), CY

(saddr) + byte

sfr, CY

sfr + byte

r, CY

r + r1

A, CY

A + (saddr)

A, CY

A + sfr

(saddr), CY

(saddr) + (saddr)

A, CY

A + (mem)

(mem), CY

(mem) + A

A, CY

A + byte + CY

(saddr), CY

(saddr) + byte + CY

sfr, CY

sfr + byte + CY

r, CY

r + r1 + CY

A, CY

A + (saddr) + CY

A, CY

A + sfr + CY

(saddr), CY

(saddr) + (saddr) + CY

A, CY

A + (mem) + CY

(mem), CY

(mem) + A + CY

MOVW

XCHW

ADD

ADDC

PD78361A, 78362A

Flag

AC P/V CY

A, CY

A byte

(saddr), CY

(saddr) byte

sfr, CY

sfr byte

r, CY

r r1

A, CY

A (saddr)

A, CY

A sfr

(saddr), CY

(saddr) (saddr)

A, CY

A (mem)

(mem), CY

(mem) A

A, CY

A byte CY

(saddr), CY

(saddr) byte CY

sfr, CY

sfr byte CY

r, CY

r r1 CY

A, CY

A (saddr) CY

A, CY

A sfr CY

(saddr), CY

(saddr) (saddr) CY

A, CY

A (mem) CY

(mem), CY

(mem) A CY

byte

(saddr)

byte

sfr

byte

(saddr)

sfr

(saddr)

(mem)

Mnemonic

Operand

Byte

Operation

Instructions

SUB

SUBC

AND

8-bit operation

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

PD78361A, 78362A

Flag

AC P/V CY

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

A, #byte

saddr, #byte

sfr, #byte

r, r1

A, saddr

A, sfr

saddr, saddr

A, mem

2-4

mem, A

2-4

byte

(saddr)

byte

sfr

byte

(saddr)

sfr

(saddr)

(mem)

byte

(saddr)

byte

sfr

byte

(saddr)

sfr

(saddr)

(mem)

A byte

(saddr) byte

sfr byte

r r1

A (saddr)

A sfr

(saddr) (saddr)

A (mem)

(mem) A

Mnemonic

Operand

Byte

Operation

Instructions

XOR

CMP

8-bit operation

PD78361A, 78362A

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

Multiplication

/division

Relative

operation

Signed

multipli-

cation

Sum-of-

products

operation

Sum-of-products

operation with

saturation

ADDW

SUBW

CMPW

MULU

DIVUW

MULUW

DIVUX

MULW

MACW

MACSW

SACW

AX, #word

saddrp, #word

sfrp, #word

rp, rp1

AX, saddrp

AX, sfrp

saddrp, saddrp

AX, #word

saddrp, #word

sfrp, #word

rp, rp1

AX, saddrp

AX, sfrp

saddrp, saddrp

AX, #word

saddrp, #word

sfrp, #word

rp, rp1

AX, saddrp

AX, sfrp

saddrp, saddrp

rp1

[DE + ], [HL + ]

AX, CY

AX + word

(saddrp), CY

(saddrp) + word

sfrp, CY

sfrp + word

rp, CY

rp + rp1

AX, CY

AX + (saddrp)

AX, CY

AX + sfrp

(saddrp), CY

(saddrp) + (saddrp)

AX, CY

AX word

(saddrp), CY

(saddrp) word

sfrp, CY

sfrp word

rp, CY

rp rp1

AX, CY

AX (saddrp)

AX, CY

AX sfrp

(saddrp), CY

(saddrp) (saddrp)

AX word

(saddrp) word

sfrp word

rp rp1

AX (saddrp)

AX sfrp

(saddrp) (saddrp)

AX (quotient), r1 (remainder)

AX (higher 16 bits), rp1 (lower 16 bits)

rp1

AXDE (quotient), rp1 (remainder)

AXDE

rp1

AX (higher 16 bits), rp1 (lower 16 bits)

rp1

AXDE

(B)

B + 2, C

C + 2, n

n 1

End if n = 0 or P/V = 1

AXDE

(B)

B + 2, C

C + 2, n

n 1

if overflow (P/V = 1) then
AXDE

7FFFFFFFH

if underflow (P/V = 1) then
AXDE

80000000H

end if n = 0 or P/V = 1

AX + | (DE) (HL) |

DE + 2 HL

HL + 2 C

C 1

end if C = 0 or cy = 1

16-bit operation

PD78361A, 78362A

saddr

rp2

saddrp

rp2

saddrp

r1, n

rp1, n

[rp1]

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

MOVTBLW

INC

DEC

INCW

DECW

ROR

ROL

RORC

ROLC

SHR

SHL

SHRW

SHLW

ROR4

ROL4

ADJBA

ADJBS

CVTBW

(addr16 + 2)

(addr16), n

n-1

addr16

addr16-2, End if n = 0

r1 + 1

(saddr)

(saddr) + 1

r1 1

(saddr)

(saddr) 1

rp2

rp2 + 1

(saddrp)

(saddrp) + 1

rp2

rp2 1

(saddrp)

(saddrp) 1

(CY, r1

m 1

)

n times

(CY, r1

m + 1

)

n times

(CY

CY, r1

)

n times

(CY

CY, r1

m + 1

)

n times

(CY

0, r1

m 1

)

n times

(CY

0, r1

m + 1

)

n times

(CY

rp1

0, rp1

m 1

rp1

)

n times

(CY

rp1

0, rp1

m+ 1

rp1

)

n times

3 0

(rp1)

3 0

(rp1)

7 4

3 0

(rp1)

3 0

(rp1)

7 4

3 0

(rp1)

7 4

(rp1)

3 0

(rp1)

7 4

(rp1)

3 0

Decimal Adjust Accumelator

When A

= 0, X

A, A

00H

When A

= 1, X

A, A

FFH

Table

shift

Increment/decrement

BCD

adjustment

Data

conversion

Shift rotate

!addr16, n

Remarks

n of the shift rotate instruction indicates the number of times the shift rotate instruction is

executed.

The address of the table shift instruction ranges from FE00H to FEFFH.

PD78361A, 78362A

Mnemonic

Operand

Byte

Operation

Flag

AC P/V CY

Instructions

CY, saddr.bit

CY, sfr.bit

CY, A.bit

CY, X.bit

CY, PSWH.bit

CY, PSWL.bit

saddr.bit, CY

sfr.bit, CY

A.bit, CY

X.bit, CY

PSWH.bit, CY

PSWL.bit, CY

CY, saddr.bit

CY, /saddr.bit

CY, sfr.bit

CY, /sfr.bit

CY, A.bit

CY, /A.bit

CY, X.bit

CY, /X.bit

CY, PSWH.bit

CY, /PSWH.bit

CY, PSWL.bit

CY, /PSWL.bit

CY, saddr.bit

CY, /saddr.bit

CY, sfr.bit

CY, /sfr.bit

CY, A.bit

CY, /A.bit

CY, X.bit

CY, /X.bit

CY, PSWH.bit

CY, /PSWH.bit

CY, PSWL.bit

CY, /PSWL.bit

(saddr.bit)

sfr.bit

A.bit

X.bit

PSW

.bit

PSW

.bit

(saddr.bit)

sfr.bit

A.bit

X.bit

PSW

.bit

PSW

.bit

(saddr.bit)

sfr.bit

A.bit

X.bit

PSW

.bit

PSW

.bit

PSW

.bit

PSW

.bit

(saddr.bit)

sfr.bit

A.bit

X.bit

PSW

.bit

PSW

.bit

PSW

.bit

PSW

.bit

MOV1

AND1

OR1

Bit manipulation

PD78361A, 78362A

Mnemonic

Operand

Byte

Operation

Flag

AC P/V CY

Instructions

(SP 1)

(PC + 3)

(SP 2)

(PC + 3)

addr16, SP

SP 2

(SP 1)

(PC + 2)

(SP 2)

(PC + 2)

15 11

00001, PC

10 0

addr11, SP

SP 2

(SP 1)

(PC + 1)

(SP 2)

(PC + 1)

(TPF, 00000000, addr5 + 1),

(TPF, 00000000, addr5 ), SP

SP 2

(SP 1)

(PC + 2)

(SP 2)

(PC + 2)

rp1

SP 2

(SP 1)

(PC + 2)

(SP 2)

(PC + 2)

(rp1 + 1), PC

(rp1), SP

SP 2

(SP 1)

PSW

(SP 2)

PSW

(SP 3)

(PC + 1)

(SP 4)

(PC + 1)

(003EH), PC

(003FH), SP

4, IE

(SP), PC

(SP + 1), SP

SP + 2

(SP), PC

(SP +1)

PSW

(SP + 2), PSW

(SP + 3)

SP + 4

(SP), PC

(SP + 1)

PSW

(SP + 2), PSW

(SP + 3)

SP + 4

(SP 1)

sfr

(SP 2)

sfr

SP 2

{(SP 1)

post

(SP 2)

post

n times

(SP 1)

PSW

(SP 2)

PSW

SP 2

{(UP 1)

post

(UP 2)

post

n times

sfr

(SP)

sfr

(SP + 1)

SP + 2

{post

(SP), post

(SP + 1), SP

SP + 2}

n times

PSW

(SP), PSW

(SP + 1), SP

SP + 2

{post

(UP), post

(UP + 1), UP

UP +

n times

word

SP + 1

SP 1

Stack manipulation

Call/return

!addr16

!addr11

[addr5]

rp1

[rp1]

sfrp

post

PSW

post

sfrp

post

PSW

post

SP, #word

SP, AX

AX, SP

CALL

CALLF

CALLT

CALL

BRK

RET

RETB

RETI

PUSH

PUSHU

POP

POPU

MOVW

INCW

DECW

Remark

n of the stack manipulation instruction is the number of registers described as post.

PD78361A, 78362A

(pin level)

(signal level before output buffer)

(pin level)

(signal level before output buffer)

addr16

rp1

(rp1 + 1), PC

(rp1)

PC + 2 + jdisp8

PC + 2 + jdisp8 if CY = 1

PC + 2 + jdisp8 if CY = 0

PC + 2 + jdisp8 if Z = 1

PC + 2 + jdisp8 if Z = 0

PC + 2 + jdisp8 if P/V = 1

PC + 2 + jdisp8 if P/V = 0

PC + 2 + jdisp8 if S = 1

PC + 2 + jdisp8 if S = 0

PC + 3 + jdisp8 if (P/V

S) / Z = 0

PC + 3 + jdisp8 if P/V

S= 0

PC + 3 + jdisp8 if P/V

S = 1

PC + 3 + jdisp8 if (P/V

S) / Z = 1

PC + 3 + jdisp8 if Z

CY = 0

PC + 3 + jdisp8 if Z

CY = 1

PC + 3 + jdisp8 if (saddr.bit) = 1

PC + 4 + jdisp8 if sfr.bit = 1

PC + 3 + jdisp8 if A.bit = 1

PC + 3 + jdisp8 if X.bit = 1

PC + 3 + jdisp8 if PSW

.bit = 1

PC + 3 + jdisp8 if PSW

.bit = 1

PC + 4 + jdisp8 if (saddr.bit) = 0

PC + 4 + jdisp8 if sfr.bit = 0

PC + 3 + jdisp8 if A.bit = 0

PC + 3 + jdisp8 if X.bit = 0

PC + 3 + jdisp8 if PSW

.bit = 0

PC + 3 + jdisp8 if PSW

.bit = 0

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

Special

Unconditional

branch

Conditional branch

CHKL

CHKLA

BNC

BNL

BNZ

BNE

BPE

BNV

BPO

BGT

BGE

BLT

BLE

BNH

sfr

!addr16

rp1

[rp1]

$addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

PD78361A, 78362A

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

BTCLR

BFSET

DBNZ

BRKCS

RETCS

RETCSB

Context switching

Conditional branch

PC + 4 + jdisp8 if (saddr.bit) = 1

then reset (saddr.bit)

PC + 4 + jdisp8 if sfr.bit = 1

then reset sfr.bit

PC + 3 + jdisp8 if A.bit = 1

then reset A.bit

PC + 3 + jdisp8 if X.bit = 1

then reset X.bit

PC + 3 + jdisp8 if PSW

.bit = 1

then reset PSW

.bit

PC + 3 + jdisp8 if PSW

.bit = 1

then reset PSW

.bit

PC + 4 + jdisp8 if (saddr.bit) = 0

then set (saddr.bit)

PC + 4 + jdisp8 if sfr.bit = 0

then set sfr.bit

PC + 3 + jdisp8 if A.bit = 0

then set A.bit

PC + 3 + jdisp8 if X.bit = 0

then set X.bit

PC + 3 + jdisp8 if PSW

.bit = 0

then set PSW

.bit

PC + 3 + jdisp8 if PSW

.bit = 0

then set PSW

.bit

r2 1,

then PC

PC + 2 + jdisp8 if 2

(saddr)

(saddr) 1,

then PC

PC + 3 + jdisp8 if (saddr)

R5, PC

R4, R7

PSW

RBS2 0

n, RSS

0, IE

R5, PC

R4, R5, R4

addr16

PSW

R7, PSW

R5, PC

R4, R5, R4

addr16

PSW

R7, PSW

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

saddr.bit, $addr16

sfr.bit, $addr16

A.bit, $addr16

X.bit, $addr16

PSWH.bit, $addr16

PSWL.bit, $addr16

r2, $addr16

saddr, $addr16

RBn

!addr16

PD78361A, 78362A

Flag

AC P/V CY

Mnemonic

Operand

Byte

Operation

Instructions

[DE + ], A

[DE ], A

[DE + ], [HL + ]

[DE ], [HL ]

[DE + ], A

[DE ], A

[DE + ], [HL + ]

[DE ], [HL ]

[DE + ], A

[DE ], A

[DE + ], [HL + ]

[DE ], [HL ]

[DE + ], A

[DE ], A

[DE + ], [HL + ]

[DE ], [HL ]

[DE + ], A

[DE ], A

[DE + ], [HL + ]

[DE ], [HL ]

(DE + )

A, C

C 1

End if C = 0

(DE )

A, C

C 1

End if C = 0

(DE + )

(HL + ), C

C 1

End if C = 0

(DE )

(HL ), C

C 1

End if C = 0

(DE + )

A, C

C 1

End if C = 0

(DE )

A, C

C 1

End if C = 0

(DE + )

(HL + ), C

C 1

End if C = 0

(DE )

(HL ), C

C 1

End if C = 0

(DE + ) A, C

C 1

End if C = 0 or Z = 0

(DE ) A, C

C 1

End if C = 0 or Z = 0

(DE + ) (HL + ), C

C 1

End if C = 0 or Z = 0

(DE ) (HL ), C

C 1

End if C = 0 or Z = 0

(DE + ) A, C

C 1

End if C = 0 or Z = 1

(DE ) A, C

C 1

End if C = 0 or Z = 1

(DE + ) (HL + ), C

C 1

End if C = 0 or Z = 1

(DE ) (HL ), C

C 1

End if C = 0 or Z = 1

(DE + ) A, C

C 1

End if C = 0 or CY = 0

(DE ) A, C

C 1

End if C = 0 or CY = 0

(DE + ) (HL + ), C

C 1

End if C = 0 or CY = 0

(DE ) (HL ), C

C 1

End if C = 0 or CY = 0

String

MOVM

MOVBK

XCHM

XCHBK

CMPME

CMPBKE

CMPMNE

CMPBKNE

CMPMC

CMPBKC

PD78361A, 78362A

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25 °C)

Parameter

Symbol

Test conditions

Rating

Unit

Power supply voltage

0.5 to +7.0

0.5 to V

+ 0.5

0.5 to +0.5

Input voltage

Pins other than

0.5 to V

+ 0.5

P70/ANI0-P77/ANI7

Output voltage

0.5 to V

+ 0.5

Low-level output current

Note

Output pins other than

4.0

those in the note

Total of all output pins

200

High-level output current

All output pins

3.0

Total of all output pins

Analog input voltage

IAN

P70/ANI0-P77/ANI7 pins

0.5 to AV

+ 0.5

A/D converter reference input voltage

REF

0.5 to AV

+ 0.5

Operating ambient temperature

40 to +85

° C

Storage temperature

stg

60 to +150

° C

Note P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40, P07/TCLRUD, and P80/TO00-

P85/TO05 pins.

Caution Product quality may suffer if the absolute rating is exceeded for any parameter, even momentarily.

In other words, an absolute maxumum rating is a value at which the possibility of psysical

damage to the product cannnot be ruled out. Care must therefore be taken to ensure that the

these ratings are not exceeded during use of the product.

Recommended Operating Conditions

Oscillation frequency

3 MHz

8 MHz

40 to +85 °C

+5.0 V

10 %

Capacitance (T

= 25 °C, V

= V

= 0 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

0 V except measured pins

I/O capacitance

PD78361A, 78362A

Oscillator Characteristics (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V)

Resonator

Recommended circuit

Parameter

MIN.

MAX.

Unit

Ceramic resonator or

Oscillation frequency (f

)

MHz

crystal resonator

External clock

X1 input frequency (f

)

MHz

X1 rise/fall time (t

, t

)

X1 input high-/low-level

170

width (t

WXH

, t

WXL

)

Caution When using system clock oscillation circuits, to reduce the effect of the wiring

capacitouce, etc, wire the area indicated by dotted-line as follows:

Make the wiring as short as possible.

Do not allow the wiring to intersect other signal lines. Keep it away from other lines in which

varying high currents flow.

Make sure that the ground point of the oscillation circuit capacitor is always at the same

electric potential as V

. Do not allow the wiring to be grounded to a ground pattern in which

very high currents are flowing.

Do not extract signals from the oscillation circuit.

Leave unconnected

HCMOS
inverter

PD78361A, 78362A

DC Characteristics (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Low-level input voltage

IL1

Note 1

0.8

IL2

Note 2

0.2V

High-level input voltage

IH1

Note 1

2.2

IH2

Note 2

0.8V

Low-level output voltage

OL1

Note 3

= 2.0 mA

0.45

OL2

Note 4

= 15 mA

1.5

OL3

Note 5

= 10 mA

1.5

High-level output voltage

= 400

1.0

Input leakage current

0 V

, AV

= V

Output leakage current

0 V

, AV

= V

supply current

DD1

Operating mode

120

DD2

HALT mode

Data retention voltage

DDDR

STOP mode

2.5

Data retention current

DDDR

STOP mode

DDDR

= 2.5 V

DDDR

= 5.0 V

10 %

Pull-up resistance

= 0 V

150

Notes 1. Pins other than those specified in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3/TI, P25/INTP4, P32/

SO/SB0, P33/SI/SB1 and P34/SCK pins.

3. Pins other than those specified in Notes 4 and 5.

4. P80/TO00-P85/TO05 pins (When I

= 15 mA is in operation, up to three pins can be ON

simultaneously.)

5. P00/RTP0-P03/RTP3, P04/PWM0, P05/TCUD/PWM1, P06/TIUD/TO40 and P07/TCLRUD pins

(When I

= 10 mA is in operation, up to four pins can be ON simultaneously.) .

Caution When the P80-P85, and P00-P07 pins are not used under the conditions specified in Notes

4 and 5, they have the same characteristics as in Note 3.

PD78361A, 78362A

AC Characteristics (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V, C

= 100 pF, f

= 8 MHz)

System Clock Cycle

Parameter

Symbol

Test conditions

MIN.

MAX.

Unit

System clock cycle time

CYK

62.5

166.7

Serial Operation (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Test conditions

MIN.

MAX.

Unit

Serial clock cycle time

CYSK

SCK output

Internal 8 dividing

500

SCK input

External clock

500

Serial clock low-level

WSKL

SCK output

Internal 8 dividing

210

width

SCK input

External clock

210

Serial clock high-level

WSKH

SCK output

Internal 8 dividing

210

width

SCK input

External clock

210

SI setup time (vs. SCK

)

SRXSK

SI hold time (vs. SCK

)

HSKRX

SCK

SO delay time

DSKTX

R = 1 k

, C = 100 pF

210

Up/Down Counter Operation (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Test conditions

MIN.

MAX.

Unit

TIUD high-/low-level

WTIUH

, t

WTIUL

Other than mode 4

width

Mode 4

TCUD high-/low-level

WTCUH

, t

WTCUL

Other than mode 4

width

Mode 4

TCLRUD high-/low-level width t

WCLUH

, t

WCLUL

TCUD setup time (vs. TIUD

)

STCU

Mode 3

TCUD hold time (vs. TIUD

)

HTCU

Mode 3

TIUD setup time (vs. TCUD)

S4TIU

Mode 4

TIUD hold time (vs. TCUD)

H4TIU

Mode 4

TIUD & TCUD cycle time

CYC

Other than mode 4

MHz

CYC4

Mode 4

MHz

Remark T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency.)

PD78361A, 78362A

Other Operations (T

= 40 to +85 °C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Test conditions

MIN.

MAX.

Unit

NMI high-/low-level width t

WNIH

, t

WNIL

RESET high-/low-level width t

WRSH

, t

WRSL

1.5

INTP0 high-/low-level

WI0H

, t

WI0L

Ts = T

250

width

Ts = 4T

1.0

Ts = 8T

2.0

Ts = 16T

4.0

INTP1 high-/low-level

WI1H

, t

WI1L

Ts = T

250

width

Ts = 4T

1.0

Ts = 8T

2.0

Ts = 16T

4.0

INTP2 high-/low-level

WI2H

, t

WI2L

Ts = T

250

width

Ts = 4T

1.0

INTP3(TI) high-/low-

WI3H

, t

WI3L

Ts = T

250

level width

Ts = 4T

1.0

Ts = 8T

2.0

Ts = 16T

4.0

Ts = 64T

16.0

Ts = 128T

32.0

Ts = 256T

64.0

INTP4 high-/low-level

WI4H

, t

WI4L

Ts = T

250

width

Ts = 4T

1.0

Ts = 8T

2.0

Ts = 16T

4.0

Remarks 1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency.)

2. Ts refers to the input sampling frequency. INTP0-INTP4 can be selected to programmable.

PD78361A, 78362A

A/D Converter Characteristics (T

= 40 to +85 °C, V

= +5 V

10 %, V

= AV

= 0 V,

 0.5 V

)

Parameter

Symbol

Test conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Total error

Note 1

4.5 V

REF

0.4

%FSR

3.4 V

REF

0.7

%FSR

Quantization error

1/2

LSB

Conversion time

CONV

62.5 ns

CYK

< 80 ns

208

CYK

80 ns

CYK

166.6 ns

169

CYK

Sampling time

SAMP

62.5 ns

CYK

< 80 ns

CYK

80 ns

CYK

166.6 ns

CYK

Zero-scale error

Note 1

4.5 V

REF

1.5

2.5

LSB

3.4 V

REF

1.5

4.5

LSB

Full-scale error

Note 1

4.5 V

REF

1.5

2.5

LSB

3.4 V

REF

1.5

4.5

LSB

Nonlinearity error

Note 1

4.5 V

REF

1.5

2.5

LSB

3.4 V

REF

1.5

4.5

LSB

Analog input voltage

Note 2

IAN

0.3

REF

+ 0.3

Analog input impedance

When not sampling

When sampling

Note 3

Reference voltage

REF

3.4

REF

current

REF

1.0

3.0

supply current

Operating mode

2.0

6.0

A/D converter data

DDDR

STOP mode

DDDR

= 2.5 V

retention current

DDDR

= 5 V

10 %

Notes 1. The quantization error is excluded.

2. When 0.3 V

IAN

0 V, the conversion result becomes 000H.

When 0 V < V

IAN

< AV

REF

, the conversion is performed with the 10-bit resolution.

When AV

REF

IAN

+0.3 V, the conversion result becomes 3FFH.

3. The analog input impedance at the time of sampling is the same as the equivalent circuit shown

below. (The values in the diagram are TYP. values; they are not guaranteed values)

Analog input pin

1 k

25 pF
(Input
capacitance
included)

4 pF

PD78361A, 78362A

APPENDIX A. DIFFERENCES BETWEEN

PD78362A AND

PD78328

Product name

Item

125 ns

internal clock : 8 MHz,

external clock : 16 MHz

250 ns

Minimum instruction

execution time

Internal

memory

ROM

RAM

PD78362A

PD78328

24K bytes

16K bytes

768 bytes

512 bytes

8 bits

8 banks

115

111

· 16-bit transfer/operation

· Multiplication/division (16 bits x 16 bits, 32 bits

16 bits)

· Bit manipulation

· String

General-purpose

registers

Number of basic

instructions

Instruction set

internal clock : 16 MHz

external clock : 8 MHz

11 (of which 8 are multiplexed with analog

input)

· 16-bit timer

· 16-bit compare register

· 16-bit capture/compare register

· Two output modes selectable

Mode 0, set-reset output : 6 channels

toggle output

: 1 channel

Mode 1, buffer output

: 8 channels

4/8 (buffer output in 4-/8-bit units)

8-bit resolution PWM output: 1 channel

· Sum-of-products operation

(16 bits

16 bits + 32 bits)

· Relative operation

14 (of which 8 are multiplexed with analog

input)

· 16-bit timer

· 16-bit compare register

· 16-bit capture register

· 16-bit capture/compare register

· Two output modes selectable

Mode 0, set-reset output : 6 channels

Mode 1, buffer output

: 6 channels

· 16-bit resolution PWM output: 1 channel

4 (buffer output in 4-bit units)

8-/9-/10-/12-bit resolution variable PWM

output: 2 channels

10-bit resolution, 8 channels

Dedicated baud rate generator

UART

: 1 channel

Clocked serial interface/SBI : 1 channel

· External: 6, internal: 14 (2 multiplexed

with external)

· 4 programmable priority levels

Real-time pulse unit

Real-time output port

PWM unit

A/D converter

Serial interface

Interrupt function

Test source

External expansion

function

PLL control circuit

Package

Others

Input

I/O

· Three service selectable

(vectored interrupt/macro service/context switching)

I/O lines

None

Internal: 1

None

Provided

Provided (external 8 MHz

internal: 16 MHz)

None

· External: 4, internal: 17

· 3 programmable priority levels

· 64-pin plastic shrink DIP (750 mil)

· 64-pin plastic shrink DIP

· 64-pin plastic QFP (14

20 mm)

· Watchdog timer

· Standby functions (HALT mode, STOP mode)

PD78361A, 78362A

Host machine

Order code (product name)

PC-9800 series

MS-DOS

IBM PC/AT and its

PC DOS

compatible model

HP9000 series 700

HP-UX

SPARC station

SunOS

NEWS

NEWS-OS

Host machine

Order code (product name)

PC-9800 series

MS-DOS

IBM PC/AT

and its

PC DOS

compatible model

HP9000 series 700

HP-UX

SPARCstation

SunOS

NEWS

NEWS-OS

APPENDIX B. TOOLS

B.1 DEVELOPMENT TOOLS

The following development tools are available to support development of

PD78362A program:

LANGUAGE PROCESSOR

Supply media

3.5" 2HD

S5A13RA78K3

5" 2HD

S5A10RA78K3

3.5" 2HC

S7B13RA78K3

5" 2HC

S7B10RA78K3

DAT

S3P16RA78K3

Cartridge tape

S3K15RA78K3

(QIC-24)

S3R15RA78K3

A relocatable assembler, that can be used commonly for the 78K/III series products. Since this

assembler is provided with macro functions, it enhances the developmnt efficency. A structured

assembler, that can explicitly describe the program control structure, is also supplied, so that

the program productivity and maintainability can be improved.

78K/III series

relocatable assembler

(RA78K3)

This is a C compiler that can be commonly used for 78K/III series.

This program converts the program written in C language to object codes microcontroller can

execute. When using this compiler, the 78K3 series relocatable assembler (RA78K/III) is

necessary.

Supply media

3.5" 2HD

S5A13CC78K3

5" 2HD

S5A10CC78K3

3.5" 2HC

S7B13CC78K3

5" 2HC

S7B10CC78K3

DAT

S3P16CC78K3

Cartridge tape

S3K15CC78K3

(QIC-24)

S3R15CC78K3

Remark

The operations of the relocatable assembler and C compiler are guaranteed only on the specified host

machine and OS described above.

78K/III series

C compiler

(CC78K3)

PD78361A, 78362A

Host machine

Order code (part number)

PC-9800 series

MS-DOS

IBM PC/AT and

PC DOS

compatible machines

PROM WRITING TOOLS

This is a PROM programmer that can program PROM-contained single-chip microcontrollers

in standalone mode or under control of a host machine when the accessory board and an

optional programmer adapter are connected. It can also program representative PROMs from

256K-bit to 4M-bit models.

PROM programmer adapters that writes a program to the

PD78P364A on a general-purpose

PROM programmer such as the PG-1500.

PA-78P364CW : for

PD78P364ACW

Connects the PG-1500 and a host machine with a serial intrface and a parallel interface to control

the PG-1500 from the host machine.

PG-1500

PA-78P364CW

PG-1500

controller

Host machine

Order code (part number)

PC-9800 series

MS-DOS

IBM PC/AT and

PC DOS

compatible machines

Remark

The operation of the PG-1500 controller is guaranteed only on the above host machine and OS.

DEBUGGING TOOLS (WHEN IE CONTROLLER IS USED)

Hardware

Software

In-circuit emulator that can be used to develop and debug application systems. Connected to

a host machine for debugging.

I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.

Emulation prove that connects the IE-78350-R to the target system.

Program that controls the IE-78350-R on the host machine. It can automatically execute

commands, enhancing debugging efficiency.

IE-78350-R

IE-78365-R-EM1

EP-78327CW-R

IE-78350-R

control program

(IE controller)

Software

Hardware

Remark

The operation of the IE controller is guaranteed only on the above host machine and OS.

Supply media

3.5" 2HD

S5A13IE78365A

5" 2HD

S5A10IE78365A

3.5" 2HC

S7B13IE78365A

5" 2HC

S7B10IE78365A

Supply media

3.5" 2HD

S5A13PG1500

5" 2HD

S5A10PG1500

3.5" 2HD

S7B13PG1500

5" 2HC

S7B10PG1500

PD78361A, 78362A

IE-784000-R

IE-78350-R-EM-A

IE-78365-R-EM1

EP-78327CW-R

IE-70000-98-IF-B

IE-70000-98N-IF

IE-70000-PC-IF-B

IE-78000-R-SV3

Integrated debugger

(ID78K3)

Device File

(DF78365)

DEBUGGING TOOLS (WHEN INTEGRATED DEBUGGER IS USED)

Hardware

In-circuit emulation that can be used to develop and debug the application system. Connected

to a host machine for debugging.

Emulation board that emulates the peripheral functions of the target device such as I/O ports.

I/O emulation board that emulates the peripheral functions of the target device such as I/O ports.

Emulation probe connecting the IE-784000-R to the target system.

Interface adapter to connect PC-9800 series (except notebook type personal computer) as the

host machine.

Interface adapter and cable to connect PC-9800 series notebook type personal computer as the

host machine.

Interface adapter to connect IBM PC as the host machine.

Interface adapter and cable to connect EWS as the host machine.

Program controlling the in-circuit emulator for the 78K/III series. Used in combination with a

device file (DF78365). Can debug a program coded in the C language, structured assembly

language, or assembly language at source program level. Can also split the screen of the host

machine into windows on each of which information is displayed, enhancing debugging

efficiency.

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

SAA13ID78K3

Windows

5" 2HD

SAA10ID78K3

IBM PC/AT and compatible

PC DOS

3.5" 2HC

SAB13ID78K3

machines (Japanese Windows)

Windows

5" 2HC

SAB10ID78K3

IBM PC/AT and compatible

3.5" 2HC

SBB13ID78K3

machines (English Windows)

5" 2HC

SBB10ID78K3

File containing information peculiar to device. Use in combination with an assembler (RA78K3),

C compiler (CC78K3), and integrated debugger (ID78K3).

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

S5A13DF78365

5" 2HD

S5A10DF78365

IBM PC/AT and compatible

PC DOS

3.5" 2HC

S7B13DF78365

machines

5" 2HC

S7B10DF78365

Software

Remark

The operation of the integrated debugger and device file is guaranteed only on the above host

machine and OS.

PD78361A, 78362A

B.2 EMBEDDED SOFTWARE

The following embedded software is available for enhancing the efficiency of program development and

maintenance.

REAL-TIME OS

Real-time OS

(RX78K/III)

Note

RX78K/III is intended to implement a multi-tasking environment for use in the control field where

real-time capability is a must. It can allocate the idle time of the CPU to other processing to

improve the overall performance of the system.

RX78K/III provides system calls conforming to the

ITRON specification.

The RX78K/III package supplies a tool (configurator) to create the nucleus of RX78K/III and

multiple information tables.

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

Pending

5" 2HD

Pending

IBM PC/AT and compatible

PC DOS

3.5" 2HC

Pending

machines

5" 2HC

Pending

Note Under development

Caution Before purchasing this product, you are requested to conclude a contract licensing use by

filling out a specified form.

Remark

When using the RX78K/III real-time OS, the RA78K3 assembler package (optional) is necessary.

PD78361A, 78362A

FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM

Fuzzy knowledge data

creation tool

(FE9000, FE9200)

Translator (FT78K3)

Note

Fuzzy inference module

(FI78K3)

Note

Fuzzy inference debugger

(FD78K3)

Program that supports input/editing and evaluation (simulation) of fuzzy knowledge (fuzzy rules

and membership functions).

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

S5A13FE9000

5" 2HD

S5A10FE9000

IBM PC/AT and compatible

PC DOS

3.5" 2HC

S7B13FE9200

machines

Windows

5" 2HC

S7B10FE9200

Program that converts the fuzzy knowledge data obtained by using the fuzzy knowledge data

creation tool into assembler source program for the RA78K3.

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

S5A13FT78K3

5" 2HD

S5A10FT78K3

IBM PC/AT and compatible

PC DOS

3.5" 2HC

S7B13FT78K3

machines

5" 2HC

S7B10FT78K3

Program that executes fuzzy inference when linked with the fuzzy knowledge data converted

by the translator.

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

S5A13FI78K3

5" 2HD

S5A10FI78K3

IBM PC/AT and compatible

PC DOS

3.5" 2HC

S7B13FI78K3

machines

5" 2HC

S7B10FI78K3

Support software that evaluates and adjusts the fuzzy knowledge data at the hardware level by

using an in-circuit emulator.

Host machine

Order code (part number)

Supply media

PC-9800 series

MS-DOS

3.5" 2HD

S5A13FD78K3

5" 2HD

S5A10FD78K3

IBM PC/AT and compatible

PC DOS

3.5" 2HC

S7B13FD78K3

machines

5" 2HC

S7B10FD78K3

Note Under development

PD78361A, 78362A

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

PD78361A, 78362A

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

PD78361A, 78362A

MS-DOS and windows are either registered trademarks or trademarks of Microsoft Corporation

in the United States and/or other countries.

PC/AT and PC DOS are trademarks of IBM Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademark of Sony Corporation.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

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