Document Outline

COVER
FEATURES
APPLICATIONS
ORDERING INFORMATION
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
FUNCTIONS
1. DIFFERENCES BETWEEN uPD784038 SUB-SERIES
2. MAIN DIFFERENCES BETWEEN uPD784038, uPD784038Y, uPD784026, AND uPD78234 SUB-SERIES
3. PIN CONFIGURATION (TOP VIEW)
4. SYSTEM CONFIGURATION EXAMPLE (PPC)
5. BLOCK DIAGRAM
6. PIN FUNCTIONS
- 6.1 Port Pins
- 6.2 Non-Port Pins
- 6.3 I/O Circuits for Pins and Handling of Unused Pins
7. CPU ARCHITECTURE
- 7.1 Memory Space
- 7.2 CPU Registers
  - 7.2.1 General-purpose registers
  - 7.2.2 Control registers
  - 7.2.3 Special function registers (SFRs)
8. PERIPHERAL HARDWARE FUNCTIONS
- 8.1 Ports
- 8.2 Clock Generator
- 8.3 Real-Time Output Port
- 8.4 Timers/Counters
- 8.5 PWM Output (PWM0, PWM1)
- 8.6 A/D Converter
- 8.7 D/A Converter
- 8.8 Serial Interface
  - 8.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE)
  - 8.8.2 Synchronous serial interface (CSI)
- 8.9 Clock Output Function
- 8.10 Edge Detection Function
- 8.11 Watchdog timer
9. INTERRUPT FUNCTION
- 9.1 Interrupt Source
- 9.2 Vectored Interrupt
- 9.3 Context Switching
- 9.4 Macro Service
- 9.5 Examples of Macro Service Applications
10. LOCAL BUS INTERFACE
- 10.1 Memory Expansion
- 10.2 Memory Space
- 10.3 Programmable Wait
- 10.4 Pseudo-Static RAM Refresh Function
- 10.5 Bus Hold Function
11. STANDBY FUNCTION
12. RESET FUNCTION
13. INSTRUCTION SET
14. ELECTRICAL CHARACTERISTICS
15. PACKAGE DRAWINGS
16. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT TOOLS
APPENDIX B RELATED DOCUMENTS

MOS INTEGRATED CIRCUIT

PD784035, 784036, 784037, 784038

16/8-BIT SINGLE-CHIP MICROCONTROLLER

The

PD784038 is a product of the

PD784038 sub-series in the 78K/IV series. It contains various peripheral

hardware such as ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt

functions, as well as a high-speed, high-performance CPU.

In addition, the

PD78P4038 (one-time PROM or EPROM product), which can be operated within the same power

supply voltage ranges as masked-ROM products, and development tools are supported.

For specific functions and other detailed information, consult the following user's manual.

This manual is required reading for design work.

PD784038, 784038Y Sub-Series User's Manual, Hardware : U11316E

78K/IV Series User's Manual, Instruction

: U10905E

FEATURES

· Pin-compatible with the

PD78234,

PD784026, and

PD784038Y sub-series

· Expanded internal memory spaces in the

PD78234

and

PD784026 sub-series

· Minimum instruction execution time: 125 ns

(at 32 MHz)

· Number of I/O ports: 64

· Timer/counters: 16-bit timer/counter

3 units

16-bit timer

1 unit

· A/D converter: 8-bit resolution

8 channels

· D/A converter: 8-bit resolution

2 channels

APPLICATIONS

LBP, automatic-focusing camera, PPC, printer, electronic typewriter, air conditioner, electronic musical instru-

ments, cellular telephone, etc.

This manual describes the

PD784038 unless otherwise specified.

DATA SHEET

· Serial interface: 3 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel

· PWM outputs: 2

· Standby function

HALT/STOP/IDLE mode

· Clock frequency division function

· Watchdog timer: 1 channel

· Clock output function

Selectable from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16

· Supply voltage: V

= 2.7 to 5.5 V

Document No.

U10847EJ2V0DS00 (2nd edition)

Date Published February 1998 J CP(K)
Printed in Japan

The mark shows major revised points.

The information in this document is subject to change without notice.

1995

PD784035, 784036, 784037, 784038

ORDERING INFORMATION

Part number

Package

Internal ROM

Internal RAM

(bytes)

PD784035GC-

×××

-3B9

80-pin plastic QFP (14

2.7 mm)

48K

2,048

PD784035GC-

×××

-8BT

80-pin plastic QFP (14

1.4 mm)

48K

2,048

PD784035GK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

48K

2,048

PD784036GC-

×××

-3B9

80-pin plastic QFP (14

2.7 mm)

64K

2,048

PD784036GC-

×××

-8BT

80-pin plastic QFP (14

1.4 mm)

64K

2,048

PD784036GK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

64K

2,048

PD784037GC-

×××

-3B9

80-pin plastic QFP (14

2.7 mm)

96K

3,584

PD784037GC-

×××

-8BT

80-pin plastic QFP (14

1.4 mm)

96K

3,584

PD784037GK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

96K

3,584

PD784038GC-

×××

-3B9

80-pin plastic QFP (14

2.7 mm)

128K

4,352

PD784038GC-

×××

-8BT

80-pin plastic QFP (14

1.4 mm)

128K

4,352

PD784038GK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

128K

4,352

Remark

×××

is ROM code suffix.

PD784035, 784036, 784037, 784038

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

PD784026

PD784038Y

C bus supported

PD784038

Enhanced internal memory capacity,
pin compatible with the PD784026

PD784225Y

Multimaster I

C bus supported

PD784225

80 pins,
added ROM correction

PD784218Y

Multimaster I

C bus supported

Multimaster I

C bus supported

PD784218

Enhanced internal memory capacity,
added ROM correction

PD784928Y

Multimaster I

C bus supported

PD784928

Enhanced function of the PD784915

PD784216Y

PD784054

PD784216

PD784046

PD784908

Equipped with 10-bit A/D

100 pins,
enhanced I/O and
internal memory capacity

Enhanced A/D,
16-bit timer,
and power
management

PD784915

For software servo control,
equipped with analog circuit
for VCR,
enhanced timer

Equipped with IEBus

controller

PD78F4943

For CD-ROM
Flash memory 56K bytes

Standard models

ASSP models

: Under mass production

: Under development

PD784955

For DC inverter control

PD784035, 784036, 784037, 784038

Note

Additional function pins are included in the I/O pins.

FUNCTIONS

PD784035

PD784036

PD784037

PD784038

113

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

125 ns/250 ns/500 ns/1,000 ns (at 32 MHz)

48K bytes

64K bytes

96K bytes

128K bytes

2,048 bytes

3,584 bytes

4,352 bytes

Program and data: 1M byte

4 bits

2, or 8 bits

Timer/counter 0:

Timer register

Pulse output capability

(16 bits)

Capture register

Toggle output

Compare register

PWM/PPG output

One-shot pulse output

Timer/counter 1:

Timer register

Pulse output capability

(8/16 bits)

Capture register

Real-time output (4 bits

Capture/compare register

Compare register

Timer/counter 2:

Timer register

Pulse output capability

(8/16 bits)

Capture register

Toggle output

Capture/compare register

PWM/PPG output

Compare register

Timer 3

Timer register

(8/16 bits)

Compare register

12-bit resolution

2 channels

UART/IOE (3-wire serial I/O)

: 2 channels (incorporating baud rate generator)

CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel

8-bit resolution

8 channels

8-bit resolution

2 channels

Selected from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16 (can be used as a 1-bit output port)

1 channel

HALT/STOP/IDLE mode

23 (16 internal, 7 external (sampling clock variable input: 1))

BRK instruction, BRKCS instruction, operand error

1 internal, 1 external

15 internal, 6 external

4-level programmable priority

3 operation statuses: vectored interrupt, macro service, context switching

= 2.7 to 5.5 V

80-pin plastic QFP (14

2.7 mm)

80-pin plastic QFP (14

1.4 mm)

80-pin plastic TQFP (fine pitch) (12

12 mm)

Product

Item

Number of basic instructions
(mnemonics)

General-purpose register

Minimum instruction execution
time

Internal
memory

Memory space

I/O ports

Additional
function
pins

Note

Real-time output ports

Timer/counter

PWM outputs

Serial interface

A/D converter

D/A converter

Clock output

Watchdog timer

Standby

Interrupt

Hardware source

Software source

Nonmaskable

Maskable

Supply voltage

Package

ROM

RAM

Total

Input

Input/output

Pins with pull-
up resistor

LED direct
drive outputs

Transistor
direct drive

PD784035, 784036, 784037, 784038

CONTENTS

DIFFERENCES BETWEEN

PD784038 SUB-SERIES ...........................................................

MAIN DIFFERENCES BETWEEN

PD784038,

PD784038Y,

PD784026,

AND

PD78234 SUB-SERIES ...................................................................................................

PIN CONFIGURATION (TOP VIEW) .........................................................................................

SYSTEM CONFIGURATION EXAMPLE (PPC) ........................................................................

BLOCK DIAGRAM .....................................................................................................................

PIN FUNCTIONS ........................................................................................................................

6.1

Port Pins .........................................................................................................................................

6.2

Non-Port Pins .................................................................................................................................

6.3

I/O Circuits for Pins and Handling of Unused Pins ..................................................................

CPU ARCHITECTURE ...............................................................................................................

7.1

Memory Space ................................................................................................................................

7.2

CPU Registers ................................................................................................................................

7.2.1

General-purpose registers ............................................................................................

7.2.2

Control registers ............................................................................................................

7.2.3

Special function registers (SFRs) ...............................................................................

PERIPHERAL HARDWARE FUNCTIONS ................................................................................

8.1

Ports ................................................................................................................................................

8.2

Clock Generator .............................................................................................................................

8.3

Real-Time Output Port ..................................................................................................................

8.4

Timers/Counters ............................................................................................................................

8.5

PWM Output (PWM0, PWM1) ........................................................................................................

8.6

A/D Converter .................................................................................................................................

8.7

D/A Converter .................................................................................................................................

8.8

Serial Interface ...............................................................................................................................

8.8.1

Asynchronous serial interface/three-wire serial I/O (UART/IOE) ............................

8.8.2

Synchronous serial interface (CSI) .............................................................................

8.9

Clock Output Function ..................................................................................................................

8.10

Edge Detection Function ..............................................................................................................

8.11

Watchdog Timer .............................................................................................................................

INTERRUPT FUNCTION ............................................................................................................

9.1

Interrupt Source .............................................................................................................................

9.2

Vectored Interrupt ..........................................................................................................................

9.3

Context Switching .........................................................................................................................

9.4

Macro Service .................................................................................................................................

9.5

Examples of Macro Service Applications ..................................................................................

PD784035, 784036, 784037, 784038

10. LOCAL BUS INTERFACE .........................................................................................................

10.1

Memory Expansion ........................................................................................................................

10.2

Memory Space ................................................................................................................................

10.3

Programmable Wait .......................................................................................................................

10.4

Pseudo-Static RAM Refresh Function ........................................................................................

10.5

Bus Hold Function .........................................................................................................................

11. STANDBY FUNCTION ...............................................................................................................

12. RESET FUNCTION .....................................................................................................................

13. INSTRUCTION SET ....................................................................................................................

14. ELECTRICAL CHARACTERISTICS .........................................................................................

15. PACKAGE DRAWINGS .............................................................................................................

16. RECOMMENDED SOLDERING CONDITIONS ........................................................................

APPENDIX A DEVELOPMENT TOOLS ..........................................................................................

APPENDIX B RELATED DOCUMENTS .........................................................................................

PD784035, 784036, 784037, 784038

Series

PD784038 sub-series

PD784026 sub-series

PD78234 sub-series

Item

PD784038Y sub-series

Number of basic instructions

113

(mnemonics)

Minimum instruction execution

125 ns

160 ns

333 ns

time

(at 32 MHz)

(at 25 MHz)

(at 12 MHz)

Memory space (program/data)

1M byte in total

64K bytes/1M byte

Timer/counter

16-bit timer/counter

8/16-bit timer/counter

8-bit timer/counter

8/16-bit timer

8-bit timer

Clock output function

Available

Unavailable

Watchdog timer

Available

Unavailable

Serial interface

UART/IOE (3-wire serial I/O)

UART

1 channel

2 channels

CSI (3-wire serial I/O, SBI)

CSI (3-wire serial I/O, 2-wire

CSI (3-wire serial I/O, SBI)

1 channel

serial I/O, I

C bus

Note

)

1 channel

Interrupt

Context switching

Available

Unavailable

Priority

4 levels

2 levels

Standby function

3 modes (HALT, STOP, IDLE)

2 modes (HALT, STOP)

Operation clock switching

Selectable from f

/2, f

/4, f

/8, or f

/16

Fixed to f

MODE pin

Unavailable

To specify ROM-less mode

functions

(always in the high level for

the

PD78233 or

PD78237)

TEST pin

Pin for testing the device

Unavailable

Low level during ordinary use

Package

80-pin plastic QFP

(14

2.7 mm)

(14

2.7 mm)

(14

2.7 mm)

80-pin plastic QFP

80-pin plastic TQFP

94-pin plastic QFP

(14

1.4 mm)

(fine pitch) (12

12 mm):

(20

20 mm)

80-pin plastic TQFP

for the

PD784021 only

84-pin plastic QFJ

(fine pitch) (12

12 mm)

80-pin ceramic WQFN

(1,150

1,150 mil)

80-pin ceramic WQFN

(14

14 mm):

94-pin ceramic WQFN

(14

14 mm):

for the

PD78P4026 only

(20

20 mm):

for the

PD78P4038 and

for the

PD78P238 only

PD78P4038Y only

2. MAIN DIFFERENCES BETWEEN

PD784038,

PD784038Y,

PD784026, AND

PD78234 SUB-

SERIES

Note

For the

PD784038Y sub-series only.

PD784035, 784036, 784037, 784038

3. PIN CONFIGURATION (TOP VIEW)

80-pin plastic QFP (14

2.7 mm)

PD784035GC-

×××

-3B9,

PD784036GC-

×××

-3B9,

PD784037GC-

×××

-3B9,

PD784038GC-

×××

-3B9

80-pin plastic QFP (14

1.4 mm)

PD784035GC-

×××

-8BT,

PD784036GC-

×××

-8BT,

PD784037GC-

×××

-8BT,

PD784038GC-

×××

-8BT

80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784035GK-

×××

-BE9,

PD784036GK-

×××

-BE9,

PD784037GK-

×××

-BE9,

PD784038GK-

×××

-BE9

Note

Connect the TEST pin to the V

SS0

pin directly.

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

DD0

P17

P16

P15

P14/T

D2/SO2

P13/R

D2/SI2

P12/ASCK2/SCK2

P11/PWM1

P10/PWM0

TEST

Note

SS0

ASTB/CLKOUT

P40/AD0

P41/AD1

P42/AD2

P32/SCK0/SCL

P33/SO0/SDA

P34/ TO0

P35/ TO1

P36/ TO2

P37/ TO3

RESET

DD1

SS1

P00

P01

P02

P03

P04

P05

P06

P07

P67/REFRQ/HLDAK

P66/

WAIT/HLDRQ

P65/

P64

/RD

P63/A19

P62

/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54

/A12

P53/A11

P52

/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44

/AD4

P43/AD3

P31/

TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4

/ASCK/SCK1

P24

/INTP3

P23/INTP2

/CI

P22

/INTP1

P21/INTP0

P20/NMI

REF3

REF2

ANO1

ANO0

REF1

P77/ANI7

P76/ANI6

P75/ANI5

PD784035, 784036, 784037, 784038

P60-P67

: Port 6

P70-P77

: Port 7

PWM0, PWM1 : Pulse width modulation output

: Read strobe

REFRQ

: Refresh request

RESET

: Reset

RxD, RxD2

: Receive data

SCK0-SCK2

: Serial clock

SCL

: Serial clock

SDA

: Serial data

SI0-SI2

: Serial input

SO0-SO2

: Serial output

TEST

: Test

TO0-TO3

: Timer output

TxD, TxD2

: Transmit data

DD0

, V

DD1

: Power supply

SS0

, V

SS1

: Ground

WAIT

: Wait

: Write strobe

X1, X2

: Crystal

A8-A19

: Address bus

AD0-AD7

: Address/data bus

ANI0-ANI7

: Analog input

ANO0, ANO1

: Analog output

ASCK, ASCK2 : Asynchronous serial clock

ASTB

: Address strobe

: Analog power supply

REF1

-AV

REF3

: Reference voltage

: Analog ground

: Clock input

CLKOUT

: Clock output

HLDAK

: Hold acknowledge

HLDRQ

: Hold request

INTP0-INTP5

: Interrupt from peripherals

NMI

: Non-maskable interrupt

P00-P07

: Port 0

P10-P17

: Port 1

P20-P27

: Port 2

P30-P37

: Port 3

P40-P47

: Port 4

P50-P57

: Port 5

PD784035, 784036, 784037, 784038

6. PIN FUNCTIONS

6.1 Port Pins (1/2)

Function

Port 0 (P0):

8-bit I/O port.

Functions as a real-time output port (4 bits

2).

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive a transistor.

Port 1 (P1):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

Port 2 (P2):

8-bit input-only port.

P20 does not function as a general-purpose port (nonmaskable inter-

rupt). However, the input level can be checked by an interrupt service

routine.

The use of the pull-up resistors can be specified by software for pins

P22 to P27 (in units of 6 bits).

The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by

CSIM1.

Port 3 (P3):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 4 (P4):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

Port 5 (P5):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

I/O

Input

I/O

P00-P07

P10

P11

P12

P13

P14

P15-P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34-P37

P40-P47

P50-P57

Dual-function

PWM0

PWM1

ASCK2/SCK2

RxD2/SI2

TxD2/SO2

NMI

INTP0

INTP1

INTP2/CI

INTP3

INTP4/ASCK/SCK1

INTP5

SI0

RxD/SI1

TxD/SO1

SCK0/SCL

SO0/SDA

TO0-TO3

AD0-AD7

A8-A15

PD784035, 784036, 784037, 784038

6.2 Non-Port Pins (1/2)

I/O

Dual-function

Function

TO0-TO3

Output

P34-P37

Timer output

Input

P23/INTP2

Input of a count clock for timer/counter 2

Input

P30/SI1

Serial data input (UART0)

P13/SI2

Serial data input (UART2)

Output

P31/SO1

Serial data output (UART0)

P14/SO2

Serial data output (UART2)

ASCK

Input

P25/INTP4/SCK1

Baud rate clock input (UART0)

ASCK2

P12/SCK2

Baud rate clock input (UART2)

SDA

I/O

P33/SO0

Serial data I/O (2-wire serial I/O)

SI0

Input

P27

Serial data input (3-wire serial I/O0)

SI1

P30/R

Serial data input (3-wire serial I/O1)

SI2

P13/R

Serial data input (3-wire serial I/O2)

SO0

Output

P33/SDA

Serial data output (3-wire serial I/O0)

SO1

P31/T

Serial data output (3-wire serial I/O1)

SO2

P14/T

Serial data output (3-wire serial I/O2)

SCK0

I/O

P32/SCL

Serial clock I/O (3-wire serial I/O0)

SCK1

P25/INTP4/ASCK

Serial clock I/O (3-wire serial I/O1)

SCK2

P12/ASCK2

Serial clock I/O (3-wire serial I/O2)

SCL

P32/SCK0

Serial clock I/O (2-wire serial I/O)

NMI

Input

P20

External interrupt request

INTP0

P21

Input of a count clock for timer/counter 1

Capture/trigger signal for CR11 or CR12

INTP1

P22

Input of a count clock for timer/counter 2

Capture/trigger signal for CR22

INTP2

P23/CI

Input of a count clock for timer/counter 2

Capture/trigger signal for CR21

INTP3

P24

Input of a count clock for timer/counter 0

Capture/trigger signal for CR02

INTP4

P25/ASCK/SCK1

INTP5

P26

Input of a conversion start trigger for A/D converter

AD0-AD7

I/O

P40-P47

Time multiplexing address/data bus (for connecting external memory)

A8-A15

Output

P50-P57

High-order address bus (for connecting external memory)

A16-A19

Output

P60-P63

High-order address bus during address expansion (for connecting external memory)

Output

P64

Strobe signal output for reading the contents of external memory

Output

P65

Strobe signal output for writing on external memory

WAIT

Input

P66/HLDRQ

Wait signal insertion

REFRQ

Output

P67/HLDAK

Refresh pulse output to external pseudo static memory

HLDRQ

Input

P66/WAIT

Input of bus hold request

HLDAK

Output

P67/REFRQ

Output of bus hold response

ASTB

Output

CLKOUT

Latch timing output of time multiplexing address (A0-A7) (for
connecting external memory)

CLKOUT

Output

ASTB

Clock output

PD784035, 784036, 784037, 784038

6.2 Non-Port Pins (2/2)

Notes 1. The potential of the V

DD0

pin must be equal to that of the V

DD1

pin.

2. The potential of the V

SS0

pin must be equal to that of the V

SS1

pin.

I/O

Dual-function

Function

RESET

Input

Chip reset

Input

Crystal input for system clock oscillation (A clock pulse can also be

input to the X1 pin.)

ANI0-ANI7

Input

P70-P77

Analog voltage inputs for the A/D converter

ANO0, ANO1

Output

Analog voltage inputs for the D/A converter

REF1

Application of A/D converter reference voltage

REF2

, AV

REF3

Application of D/A converter reference voltage

Positive power supply for the A/D converter

Ground for the A/D converter

DD0

Note 1

Positive power supply of the port part

DD1

Note 1

Positive power supply except for the port part

SS0

Note 2

Ground of the port part

SS1

Note 2

Ground except for the port part

TEST

Directly connect to the V

pin. (The TEST pin is for the IC test.)

PD784035, 784036, 784037, 784038

6.3 I/O Circuits for Pins and Handling of Unused Pins

Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins.

Figure 6-1 shows the configuration of these various types of I/O circuits.

Table 6-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

I/O circuit type

I/O

Recommended connection method for unused pins

P00-P07

5-H

I/O

Input state : Connect these pins to the V

DD0

pin.

P10/PWM0

Output state: Leave open.

P11/PWM1

P12/ASCK2/SCK2

8-C

P13/RxD2/SI2

5-H

P14/TxD2/SO2

P15-P17

P20/NMI

Input

Connect these pins to the V

DD0

or V

SS0

pin.

P21/INTP0

P22/INTP1

2-C

Connect these pins to the V

DD0

pin.

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1

8-C

I/O

Input state : Connect this pin to the V

DD0

pin.

Output state: Leave open.

P26/INTP5

2-C

Input

Connect these pins to the V

DD0

pin.

P27/SI0

P30/RxD/SI1

5-H

I/O

Input state : Connect these pins to the V

DD0

pin.

P31/TxD/SO1

Output state: Leave open.

P32/SCK0/SCL

10-B

P33/SO0/SDA

P34/TO0-P37/TO3

5-H

P40/AD0-P47/AD7

P50/A8-P57/A15

P60/A16-P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0-P77/ANI7

20-A

I/O

Input state : Connect this pin to the V

DD0

or V

SS0

pin.

Output state: Leave open.

ANO0, ANO1

Output

Leave open.

ASTB/CLKOUT

4-B

PD784035, 784036, 784037, 784038

7. CPU ARCHITECTURE

7.1 Memory Space

A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal

data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be

executed after a reset, and can be used only once.

(1) When the LOCATION 0 instruction is executed

· Internal memory

The table below indicates the internal data areas and internal ROM areas of each product.

Caution The following internal ROM areas, existing at the same addresses as the internal data areas,

cannot be used when the LOCATION 0 instruction is executed:

· External memory

External memory is accessed in external memory expansion mode.

(2) When the LOCATION 0FH instruction is executed

· Internal memory

The table below lists the internal data areas and internal ROM areas for each product.

· External memory

External memory is accessed in external memory expansion mode.

Product name

Unusable area

PD784035

PD784036

0F700H-0FFFFH (2,304 bytes)

PD784037

0F100H-0FFFFH (3,840 bytes)

PD784038

0EE00H-0FFFFH (4,608 bytes)

Product name

Internal data area

Internal ROM area

PD784035

0F700H-0FFFFH

00000H-0BFFFH

PD784036

00000H-0F6FFH

PD784037

0F100H-0FFFFH

00000H-0F0FFH

10000H-17FFFH

PD784038

0EE00H-0FFFFH

00000H-0FDFFH

10000H-1FFFFH

Product name

Internal data area

Internal ROM area

PD784035

FF700H-FFFFFH

00000H-0BFFFH

PD784036

00000H-0FFFFH

PD784037

0F100H-FFFFFH

00000H-17FFFH

PD784038

FEE00H-FFFFFH

00000H-1FFFFH

PD784035,

784036,

784037,

784038

Figure 7-1.

PD784035 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

FFE FFH

F F F F F H
F F F D F H
F F F D 0 H

F F F 0 0 H

FFE 8 0H
FFE 7FH

FF7 0 0H
FF6 FFH

1 00 0 0H
0FF FFH

0C0 0 0H
0BF FFH

0 00 0 0H

FFE 2FH

FFE 0 6H

FFD 0 0H
FFC FFH

FF7 0 0H

When the LOCATION 0
instruction is executed

External memory
(960K bytes)

Note 1

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(2,048 bytes)

Note 2

External memory
(14,080 bytes)

Note 1

Internal ROM
(48K bytes)

0 F FFH

0 F 8 0H

0 F 7FH

0 F 0 0H

0 F FFH

0 1 0 0H

0 0 FFH

0 0 0 0H

0 0 FFH

0 0 8 0H

0 0 7FH

0 0 4 0H

0 0 3FH

0 0 0 0H

0 F 0 0H

0B FFH

0 F 2FH

0 F 0 6H

FF F F H

0 F F F H

1 0 0 0 H

0 F DF H

0 F D0 H

0 F 0 0 H

0 F F F H

0 F 0 0 H

0 F F F H

0C 0 0 H

0B F F H

0 0 0 0 H

Note 2

General-purpose
registers (128 bytes)

Macro service control
word area (42 bytes)

Data area (512 bytes)

Program/data area
(1,536 bytes)

Program/data area
(48K bytes)

CALLF entry area
(2K bytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

When the LOCATION
0FH instruction is executed

Special function registers (SFRs)

(256 bytes)

Note 1

Internal RAM
(2,048 bytes)

External memory
(997,120 bytes)

Note 1

Internal ROM
(48K bytes)

PD784035,

784036,

784037,

784038

Figure 7-2.

PD784036 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. This 2,304-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed

: 63,232 bytes

When the LOCATION 0FH instruction is executed: 65,536 bytes

4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

F FFF FH

0 FFF FH
0 FFDFH
0 FFD0 H
0 FF 0 0 H
0 FEF FH

1 0 0 0 0 H

0 F 7 0 0 H
0 F 6 F FH

0 0 0 0 0 H

0 FEF FH

0 FE8 0 H
0 FE7 FH

0 FE2 FH

0 FE0 6 H

0 FD0 0 H
0 FCF FH

0 F 7 0 0 H

0 F 6 F FH

0 1 0 0 0 H
0 0 FF FH

0 0 8 0 0 H
0 0 7 F FH

0 0 0 8 0 H
0 0 0 7 FH

0 0 0 4 0 H
0 0 0 3 FH

0 0 0 0 0 H

F FEF FH

F FE8 0 H
F FE7 FH

F FE2 FH

F FE0 6 H

F FD0 0 H
F FCF FH

F F 7 0 0 H

0 FFF FH

1 0 0 0 0 H

0 FFF FH

0 0 0 0 0 H

F F 6 F FH

F F 7 0 0 H

F FEF FH

F F F 0 0 H

F F F D 0 H

F F F D F H

F F F F F H

When the LOCATION 0
instruction is executed

External memory
(960K bytes)

Note 1

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(2,048 bytes)

Note 4

Internal ROM
(63,232 bytes)

General-purpose
registers (128 bytes)

Macro service control
word area (42 bytes)

Data area (512 bytes)

Program/data area
(1,536 bytes)

Program/data area

Note 3

Note 2

CALLF entry
area (2K bytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

Internal ROM
(64K bytes)

Note 4

External memory
(980,736 bytes)

Note 1

When the LOCATION 0FH
instruction is executed

Special function registers (SFRs)

(256 bytes)

Internal RAM
(2,048 bytes)

Note 1

PD784035,

784036,

784037,

784038

Figure 7-3.

PD784037 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed

: 94,464 bytes

When the LOCATION 0FH instruction is executed: 98,304 bytes

4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

F FF F FH

1 8 0 0 0H
1 7 F F FH

0 FF F FH
0 FFDFH
0 FFD0H
0 FF 0 0H

1 0 0 0 0H

0 FEF FH

0 F 1 0 0H
0 F 0 F FH

0 0 0 0 0H

0 FEF FH

0 FE 8 0H
0 FE 7 FH

0 FE 2 FH

0 FE 0 6H

0 FD0 0H
0 FCF FH

0 F 1 0 0H

1 7 F F F H
1 0 0 0 0 H

0 F 0 F FH

0 1 0 0 0H
0 0 F F FH

0 0 8 0 0H
0 0 7 F FH
0 0 0 8 0H
0 0 0 7 FH

0 0 0 4 0H
0 0 0 3 FH

0 0 0 0 0H

F FEF FH

F FE 8 0H
F FE 7 FH

F FE 2 FH

F FE 0 6H

F FD0 0H
F FCF FH

F F 1 0 0H

F F 1 0 0H
F F 0 F FH

1 8 0 0 0H
1 7 F F FH

0 0 0 0 0H

F FEF FH

F F F D F H
F F F D 0 H
F F F 0 0 H

F F F F F H

1 7 F F FH

When the LOCATION 0
instruction is executed

External memory
(928K bytes)

Note 1

Internal ROM
(32,768 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(3,584 bytes)

Internal ROM
(61,696 bytes)

Note 4

General-purpose
registers (128 bytes)

Macro service control

word area (42 bytes)

Data area (512 bytes)

Program/data area
(3,072 bytes)

Program/data area

Note 3

Note 2

CALLF entry area
(2K bytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

When the LOCATION 0FH
instruction is executed

Internal RAM
(3,584 bytes)

External memory
(946,432 bytes)

Note 1

Internal ROM

(96K bytes)

Note 4

Special function registers (SFRs)

(256 bytes)

Note 1

PD784035,

784036,

784037,

784038

Figure 7-4.

PD784038 Memory Map

Notes 1. Accessed in external memory expansion mode.

2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.

3. When the LOCATION 0 instruction is executed

: 126,464 bytes

When the LOCATION 0FH instruction is executed: 131,072 bytes

4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.

FF F F FH

2 0 0 0 0H

0F F F FH

1F F F FH

0F FDFH
0F FD0H
0F F 0 0H
0FEF FH

1 0 0 0 0H

0EE 0 0H
0EDF FH

0 0 0 0 0H

0FEF FH

0FE 8 0H
0FE 7 FH

0FE 2 FH

0FE 0 6H

0FD0 0H
0FCF FH

0EE 0 0H

1 F F F F H
1 0 0 0 0 H

0EDF FH

0 0 8 0 0H
0 0 7 F FH

0 1 0 0 0H
0 0 F F FH

0 0 0 8 0H
0 0 0 7 FH

0 0 0 4 0H
0 0 0 3 FH

0 0 0 0 0H

FFEF FH

FFE 8 0H
FFE 7 FH

FFE 2 FH

FFE 0 6H

FFD0 0H
FFCF FH

FEE 0 0H

FEE 0 0H
FEDF FH

FFEF FH

F F F 0 0 H

F F F D 0 H

F F F D F H

F F F F F H

2 0 0 0 0H
1F F F FH

1F F F FH

0 0 0 0 0H

When the LOCATION 0
instruction is executed

External memory
(896K bytes)

Note 1

Internal ROM
(65,536 bytes)

Special function registers (SFRs)

Note 1

(256 bytes)

Internal RAM
(4,352 bytes)

Note 4

Internal ROM

(60,928 bytes)

General-purpose
registers (128 bytes)

Macro service control
word area (42 bytes)

Data area (512 bytes)

Program/data area
(3,840 bytes)

Note 2

Program/data area

Note 3

CALLF entry area
(2K bytes)

CALLT table area
(64 bytes)

Vector table area
(64 bytes)

When the LOCATION 0FH
instruction is executed

Special function registers (SFRs)

Note 4

Internal ROM

(128K bytes)

External memory
(912,896 bytes)

Note 1

Internal RAM
(4,352 bytes)

Note 1

(256 bytes)

PD784035, 784036, 784037, 784038

7.2 CPU Registers

7.2.1 General-purpose registers

A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose

registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers,

when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.

Eight banks of this register set are provided. The user can switch between banks by software or the context

switching function.

General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto

internal RAM.

Figure 7-5. General-Purpose Register Format

Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B,

AX, and BC registers, respectively. However, this function must be used only when using

programs for the 78K/III series.

A (R1)

X (R0)

B (R3)

C (R2)

R11

R10

D (R13)

E (R12)

H (R15)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

The character strings enclosed in
parentheses represent absolute names.

8 banks

PD784035, 784036, 784037, 784038

7.2.3 Special function registers (SFRs)

The special function registers are registers with special functions such as mode registers and control registers

for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H

and 0FFFFH

Note

Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH

instruction is executed.

Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the

PD784038 may be placed in the deadlock state. The deadlock state can be cleared only by a

reset.

Table 7-1 lists the special function registers (SFRs). The titles of the table columns are explained below.

· Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are

reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows

the abbreviations to be used as sfr variables with the #pragma sfr command.

· R/W ................................. Indicates whether each SFR allows read and/or write operations.

R/W : Allows both read and write operations.

: Allows read operations only.

: Allows write operations only.

· Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is

manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp

operand. For address specification, an even-numbered address must be speci-

fied.

An SFR that supports 1-bit manipulation can be described in a bit manipulation

instruction.

· When reset ..................... Indicates the state of each register when RESET is applied.

PD784035, 784036, 784037, 784038

Table 7-1. Special Function Registers (SFRs) (1/4)

Address

Note

Special function register (SFR) name

Abbreviation

R/W

Manipulatable bits

When reset

1 bit

8 bits 16 bits

0FF00H

Port 0

R/W

Undefined

0FF01H

Port 1

0FF02H

Port 2

0FF03H

Port 3

R/W

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

00H

0FF07H

Port 7

Undefined

0FF0EH

Port 0 buffer register L P0L

0FF0FH

Port 0 buffer register H

P0H

0FF10H

Compare register (timer/counter 0)

CR00

0FF12H

Capture/compare register (timer/counter 0)

CR01

0FF14H

Compare register L (timer/counter 1)

CR10 CR10W

0FF15H

Compare register H (timer/counter 1)

0FF16H

Capture/compare register L (timer/counter 1)

CR11 CR11W

0FF17H

Capture/compare register H (timer/counter 1)

0FF18H

Compare register L (timer/counter 2)

CR20 CR20W

0FF19H

Compare register H (timer/counter 2)

0FF1AH

Capture/compare register L (timer/counter 2)

CR21 CR21W

0FF1BH

Capture/compare register H (timer/counter 2)

0FF1CH

Compare register L (timer 3)

CR30 CR30W

0FF1DH

Compare register H (timer 3)

0FF20H

Port 0 mode register

PM0

FFH

0FF21H

Port 1 mode register

PM1

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF27H

Port 7 mode register

PM7

0FF2EH

Real-time output port control register

RTPC

00H

0FF30H

Capture/compare control register 0

CRC0

10H

0FF31H

Timer output control register

TOC

00H

0FF32H

Capture/compare control register 1

CRC1

0FF33H

Capture/compare control register 2

CRC2

10H

Note

Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

PD784035, 784036, 784037, 784038

Table 7-1. Special Function Registers (SFRs) (2/4)

Note

Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

Address

Note

Special function register (SFR) name

Abbreviation

R/W

Manipulatable bits

When reset

1 bit

8 bits 16 bits

0FF36H

Capture register (timer/counter 0)

CR02

0000H

0FF38H

Capture register L (timer/counter 1)

CR12 CR12W

0FF39H

Capture register H (timer/counter 1)

0FF3AH

Capture register L (timer/counter 2)

CR22 CR22W

0FF3BH

Capture register H (timer/counter 2)

0FF41H

Port 1 mode control register

PMC1

R/W

00H

0FF43H

Port 3 mode control register

PMC3

0FF4EH

PUO

0FF50H

Timer register 0

TM0

0000H

0FF51H

0FF52H

Timer register 1

TM1

TM1W

0FF53H

0FF54H

Timer register 2

TM2

TM2W

0FF55H

0FF56H

Timer register 3

TM3

TM3W

0FF57H

0FF5CH

Prescaler mode register 0

PRM0

R/W

11H

0FF5DH

Timer control register 0

TMC0

00H

0FF5EH

Prescaler mode register 1

PRM1

11H

0FF5FH

Timer control register 1

TMC1

00H

0FF60H

D/A conversion value setting register 0

DACS0

0FF61H

D/A conversion value setting register 1

DACS1

0FF62H

D/A converter mode register

DAM

03H

0FF68H

A/D converter mode register

ADM

00H

0FF6AH

A/D conversion result register

ADCR

Undefined

0FF70H

PWM control register

PWMC

R/W

05H

0FF71H

PWM prescaler register

PWPR

00H

0FF72H

PWM modulo register 0

PWM0

Undefined

0FF74H

PWM modulo register 1

PWM1

0FF7DH

One-shot pulse output control register

OSPC

00H

0FF80H

C bus control register

IICC

0FF81H

Prescaler mode register for serial clock

SPRM

04H

0FF82H

Synchronous serial interface mode register

CSIM

00H

PD784035, 784036, 784037, 784038

Address

Note 1

Special function register (SFR) name

Abbreviation

R/W

Manipulatable bits

When reset

1 bit

8 bits 16 bits

0FF84H

Synchronous serial interface mode register 1

CSIM1

R/W

00H

0FF85H

Synchronous serial interface mode register 2

CSIM2

0FF86H

Serial shift register

SIO

0FF88H

Asynchronous serial interface mode register

ASIM

0FF89H

Asynchronous serial interface mode register 2

ASIM2

0FF8AH

Asynchronous serial interface status register

ASIS

0FF8BH

Asynchronous serial interface status register 2

ASIS2

0FF8CH

Serial receive buffer: UART0

RXB

Undefined

Serial transmission shift register: UART0

TXS

Serial shift register: IOE1

SIO1

R/W

0FF8DH

Serial receive buffer: UART2

RXB2

Serial transmission shift register: UART2

TXS2

Serial shift register: IOE2

SIO2

R/W

0FF90H

Baud rate generator control register

BRGC

00H

0FF91H

Baud rate generator control register 2

BRGC2

0FFA0H

External interrupt mode register 0

INTM0

0FFA1H

External interrupt mode register 1

INTM1

0FFA4H

Sampling clock selection register

SCS0

0FFA8H

In-service priority register

ISPR

0FFAAH

Interrupt mode control register

IMC

R/W

80H

0FFACH

Interrupt mask register 0L

MK0L MK0

FFFFH

0FFADH

Interrupt mask register 0H

MK0H

0FFAEH

Interrupt mask register 1L

MK1L

FFH

0FFC0H

Standby control register

STBC

Note 2

30H

0FFC2H

Watchdog timer mode register

WDM

Note 2

00H

0FFC4H

Memory expansion mode register

20H

0FFC5H

Hold mode register

HLDM

00H

0FFC6H

Clock output mode register

CLOM

0FFC7H

Programmable wait control register 1

PWC1

AAH

0FFC8H

Programmable wait control register 2

PWC2

AAAAH

Table 7-1. Special Function Registers (SFRs) (3/4)

Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV

WDM,#byte. Other instructions cannot perform a write operation.

PD784035, 784036, 784037, 784038

Table 7-1. Special Function Registers (SFRs) (4/4)

Note

Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is

executed, F0000H is added to each address.

Address

Note

Special function register (SFR) name

Abbreviation

R/W

Manipulatable bits

When reset

1 bit

8 bits 16 bits

0FFCCH

Refresh mode register

RFM

R/W

00H

0FFCDH

Refresh area specification register

RFA

0FFCFH

Oscillation settling time specification register

OSTS

0FFD0H-

External SFR area

0FFDFH

0FFE0H

Interrupt control register (INTP0)

PIC0

43H

0FFE1H

Interrupt control register (INTP1)

PIC1

0FFE2H

Interrupt control register (INTP2)

PIC2

0FFE3H

Interrupt control register (INTP3)

PIC3

0FFE4H

Interrupt control register (INTC00)

CIC00

0FFE5H

Interrupt control register (INTC01)

CIC01

0FFE6H

Interrupt control register (INTC10)

CIC10

0FFE7H

Interrupt control register (INTC11)

CIC11

0FFE8H

Interrupt control register (INTC20)

CIC20

0FFE9H

Interrupt control register (INTC21)

CIC21

0FFEAH

Interrupt control register (INTC30)

CIC30

0FFEBH

Interrupt control register (INTP4)

PIC4

0FFECH

Interrupt control register (INTP5)

PIC5

0FFEDH

Interrupt control register (INTAD)

ADIC

0FFEEH

Interrupt control register (INTSER)

SERIC

0FFEFH

Interrupt control register (INTSR)

SRIC

Interrupt control register (INTCSI1)

CSIIC1

0FFF0H

Interrupt control register (INTST)

STIC

0FFF1H

Interrupt control register (INTCSI)

CSIIC

0FFF2H

Interrupt control register (INTSER2)

SERIC2

0FFF3H

Interrupt control register (INTSR2)

SRIC2

Interrupt control register (INTCSI2)

CSIIC2

0FFF4H

Interrupt control register (INTST2)

STIC2

PD784035, 784036, 784037, 784038

Table 8-1. Port Functions

8.2 Clock Generator

A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency

divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed

operation is not necessary.

Figure 8-2. Block Diagram of Clock Generator

Remark f

: Oscillator frequency or external clock input frequency

CLK

: Internal operating frequency

Port name

Function

Pull-up specification by software

Port 0

P00-P07

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

· Operable as 4-bit real-time outputs

input mode.

(P00-P03, P04-P07)

· Capable of driving transistors

Port 1

P10-P17

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

· Capable of driving LEDs

input mode.

Port 2

P20-P27

· Input port

Specified for the 6 bits (P22-P27) as a batch.

Port 3

P30-P37

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

input mode.

Port 4

P40-P47

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

· Capable of driving LEDs

input mode.

Port 5

P50-P57

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

· Capable of driving LEDs

input mode.

Port 6

P60-P67

· Bit-by-bit input/output setting supported

Specified as a batch for all pins placed in

input mode.

Port 7

P70-P77

· Bit-by-bit input/output setting supported

CLK

CPU
Peripheral circuits

Oscillator

UART/IOE
INTP0 noise eliminator
Oscillation settling timer

Selector

1/2

PD784035, 784036, 784037, 784038

Figure 8-5. Timer/Counter Block Diagram

Timer/counter 0

Timer/counter 1

Timer/counter 2

Timer 3

Remark OVF: Overflow flag

TO1

OVF

TO0

INTP3

INTC00

INTC01

Clear information

Prescaler

Selector

Timer register 0

(TM0)

Software trigger

Compare register

(CR00)

Match

Pulse output control

Compare register

(CR01)

Edge
detection

Capture register

(CR02)

Timer register 3

(TM3/TM3W)

Compare register

(CR30/CR30W)

Prescaler

CSI

Clear

Match

INTC30

OVF

INTP0

INTC10

INTC11

Clear information

Prescaler

Selector

Timer register 1

(TM1/TM1W)

Event input

Compare register

(CR10/CR10W)

Match

Edge
detection

Capture/compare register

(CR11/CR11W)

To real-time
output port

Capture register

(CR12/CR12W)

TO3

OVF

TO2

INTP1

INTC20

INTC21

INTP2/C1

INTP2

Clear information

Prescaler

Selector

Timer register 2

(TM2/TM2W)

Edge
detection

Compare register

(CR20/CR20W)

Match

Capture/compare register

(CR21/CR21W)

Pulse output control

Capture register

(CR22/CR22W)

PD784035, 784036, 784037, 784038

8.6 A/D Converter

An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated.

The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D

conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time

is about 7.5

s at f

CLK

= 16 MHz.)

A/D conversion can be started in any of the following modes:

· Hardware start : Conversion is started by means of trigger input (INTP5).

· Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM).

After conversion has started, one of the following modes can be selected:

· Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins.

· Select mode: A single analog input is selected at all times to enable conversion data to be obtained

continuously.

ADM is used to specify the above modes, as well as the termination of conversion.

When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,

the results of conversion can be continuously transferred to memory by the macro service.

Figure 8-7. Block Diagram of A/D Converter

ANI0

ANI7

INTP5

REF1

R/2

Input selector

Tap selector

Sample-and-hold circuit

Voltage comparator

Successive conver-
sion register (SAR)

Series resistor string

Control
circuit

A/ D converter mode
register (ADM)

A/ D conversion
result register (ADCR)

Internal bus

Edge
detector

Conversion
trigger

Trigger enable

INTAD

ANI1
ANI2
ANI3
ANI4
ANI5
ANI6

PD784035, 784036, 784037, 784038

8.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE)

Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire

serial I/O mode can be selected.

(1) Asynchronous serial interface mode

In this mode, 1-byte data is transferred after a start bit.

A baud rate generator is incorporated to enable communication at a wide range of baud rates.

Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate.

With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.

Figure 8-10. Block Diagram of Asynchronous Serial Interface Mode

Remark f

: Oscillator frequency or external clock input frequency

n = 0 to 11

m = 16 to 30

RXB, RXB2

TXS, TXS2

INTST, INTST2

INTSR,
INTSR2
INTSER,
INTSER2

1/2m

ASCK, ASCK2

TxD, TxD2

RxD, RxD2

1/2

n+1

1/2m

Baud rate generator

Receive
shift register

Receive buffer

Selector

Transmission
control parity
bit addition

Transmission
shift register

Internal bus

Reception
control parity
check

PD784035, 784036, 784037, 784038

(1) Three-wire serial I/O mode

This mode is designed for communication with a device incorporating a conventional synchronous serial interface.

Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0).

In general, a handshake line is required to check the communication state.

(2) Two-wire serial I/O mode

In this mode, 8-bit data is transferred using two lines: the serial clock line (SCL) and serial data bus (SDA).

In general, a handshake line is required to check the communication state.

8.9 Clock Output Function

The frequency of the CPU clock signal can be divided for output to a point external to the system. Moreover, the

port can be used as a 1-bit port.

The ASTB pin is also used for the CLKOUT pin, so that when this function is used, the local bus interface cannot

be used.

Figure 8-13. Block Diagram of Clock Output Function

CLKOUT

CLK

/16

Selector

Output control

Enable output

Output level

PD784035, 784036, 784037, 784038

8.10 Edge Detection Function

The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals

for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge

detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection

caused by noise.

Note

INTP0 is used for sampling clock selection.

8.11 Watchdog Timer

A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within

a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled,

it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the

watchdog timer or on an interrupt based on the NMI pin.

Figure 8-14. Block Diagram of Watchdog Timer

Detectable edge

Noise suppression method

NMI

Rising edge or falling edge

Analog delay

INTP0-INTP3

Rising edge or falling edge, or both edges

Clock sampling

Note

INTP4, INTP5

Analog delay

CLK

INTWDT

CLK

Timer

Clear signal

Selector

PD784035, 784036, 784037, 784038

9. INTERRUPT FUNCTION

Table 9-1 lists the interrupt request handling modes. These modes are selected by software.

Table 9-1. Interrupt Request Handling Modes

9.1 Interrupt Source

An interrupt can be issued from any one of the interrupt sources listed in Table 9-2: execution of a BRK instruction

and BRKCS instruction, an operand error, or any of the 23 other interrupt sources.

Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling

or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension.

When interrupt requests having the same priority level are generated, they are handled according to the default

priority (fixed). (See Table 9-2.)

Handling mode

Handled by

Handling

PC and PSW contents

Vectored interrupt

Software

Branches to a handling routine for execution

The PC and PSW contents are pushed

(arbitrary handling).

to and popped from the stack.

Context switching

Automatically selects a register bank, and

The PC and PSW contents are saved to

branches to a handling routine for execution

and read from a fixed area in the

(arbitrary handling).

Macro service

Firmware

Performs operations such as memory-to-I/O-

Maintained

device data transfer (fixed handling).

PD784035, 784036, 784037, 784038

Table 9-2. Interrupt Sources

Type

Default

Source

Internal/

Macro

priority

Name

Trigger

external

service

Software

BRK instruction

Instruction execution

BRKCS instruction

Operand error

When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION

instruction is executed, exclusive OR of the byte operand and byte

does not produce FFH.

Nonmaskable

NMI

Detection of edge input on the pin

External

WDT

Watchdog timer overflow

Internal

Maskable

0 (highest)

INTP0

Detection of edge input on the pin

External

Enabled

(TM1/TM1W capture trigger, TM1/TM1W event counter input)

INTP1

Detection of edge input on the pin

(TM2/TM2W capture trigger, TM2/TM2W event counter input)

INTP2

Detection of edge input on the pin

(TM2/TM2W capture trigger, TM2/TM2W event counter input)

INTP3

Detection of edge input on the pin

(TM0 capture trigger, TM0 event counter input)

INTC00

TM0-CR00 match signal issued

Internal

Enabled

INTC01

TM0-CR01 match signal issued

INTC10

TM1-CR10 match signal issued (in 8-bit operation mode)

TM1W-CR10W match signal issued (in 16-bit operation mode)

INTC11

TM1-CR11 match signal issued (in 8-bit operation mode)

TM1W-CR11W match signal issued (in 16-bit operation mode)

INTC20

TM2-CR20 match signal issued (in 8-bit operation mode)

TM2W-CR20W match signal issued (in 16-bit operation mode)

INTC21

TM2-CR21 match signal issued (in 8-bit operation mode)

TM2W-CR21W match signal issued (in 16-bit operation mode)

INTC30

TM3-CR30 match signal issued (in 8-bit operation mode)

TM3W-CR30W match signal issued (in 16-bit operation mode)

INTP4

Detection of edge input on the pin

External

Enabled

INTP5

Detection of edge input on the pin

INTAD

A/D converter processing completed (ADCR transfer)

Internal

Enabled

INTSER

ASI0 reception error

INTSR

ASI0 reception completed or CSI1 transfer completed

Enabled

INTCSI1

INTST

ASI0 transmission completed

INTCSI

CSI0 transfer completed

INTSER2

ASI2 reception error

INTSR2

ASI2 reception completed or CSI2 transfer completed

Enabled

INTCSI2

20 (lowest)

INTST2

ASI2 transmission completed

Remark ASI: Asynchronous serial interface

CSI: Synchronous serial interface

PD784035, 784036, 784037, 784038

9.2 Vectored Interrupt

When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt

source is used as the branch address.

Interrupt handling by the CPU consists of the following operations :

· When a branch occurs

: Push the CPU status (PC and PSW contents) to the stack.

· When control is returned : Pop the CPU status (PC and PSW contents) from the stack.

To return control from the handling routine to the main routine, use the RETI instruction. The branch destination

addresses must be within the range of 0 to FFFFH.

Table 9-3. Vector Table Address

Interrupt source

Vector table address

BRK instruction

003EH

Operand error

003CH

NMI

0002H

WDT

0004H

INTP0

0006H

INTP1

0008H

INTP2

000AH

INTP3

000CH

INTC00

000EH

INTC01

0010H

INTC10

0012H

INTC11

0014H

INTC20

0016H

INTC21

0018H

INTC30

001AH

INTP4

001CH

INTP5

001EH

INTAD

0020H

INTSER

0022H

INTSR

0024H

INTCSI1

INTST

0026H

INTCSI

0028H

INTSER2

002AH

INTSR2

002CH

INTCSI2

INTST2

002EH

PD784035, 784036, 784037, 784038

9.3 Context Switching

When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank

is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same

time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register

bank.

The branch address must be within the range of 0 to FFFFH.

Figure 9-1. Context Switching Caused by an Interrupt Request

9.4 Macro Service

The macro service function enables data transfer between memory and special function registers (SFRs) without

requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same

transfer cycle to directly transfer data without having to perform data fetch.

Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is

possible.

Figure 9-2. Macro Service

PSW

PC19-16

0000B

PC15-0

Exchange

Save

Transfer

(Bits 8 to 11 of
temporary register)

Temporary register

Switching between register banks

(RBS0-RBS2

RSS

CPU

SFR

Memory

Read

Write

Read

Write

Macro service
controller

Internal bus

PD784035, 784036, 784037, 784038

9.5 Examples of Macro Service Applications

(1) Serial interface transmission

Each time macro service request (INTST) is generated, the next transmission data is transferred from memory

to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer

becomes empty), vectored interrupt request (INTST) is generated.

(2) Serial interface reception

Each time macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When

data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full),

vectored interrupt request (INTSR) is generated.

Transmission data storage buffer (memory)

INTST

TXS (SFR)

TxD

Data n

Data n-1

Data 2

Data 1

Internal bus

Transmission

shift register

Transmission control

Reception data storage buffer (memory)

INTSR

RXB (SFR)

RxD

Data n

Data n-1

Data 2

Data 1

Internal bus

Reception buffer

Reception
shift register

Reception control

PD784035, 784036, 784037, 784038

(3) Real-time output port

INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro

service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used

to independently control two stepping motors. They can also be applied to PWM and DC motor control.

Each time macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer

match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When T

(last

byte) is transferred to CR10, vectored interrupt request (INTC10) is generated.

For INTC11, the same operation as that performed for INTC10 is performed.

Match

(SFR)

INTC10

P00-P03

(SFR)

Output pattern profile (memory)

Output timing profile (memory)

Internal bus

P0L

Output latch

CR10

TM1

Internal bus

PD784035, 784036, 784037, 784038

10.3 Programmable Wait

When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory

space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even

when memory devices having different access times are connected.

In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer

address decode time. (This function is set for the entire space.)

10.4 Pseudo-Static RAM Refresh Function

Refresh is performed as follows:

· Pulse refresh

: A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular

intervals. When the memory space is divided into eight, and a specified area

is being accessed, refresh pulses can also be output on the REFRQ pin as the

memory is being accessed. This can prevent the refresh cycle from suspending

normal memory access.

· Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the

contents of pseudo-static RAM.

10.5 Bus Hold Function

A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus

hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus

cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance

state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master.

While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.

PD784035, 784036, 784037, 784038

11. STANDBY FUNCTION

The standby function allows the power consumption of the chip to be reduced. The following standby modes are

supported:

· HALT mode : The CPU operation clock is stopped. By occasionally inserting the HALT mode during normal

operation, the overall average power consumption can be reduced.

· IDLE mode : The entire system is stopped, with the exception of the oscillator circuit. This mode consumes

only very little more power than STOP mode, but normal program operation can be restored in

almost as little time as that required to restore normal program operation from HALT mode.

· STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows.

These modes can be selected by software.

A macro service can be initiated in HALT mode.

Figure 11-1. Standby Mode Status Transition

Notes 1. INTP4 and INTP5 are applied when not masked.

2. Only when the interrupt request is not masked

Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby

modes (STOP or IDLE mode).

STOP

(standby)

IDLE

(standby)

Request for masked interrupt

HALT

(standby)

NMI, INTP4, INTP5 input

Note 1

Set STOP

RESET input

Set IDLE

RESET input

NMI, INTP4, INTP5 input

Note 1

Oscillation settling

time elapses

Wait for

oscillation

settling

Program

operation

Macro service request

End of one operation

End of macro service

Macro

service

Set HALT

RESET input

Interrupt request

Note 2

Macro service request

End of one operation

PD784035, 784036, 784037, 784038

12. RESET FUNCTION

Applying a low-level signal to the RESET pin initializes the internal hardware (reset status).

When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):

· Eight low-order bits of the PC

: Contents of location at address 0000H

· Intermediate eight bits of the PC : Contents of location at address 0001H

· Four high-order bits of the PC

: 0

The PC contents are used as a branch destination address. Program execution starts from that address. Therefore,

a reset start can be performed from an arbitrary address.

The contents of each register can be set by software, as required.

The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator

is an analog delay sampling circuit.

Figure 12-1. Accepting a Reset

For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms)

has elapsed.

Figure 12-2. Power-On Reset

Oscillation settling time

Delay

Initialize PC

Execute instruction at
reset start address

RESET

(input)

Internal reset signal

End reset

RESET
(input)

Delay

Initialize PC

Execute instruction
at reset start address

Internal reset signal

Start reset

End reset

PD784035, 784036, 784037, 784038

13. INSTRUCTION SET

(1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of

operands, where A is described as r.)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC,

MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 13-1. Instructions Implemented by 8-Bit Addressing

2nd operand

#byte

saddr

sfr

!addr16

mem

[WHL+]

None

Note 2

saddr'

!!addr24

[saddrp]

PSWL

[WHL]

1st operand

[%saddrg]

PSWH

(MOV)

MOV

(MOV)

Note 6

MOV

(MOV)

MOV

(MOV)

ADD

Note 1

(XCH)

XCH

(XCH)

Note 6

(XCH)

XCH

(XCH)

(ADD)

Note 1

(ADD)

Note 1

(ADD)

Notes 1, 6

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

MOV

(MOV)

MOV

ROR

Note 3

MULU

ADD

Note 1

(XCH)

XCH

DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

INC

DEC

saddr

MOV

(MOV)

Note 6

MOV

INC

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

XCH

DEC

ADD

Note 1

DBNZ

sfr

MOV

PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16

MOV

(MOV)

MOV

!!addr24

ADD

Note 1

mem

MOV

[saddrp]

ADD

Note 1

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

(MOV)

MOVBK

Note 5

[TDE]

(ADD)

Note 1

MOVM

Note 4

Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.

2. There is no second operand, or the second operand is not an operand address.

3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.

4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.

5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.

6. When saddr is saddr2 with this combination, an instruction with a short code exists.

PD784035, 784036, 784037, 784038

(2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of

operands, where AX is described as rp.)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,

ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 13-2. Instructions Implemented by 16-Bit Addressing

2nd operand

#word

saddrp

sfrp

!addr16

mem

[WHL+]

byte

None

Note 2

rp'

saddrp'

!!addr24

[saddrp]

1st operand

[%saddrg]

(MOVW)

Note 3

MOVW

(MOVW)

MOVW

(MOVW)

ADDW

Note 1

(XCHW)

Note 3

(XCHW)

XCHW

(XCHW)

(ADD)

Note 1

(ADDW)

Note 1

(ADDW)

Notes 1,3

(ADDW)

Note 1

MOVW

(MOVW)

MOVW

SHRW

MULW

Note 4

ADDW

Note 1

(XCHW)

XCHW

SHLW

INCW

(ADDW)

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

DECW

saddrp

MOVW

(MOVW)

Note 3

MOVW

INCW

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

XCHW

DECW

ADDW

Note 1

sfrp

MOVW

PUSH

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. SUBW and CMPW are the same as ADDW.

2. There is no second operand, or the second operand is not an operand address.

3. When saddrp is saddrp2 with this combination, an instruction with a short code exists.

4. MULUW and DIVUX are the same as MULW.

PD784035, 784036, 784037, 784038

14. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Parameter

Symbol

Conditions

Rating

Unit

Supply voltage

-0.5 to +7.0

to V

+ 0.5

-0.5 to +0.5

Input voltage

-0.5 to V

+ 0.5

Output voltage

-0.5 to V

+ 0.5

Output low current

At one pin

Total of all output pins

100

Output high current

At one pin

-10

Total of all output pins

-100

A/D converter reference input

REF1

-0.5 to V

+ 0.3

voltage

REF2

-0.5 to V

+ 0.3

REF3

-0.5 to V

+ 0.3

Operating ambient temperature

-40 to +85

Storage temperature

stg

-65 to +150

D/A converter reference input

voltage

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even

momentarily, the quality of the product may deteriorate. Always use the product within its rated

values.

PD784035, 784036, 784037, 784038

OSCILLATOR CHARACTERISTICS (T

= -40 to +85

C, V

= +4.5 to 5.5 V, V

= 0 V)

Caution When using the system clock generator, run wires in the portion surrounded by broken lines

according to the following rules to avoid effects such as stray capacitance:

Minimize the wiring.

Never cause the wires to cross other signal lines.

Never cause the wires to run near a line carrying a large varying current.

Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

as V

SS1

. Never connect the capacitor to a ground pattern carrying a large current.

Never extract a signal from the oscillator.

Resonator

Ceramic resonator

or crystal

External clock

Recommended circuit

Parameter

Oscillator frequency (f

)

X1 input frequency (f

)

X1 input rise and fall times

, t

)

X1 input high-level and low-

level widths (t

WXH

, t

WXL

)

MIN.

MAX.

125

Unit

MHz

SS1

HCMOS
inverter

PD784035, 784036, 784037, 784038

OSCILLATOR CHARACTERISTICS (T

= -40 to +85

C, V

= +2.7 to 5.5 V, V

= 0 V)

Caution When using the system clock generator, run wires in the portion surrounded by broken lines

according to the following rules to avoid effects such as stray capacitance:

Minimize the wiring.

Never cause the wires to cross other signal lines.

Never cause the wires to run near a line carrying a large varying current.

Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

as V

SS1

. Never connect the capacitor to a ground pattern carrying a large current.

Never extract a signal from the oscillator.

Resonator

Ceramic resonator

or crystal

External clock

Recommended circuit

Parameter

Oscillator frequency (f

)

X1 input frequency (f

)

X1 input rise and fall times

, t

)

X1 input high-level and low-

level widths (t

WXH

, t

WXL

)

MIN.

MAX.

125

Unit

MHz

SS1

HCMOS
inverter

PD784035, 784036, 784037, 784038

DC CHARACTERISTICS (T

= -40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V) (1/2)

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST

2. P40/AD0-P47/AD7, P50/A8-P57/A15

3. P60/A16-P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK

4. P00-P07

5. P10-P17

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

X1 input low current

X1 input high current

Symbol

IL1

IL2

IL3

IH1

IH2

IH3

OL1

OL2

OH1

OH2

Conditions

For pins other than those described in

Notes 1, 2, 3, and 4

For pins described in Notes 1, 2, 3, and

= +5.0 V

10 %

For pins described in Notes 2, 3, and 4

For pins other than those described in

Note 1

For pins described in Note 1

= +5.0 V

10 %

For pins described in Notes 2, 3, and 4

= 2 mA

= +5.0 V

10 %

= 8 mA

For pins described in Notes 2 and 5

= -2 mA

= +5.0 V

10 %

= -5 mA

For pins described in Note 4

EXTC = 0

0 V

IL2

EXTC = 0

IH2

MIN.

-0.3

0.7V

0.8V

2.2

- 1.0

- 1.4

TYP.

MAX.

0.3V

0.2V

+0.8

+ 0.3

0.4

1.0

-30

+30

Unit

PD784035, 784036, 784037, 784038

AC CHARACTERISTICS (T

= -40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Remarks

T: T

CYK

(system clock cycle time)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Unit

Parameter

Address setup time

ASTB high-level width

Address hold time (to ASTB

)

Address hold time (to RD

)

Delay from address to RD

Address float time (to RD

)

Delay from address to data input

Delay from ASTB

to data input

Delay from RD

to data input

Delay from ASTB

to RD

Data hold time (to RD

)

Delay from RD

to address active

Delay from RD

to ASTB

RD low-level width

Address hold time (to WR

)

Delay from address to WR

Delay from ASTB

to data output

Delay from WR

to data output

Delay from ASTB

to WR

Symbol

SAST

WSTH

HSTLA

HRA

DAR

FRA

DAID

DSTID

DRID

DSTR

HRID

DRA

DRST

WRL

HWA

DAW

DSTOD

DWOD

DSTW

MIN.

(0.5 + a) T - 15

(0.5 + a) T - 31

(0.5 + a) T - 17

(0.5 + a) T - 40

0.5T - 24

0.5T - 34

0.5T - 14

(1 + a) T - 9

(1 + a) T - 15

0.5T - 9

0.5T - 8

0.5T - 12

1.5T - 8

1.5T - 12

0.5T - 17

(1.5 + n) T - 30

(1.5 + n) T - 40

0.5T - 14

(1 + a) T - 5

(1 + a) T - 15

0.5T - 9

MAX.

(2.5 + a + n) T - 37

(2.5 + a + n) T - 52

(2 + n) T - 40

(2 + n) T - 60

(1.5 + n) T - 50

(1.5 + n) T - 70

0.5T + 19

0.5T + 35

0.5T - 11

After program

is read

After data is

read

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

PD784035, 784036, 784037, 784038

(1) Read/write operation (2/2)

Note

The hold time includes the time during which V

OH1

and V

OL1

are held under the load conditions of

= 50 pF and R

= 4.7 k

Remarks

T: T

CYK

(system clock cycle time)

n: Number of wait states (n

(2) Bus hold timing

Remarks

T: T

CYK

(system clock cycle time)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Unit

Parameter

Data setup time (to WR

)

Data hold time (to WR

)

Note

Delay from WR

to ASTB

WR low-level width

Symbol

SODW

HWOD

DWST

WWL

MIN.

(1.5 + n) T - 30

(1.5 + n) T - 40

0.5T - 5

0.5T - 25

0.5T - 12

(1.5 + n) T - 30

(1.5 + n) T - 40

MAX.

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

Unit

Parameter

Delay from HLDRQ

to float

Delay from HLDRQ

to HLDAK

Delay from float to HLDAK

Delay from HLDRQ

to HLDAK

Delay from HLDAK

to active

MIN.

1T - 20

1T - 30

MAX.

(6 + a + n) T + 50

(7 + a + n) T + 30

(7 + a + n) T + 40

1T + 30

2T + 40

2T + 60

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

Symbol

FHQC

DHQHHAH

DCFHA

DHQLHAL

DHAC

PD784035, 784036, 784037, 784038

(3) External wait timing

Remarks

T: T

CYK

(system clock cycle time)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

(4) Refresh timing

Remark

T: T

CYK

(system clock cycle time)

Parameter

Delay from address to WAIT

input

Delay from ASTB

to WAIT

input

Hold time from ASTB

to WAIT

Delay from ASTB

to WAIT

Delay from RD

to WAIT

input

Hold time from RD

to WAIT

Delay from RD

to WAIT

Delay from WAIT

to data input

Delay from WAIT

to WR

Delay from WAIT

to RD

Delay from WR

to WAIT

input

Hold time from WR

to WAIT

Delay from WR

to WAIT

Unit

MIN.

(0.5 + n) T + 5

(0.5 + n) T +10

nT + 5

nT + 10

0.5T

nT + 5

nT + 10

MAX.

(2 + a) T - 40

(2 + a) T - 60

1.5T - 40

1.5T - 60

(1.5 + n) T - 40

(1.5 + n) T - 60

T - 50

T - 70

(1 + n) T - 40

(1 + n) T - 60

0.5T - 5

0.5T - 10

T - 50

T - 75

(1 + n) T - 40

(1 + n) T - 70

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

Symbol

DAWT

DSTWT

HSTWTH

DSTWTH

DRWTL

HRWT

DRWTH

DWTID

DWTW

DWTR

DWWTL

HWWT

DWWTH

Unit

Parameter

Random read/write cycle time

REFRQ low-level pulse width

Delay from ASTB

to REFRQ

Delay from RD

to REFRQ

Delay from WR

to REFRQ

Delay from REFRQ

to ASTB

REFRQ high-level pulse width

MAX.

MIN.

1.5T - 25

1.5T - 30

0.5T - 9

1.5T - 9

0.5T - 15

1.5T - 25

1.5T - 30

Symbol

WRFQL

DSTRFQ

DRRFQ

DWRFQ

DRFQST

WRFQH

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

PD784035, 784036, 784037, 784038

SERIAL OPERATION (T

= -40 to +85

C, V

= +2.7 to 5.5 V, AV

= V

= 0 V)

(1) CSI

Remarks 1. The values in this table are those when C

is 100 pF.

2. T : Serial clock cycle set by software. The minimum value is 16/f

3. f

: Oscillator frequency

Unit

Parameter

Serial clock cycle time (SCK0)

Serial clock low-level width

(SCK0)

Serial clock high-level width

(SCK0)

SI0 setup time (to SCK0

)

SI0 hold time (to SCK0

)

SO0 output delay time

(to SCK0

)

MIN.

10/f

+ 380

5/f

+ 150

0.5T - 40

5/f

+ 150

0.5T - 40

5/f

+ 40

MAX.

5/f

+ 150

5/f

+ 400

Conditions

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

CMOS push-pull output

(3-wire serial I/O mode)

Open-drain output

(2-wire serial I/O mode), R

= 1 k

Symbol

CYSK0

WSKL0

WSKH0

SSSK0

HSSK0

DSBSK1

DSBSK2

PD784035, 784036, 784037, 784038

(2) IOE1, IOE2

Remarks 1. The values in this table are those when C

is 100 pF.

2. T: Serial clock cycle set by software. The minimum value is 16/f

(3) UART, UART2

Unit

MIN.

250

500

210

0.5T - 40

210

0.5T - 40

0.5t

CYSK1

- 40

MAX.

Symbol

CYSK1

WSKL1

WSKH1

SSSK1

HSSK1

DSOSK

HSOSK

Conditions

Input

= +5.0 V

10 %

Output

Internal, divided by 16

Input

= +5.0 V

10 %

Output

Internal, divided by 16

Input

= +5.0 V

10 %

Output

Internal, divided by 16

When data is transferred

Unit

Parameter

ASCK clock input cycle time

ASCK clock low-level width

ASCK clock high-level width

Symbol

CYASK

WASKL

WASKH

MIN.

125

250

52.5

MAX.

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

Parameter

Serial clock cycle time

(SCK1, SCK2)

Serial clock low-level width

(SCK1, SCK2)

Serial clock high-level width

(SCK1, SCK2)

Setup time for SI1 and SI2

(to SCK1, SCK2

)

Hold time for SI1 and SI2

(to SCK1, SCK2

)

Output delay time for SO1 and

SO2 (to SCK1, SCK2

)

Output hold time for SO1 and

SO2 (to SCK1, SCK2

)

PD784035, 784036, 784037, 784038

CLOCK OUTPUT OPERATION

Remarks n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)

T: T

CYK

(system clock cycle time)

OTHER OPERATIONS

Remarks t

CYSMP

: Sampling clock set by software

CYCPU

: CPU operation clock set by software in the CPU

Unit

Parameter

CLKOUT cycle time

CLKOUT low-level width

CLKOUT high-level width

CLKOUT rise time

CLKOUT fall time

MIN.

0.5t

CYCL

- 10

0.5t

CYCL

- 20

0.5t

CYCL

- 10

0.5t

CYCL

- 20

MAX.

Conditions

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

= +5.0 V

10 %

Symbol

CYCL

CLL

CLH

CLR

CLF

Unit

Parameter

NMI low-level width

NMI high-level width

INTP0 low-level width

INTP0 high-level width

Low-level width for INTP1-

INTP3 and CI

High-level width for INTP1-

INTP3 and CI

Low-level width for INTP4 and

INTP5

High-level width for INTP4 and

INTP5

RESET low-level width

RESET high-level width

Symbol

WNIL

WNIH

WIT0L

WIT0H

WIT1L

WIT1H

WIT2L

WIT2H

WRSL

WRSH

MIN.

CYSMP

CYCPU

MAX.

Conditions

PD784035, 784036, 784037, 784038

80 PIN PLASTIC QFP (14

14)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

P80GC-65-8BT

0.825

0.032

14.00

0.20

0.551+0.009

0.008

1.70 MAX.

0.067 MAX.

0.17

0.007+0.001

0.003

+0.03

0.07

+0.009

0.008

14.00

0.20

0.551+0.009

0.008

17.20

0.20

0.677

0.008

0.825

0.032

0.32

0.06

0.013+0.002

0.003

0.13

0.005

0.65 (T.P.)

0.026 (T.P.)

1.60

0.20

0.063

0.008

0.80

0.20

0.031+0.009

0.008

0.10

0.004

1.40

0.10

0.055

0.004

0.125

0.075

0.005

0.003

17.20

0.20

0.677

0.008

detail of lead end

Remark The shape and material of the ES version are the same as those of the corresponding mass-produced

product.

PD784035, 784036, 784037, 784038

16. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the

PD784035,

PD784036,

PD784037, or

PD784038.

For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting

Technology Manual (C10535E).

Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under

different conditions.

Table 16-1. Soldering Conditions for Surface-Mount Devices (1/2)

(1)

PD784035GC-

×××

-3B9: 80-pin plastic QFP (14

2.7 mm)

PD784036GC-

×××

-3B9: 80-pin plastic QFP (14

2.7 mm)

PD784037GC-

×××

-3B9: 80-pin plastic QFP (14

2.7 mm)

PD784038GC-

×××

-3B9: 80-pin plastic QFP (14

2.7 mm)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

(2)

PD784035GC-

×××

-8BT: 80-pin plastic QFP (14

1.4 mm)

PD784036GC-

×××

-8BT: 80-pin plastic QFP (14

1.4 mm)

PD784037GC-

×××

-8BT: 80-pin plastic QFP (14

1.4 mm)

PD784038GC-

×××

-8BT: 80-pin plastic QFP (14

1.4 mm)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak package's surface temperature: 235

IR35-00-3

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 3

VPS

Peak package's surface temperature: 215

VP15-00-3

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 3

Wave soldering

Solder temperature: 260

C or less

WS60-00-1

Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature

: 120

C max. (measured on the package surface)

Partial heating method

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

Soldering process

Soldering conditions

Symbol

Infrared ray reflow

Peak package's surface temperature: 235

IR35-00-2

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 2

VPS

Peak package's surface temperature: 215

VP15-00-2

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 2

Wave soldering

Solder temperature: 260

C or less

WS60-00-1

Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature

: 120

C max. (measured on the package surface)

Partial heating method

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

PD784035, 784036, 784037, 784038

Table 16-1. Soldering Conditions for Surface-Mount Devices (2/2)

(3)

PD784035GK-

×××

-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784036GK-

×××

-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784037GK-

×××

-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784038GK-

×××

-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

Note

Maximum number of days during which the product can be stored at a temperature of 25

C and a relative

humidity of 65 % or less after dry-pack package is opened.

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

Soldering process

Infrared ray reflow

VPS

Partial heating method

Symbol

IR35-107-2

VP15-107-2

Soldering conditions

Peak package's surface temperature: 235

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 2

Exposure limit: 7 days

Note

(10 hours of pre-baking is required at 125

afterward)

Non-heat-resistant trays, such as magazine and taping trays, cannot be

baked before unpacking.

Peak package's surface temperature: 215

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 2

Exposure limit: 7 days

Note

(10 hours of pre-baking is required at 125

afterward)

Non-heat-resistant trays, such as magazine and taping trays, cannot be

baked before unpacking.

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

PD784035, 784036, 784037, 784038

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD784038.

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Document Outline

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