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COVER
MAJOR REVISIONS IN THIS EDITION
INTRODUCTION
CHAPTER 1 GENERAL
- 1.1 Features
- 1.2 Ordering Information
- 1.3 Quality Grades
- 1.4 Pin Configuration (Top View)
- 1.5 System Configuration Example (PPC)
- 1.6 Block Diagram
- 1.7 List of Functions
- 1.8 Differences between uPD784054 and uPD784046 Subseries
- 1.9 Differences between uPD784054 and uPD784054(A)
- 1.10 Differences between uPD784054(A), 784054(A1), and 784054(A2)
CHAPTER 2 PIN FUNCTIONS
- 2.1 List of Pin Functions
- 2.2 Description of Pin Functions
- 2.3 I/O Circuits of Pins and Processing of Unused Pins
CHAPTER 3 CPU ARCHITECTURE
- 3.1 Memory Space
- 3.2 Internal ROM Area
- 3.3 Base Area
  - 3.3.1 Vector table area
  - 3.3.2 CALLT instruction table area
  - 3.3.3 CALLF instruction entry area
- 3.4 Internal Data Area
  - 3.4.1 Internal RAM area
  - 3.4.2 Special function register (SFR) area
  - 3.4.3 External SFR area
- 3.5 External Memory Space
- 3.6 Control Registers
  - 3.6.1 Program counter (PC)
  - 3.6.2 Program status word (PSW)
  - 3.6.3 Use of RSS bit
  - 3.6.4 Stack pointer (SP)
- 3.7 General-Purpose Registers
  - 3.7.1 Configuration
  - 3.7.2 Functions
- 3.8 Special Function Registers (SFRs)
- 3.9 Cautions
CHAPTER 4 CLOCK GENERATOR
- 4.1 Configuration and Function
- 4.2 Control Registers
  - 4.2.1 Standby control register (STBC)
  - 4.2.2 Oscillation stabilization time specification register (OSTS)
- 4.3 Clock Generator Operation
  - 4.3.1 Clock oscillator
  - 4.3.2 Frequency divider
- 4.4 Cautions
  - 4.4.1 When an external clock is input
  - 4.4.2 When crystal/ceramic oscillation is used
CHAPTER 5 PORT FUNCTIONS
- 5.1 Digital Input/Output Port
- 5.2 Port 0
  - 5.2.1 Hardware configuration
  - 5.2.2 Input/output mode/control mode setting
  - 5.2.3 Operating status
  - 5.2.4 Internal pull-up resistors
- 5.3 Port 1
  - 5.3.1 Hardware configuration
  - 5.3.2 Setting I/O mode/control mode
  - 5.3.3 Operating status
- 5.4 Port 2
  - 5.4.1 Hardware configuration
  - 5.4.2 Setting I/O mode/control mode
  - 5.4.3 Operating status
- 5.5 Port 3
  - 5.5.1 Hardware configuration
  - 5.5.2 Input/output mode/control mode setting
  - 5.5.3 Operating status
- 5.6 Port 4
  - 5.6.1 Hardware configuration
  - 5.6.2 Input/output mode/control mode setting
  - 5.6.3 Operating status
  - 5.6.4 Internal pull-up resistors
- 5.7 Port 5
  - 5.7.1 Hardware configuration
  - 5.7.2 Input/output mode/control mode setting
  - 5.7.3 Operating status
  - 5.7.4 Internal pull-up resistors
- 5.8 Port 6
  - 5.8.1 Hardware configuration
  - 5.8.2 Setting of I/O mode/control mode
  - 5.8.3 Operating status
  - 5.8.4 Internal pull-up resistors
- 5.9 Port 7
  - 5.9.1 Hardware configuration
  - 5.9.2 Notes
- 5.10 Port 8
  - 5.10.1 Hardware configuration
  - 5.10.2 Cautions
- 5.11 Port 9
  - 5.11.1 Hardware configuration
  - 5.11.2 Setting of I/O mode/control mode
  - 5.11.3 Operating status
  - 5.11.4 Internal pull-up resistor
- 5.12 Port Output Data Check Function
- 5.13 Cautions
CHAPTER 6 OUTLINE OF TIMER
CHAPTER 7 TIMER 0
- 7.1 Function
- 7.2 Configuration
- 7.3 Timer 0 Control Register
- 7.4 Operation of Timer Register 0 (TM0)
  - 7.4.1 Basic operation
  - 7.4.2 Clear operation
- 7.5 Operation of Capture/Compare Register
  - 7.5.1 Compare operation
  - 7.5.2 Capture operation
- 7.6 Basic Operation of Output Control Circuit
  - 7.6.1 Basic operation
  - 7.6.2 Toggle output
  - 7.6.3 Set/reset output
- 7.7 Examples of Use
  - 7.7.1 Operation as interval timer
  - 7.7.2 Pulse width measurement operation
- 7.8 Cautions
CHAPTER 8 TIMER 1
- 8.1 Function
- 8.2 Configuration
- 8.3 Timer 1 Control Register
- 8.4 Operation of Timer Register 1 (TM1)
  - 8.4.1 Basic operation
  - 8.4.2 Clear operation
- 8.5 Operation of Compare Register
- 8.6 Basic Operation of Output Control Circuit
  - 8.6.1 Basic operation
  - 8.6.2 Toggle output
  - 8.6.3 Set/reset output
- 8.7 Examples of Use
  - 8.7.1 Operation as interval timer (1)
  - 8.7.2 Operation as interval timer (2)
- 8.8 Cautions
CHAPTER 9 TIMER 4
- 9.1 Function
- 9.2 Configuration
- 9.3 Timer 4 Control Register
- 9.4 Operation of Timer Register 4 (TM4)
  - 9.4.1 Basic operation
  - 9.4.2 Clear operation
- 9.5 Operation of Compare Register
- 9.6 Example of Use
  - 9.6.1 Operation as interval timer (1)
  - 9.6.2 Operation as interval timer (2)
- 9.7 Cautions
CHAPTER 10 WATCHDOG TIMER FUNCTION
- 10.1 Configuration
- 10.2 Watchdog Timer Mode Register (WDM)
- 10.3 Operation
  - 10.3.1 Count operation
  - 10.3.2 Interrupt priorities
- 10.4 Cautions
  - 10.4.1 General cautions on use of watchdog timer
  - 10.4.2 Cautions on uPD784054 watchdog timer
CHAPTER 11 A/D CONVERTER
- 11.1 Configuration
- 11.2 A/D Converter Mode Register (ADM)
- 11.3 A/D Conversion Result Registers (ADCR0 through ADCR7)
- 11.4 Operation
  - 11.4.1 Basic A/D converter operation
  - 11.4.2 Select mode
  - 11.4.3 Scan mode
  - 11.4.4 A/D conversion operation start by software
  - 11.4.5 A/D conversion operation start by hardware
- 11.5 External Circuit of A/D Converter
- 11.6 Cautions
CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
- 12.1 Switching between Asynchronous Serial Interface Mode and 3-wire Serial I/O Mode
- 12.2 Asynchronous Serial Interface Mode
  - 12.2.1 Configuration in asynchronous serial interface mode
  - 12.2.2 Asynchronous serial interface control registers
  - 12.2.3 Data format
  - 12.2.4 Parity types and operations
  - 12.2.5 Transmission
  - 12.2.6 Reception
  - 12.2.7 Receive errors
  - 12.2.8 Transmitting/receiving data with macro service
- 12.3 3-wire Serial I/O Mode
  - 12.3.1 Configuration in 3-wire serial I/O mode
  - 12.3.2 Clocked serial interface mode registers (CSIM1, CSIM2)
  - 12.3.3 Basic operation timing
  - 12.3.4 Operation when transmission only is enabled
  - 12.3.5 Operation when reception only is enabled
  - 12.3.6 Operation when transmission/reception is enabled
  - 12.3.7 Corrective action in case of slippage of serial clock and shift operations
- 12.4 Baud Rate Generator
  - 12.4.1 Baud rate generator configuration
  - 12.4.2 Baud rate generator control register
  - 12.4.3 Baud rate generator operation
  - 12.4.4 Baud rate setting in asynchronous serial interface mode
- 12.5 Cautions
CHAPTER 13 EDGE DETECTION FUNCTION
- 13.1 Edge Detection Function Control Registers
  - 13.1.1 External interrupt mode registers (INTM0, INTM1)
  - 13.1.2 Interrupt valid edge flag registers (IEF1, IEF2)
  - 13.1.3 Noise protection control register (NPC)
- 13.2 Edge Detection for Pin P20
- 13.3 Pin Edge Detection for Pins P21 to P27
- 13.4 Cautions
CHAPTER 14 INTERRUPT FUNCTIONS
- 14.1 Interrupt Request Sources
  - 14.1.1 Software interrupts
  - 14.1.2 Operand error interrupts
  - 14.1.3 Non-maskable interrupts
  - 14.1.4 Maskable interrupts
- 14.2 Interrupt Processing Modes
  - 14.2.1 Vectored interrupt processing
  - 14.2.2 Macro service
  - 14.2.3 Context switching
- 14.3 Interrupt Processing Control Registers
  - 14.3.1 Interrupt control registers
  - 14.3.2 Interrupt mask registers (MK0, MK1)
  - 14.3.3 In-service priority register (ISPR)
  - 14.3.4 Interrupt mode control register (IMC)
  - 14.3.5 Watchdog timer mode register (WDM)
  - 14.3.6 Program status word (PSW)
- 14.4 Software Interrupt Acknowledgment Operations
  - 14.4.1 BRK instruction software interrupt acknowledgment operation
  - 14.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation
- 14.5 Operand Error Interrupt Acknowledgment Operation
- 14.6 Non-Maskable Interrupt Acknowledgment Operation
- 14.7 Maskable Interrupt Acknowledgment Operation
  - 14.7.1 Vectored interrupt
  - 14.7.2 Context switching
  - 14.7.3 Maskable interrupt priority levels
- 14.8 Macro Service Function
  - 14.8.1 Outline of macro service function
  - 14.8.2 Types of macro service
  - 14.8.3 Basic operation of macro service (except CPU monitor modes 0 and 1)
  - 14.8.4 Operation on completion of macro servicing (except CPU monitor modes 0 and 1)
  - 14.8.5 Macro service control register
  - 14.8.6 Macro service mode
  - 14.8.7 Operation of macro service
- 14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending
- 14.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service
- 14.11 Interrupt and Macro Service Operation Timing
  - 14.11.1 Interrupt acceptance processing time
  - 14.11.2 Processing time of macro service
- 14.12 Restoring Interrupt Function To Initial State
- 14.13 Cautions
CHAPTER 15 LOCAL BUS INTERFACE FUNCTION
- 15.1 Memory Extension Function
  - 15.1.1 Memory extension mode register (MM)
  - 15.1.2 Memory map with external memory extension
  - 15.1.3 Basic operation of local bus interface
- 15.2 Wait Function
  - 15.2.1 Wait function control registers
  - 15.2.2 Address waits
  - 15.2.3 Access waits
- 15.3 Bus Sizing Function
  - 15.3.1 Bus width specification register (BW)
- 15.4 Cautions
CHAPTER 16 STANDBY FUNCTION
- 16.1 Configuration and Function
- 16.2 Control Registers
  - 16.2.1 Standby control register (STBC)
  - 16.2.2 Oscillation stabilization time specification register (OSTS)
- 16.3 HALT Mode
  - 16.3.1 HALT mode setting and operating states
  - 16.3.2 HALT mode release
- 16.4 STOP Mode
  - 16.4.1 STOP mode setting and operating states
  - 16.4.2 STOP mode release
- 16.5 IDLE Mode
  - 16.5.1 IDLE mode setting and operating states
  - 16.5.2 IDLE mode release
- 16.6 Check Items When STOP Mode/IDLE Mode Is Used
- 16.7 Cautions
CHAPTER 17 RESET FUNCTION
- 17.1 Reset Function
- 17.2 Caution
CHAPTER 18 uPD78F4046
- 18.1 Memory Mapping of uPD78F4046
- 18.2 Programming uPD78F4046
  - 18.2.1 Selecting communication mode
  - 18.2.2 Function of flash memory programming
  - 18.2.3 Connecting Flashpro II
- 18.3 Cautions
CHAPTER 19 INSTRUCTION OPERATIONS
- 19.1 Legend
- 19.2 List of Operations
- 19.3 Instructions Listed by Type of Addressing
CHAPTER 20 CAUTIONS ON USING DEVELOPMENT TOOLS
APPENDIX A DEVELOPMENT TOOLS
- A.1 Language Processing Software
- A.2 Flash Memory Writing Tools
- A.3 Debugging Tools
  - A.3.1 Hardware
  - A.3.2 Software
- A.4 Dimensions of Conversion Socket (EV-9200GC-80) and Recommended Board Mounting Pattern
APPENDIX B EMBEDDED SOFTWARE
APPENDIX C REGISTER INDEX
APPENDIX D REVISION HISTORY

PD784054

16-bit Single-chip Microcontrollers

Hardware

PD784054

PD784054(A)

PD784054(A1)

PD784054(A2)

Document No. U11719EJ2V0UM00 (2nd edition)
Date Published February 1998 N CP(K)

1996

User's Manual

Printed in Japan

[MEMO]

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions

need to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input

levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered to have a

possibility of being an output pin. All handling related to the unused pins must be judged device

by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until

the reset signal is received. Reset operation must be executed immediately after power-on for

devices having reset function.

IEBus is a trademark of NEC Corporation.

Windows and Windows NT are either registered trademarks or trademarks of Microsoft

Corporation in the United States and/or other countries.

PC/AT is a trademark of IBM Corporation.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

NEWS and NEWS-OS are trademarks of Sony Corporation.

Ethernet is a trademark of Zerox Corporation.

OSF/Motif is a trademark of Open Software Foundation, Inc.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M7 96.5

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000

800-366-9782

Fax: 408-588-6130

800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J97. 8

· Change of

PD784054 from "under development" to " development completed".

· Addition of the following products to the relevant products:

PD784054(A), 784054(A1), 784054(A2)

CHAPTER 1 GENERAL

· Change of 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM.

· Change of the minimum value of the supply voltage (V

) from 4.0 V to 4.5 V.

· Addition of 1.3 Quality Grades.

· Addition of 1.9 Differences between

PD784054 and

PD784054(A).

· Addition of 1.10 Differences between

PD784054(A), 784054(A1), and 784054(A2).

· Addition of the functional description of the CLKOUT pin in CHAPTER 2 PIN FUNCTIONS.

CHAPTER 7 TIMER 0

· Addition of description of the CLKOUT pin in (2) Capture/compare registers (CC00 through CC03) in 7.2

Configuration.

· Addition of caution when the timer output is enabled while the active level is changed.

· Addition of caution when the active level of the timer output is changed.

CHAPTER 8 TIMER 1

· Addition of caution when the timer output is enabled while the active level is changed.

· Addition of caution when the active level of the timer output is changed.

CHAPTER 10 WATCHDOG TIMER FUNCTION

· Change of the description of <5> in (2) of 10.4.1 General cautions on use of watchdog timer from "If the

STOP mode or IDLE mode is entered as the result of an inadvertent program loop" to "If the STOP mode,

HALT mode, or IDLE mode is entered as the result of an inadvertent program loop".

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Addition of caution and calculating method of the wait time if the reception completion interrupt is disabled

when a reception error occurs.

CHAPTER 14 INTERRUPT FUNCTIONS

Change of instructions in 14.9 When Interrupt Request and Macro Service Are Temporarily Held

Pending.

CHAPTER 16 STANDBY FUNCTION

· Change of description from "The watchdog timer must not be used to release the standby mode (STOP or

IDLE mode)" to "The watchdog timer must not be used to release the standby mode (STOP, HALT, or IDLE

mode)".

· Deletion of watchdog timer of "Non-maskable interrupt request (NMI pin input/watchdog timer)"

· Addition of Caution concerning the malfunction that causes a wait for the oscillation stabilization time when

the IDLE mode is released.

MAJOR REVISIONS IN THIS EDITION (1/2)

Page

Contents

Throughout

P.32

P.33

P.40

P.44, 49

p.158

p.181

p.206

p.229

p.262, 263, 267, 269, 289

p.354

p.392

p.399

p.404, 407

MAJOR REVISIONS IN THIS EDITION (2/2)

Page

Contents

P.451

P.453

P.463

P.469

Addition of (2) Output of CLKOUT pin in CHAPTER 20 CAUTIONS ON USING DEVELOPMENT TOOLS.

General revision of APPENDIX A DEVELOPMENT TOOLS for supporting IE-78K4-NS.

APPENDIX B EMBEDDED SOFTWARE

· Change of target host machines.

· Change of versions of OSs to be supported.

Addition of APPENDIX D REVISION HISTORY.

The mark shows major revised points.

[MEMO]

INTRODUCTION

Intended Readership

This manual is intended for user engineers who understand the functions of the

PD784054 and wish to design application

systems using this subseries.

The relevant products are as follows:

· Standard products:

PD784054

· Special products :

PD784054(A), (A1), (A2)

Purpose

The purpose of this manual is to give users an understanding of the various hardware functions of the

PD784054.

Organization

The

PD784054 manual is divided into two volumes the hardware volume (this manual) and the instruction volume.

Hardware volume

Instruction volume

Pin functions

CPU functions

Internal block functions

Addressing

Interrupts

Instruction set

Other on-chip peripheral functions

Certain operating precautions apply to these products.

These precautions are stated at the relevant points in the text of each chapter, and are

also summarized at the end of each chapter. Be sure to read them.

How to Read This Manual

Readers are required a general knowledge of electrical and logic circuits and microcomputers.

To readers using this manual as a

PD784054(A), 784054(A1), 784054(A2) manual:

The

PD784054 is treated as the representative model. Therefore, when using this manual for the

PD784054(A),

784054(A1), 784054(A2) manual,

PD784054 should be read as each product name as appropriate. For the

differences between products, refer to 1.8 Differences between

PD784054 and

PD784046 Subseries, 1.9

Differences between

PD784054 and

PD784054(A), and 1.10 Differences between

PD784054(A), 784054(A1),

and 784054(A2).

The application examples presented in this manual are for the "standard" quality

models in general-purpose electronic systems. If you wish to use the applications

presented in this manual for electronic systems that require "special" quality models,

thoroughly study the parts and circuits to be actually used, and their quality grade.

To check the details of a register when the register name is known:

Use APPENDIX C REGISTER INDEX.

If the device operates strangely after debugging:

Cautions are summarized at the end of each chapter, so refer to the Cautions for the relevant function.

For a general understanding of the functions

Read in accordance with the TABLE OF CONTENTS.

For the details of the instruction functions:

Refer to the separate 78K/IV Series User's Manual - Instruction (U10905E).

To find out about electrical specifications

Refer to the each Data Sheet.

To find out about application examples of each function,

Refer to the Application Note separately available.

Legend

Significance in data notation : High-order digit on left, low-order digit on right

Active-low notation

× × ×

(Line above pin or signal name)

Note

: Explanation of item marked with Note in the text

Caution

: Item to be especially noted

Remark

: Supplementary information

Numeric notations

: Binary .................

× × × ×

B or

× × × ×

Decimal ..............

× × × ×

Hexadecimal .......

× × × ×

Register Notation

Code combinations marked "Setting prohibited" in the register notations in the text must not be written.

Easily confused characters : 0 (Zero), O (Letter O)

: 1 (One), l (Lower-case letter L), I (Upper-case letter I)

EDC

Write Operation

Read Operation

0 or 1 is written. The
operation is not affected
by either value.

0 must be written

1 must be written

A value is written
according to the
function to be used.

A value is read
according to the
operating status.

0 or 1 is read.

Where the bit number is marked with a circle, the
bit name is reserved for NEC's assembler and is
defined as a sfr variable by the #pragma sfr
directive for C compiler.

Related Documents Some of the related documents in this document are preliminary versions but are not so specified.

Device-related documents

Document Name

Document No.

Japanese

English

PD784054 Data Sheet

U11154J

U11154E

PD78F4046 Preliminary Product Information

U11447J

U11447E

PD784054(A) Data Sheet

On preparation

Planned

PD784054 Special Function Register Table

U11113J

PD784054 User's Manual - Hardware

U11719J

This manual

78K/IV Series Application Note - Software Fundamentals

U10095J

U10095E

78K/IV Series User's Manual - Instruction

U10905J

U10905E

78K/IV Series Instruction List

U10594J

78K/IV Series Instruction Set

U10595J

Documents on development tools (User's Manuals)

Document Name

Document No.

Japanese

English

RA78K4 Assembler Package

Operation

U11334J

U11334E

Language

U11162J

U11162E

RA78K4 Structured Assembler Preprocessor

U11743J

U11743E

CC78K4 C Compiler

Operation

U11572J

U11572E

Language

U11571J

U11571E

CC78K Series Library Source File

U12322J

IE-78K4-NS

On preparation

Planned

IE-784000-R

U12903J

EEU-1534

IE-784046-NS-EM1

Planned

IE-784046-R-EM1

U11677J

U11677E

EP-78230

EEU-985

EEU-1515

SM78K4 System Simulator Windows

Based

Reference

U10093J

U10093E

SM78K Series System Simulator

External part user

U10092J

U10092E

open interface specifications

ID78K4-NS Integrated Debugger

Reference

U12796J

U12796E

ID78K4 Integrated Debugger Windows Based

Reference

U10440J

U10440E

ID78K4 Integrated Debugger HP-UX

, SunOS

Reference

U11960J

U11960E

NEWS-OS

Based

Caution

The contents of the above documents are subject to change without notice. Be sure to use the latest edition

of each document for designing.

Documents on embedded software (User's Manuals)

Document Name

Document No.

Japanese

English

78K/IV Series Real-Time OS

Fundamental

U10603J

U10603E

Installation

U10604J

U10604E

Debugger

U10364J

78K/IV Series OS MX78K4

Fundamental

U11779J

Other documents

Document Name

Document No.

Japanese

English

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

C11531J

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic

C11892J

C11892E

Discharge (ESD)

Guide to Quality Assurance for Semiconductor Devices

MEI-1202

Microcomputer Product Series Guide

C11416J

Caution

The documents listed above are subject to change without notice. Be sure to use the latest documents for

designing, etc.

[MEMO]

TABLE OF CONTENTS

CHAPTER 1 GENERAL ............................................................................................................................... 31

1.1

Features ...................................................................................................................................... 33

1.2

Ordering Information ................................................................................................................. 33

1.3

Quality Grades ........................................................................................................................... 33

1.4

Pin Configuration (Top View) ................................................................................................... 34

1.5

System Configuration Example (PPC) .................................................................................... 36

1.6

Block Diagram ............................................................................................................................ 37

1.7

List of Functions ........................................................................................................................ 38

1.8

Differences between

PD784054 and

PD784046 Subseries .............................................. 39

1.9

Differences between

PD784054 and

PD784054(A) ............................................................ 40

1.10

Differences between

PD784054(A), 784054(A1), and 784054(A2) ..................................... 40

CHAPTER 2 PIN FUNCTIONS ..................................................................................................................... 41

2.1

List of Pin Functions ................................................................................................................. 41

2.2

Description of Pin Functions ................................................................................................... 45

2.3

I/O Circuits of Pins and Processing of Unused Pins ........................................................... 51

CHAPTER 3 CPU ARCHITECTURE .......................................................................................................... 53

3.1

Memory Space ............................................................................................................................ 53

3.2

Internal ROM Area ..................................................................................................................... 55

3.3

Base Area .................................................................................................................................... 55

3.3.1

Vector table area ............................................................................................................................

3.3.2

CALLT instruction table area .........................................................................................................

3.3.3

CALLF instruction entry area ........................................................................................................

3.4

Internal Data Area .................................................................................................................... 58

3.4.1

Internal RAM area ..........................................................................................................................

3.4.2

Special function register (SFR) area .............................................................................................

3.4.3

External SFR area .........................................................................................................................

3.5

External Memory Space ............................................................................................................ 61

3.6

Control Registers ....................................................................................................................... 62

3.6.1

Program counter (PC) ....................................................................................................................

3.6.2

Program status word (PSW) ..........................................................................................................

3.6.3

Use of RSS bit ................................................................................................................................

3.6.4

Stack pointer (SP) ..........................................................................................................................

3.7

General-Purpose Registers ...................................................................................................... 71

3.7.1

Configuration ..................................................................................................................................

3.7.2

Functions ........................................................................................................................................

3.8

Special Function Registers (SFRs) ......................................................................................... 76

3.9

Cautions ...................................................................................................................................... 81

CHAPTER 4 CLOCK GENERATOR .......................................................................................................... 83

4.1

Configuration and Function ..................................................................................................... 83

4.2

Control Registers ....................................................................................................................... 85

4.2.1

Standby control register (STBC) ...................................................................................................

4.2.2

Oscillation stabilization time specification register (OSTS) .........................................................

4.3

Clock Generator Operation ...................................................................................................... 87

4.3.1

Clock oscillator ...............................................................................................................................

4.3.2

Frequency divider ...........................................................................................................................

4.4

Cautions ...................................................................................................................................... 88

4.4.1

When an external clock is input ....................................................................................................

4.4.2

When crystal/ceramic oscillation is used ......................................................................................

CHAPTER 5 PORT FUNCTIONS .............................................................................................................. 93

5.1

Digital Input/Output Port ........................................................................................................... 93

5.2

Port 0 ........................................................................................................................................... 95

5.2.1

Hardware configuration ..................................................................................................................

5.2.2

Input/output mode/control mode setting ........................................................................................

5.2.3

Operating status .............................................................................................................................

5.2.4

Internal pull-up resistors ................................................................................................................

5.3

Port 1 ........................................................................................................................................... 100

5.3.1

Hardware configuration .................................................................................................................. 100

5.3.2

Setting I/O mode/control mode ...................................................................................................... 101

5.3.3

Operating status ............................................................................................................................. 101

5.4

Port 2 ........................................................................................................................................... 103

5.4.1

Hardware configuration .................................................................................................................. 104

5.4.2

Setting I/O mode/control mode ...................................................................................................... 106

5.4.3

Operating status ............................................................................................................................. 107

5.5 Port 3 ............................................................................................................................................. 110

5.5.1

Hardware configuration .................................................................................................................. 111

5.5.2

Input/output mode/control mode setting ........................................................................................ 113

5.5.3

Operating status ............................................................................................................................. 115

5.6

Port 4 .......................................................................................................................................... 118

5.6.1

Hardware configuration .................................................................................................................. 118

5.6.2

Input/output mode/control mode setting ........................................................................................ 119

5.6.3

Operating status ............................................................................................................................. 120

5.6.4

Internal pull-up resistors ................................................................................................................ 122

5.7

Port 5 .......................................................................................................................................... 124

5.7.1

Hardware configuration .................................................................................................................. 124

5.7.2

Input/output mode/control mode setting ........................................................................................ 125

5.7.3

Operating status ............................................................................................................................. 126

5.7.4

Internal pull-up resistors ................................................................................................................ 128

5.8

Port 6 .......................................................................................................................................... 130

5.8.1

Hardware configuration .................................................................................................................. 130

5.8.2

Setting of I/O mode/control mode ................................................................................................. 131

5.8.3

Operating status ............................................................................................................................. 132

5.8.4

Internal pull-up resistors ................................................................................................................ 134

5.9

Port 7 ........................................................................................................................................... 136

5.9.1

Hardware configuration .................................................................................................................. 136

5.9.2

Notes ............................................................................................................................................... 136

5.10

Port 8 ........................................................................................................................................... 137

5.10.1

Hardware configuration .................................................................................................................. 137

5.10.2

Cautions .......................................................................................................................................... 137

5.11 Port 9 ............................................................................................................................................. 138

5.11.1

Hardware configuration .................................................................................................................. 139

5.11.2

Setting of I/O mode/control mode ................................................................................................. 141

5.11.3

Operating status ............................................................................................................................. 142

5.11.4

Internal pull-up resistor .................................................................................................................. 144

5.12

Port Output Data Check Function ........................................................................................... 146

5.13

Cautions ...................................................................................................................................... 149

CHAPTER 6 OUTLINE OF TIMER ............................................................................................................. 151

CHAPTER 7 TIMER 0 .................................................................................................................................... 155

7.1

Function ...................................................................................................................................... 155

7.2

Configuration .............................................................................................................................. 156

7.3

Timer 0 Control Register .......................................................................................................... 159

7.4

Operation of Timer Register 0 (TM0) ....................................................................................... 162

7.4.1

Basic operation ............................................................................................................................... 162

7.4.2

Clear operation ............................................................................................................................... 164

7.5

Operation of Capture/Compare Register ................................................................................ 165

7.5.1

Compare operation ........................................................................................................................ 165

7.5.2

Capture operation .......................................................................................................................... 167

7.6

Basic Operation of Output Control Circuit ............................................................................ 169

7.6.1

Basic operation ............................................................................................................................... 171

7.6.2

Toggle output .................................................................................................................................. 171

7.6.3

Set/reset output .............................................................................................................................. 172

7.7

Examples of Use ........................................................................................................................ 173

7.7.1

Operation as interval timer ............................................................................................................ 173

7.7.2

Pulse width measurement operation ............................................................................................. 176

7.8

Cautions ...................................................................................................................................... 179

CHAPTER 8 TIMER 1 .................................................................................................................................... 183

8.1

Function ...................................................................................................................................... 183

8.2

Configuration .............................................................................................................................. 183

8.3

Timer 1 Control Register .......................................................................................................... 186

8.4

Operation of Timer Register 1 (TM1) ....................................................................................... 189

8.4.1

Basic operation ............................................................................................................................... 189

8.4.2

Clear operation ............................................................................................................................... 191

8.5

Operation of Compare Register ............................................................................................... 193

8.6

Basic Operation of Output Control Circuit ............................................................................ 196

8.6.1

Basic operation ............................................................................................................................... 197

8.6.2

Toggle output .................................................................................................................................. 197

8.6.3

Set/reset output .............................................................................................................................. 198

8.7

Examples of Use ........................................................................................................................ 199

8.7.1

Operation as interval timer (1) ....................................................................................................... 199

8.7.2

Operation as interval timer (2) ....................................................................................................... 202

8.8

Cautions ...................................................................................................................................... 204

CHAPTER 9 TIMER 4 .................................................................................................................................... 207

9.1

Function ...................................................................................................................................... 207

9.2

Configuration.............................................................................................................................. 207

9.3

Timer 4 Control Register .......................................................................................................... 210

9.4

Operation of Timer Register 4 (TM4) ....................................................................................... 212

9.4.1

Basic operation ............................................................................................................................... 212

9.4.2

Clear operation ............................................................................................................................... 214

9.5

Operation of Compare Register ............................................................................................... 216

9.6

Example of Use .......................................................................................................................... 218

9.6.1

Operation as interval timer (1) ....................................................................................................... 218

9.6.2

Operation as interval timer (2) ....................................................................................................... 221

9.7 Cautions ........................................................................................................................................ 223

CHAPTER 10 WATCHDOG TIMER FUNCTION .......................................................................................... 225

10.1

Configuration.............................................................................................................................. 225

10.2

Watchdog Timer Mode Register (WDM) .................................................................................. 226

10.3

Operation .................................................................................................................................... 228

10.3.1

Count operation .............................................................................................................................. 228

10.3.2

Interrupt priorities ........................................................................................................................... 228

10.4

Cautions ...................................................................................................................................... 229

10.4.1

General cautions on use of watchdog timer ................................................................................. 229

10.4.2

Cautions on

PD784054 watchdog timer ..................................................................................... 229

CHAPTER 11 A/D CONVERTER ................................................................................................................. 231

11.1

Configuration.............................................................................................................................. 231

11.2

A/D Converter Mode Register (ADM) ...................................................................................... 235

11.3

A/D Conversion Result Registers (ADCR0 through ADCR7) ............................................... 238

11.4

Operation .................................................................................................................................... 240

11.4.1

Basic A/D converter operation ....................................................................................................... 240

11.4.2 Select mode ..................................................................................................................................... 243

11.4.3 Scan mode ....................................................................................................................................... 245

11.4.4

A/D conversion operation start by software .................................................................................. 247

11.4.5

A/D conversion operation start by hardware ................................................................................. 249

11.5

External Circuit of A/D Converter ............................................................................................ 252

11.6

Cautions ...................................................................................................................................... 252

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O ......................................... 255

12.1

Switching between Asynchronous Serial Interface Mode and 3-wire Serial I/O Mode ... 256

12.2

Asynchronous Serial Interface Mode ..................................................................................... 257

12.2.1

Configuration in asynchronous serial interface mode .................................................................. 257

12.2.2

Asynchronous serial interface control registers ............................................................................ 260

12.2.3

Data format ..................................................................................................................................... 264

12.2.4

Parity types and operations ........................................................................................................... 265

12.2.5

Transmission ................................................................................................................................... 266

12.2.6

Reception ........................................................................................................................................ 267

12.2.7

Receive errors ................................................................................................................................ 268

12.2.8

Transmitting/receiving data with macro service ............................................................................ 269

12.3

3-wire Serial I/O Mode ............................................................................................................... 271

12.3.1

Configuration in 3-wire serial I/O mode ........................................................................................ 271

12.3.2

Clocked serial interface mode registers (CSIM1, CSIM2) ........................................................... 274

12.3.3

Basic operation timing ................................................................................................................... 275

12.3.4

Operation when transmission only is enabled .............................................................................. 277

12.3.5

Operation when reception only is enabled .................................................................................... 278

12.3.6

Operation when transmission/reception is enabled ...................................................................... 279

12.3.7

Corrective action in case of slippage of serial clock and shift operations ................................... 279

12.4

Baud Rate Generator ................................................................................................................. 280

12.4.1

Baud rate generator configuration ................................................................................................. 280

12.4.2 Baud rate generator control register ............................................................................................... 282

12.4.3 Baud rate generator operation ........................................................................................................ 284

12.4.4 Baud rate setting in asynchronous serial interface mode .............................................................. 286

12.5

Cautions ...................................................................................................................................... 289

CHAPTER 13 EDGE DETECTION FUNCTION ........................................................................................... 291

13.1

Edge Detection Function Control Registers .......................................................................... 291

13.1.1

External interrupt mode registers (INTM0, INTM1) ...................................................................... 291

13.1.2

Interrupt valid edge flag registers (IEF1, IEF2) ............................................................................ 294

13.1.3

Noise protection control register (NPC) ........................................................................................ 296

13.2

Edge Detection for Pin P20 ...................................................................................................... 297

13.3

Pin Edge Detection for Pins P21 to P27 ................................................................................. 298

13.4

Cautions ...................................................................................................................................... 299

CHAPTER 14 INTERRUPT FUNCTIONS .................................................................................................... 301

14.1

Interrupt Request Sources ....................................................................................................... 302

14.1.1

Software interrupts ......................................................................................................................... 304

14.1.2

Operand error interrupts ................................................................................................................ 304

14.1.3

Non-maskable interrupts ................................................................................................................ 304

14.1.4

Maskable interrupts ........................................................................................................................ 304

14.2

Interrupt Processing Modes ..................................................................................................... 305

14.2.1

Vectored interrupt processing ........................................................................................................ 305

14.2.2

Macro service ................................................................................................................................. 305

14.2.3

Context switching ........................................................................................................................... 305

14.3

Interrupt Processing Control Registers ................................................................................. 306

14.3.1

Interrupt control registers ............................................................................................................... 308

14.3.2

Interrupt mask registers (MK0, MK1) ............................................................................................ 312

14.3.3

In-service priority register (ISPR) .................................................................................................. 314

14.3.4

Interrupt mode control register (IMC) ............................................................................................ 315

14.3.5

Watchdog timer mode register (WDM) .......................................................................................... 316

14.3.6

Program status word (PSW) .......................................................................................................... 317

14.4

Software Interrupt Acknowledgment Operations .................................................................. 318

14.4.1

BRK instruction software interrupt acknowledgment operation ................................................... 318

14.4.2

BRKCS instruction software interrupt (software context switching) acknowledgment operation 318

14.5

Operand Error Interrupt Acknowledgment Operation .......................................................... 319

14.6

Non-Maskable Interrupt Acknowledgment Operation .......................................................... 320

14.7

Maskable Interrupt Acknowledgment Operation ................................................................... 324

14.7.1

Vectored interrupt ........................................................................................................................... 326

14.7.2

Context switching ........................................................................................................................... 326

14.7.3

Maskable interrupt priority levels ................................................................................................... 328

14.8

Macro Service Function ............................................................................................................ 334

14.8.1

Outline of macro service function .................................................................................................. 334

14.8.2

Types of macro service .................................................................................................................. 334

14.8.3

Basic operation of macro service (except CPU monitor modes 0 and 1) ................................... 338

14.8.4

Operation on completion of macro servicing (except CPU monitor modes 0 and 1) ................. 339

14.8.5

Macro service control register ....................................................................................................... 340

14.8.6

Macro service mode ....................................................................................................................... 342

14.8.7

Operation of macro service ........................................................................................................... 342

14.9

When Interrupt Request and Macro Service Are Temporarily Held Pending .................... 354

14.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro

Service ......................................................................................................................................... 356

14.11 Interrupt and Macro Service Operation Timing ..................................................................... 356

14.11.1 Interrupt acceptance processing time ........................................................................................... 357

14.11.2 Processing time of macro service ................................................................................................. 358

14.12 Restoring Interrupt Function To Initial State ......................................................................... 359

14.13 Cautions ...................................................................................................................................... 360

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION ................................................................................ 363

15.1 Memory Extension Function ..................................................................................................... 363

15.1.1

Memory extension mode register (MM) ........................................................................................ 363

15.1.2

Memory map with external memory extension ............................................................................. 365

15.1.3

Basic operation of local bus interface ........................................................................................... 368

15.2

Wait Function ............................................................................................................................. 371

15.2.1

Wait function control registers ....................................................................................................... 371

15.2.2

Address waits ................................................................................................................................. 377

15.2.3

Access waits ................................................................................................................................... 380

15.3

Bus Sizing Function .................................................................................................................. 387

15.3.1

Bus width specification register (BW) ........................................................................................... 387

15.4

Cautions ...................................................................................................................................... 389

CHAPTER 16 STANDBY FUNCTION .......................................................................................................... 391

16.1

Configuration and Function ..................................................................................................... 391

16.2

Control Registers ....................................................................................................................... 394

16.2.1

Standby control register (STBC) ................................................................................................... 394

16.2.2

Oscillation stabilization time specification register (OSTS) ......................................................... 396

16.3

HALT Mode .................................................................................................................................. 398

16.3.1

HALT mode setting and operating states ...................................................................................... 398

16.3.2

HALT mode release ........................................................................................................................ 398

16.4

STOP Mode ................................................................................................................................. 401

16.4.1

STOP mode setting and operating states ..................................................................................... 401

16.4.2

STOP mode release ....................................................................................................................... 402

16.5

IDLE Mode ................................................................................................................................... 403

16.5.1

IDLE mode setting and operating states ....................................................................................... 403

16.5.2

IDLE mode release ........................................................................................................................ 404

16.6

Check Items When STOP Mode/IDLE Mode Is Used ............................................................. 405

16.7

Cautions ...................................................................................................................................... 407

CHAPTER 17 RESET FUNCTION ............................................................................................................... 409

17.1

Reset Function ........................................................................................................................... 409

17.2

Caution ........................................................................................................................................ 412

CHAPTER 18

PD78F4046 .......................................................................................................................... 413

18.1

Memory Mapping of

PD78F4046 ............................................................................................ 413

18.2

Programming

PD78F4046 ....................................................................................................... 414

18.2.1

Selecting communication mode ..................................................................................................... 415

18.2.2

Function of flash memory programming ....................................................................................... 415

18.2.3

Connecting Flashpro II ................................................................................................................... 416

18.3

Cautions ...................................................................................................................................... 416

CHAPTER 19 INSTRUCTION OPERATIONS .............................................................................................. 417

19.1

Legend ......................................................................................................................................... 417

19.2

List of Operations ...................................................................................................................... 421

19.3

Instructions Listed by Type of Addressing ............................................................................ 446

CHAPTER 20 CAUTIONS ON USING DEVELOPMENT TOOLS ............................................................... 451

APPENDIX A DEVELOPMENT TOOLS ...................................................................................................... 453

A.1

Language Processing Software ............................................................................................... 455

A.2

Flash Memory Writing Tools ..................................................................................................... 456

A.3

Debugging Tools ........................................................................................................................ 457

A.3.1

Hardware ........................................................................................................................................ 457

A.3.2

Software .......................................................................................................................................... 459

A.4

Dimensions of Conversion Socket (EV-9200GC-80) and Recommended Board

Mounting Pattern ....................................................................................................................... 461

APPENDIX B EMBEDDED SOFTWARE ...................................................................................................... 463

APPENDIX C REGISTER INDEX ................................................................................................................. 465

APPENDIX D REVISION HISTORY .............................................................................................................. 469

LIST OF FIGURES (1/6)

Figure No.

Title

Page

2-1

I/O Circuits of Pins .......................................................................................................................................

3-1

Memory Map .................................................................................................................................................

3-2

Internal RAM Memory Map ..........................................................................................................................

3-3

Format of Program Counter (PC) ................................................................................................................

3-4

Format of Program Status Word (PSW) ......................................................................................................

3-5

Format of Stack Pointer (SP) .......................................................................................................................

3-6

Data Saved to Stack Area ............................................................................................................................

3-7

Data Restored from Stack Area ...................................................................................................................

3-8

Format of General-Purpose Register ..........................................................................................................

3-9

General-Purpose Register Addresses .........................................................................................................

4-1

Block Diagram of Clock Generator ..............................................................................................................

4-2

Clock Oscillator External Circuitry ...............................................................................................................

4-3

Standby Control Register (STBC) Format ...................................................................................................

4-4

Format of Oscillation Stabilization Time Specification Register (OSTS) ...................................................

4-5

Signal Extraction with External Clock Input ................................................................................................

4-6

Cautions on Resonator Connection .............................................................................................................

4-7

Incorrect Example of Resonator Connection ..............................................................................................

5-1

Port Configuration .........................................................................................................................................

5-2

Block Diagram of Port 0 ...............................................................................................................................

5-3

Format of Port 0 Mode Register (PM0) .......................................................................................................

5-4

Port Specified as Output Port ......................................................................................................................

5-5

Port Specified as Input Port .........................................................................................................................

5-6

Pull-Up Resistor Option Register L (PUOL) Format ...................................................................................

5-7

Pull-Up Resistor Specification (Port 0) ........................................................................................................

5-8

Block Diagram of Port 1 ............................................................................................................................... 100

5-9

Format of Port 1 Mode Register (PM1) ....................................................................................................... 101

5-10

Port Specified as Output Port ...................................................................................................................... 101

5-11

Port Specified as Input Port ......................................................................................................................... 102

5-12

Block Diagram of P20 (Port 2) ..................................................................................................................... 104

5-13

Block Diagram of P21 to P24 (Port 2) ......................................................................................................... 105

5-14

Block Diagram of P25 to P27 (Port 2) ......................................................................................................... 105

5-15

Format of Port 2 Mode Register (PM2) ....................................................................................................... 106

5-16

Format of Port 2 Mode Control Register (PMC2) ....................................................................................... 106

5-17

Port in Output Port Mode ............................................................................................................................. 107

5-18

Port in Input Port Mode ................................................................................................................................ 108

5-19

Port in Control Mode .................................................................................................................................... 109

5-20

Block Diagram of P30, P31, P33 and P36 (Port 3) .................................................................................... 111

5-21

Block Diagram of P32 and P35 (Port 3) ...................................................................................................... 111

5-22

Block Diagram of P34 and P37 (Port 3) ...................................................................................................... 112

5-23

Format of Port 3 Mode Register (PM3) ....................................................................................................... 113

5-24

Format of Port 3 Mode Control Register (PMC3) ....................................................................................... 114

5-25

Port Specified as Output Port ...................................................................................................................... 115

5-26

Port Specified as Input Port ......................................................................................................................... 116

5-27

Control Specification .................................................................................................................................... 117

5-28

Block Diagram of Port 4 ............................................................................................................................... 118

5-29

Format of Port 4 Mode Register (PM4) ....................................................................................................... 119

5-30

Port Specified as Output Port ...................................................................................................................... 120

5-31

Port Specified as Input Port ......................................................................................................................... 121

5-32

Format of Pull-up Resistor Option Register L (PUOL) ............................................................................... 122

5-33

Pull-Up Resistor Specification (Port 4) ........................................................................................................ 123

5-34

Block Diagram of Port 5 ............................................................................................................................... 124

5-35

Format of Port 5 Mode Register (PM5) ....................................................................................................... 125

5-36

Port Specified as Output Port ...................................................................................................................... 126

5-37

Port Specified as Input Port ......................................................................................................................... 127

5-38

Format of Pull-Up Resistor Option Register L (PUOL) ............................................................................... 128

5-39

Pull-Up Resistor Specification (Port 5) ........................................................................................................ 129

5-40

Block Diagram of Port 6 ............................................................................................................................... 130

5-41

Format of Port 6 Mode Register (PM6) ....................................................................................................... 131

5-42

Port Specified as Output Port ...................................................................................................................... 132

5-43

Port Specified as Input Port ......................................................................................................................... 133

5-44

Format of Pull-Up Resistor Option Register L (PUOL) ............................................................................... 134

5-45

Pull-Up Resistor Specification (Port 6) ........................................................................................................ 135

5-46

Block Diagram of Port 7 ............................................................................................................................... 136

5-47

Block Diagram of Port 8 ............................................................................................................................... 137

5-48

Block Diagram of P90 to P93 (Port 9) ......................................................................................................... 139

5-49

Block Diagram of P94 (Port 9) ..................................................................................................................... 140

5-50

Format of Port 9 Mode Register (PM9) ....................................................................................................... 141

5-51

Format of Port 9 Mode Control Register (PMC9) ....................................................................................... 141

5-52

Port in Output Port Mode ............................................................................................................................. 142

5-53

Port in Input Port Mode ................................................................................................................................ 143

5-54

Format of Pull-up Resistor Option register H (PUOH) ................................................................................ 144

5-55

Specifying Pull-up Resistor (port 9) ............................................................................................................. 145

5-56

Format of Port Read Control Register (PRDC) ........................................................................................... 146

5-57

Concept of Control (in output port mode) ................................................................................................... 147

6-1

Block Diagram of Timer ................................................................................................................................ 152

7-1

Block Diagram of Timer 0 ............................................................................................................................. 157

7-2

Format of Timer Unit Mode Register 0 (TUM0) .......................................................................................... 159

7-3

Format of Timer Mode Control Register (TMC) .......................................................................................... 160

7-4

Format of Timer Output Control Register 0 (TOC0) ................................................................................... 160

7-5

Format of Prescaler Mode Register (PRM) ................................................................................................. 161

7-6

Basic Operation of Timer Register 0 (TM0) ................................................................................................ 163

LIST OF FIGURES (2/6)

Figure No.

Title

Page

7-7

Clear Operation of Timer Register 0 (TM0) ................................................................................................. 164

7-8

Compare Operation (timer 0) ....................................................................................................................... 166

7-9

Capture Operation (timer 0) ......................................................................................................................... 168

7-10

Block Diagram of Timer Output Operation of Timer 0 ................................................................................ 170

7-11

Operation of Toggle Output .......................................................................................................................... 171

7-12

Operation of Set/Reset Output (timer 0) ..................................................................................................... 172

7-13

Timing of Interval Timer Operation .............................................................................................................. 173

7-14

Set Contents of Control Register for Interval Timer Operation .................................................................. 174

7-15

Setting Procedure of Interval Timer Operation ........................................................................................... 175

7-16

Interrupt Request Processing of Interval Timer Operation ......................................................................... 175

7-17

Timing of Pulse Width Measurement ........................................................................................................... 176

7-18

Control Register Settings for Pulse Width Measurement ........................................................................... 177

7-19

Pulse Width Measurement Setting Procedure ............................................................................................ 178

7-20

Interrupt Request Processing that Calculates Pulse Width ........................................................................ 178

7-21

Operation When Counting Is Started .......................................................................................................... 179

7-22

Operation When Compare Register (CC00 to CC03) Is Set to 0000H ...................................................... 180

8-1

Block Diagram of Timer 1 ............................................................................................................................. 184

8-2

Format of Timer Unit Mode Register 0 (TUM0) .......................................................................................... 186

8-3

Format of Timer Mode Control Register (TMC) .......................................................................................... 187

8-4

Format of Timer Output Control Register 1 (TOC1) ................................................................................... 187

8-5

Format of Prescaler Mode Register (PRM) ................................................................................................. 188

8-6

Basic Operation of Timer Register 1 (TM1) ................................................................................................ 190

8-7

TM1 Clear Operation by Match with Compare Register (CM10) ............................................................... 191

8-8

TM1 Clear Operation When CE1 Bit is Cleared (0) .................................................................................... 192

8-9

Compare Operation (timer 1) ....................................................................................................................... 194

8-10

Clearing TM1 after Detection of Match ........................................................................................................ 195

8-11

Block Diagram of Timer Output Operation of Timer 1 ................................................................................ 196

8-12

Operation of Toggle Output .......................................................................................................................... 197

8-13

Operation of Set/Reset Output (timer 1) ..................................................................................................... 198

8-14

Timing of Interval Timer Operation (1) ........................................................................................................ 199

8-15

Control Register Settings for Interval Timer Operation (1) ......................................................................... 200

8-16

Setting Procedure of Interval Timer Operation (1) ...................................................................................... 201

8-17

Interrupt Request Processing of Interval Timer Operation (1) ................................................................... 201

8-18

Timing of Interval Timer Operation (2) ........................................................................................................ 202

8-19

Control Register Settings for Interval Timer Operation (2) ......................................................................... 203

8-20

Setting Procedure of Interval Timer Operation (2) ...................................................................................... 203

8-21

Operation When Counting Is Started .......................................................................................................... 204

8-22

Operation When Compare Register (CM10, CM11) Is Set to 0000H ........................................................ 206

9-1

Block Diagram of Timer 4 ............................................................................................................................. 208

9-2

Format of Timer Mode Control Register 4 (TMC4) ..................................................................................... 210

9-3

Format of Prescaler Mode Register 4 (PRM4) ........................................................................................... 211

LIST OF FIGURES (3/6)

Figure No.

Title

Page

9-4

Basic Operation of Timer Register 4 (TM4) ................................................................................................ 213

9-5

TM4 Clear Operation by Match with Compare Register (CM40, CM41) ................................................... 214

9-6

Clear Operation of TM4 When CE4 Bit is Cleared (0) ................................................................................ 215

9-7

Compare Operation (timer 4) ....................................................................................................................... 217

9-8

TM4 Clearance after Match Detection ......................................................................................................... 217

9-9

Timing of Interval Timer Operation (1) ........................................................................................................ 218

9-10

Set Contents of Control Registers for Interval Timer Operation (1) ........................................................... 219

9-11

Setting Procedure of Interval Timer Operation (1) ...................................................................................... 220

9-12

Interrupt Request Processing of Interval Timer Operation (1) ................................................................... 220

9-13

Timing of Interval Timer Operation (2) ........................................................................................................ 221

9-14

Set Contents of Control Register for Interval Timer Operation (2) ............................................................. 222

9-15

Setting Procedure of Interval Timer Operation (2) ...................................................................................... 222

9-16

Operation When Count Starts ...................................................................................................................... 223

9-17

Operation When Compare Register (CM40, CM41) Is Set to 0000H ........................................................ 224

10-1

Block Diagram of Watchdog Timer .............................................................................................................. 225

10-2

Format of Watchdog Timer Mode Register (WDM) ..................................................................................... 227

11-1

Block Diagram of A/D Converter .................................................................................................................. 232

11-2

Example of Capacitor Connection on A/D Converter Pins ......................................................................... 233

11-3

Format of A/D Converter Mode Register (ADM) ......................................................................................... 236

11-4

Word Access to A/D Conversion Result Register ....................................................................................... 238

11-5

Byte Access to A/D Conversion Result Register ........................................................................................ 239

11-6

Basic Operation of A/D Converter ............................................................................................................... 241

11-7

Relationship Between Analog Input Voltage and A/D Conversion Result ................................................. 242

11-8

Operating Timing in Select Mode (1-buffer mode) ...................................................................................... 243

11-9

Operation Timing in Select Mode (4-buffer mode) ...................................................................................... 245

11-10

Operation Timing in Scan Mode .................................................................................................................. 246

11-11

A/D Conversion in Select Mode (1-buffer mode) Started by Software ...................................................... 247

11-12

A/D Conversion in Select Mode (4-buffer mode) Started by Software ...................................................... 248

11-13

A/D Conversion in Scan Mode Started by Software ................................................................................... 248

11-14

A/D Conversion in Select Mode (1-buffer mode) Started by Hardware ..................................................... 249

11-15

A/D Conversion in Select Mode (4-buffer mode) Started by Hardware ..................................................... 250

11-16

A/D Conversion in Scan Mode Started by Hardware ................................................................................. 251

11-17

Example of Capacitor Connection on A/D Converter Pins ......................................................................... 252

12-1

Switching Between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode ............................ 256

12-2

Block Diagram of Asynchronous Serial Interface ........................................................................................ 258

12-3

Formats of Asynchronous Serial Interface Mode Register (ASIM) and Asynchronous Serial

Interface Mode Register 2 (ASIM2) ............................................................................................................. 261

12-4

Formats of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial

Interface Status Register 2 (ASIS2) ............................................................................................................ 263

12-5

Data Format of Asynchronous Serial Interface Transmit/Receive .............................................................. 264

LIST OF FIGURES (4/6)

Figure No.

Title

Page

12-6

Interrupt Timing of Asynchronous Serial Interface Transmission Completion ........................................... 266

12-7

Interrupt Timing of Asynchronous Serial Interface Reception Completion ................................................ 267

12-8

Timing of Receive Error ............................................................................................................................... 268

12-9

Transmission/Reception with Macro Service ............................................................................................... 270

12-10

Example of 3-Wire Serial I/O System Configuration ................................................................................... 271

12-11

Block Diagram of 3-Wire Serial I/O Mode ................................................................................................... 272

12-12

Formats of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface Mode

Register 2 (CSIM2) ....................................................................................................................................... 274

12-13

Timing of 3-Wire Serial I/O Mode ................................................................................................................ 275

12-14

Example of Connection to 2-Wire Serial I/O ............................................................................................... 276

12-15

Block Diagram of Baund Rate Generator .................................................................................................... 281

12-16

Formats of Baud Rate Generator Control Register (BRGC) and Baud Rate Generator Control

Register 2 (BRGC2) ..................................................................................................................................... 283

13-1

Format of External Interrupt Mode Register 0 (INTM0) .............................................................................. 292

13-2

Format of External Interrupt Mode Register 1 (INTM1) .............................................................................. 293

13-3

Format of Interrupt Valid Edge Flag Register 1 (IEF1) ............................................................................... 294

13-4

Format of Interrupt Valid Edge Flag Register 2 (IEF2) ............................................................................... 295

13-5

Format of Noise Protection Control Register (NPC) ................................................................................... 296

13-6

Edge Detection for Pin P20 .......................................................................................................................... 297

13-7

Edge Detection for Pins P21 to P27 ............................................................................................................ 298

14-1

Interrupt Control Registers (

××

ICn) ............................................................................................................. 309

14-2

Format of Interrupt Mask Registers (MK0, MK1) ........................................................................................ 313

14-3

Format of In-Service Priority Register (ISPR) ............................................................................................. 314

14-4

Format of Interrupt Mode Control Register (IMC) ....................................................................................... 315

14-5

Format of Watchdog Timer Mode Register (WDM) ..................................................................................... 316

14-6

Format of Program Status Word (PSWL) .................................................................................................... 317

14-7

Context Switching Operation by Execution of a BRKCS Instruction .......................................................... 318

14-8

Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) .............................. 319

14-9

Operations of Non-Maskable Interrupt Request Acknowledgment ............................................................ 321

14-10

Algorithm of Interrupt Acknowledgment Processing ................................................................................... 325

14-11

Context Switching Operation by Generation of an Interrupt Request ........................................................ 326

14-12

Return from Interrupt that Uses Context Switching by Means of RETCS Instruction ............................... 327

14-13

Examples of Processing When Another Interrupt Request Is Generated During Interrupt Processing ... 329

14-14

Examples of Processing of Simultaneously Generated Interrupts ............................................................. 332

14-15

Differences in Level 3 Interrupt Acknowledgment According to Setting of Interrupt Mode Control

Register (IMC) .............................................................................................................................................. 333

14-16

Differences between Vectored Interrupt and Macro Service Processing ................................................... 334

14-17

Example of Macro Service Processing Sequence ...................................................................................... 338

14-18

Operation on Completion of Macro Service ................................................................................................ 339

14-19

Basic Configuration of Macro Service Control Word .................................................................................. 340

14-20

Format of Macro Service Control Word ....................................................................................................... 341

14-21

Interrupt Request Generation and Acknowledgment (Unit: Clocks) ........................................................... 356

LIST OF FIGURES (5/6)

Figure No.

Title

Page

15-1

Format of Memory Expansion Mode Register (MM) ................................................................................... 364

15-2

Memory Map ................................................................................................................................................. 366

15-3

Read Timing (8 Bits) ..................................................................................................................................... 368

15-4

Write Timing (8 Bits) ..................................................................................................................................... 368

15-5

Read Timing (16 Bits, Even Address Access) ............................................................................................ 369

15-6

Write Timing (16 Bits, Even Address Access) ............................................................................................ 369

15-7

Read Timing (16 Bits, Odd Address Access) .............................................................................................. 370

15-8

Write Timing (16 Bits, Odd Address Access) .............................................................................................. 370

15-9

Format of Memory Extension Mode Register (MM) .................................................................................... 371

15-10

Format of Programmable Wait Control Register 1 (PWC1) ........................................................................ 373

15-11

Format of Programmable Wait Control Register 2 (PWC2) ........................................................................ 375

15-12

Read/Write Timing of Address Wait Function ............................................................................................. 377

15-13

Format of Port 9 Mode Control Register (PMC9) ....................................................................................... 380

15-14

Wait Control Spaces ..................................................................................................................................... 381

15-15

Read Timing of Access Wait Function ......................................................................................................... 382

15-16

Write Timing of Access Wait Function ......................................................................................................... 384

15-17

Timing with External Wait Signal ................................................................................................................. 386

15-18

Format of Bus Width Specification Register (BW) ...................................................................................... 388

16-1

Diagram of Standby Mode Transition ........................................................................................................... 392

16-2

Block Diagram of Standby Function ............................................................................................................ 393

16-3

Standby Control Register (STBC) Format ................................................................................................... 395

16-4

Format of Oscillation Stabilization Time Specification Register (OSTS) ................................................... 397

16-5

STOP Mode Release by NMI Input ............................................................................................................. 402

16-6

Example of Address/Data Bus Processing ................................................................................................. 406

17-1

Acknowledgment of Reset Signal ................................................................................................................ 409

17-2

Power-On Reset Operation .......................................................................................................................... 409

17-3

Timing on Reset Input .................................................................................................................................. 410

18-1

Format of Internal Memory Size Select Register (IMS) .............................................................................. 414

18-2

Selecting Format of Communication Mode ................................................................................................. 415

18-3

Connecting Flashpro II in 3-Wire Serial I/O Mode ...................................................................................... 416

18-4

Connecting Flashpro II in UART Mode ........................................................................................................ 416

A-1

Development Tool Configuration .................................................................................................................. 453

A-2

Dimensions of EV-9200GC-80 (reference) .................................................................................................. 461

A-3

Recommended Board Mounting Pattern of EV-9200GC-80 (reference) .................................................... 462

LIST OF FIGURES (6/6)

Figure No.

Title

Page

LIST OF TABLES (1/3)

Table No.

Title

Page

1-1

Differences between

PD784054 and

PD784046 Subseries ...................................................................

1-2

Differences between

PD784054 and

PD784054(A) ...............................................................................

1-3

Differences between

PD784054(A), 784054(A1), and 784054(A2) .........................................................

2-1

Operation Mode of Port 2 .............................................................................................................................

2-2

Operation Mode of Port 3 .............................................................................................................................

2-3

Operation Mode of Port 9 .............................................................................................................................

2-4

I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins ..........................................

3-1

Internal ROM Area .......................................................................................................................................

3-2

Vector Table ..................................................................................................................................................

3-3

Internal RAM Area ........................................................................................................................................

3-4

Register Bank Selection ...............................................................................................................................

3-5

Correspondence between Function Names and Absolute Names ............................................................

3-6

Special Function Registers (SFRs) List ......................................................................................................

5-1

Port Function ................................................................................................................................................

5-2

Operation Mode of Port 2 ............................................................................................................................. 103

5-3

Port 3 Operating Modes ............................................................................................................................... 110

5-4

Operation Mode of Port 4 ............................................................................................................................. 119

5-5

Operation Mode of Port 5 ............................................................................................................................. 125

5-6

Operation Mode of Port 6 ............................................................................................................................. 131

5-7

Operation Mode of Port 9 ............................................................................................................................. 138

5-8

Operation Mode of P90 through P93 ........................................................................................................... 141

6-1

Operations of Timer ...................................................................................................................................... 151

7-1

Interval Time of Timer 0 ............................................................................................................................... 155

7-2

Pulse Width Measurement Range of Timer 0 ............................................................................................. 156

7-3

Interrupt Request Signal from Compare Register (timer 0) ....................................................................... 165

7-4

Operation Mode of Timer Output Pin (timer 0) ........................................................................................... 165

7-5

Capture Trigger Signal to Capture Register (timer 0) ................................................................................. 167

7-6

Toggle Signal of Timer Output Pin (timer 0) ................................................................................................ 169

7-7

Set/Reset Signal of Timer Output Pin (timer 0) .......................................................................................... 169

7-8

Toggle Output of TO00 through TO03 (f

CLK

= 16 MHz) ............................................................................... 172

8-1

Interval Time of Timer 1 ............................................................................................................................... 183

8-2

Interrupt Request Signal from Compare Register (timer 1) ....................................................................... 193

8-3

Operation Mode of Timer Output Pin (timer 1) ........................................................................................... 193

8-4

Toggle Signal of Timer Output Pin (timer 1) ................................................................................................ 196

8-5

Set/Reset Signal of Timer Output Pin (timer 1) .......................................................................................... 196

8-6

Toggle Output of TO10 and TO11 (f

CLK

= 16 MHz) ..................................................................................... 197

9-1

Interval Time of Timer 4 ............................................................................................................................... 207

9-2

Interrupt Request Signal from Compare Register (timer 4) ....................................................................... 216

11-1

Conversion Time Set by FR Bit .................................................................................................................... 237

11-2

Time of A/D Conversion ............................................................................................................................... 242

11-3

Correspondence between Analog Input and A/D Conversion Result Register

(select mode: 1-buffer mode) ....................................................................................................................... 243

11-4

Correspondence between Analog Input and A/D Conversion Result Register

(select mode: 4-buffer mode) ....................................................................................................................... 244

11-5

Correspondence between Analog Input and A/D Conversion Result Register (scan mode) ................... 246

12-1

Differences Between UART/IOE1 and UART2/IOE2 Names ...................................................................... 255

12-2

Causes of Receive Error .............................................................................................................................. 268

12-3

Methods of Baud Rate Setting ..................................................................................................................... 286

12-4

Examples of BRGC Settings When Baud Rate Generator Is Used ........................................................... 287

12-5

Examples of Settings When External Baud Rate Input (ASCK) Is Used ................................................... 288

13-1

Pins P20 to P27 and Use of Detected Edge ............................................................................................... 291

14-1

Processing Modes of Interrupt Request ...................................................................................................... 301

14-2

Sources of Interrupt Request ....................................................................................................................... 302

14-3

Control Registers .......................................................................................................................................... 306

14-4

Interrupt Control Register Flags Corresponding to Interrupt Sources ....................................................... 307

14-5

Multiple Interrupt Processing ....................................................................................................................... 328

14-6

Interrupts for Which Macro Service Can Be Used ...................................................................................... 335

14-7

Classification of Macro Service Mode ......................................................................................................... 342

14-8

Specifying Operation of Counter Mode ....................................................................................................... 343

14-9

Specifying Operation in Block Transfer Mode ............................................................................................. 344

14-10

Specifying Operation in Block Transfer Mode (with memory pointer) ........................................................ 346

14-11

Interrupt Acceptance Processing Time ........................................................................................................ 357

14-12

Macro Service Processing Time .................................................................................................................. 358

16-1

Operating States in HALT Mode .................................................................................................................. 398

16-2

HALT Mode Release and Operations after Release ................................................................................... 399

16-3

Operating States in STOP Mode ................................................................................................................. 401

16-4

STOP Mode Release and Operations after Release .................................................................................. 402

16-5

Operating States in IDLE Mode ................................................................................................................... 403

16-6

IDLE Mode Release and Operations after Release ................................................................................... 404

17-1

Pin Status during Reset Input and after Clearing Reset ............................................................................ 410

17-2

State of Hardware after Reset ..................................................................................................................... 411

LIST OF TABLES (2/3)

Table No.

Title

Page

18-1

Communication Modes ................................................................................................................................. 415

18-2

Major Functions of Flash Memory Programming. ....................................................................................... 415

19-1

List of Instructions by 8-Bit Addressing ....................................................................................................... 446

19-2

List of Instructions by 16-Bit Addressing ..................................................................................................... 447

19-3

List of Instructions by 24-Bit Addressing ..................................................................................................... 448

19-4

List of Instructions by Bit Manipulation Instruction Addressing .................................................................. 448

19-5

List of Instructions by Call/Return Instruction/Branch Instruction Addressing .......................................... 449

LIST OF TABLES (3/3)

Table No.

Title

Page

CHAPTER 1 GENERAL

The

PD784054 is a product in the 78K/IV series and is provided with a 10-bit A/D converter. The 78K/IV series is a collection

of 16-bit single-chip microcontrollers with a high-performance CPU that has a function to access a 1M-byte memory space.

The

PD784054 is based on the

PD784046 subseries in the 78K/IV series but does not have the real-time output function

and two timer/counter units of the

PD784046 subseries. It is provided with a standby function invalid mode.

The

PD784054 has a 32K-byte mask ROM and a 1024-byte RAM. In addition, it also has a high-performance timer, 10-

bit A/D converter, and two independent serial interface channels.

The

PD78F4046 is under development as a flash memory model that can operate at the same supply voltage as the mask

ROM model. The

PD78F4046 is a model of the

PD784046 subseries and its functions are different from the

PD784054.

For the differences, refer to 1.8 Differences between

PD784054 and

PD784046 Subseries.

The

PD784054(A), 784054(A1), and 784054(A2) are the "special" quality revisions of the

PD784054.

These products can be used for the following applications.

[Standard models]

· Office machines such as PPCs and printers

· Factory machines such as robots and automatic machine tools

[Special models]

· Control units of automotive appliances

PD784046
subseries

PD78F4046

Flash memory
RAM

PD784046, 784046(A), (A1), (A2)

ROM
RAM

64K
2048

PD784044, 784044(A), (A1), (A2)

ROM
RAM

32K
1024

PD784054, 784054(A), (A1), (A2)

ROM
RAM

32K
1024

Mask ROM model

On-chip flash memory model

64K
2048

CHAPTER 1 GENERAL

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

PD784026

PD784038Y

C Bus Supported

Multi-Master I

C Bus Supported

PD784038

Increased Internal
Memory Capacity,
Pin-Compatible with PD784026

PD784225Y

Multi-Master I

C Bus Supported

PD784225

80 Pins,
ROM Collection Added

PD784218Y

Multi-Master I

C Bus Supported

PD784218

Increased Internal Memory Capacity,
ROM Collection Added

PD784928Y

Multi-Master I

C Bus Supported

PD784928

Reinforced Functions of PD784915

PD784216Y

PD784054

PD784046

PD784955

10-bit A/D

100 Pins,
Reinforced I/O and Internal Memory
Capacity

A/D, 16-Bit Timer,
Reinforced Power
Management

PD784915

Software Servo Control,
Analog Circuit for VCR,
Reinforced Timer

For DC Inverter Control

PD784943

Flash Memory for
CD-ROM: 56K Bytes

Standard Models

ASSP Models

: Under Mass Production

: Under Development

PD784216

PD784908

IEBus

Controller

CHAPTER 1 GENERAL

1.1 Features

78K/IV series

Minimum instruction execution time: 125 ns (at internal 16-MHz)

Internal memory

· ROM

Mask ROM

: 32K bytes

· RAM

: 1024 bytes

I/O port: 64 pins

Timer

: 16-bit timer x 3 units

Watchdog timer : 1 channel

A/D converter

: 10-bit resolution x 16 channels

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)

Interrupt controller (4 priority levels)

Vectored interrupt/macro service/context switching

Standby function

HALT/STOP/IDLE/standby function invalid mode

Supply voltage : V

= 4.5 to 5.5 V

1.2 Ordering Information

Part Number

Package

PD784054GC-xxx-3B9

80-pin plastic QFP (14

14 mm)

PD784054GC(A)-xxx-3B9

80-pin plastic QFP (14

14 mm)

PD784054GC(A1)-xxx-3B9

80-pin plastic QFP (14

14 mm)

PD784054GC(A2)-xxx-3B9

80-pin plastic QFP (14

14 mm)

Remark xxx indicates ROM code suffix.

1.3 Quality Grades

Part Number

Package

Quality Grade

PD784054GC-xxx-3B9

80-pin plastic QFP (14

14 mm)

Standard

PD784054GC(A)-xxx-3B9

80-pin plastic QFP (14

14 mm)

Special

PD784054GC(A1)-xxx-3B9

80-pin plastic QFP (14

14 mm)

Special

PD784054GC(A2)-xxx-3B9

80-pin plastic QFP (14

14 mm)

Special

Remark xxx indicates ROM code suffix.

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

CHAPTER 1 GENERAL

1.4 Pin Configuration (Top View)

· 80-pin plastic QFP (14 x 14 mm)

PD784054GC-xxx-3B9, 784054GC(A)-xxx-3B9, 784054GC(A1)-xxx-3B9, 784054GC(A2)-xxx-3B9

Cautions 1. Do not directly connect the MODE pin to V

2. Normally, directly connect the MODE1 pin to V

P70/ANI0

P71/ANI1

P72/ANI2

P73/ANI3

P74/ANI4

P75/ANI5

P76/ANI6

P77/ANI7

REF

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P22/INTP1/TO01

BWD

P21/INTP0/TO00

MODE

P20/NMI

MODE1

P12

P11

P10

P03

P02

P01

P00

P37/ASCK2/SCK2

P36/TxD2/SO2

P35/RxD2/SI2

P34/ASCK/SCK1

P33/TxD/SO1

P50/AD8

P51/AD9

P52/AD10

P53/AD11

P54/AD12

P55/AD13

P56/AD14

P57/AD15

P60/A16

P61/A17

P62/A18

P63/A19

P90/RD

P91/LWR

P92/HWR

P93/ASTB

P94/WAIT

P30/TO10

P31/TO11

P32/RxD/SI1

P87/ANI15

P86/ANI14

P85/ANI13

P84/ANI12

P83/ANI11

P82/ANI10

P81/ANI9

P80/ANI8

CLKOUT

P27/INTP6

P26/INTP5

P25/INTP4

P24/INTP3/TO03

RESET

P23/INTP2/TO02

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

CHAPTER 1 GENERAL

P40-P47

: Port4

P50-P57

: Port5

P60-P63

: Port6

P70-P77

: Port7

P80-P87

: Port8

P90-P94

: Port9

: Read Strobe

RESET

: Reset

RxD, RxD2

: Receive Data

SCK1, SCK2

: Serial Clock

SI1, SI2

: Serial Input

SO1, SO2

: Serial Output

TO00-TO03, TO10, TO11: Timer Output

TxD, TxD2

: Transmit Data

: Power Supply

: Ground

WAIT

: Wait

X1, X2

: Crystal

A16-A19

: Address Bus

AD0-AD15

: Address/Data Bus

ANI0-ANI15

: Analog Input

ASCK, ASCK2

: Asynchronous Serial Clock

ASTB

: Address Strobe

: Analog Power Supply

REF

: Analog Reference Voltage

: Analog Ground

BWD

: Bus Width Definition

CLKOUT

: Clock Out

HWR

: High Address Write Strobe

INTP0-INTP6

: Interrupt from Peripherals

LWR

: Low Address Write Strobe

MODE, MODE1

: Mode

NMI

: Non-maskable Interrupt

P00-P03

: Port0

P10-P12

: Port1

P20-P27

: Port2

P30-P37

: Port3

CHAPTER 1 GENERAL

1.5 System Configuration Example (PPC)

Serial communication

Paper feed/transporta-
tion detection

Fusion unit heater
temperature

Lamp light
quantity

Copy density
adjuster lever

Copy density
correction
lever

RxD

TxD

INTP0

ANI0

ANI1

ANI2

ANI3

Reset
circuit

RESET

P60

P61

P62

P63

SCK2

SI2

SO2

P10-P12

P40

P41

TO10

P00-P03

P42

P43

P44

P45

P46

Paper detection

Paper feed detection

Paper ejection detection

Manuscript table (scanner) position detection

Operation
panel

High-voltage
control circuit

Fusion unit
heater control
circuit

Lamp regulator

Driver

Drum, toner, charge for transcription

Fusion unit roller

Manuscript illumination lamp,
lamp for elimination of electric charge

(DC, stepping)

Main motor

Manuscript table (scanner)
stop clutch

Manuscript table (scanner)
forward clutch

Resist shutter clutch

Manual paper feed clutch

Cassette paper feed clutch

Solenoid

PD784054

CHAPTER 1 GENERAL

1.6 Block Diagram

Programmable
interrupt
controller

INTP0-INTP6

NMI

TO00-TO03

INTP0-INTP3

TO10, TO11

A/D
converter

REF

INTP4

ANI0-ANI15

Watchdog

timer

Timer 4

(16 bits)

Timer 1

(16 bits)

Timer 0

(16 bits)

78K/IV

CPU core

ROM

RAM

BUS I/F

BWD
AD0-AD15
A16-A19
RD
LWR, HWR
ASTB
WAIT

CLKOUT
RESET
MODE
MODE1
X1
X2

System
control

P00-P03

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

Port 8

Port 9

P10-P12

P20
P21-P27

P30-P37

P40-P47

P50-P57

P60-P63

P70-P77

P80-P87

P90-P94

UART/IOE1

ASCK/SCK1

RxD/SI1

TxD/SO1

Baud-rate

generator

UART/IOE2

ASCK2/SCK2

RxD2/SI2

TxD2/SO2

Baud-rate

generator

CHAPTER 1 GENERAL

1.7 List of Functions

Item

Function

Number of basic instructions

113

(mnemonics)

General-purpose register

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

Minimum instruction execution time

125 ns (at internal 16 MHz operation)

Internal memory

ROM

32 KB (mask ROM)

RAM

1024 B

Memory space

1 MB with program and data memories combined

I/O port

Total

64 lines

Input

17 lines

I/O

47 lines

Pins with ancially

Pin with pull-

29 pins

functions

Note

up resistor

Timer

Timer 0 (16 bits)

: Timer register

1 Pulse output

Capture/Compare register

· Toggle output

· Set/Reset output

Timer 1 (16 bits)

: Timer register

1 Pulse output

Compare register

· Toggle output

· Set/Reset output

Timer 4 (16 bits)

: Timer register

Compare register

A/D converter

10-bit resolution

16 channels

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)

Watchdog timer

1 channel

Interrupt

Hardware source

23 (internal: 19, external: 8 (shared with internal: 4)

Software source

BRK instruction, BRKCS instruction, operand error

Non-maskable

Internal : 1, external : 1

Maskable

Internal : 18, external: 7 (shared with internal: 4)

· 4 priority levels

· Three processing formats: vectored interrupt/macro service/context switching

Bus sizing

8 bits/16 bits external data bus width selectable

Standby

HALT/STOP/IDLE/standby function invalid mode

Supply voltage

= 4.5 to 5.5 V

Package

80-pin plastic QFP (14

14 mm)

Note

The pins with ancillary functions are included in the I/O pins.

CHAPTER 1 GENERAL

1.8 Differences between

PD784054 and

PD784046 Subseries

The differences between

PD784054 and

PD784046 subseries are shown in Table 1-1.

Table 1-1. Differences between

PD784054 and

PD784046 Subseries

Part Number

PD784054

PD784046 Subseries

Item

PD784044

PD784046

PD78F4046

Internal ROM

32 KB

64 KB

(mask ROM)

(flash memory)

Internal RAM

1024 B

2048 B

Port 1

P10-P12

P10-P13

Real-time output port

Not provided

4 bits

Timer/counter

16 bits timer

16 bits timer/counter

2 units

3 units

16 bits timer

3 units

Standby function

HALT/STOP/IDLE/

HALT/STOP/IDLE mode

standby function

invalid mode

MODE1 pin

Provided

Not provided

Function of pin 57

Mode

Mode/V

Interrupt hardware source

CHAPTER 1 GENERAL

1.9 Differences between

PD784054 and

PD784054(A)

Table 1-2. Differences between

PD784054 and

PD784054(A)

Part Number

PD784054

PD784054(A)

Item

Quality grade

Standard

Special

Operating ambient temperature (T

)

10 to +70

40 to +85

Operating frequency

8 to 32 MHz

8 to 25 MHz

Minimum instruction execution time

125 ns (operates at 16 MHz internally)

160 ns (operates at 12.5 MHz internally)

DC characteristics

supply current differs.

AC characteristics

Bus timing and serial operation differ.

A/D converter characteristics

Conversion time and sampling time differ.

1.10 Differences between

PD784054(A), 784054(A1), and 784054(A2)

Table 1-3. Differences between

PD784054(A), 784054(A1), and 784054(A2)

Part Number

PD784054(A)

PD784054(A1)

PD784054(A2)

Item

Operating ambient temperature (T

)

40 to +85

40 to +110

40 to +125

Operating frequency

8 to 25 MHz

8 to 20 MHz

Minimum instruction execution time

160 ns

200 ns

(operates at 12.5 MHz internally)

(operates at 10 MHz internally)

DC characteristics

Analog pin input leakage current, V

supply current, and data retention current differ.

AC characteristics

Bus timing and serial operation differ.

A/D converter characteristics

REF

current, A/D converter data retention current differ.

CHAPTER 2 PIN FUNCTIONS

2.1 List of Pin Functions

(1) Port (1/2)

Pin Name

I/O

Dual-Function Pins

Function

P00-P03

I/O

Port 0 (P0):

· 4-bit I/O port

· Can be set in input/output mode bit-wise.

· Pins in input mode can all be connected to pull-up resistors at once

via software.

P10-P12

I/O

Port 1 (P1):

· 3-bit I/O port

· Can be set in input/output mode bit-wise.

P20

Input

NMI

Port 2 (P2):

Input only

P21

I/O

INTP0/TO00

· 8-bit I/O port

Can be set in input/output mode

P22

INTP1/TO01

bit-wise.

P23

INTP2/TO02

P24

INTP3/TO03

P25

INTP4

P26

INTP5

P27

INTP6

P30

I/O

TO10

Port 3 (P3):

P31

TO11

· 8-bit I/O port

P32

RxD/SI1

· Can be set in input/output mode bit-wise.

P33

TxD/SO1

P34

ASCK/SCK1

P35

RxD2/SI2

P36

TxD2/SO2

P37

ASCK2/SCK2

P40-P47

I/O

AD0-AD7

Port 4 (P4):

· 8-bit I/O port

· Can be set in input/output mode bit-wise.

· Pins in input mode can all be connected to pull-up resistors at once

via software.

P50-P57

I/O

AD8-AD15

Port 5 (P5):

· 8-bit I/O port

· Can be set in input/output mode bit-wise.

· Pins in input mode can all be connected to pull-up resistors at once

via software.

P60-P63

I/O

A16-A19

Port 6 (P6):

· 4-bit I/O port

· Can be set in input/output mode bit-wise.

· Pins in input mode can all be connected to pull-up resistors at once

via software.

CHAPTER 2 PIN FUNCTIONS

(1) Port (2/2)

Pin Name

I/O

Dual-Function Pins

Function

P70-P77

Input

ANI0-ANI7

Port 7 (P7):

· 8-bit input port

P80-P87

Input

ANI8-ANI15

Port 8 (P8):

· 8-bit input port

P90

I/O

Port 9 (P9):

P91

LWR

· 5-bit I/O port

P92

HWR

· Can be set in input/output mode bit-wise.

P93

ASTB

· Pins in input mode can all be connected to pull-up resistors at once

P94

WAIT

via software.

CHAPTER 2 PIN FUNCTIONS

(2) Pins other than port pins (1/2)

Pin Name

I/O

Dual-Function Pins

Function

NMI

Input

P20

Non-maskable interrupt request input

INTP0

P21/TO00

External interrupt

Capture trigger signal of CC00

INTP1

P22/TO01

request input

Capture trigger signal of CC01

INTP2

P23/TO02

Capture trigger signal of CC02

INTP3

P24/TO03

Capture trigger signal of CC03

INTP4

P25

Conversion start trigger input of A/D converter

INTP5

P26

INTP6

P27

TO00

Output

P21/INTP0

Timer output

TO01

P22/INTP1

TO02

P23/INTP2

TO03

P24/INTP3

TO10

P30

TO11

P31

RxD

Input

P32/SI1

Serial data input (UART0)

RxD2

P35/SI2

Serial data input (UART2)

TxD

Output

P33/SO1

Serial data output (UART0)

TxD2

P36/SO2

Serial data output (UART2)

ASCK

Input

P34/SCK1

Baud rate clock input (UART0)

ASCK2

P37/SCK2

Baud rate clock input (UART2)

SI1

Input

P32/RxD

Serial data input (3-wire serial I/O1)

SI2

P35/RxD2

Serial data input (3-wire serial I/O2)

SO1

Output

P33/TxD

Serial data output (3-wire serial I/O1)

SO2

P36/TxD2

Serial data output (3-wire serial I/O2)

SCK1

I/O

P34/ASCK

Serial clock input/output (3-wire serial I/O1)

SCK2

P37/ASCK2

Serial clock input/output (3-wire serial I/O2)

AD0-AD7

I/O

P40 to P47

Lower multiplexed address/data bus when external memory is connected

AD8-AD15

Note

I/O

P50 to P57

· When 8-bit bus is specified

Higher address bus when external memory is connected

· When external 16-bit bus is specified

Higher multiplexed address/data bus when external memory is connected

A16-A19

Note

Output

P60 to P63

Higher address bus when external memory is connected

Output

P90

Read strobe to external memory

Note

The number of pins used as address bus pins differs depending on the external address space (refer to

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION).

CHAPTER 2 PIN FUNCTIONS

(2) Pins other than port pins (2/2)

Pin Name

I/O

Dual-Function Pins

Function

LWR

Output

P91

· When external 8-bit bus is specified

Write strobe to external memory

· When external 16-bit bus is specified

Write strobe to external memory located at lower position

HWR

P92

Write strobe to external memory located at higher position when external

16-bit bus is specified

ASTB

Output

P93

Timing signal output to externally latch address information output from

AD0 through AD15 pins to access external memory

WAIT

Input

P94

Inserts wait.

BWD

Input

Sets bus width.

MODE

Input

Directly connect this pin to V

(this pin specifies test mode of IC).

MODE1

Input

Specifies standby function invalid mode.

Connect this pin to V

when this mode is not used.

CLKOUT

Output

Clock output. Low level is output in the IDLE mode or STOP mode, otherwise

(oscillation frequency) is always output.

Input

Connect crystal for system clock oscillation (clock can be also input to X1).

RESET

Input

Chip reset

ANI0-ANI7

Input

P70 to P77

Analog voltage input for A/D converter

ANI8-ANI15

P80 to P87

REF

Reference voltage for A/D converter

Positive power for A/D converter

GND for A/D converter

Positive power

GND

CHAPTER 2 PIN FUNCTIONS

2.2 Description of Pin Functions

(1) P00 through P03 (Port 0) ... 3-state I/O

Port 0 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 0 mode register (PM0). Each pin of this port is provided with a software programmable pull-up resistor.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

(2) P10 through P12 (Port 1) ... 3-state I/O

Port 1 is a 3-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 1 mode register (PM1).

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

(3) P20 through P27 (Port 2) ... 3-state I/O

Port 2 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 2 mode register (PM2) (however, P20 is input-only).

In addition to the input/output port function, port 2 also functions as external interrupt signals, and to output the

timer signal of timer 0 (refer to Table 2-1). P21 through P24 serve as the timer output pins of timer 0 if so specified

by port 2 mode control register (PMC2). The level of each pin of this port can always be read or tested regardless

of the multiplexed function. All the eight pins are Schmitt trigger input pins to prevent malfunctioning due to noise.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

Table 2-1. Operation Mode of Port 2

(n = 0 to 7)

Mode

Port Mode

Control Signal Output Mode

Set condition

PMC2n = 0

PMC2n = 1

PM2n = 0

PM2n = 1

PM2n =

P20

Input port/NMI input

Note

P21

Output port

Input port/INTP0 input

TO00 output

P22

Input port/INTP1 input

TO01 output

P23

Input port/INTP2 input

TO02 output

P24

Input port/INTP3 input

TO03 output

P25

Input port/INTP4 input

P26

Input port/INTP5 input

P27

Input port/INTP6 input

Note

The NMI input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled.

Remark

: don't care

(a) Port mode

(i) Function as port pin

Each port pin set in the port mode by the port 2 mode control register (PMC2) can be set in the input or

output mode in 1-bit units by the port 2 mode register (PM2) (however, P20 is fixed in input only).

CHAPTER 2 PIN FUNCTIONS

(ii) Function as control signal input pins

If PMC2n (n = 0 to 7) bit of PMC2 is "0" and if PM2n (n = 0 to 7) bit of PM2 is "1", the pins of port 2 can

be used as the following control signal input pins.

NMI (Non-maskable Interrupt)

This pin inputs an external non-maskable interrupt request. Whether the interrupt request is detected

at the rising or falling edge can be specified by using external interrupt mode register 0 (INTM0).

INTP0 through INTP6 (Interrupt from Peripherals)

These pins input external interrupt requests. When the valid edge specified by external interrupt mode

registers (INTM0 and INTM1) is detected on the INTP0 to INTP6 pins, an interrupt occurs (refer to

CHAPTER 13 EDGE DETECTION FUNCTION).

The INTP0 through INTP4 pins can also be used as external trigger input pins of each function, as

follows:

INTP0 ... Capture trigger input pin of capture/compare register 00 (CC00) of timer 0

INTP1 ... Capture trigger input pin of capture/compare register 01 (CC01) of timer 0

INTP2 ... Capture trigger input pin of capture/compare register 02 (CC02) of timer 0

INTP3 ... Capture trigger input pin of capture/compare register 03 (CC03) of timer 0

INTP4 ... External trigger input pin of A/D converter

(b) Control signal output mode

The P21 through P24 pins can be used as the timer output pins (TO00 through TO03) of timer 0 in 1-bit units

if so specified by the port 2 mode control register (PMC2).

(4) P30 through P37 (Port 3) ... 3-state I/O

Port 3 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 3 mode register (PM3).

In addition to the input/output port function, port 3 also has a function to input or output control signals. The

operation mode of each pin can be specified by using port 3 mode control register (PMC3), as shown in Table 2-

2. The level of each pin of this port can always be read or tested regardless of the multiplexed function.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

Table 2-2. Operation Mode of Port 3

(n = 0 to 7)

Mode

Port Mode

Control Signal I/O Mode

Setting condition

PMC3n = 0

PMC3n = 1

P30

I/O port

TO10 output

P31

TO11 output

P32

RxD/SI1 input

P33

TxD/SO1 output

P34

ASCK input/SCK1 I/O

P35

RxD2/SI2 input

P36

TxD2/SO2 output

P37

ASCK2 input/SCK2 I/O

CHAPTER 2 PIN FUNCTIONS

(a) Port mode

Each port pin set in the port mode by the port 3 mode control register (PMC3) can be set in the input or output

mode by the port 3 mode register (PM3).

(b) Control signal I/O mode

Each pin of port 3 can be set in the control mode in 1-bit units by using the port 3 mode control register (PMC3).

(i) TO10, TO11 (Timer Output)

These are timer output pins of timer 1.

(ii) RxD, RxD2 (Receive Data)

These are serial data input pins of the asynchronous serial interface.

(iii) TxD, TxD2 (Transmit data)

These are serial data output pins of the asynchronous serial interface.

(iv) SI1, SI2 (Serial Input)

These are serial data input pins of the 3-wire serial I/O.

(v) SO1, SO2 (Serial Output)

These are serial data output pins of the 3-wire serial I/O.

(vi) ASCK, ASCK2 (Asynchronous Serial Clock)

These are external baud rate clock input pins.

(vii) SCK1, SCK2 (Serial Clock)

These are serial clock I/O pins of the 3-wire serial I/O.

(5) P40 through P47 (Port 4) ... 3-state I/O

Port 4 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 4 mode register (PM4). Each pin is provided with a software programmable pull-up resistor.

Port 4 functions as the low-order multiplexed address/data bus (AD0 through AD7) if so specified by memory

expansion mode register (MM) when an external memory or I/O is connected, in addition to the I/O port function.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

(6) P50 through P57 (Port 5) ... 3-state I/O

Port 5 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 5 mode register (PM5). Each pin is provided with a software programmable pull-up resistor.

This port functions as follows if so specified by memory expansion mode register (MM) when an external memory

or I/O is connected:

When external 8-bit bus is specified

As the high-order address bus (AD8 through AD15)

When external 16-bit bus is specified

As the high-order multiplexed address/data bus (AD8 through AD15).

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

CHAPTER 2 PIN FUNCTIONS

(7) P60 through P63 (Port 6) ... 3-state I/O

Port 6 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 6 mode register (PM6). Each pin is provided with a software programmable pull-up resistor.

In addition to as an I/O port, this port also functions as the high-order address bus (A16 through A19) if so specified

by the memory expansion mode register when an external memory or I/O is connected.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

(8) P70 through P77 (Port 7) ... Input

Port 7 is an 8-bit input port. In addition to as input port pins, its pins also function as an A/D converter analog input

(low-order 8 channels) pins (ANI0 through ANI7), and can always input analog signals. This port is set in the analog

input mode by using A/D converter mode register (ADM).

The level of each pin of this port can always be read or tested, regardless of the multiplexed function.

(9) P80 through P87 (Port 8) ... Input

Port 8 is an 8-bit input port. In addition to functioning as input port pins, its pins also functions as an A/D converter

analog input (high-order 8 channels) pins (ANI8 through ANI15), and can always input analog signals. This port

is set in the analog input mode by using A/D converter mode register (ADM).

The level of each pin of this port can always be read or tested, regardless of the multiplexed function.

(10) P90 through P94 (Port 9) ... 3-state I/O

Port 9 is a 5-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 9 mode register (PM9). Each pin is provided with a software programmable pull-up resistor.

In addition to the I/O port function, port 9 also functions as control signal pins (refer to Table 2-3). P90 through

P93 function as read/write strobe signals and an address strobe signal if so specified by the memory extension

mode register (MM) when an external memory or I/O is connected. P94 functions as a wait signal input pin if so

specified by port 9 mode control register (PMC9).

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the

output latch are undefined.

Table 2-3. Operation Mode of Port 9

Pin Name

Port Mode

Control Signal I/O Mode

Manipulation to Use Port 9 as Control Pins

P90

I/O Port

Specifying external memory expansion mode by

P91

LWR

MM0 through MM3 bits of MM

P92

HWR

P93

ASTB

P94

WAIT

Setting of PMC94 bit of PMC9 to 1

Remark

For details, refer to CHAPTER 15 LOCAL BUS INTERFACE FUNCTION.

CHAPTER 2 PIN FUNCTIONS

(a) Port mode

Each port pin not set in the control mode can be set in the input or output mode by using the port 9 mode register

(PM9).

(b) Control signal I/O mode

(i) RD (Read Strobe)

This pin outputs a strobe signal to read an external memory. The operation of this pin is specified by the

memory extension mode register (MM).

(ii) LWR, HWR (Low/High Write Strobe)

These pins output strobe signals to write an external memory. The operations of these pins are specified

by the memory extension mode register (MM).

(iii) ASTB (Address Strobe)

This is a timing signal output pin to latch the address information output from the AD0 through AD15 pins

to access the external memory. The operation of this pin is specified by the memory extension mode

(iv) WAIT (Wait)

This pin inputs a wait signal. The operation of this pin is specified by the port 9 mode control register

(PMC9).

(11) BWD (Bus Width Definition) ... Input

This pin specifies the width of the bus. Depending on the setting of this pin, the value of the bus width specification

BWD

External Bus Width

Value of BW at Reset

8 bits

0000H

16 bits

00FFH

(12) MODE (Mode) ... Input

This pin is used by NEC for testing IC. Be sure to directly connect this pin to V

(13) MODE1 (Mode) ... Input

This pin specifies the standby function invalid mode.

Connect this pin to V

when this mode is not used.

(14) CLKOUT (Clock Output) ... Output

Clock output. Low level is output in the IDLE mode or STOP mode, otherwise f

(oscillation frequency) is always

output.

(15) X1, X2 (Crystal)

These pins are used to connect a crystal for internal clock oscillation. To supply an external clock, input the clock

to the X1 pin. For the processing of the X2 pin at this time, refer to CHAPTER 4 CLOCK GENERATOR.

(16) RESET (Reset) ... Input

Active-low reset input

CHAPTER 2 PIN FUNCTIONS

(17) AV

REF

(Analog Reference Voltage)

This pin inputs a reference voltage to the A/D converter.

(18) AV

(Analog Power Supply)

This is the power supply pin of the A/D converter. Keep the potential at this pin same as that of the V

pin.

(19) AV

(Analog Ground)

This is the GND pin of the A/D converter. Keep the potential at this pin same as that of the V

pin.

(20) V

(Power Supply)

This is a positive power supply. Connect all the V

pins to a positive power supply.

(21) V

(Ground)

This is a GND pin. Ground all the V

pins.

CHAPTER 2 PIN FUNCTIONS

2.3 I/O Circuits of Pins and Processing of Unused Pins

Table 2-4 shows the I/O circuit type of each pin and recommended processing of the unused pins.

For the I/O circuit type, refer to Figure 2-1.

Table 2-4. I/O Circuit Type of Each Pin and Recommended Processing of Unused Pins

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

P00-P03

5-A

I/O

Input: Individually connect to V

or V

via resistor.

P10-P12

Output: Leave unconnected.

P20/NMI

Input

Connect to V

P21/INTP0/TO00

I/O

Input: Individually connect to V

or V

via resistor.

P22/INTP1/TO01

Output: Leave unconnected.

P23/INTP2/TO02

P24/INTP3/TO03

P25/INTP4

P26/INTP5

P27/INTP6

P30/TO10

P31/TO11

P32/RxD/SI1

P33/TxD/SO1

P34/ASCK/SCK1

P35/RxD2/SI2

P36/TxD2/SO2

P37/ASCK2/SCK2

P40/AD0-P47/AD7

5-A

P50/AD8-P57/AD15

P60/A16-P63/A19

P70/ANI0-P77/ANI7

Input

Connect to V

P80/ANI8-P87/ANI15

P90/RD

5-A

I/O

Input: Individually connect to V

or V

via resistor.

P91/LWR

Output: Leave unconnected.

P92/HWR

P93/ASTB

P94/WAIT

MODE, MODE1

Input

Directly connect to V

RESET

CLKOUT

Output

Leave unconnected.

REF

Connect to V

Remark

The circuit type numbers are serial in the 78K series but are not always so with some models (because some

models are not provided with particular circuits).

CHAPTER 2 PIN FUNCTIONS

Type 2

Schmitt trigger input with hysteresis characteristics

Type 1

P-ch

N-ch

Type 3

Type 5

Data

Output

Disable

P-ch

IN/OUT

N-ch

Input

Enable

Type 5-A

Data

Output

Disable

P-ch

IN/OUT

N-ch

Input

Enable

P-ch

Pullup

Enable

Type 8

Data

Output

Disable

P-ch

IN/OUT

N-ch

Comparator

+
_

REF

(Threshold voltage)

P-ch

N-ch

Input
enable

Type 9

P-ch

OUT

N-ch

Figure 2-1. I/O Circuits of Pins

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Space

The

PD784054 can access a 1 M-byte memory space. The mapping of the internal data area (special function registers

and internal RAM) depends on the LOCATION instruction. A LOCATION instruction must be executed after reset release,

and can only be used once.

The program after reset release must be as follows:

RSTVCT

CSEG

AT 0

RSTSTRT

INITSEG

CSEG

BASE

RSTSTRT:

LOCATION 0H; or LOCATION 0FH

MOVG SP, #STKBGN

(1) When LOCATION 0 instruction is executed

The internal data area is mapped onto addresses 0FB00H to 0FFFFH.

Internal ROM is mapped onto addresses 0 to 07FFFH.

External memory is accessed in external memory extension mode.

(2) When LOCATION 0FH instruction is executed

The internal data area is mapped onto addresses FFB00H to FFFFFH.

Internal ROM is mapped onto addresses 0 to 07FFFH.

External memory is accessed in external memory extension mode.

CHAPTER 3 CPU ARCHITECTURE

Figure 3-1. Memory Map

Notes 1. Accessed in the external memory extension mode.

2. Base area or entry area by reset or interrupt. The internal RAM is not reset.

External Memory

Note 1

(960K Bytes)

Special Function Registers (SFRs)

Note 1

(256 Bytes)

Internal RAM

(1K Bytes)

Cannot Be Used

(1280 Bytes)

Internal ROM

(32K Bytes)

General-Purpose Registers

(128 Bytes)

Macro Service Control

Word Area (50 Bytes)

Data Area (512 Bytes)

Program/Data Area

(512 Bytes)

Program/Data Area

(32K Bytes)

CALLF Entry Area

(2K Bytes)

CALLT Table Area

(64 Bytes)

Vector Table Area

(64 Bytes)

When LOCATION 0

Instruction Is Executed

Cannot Be Used

(1280 Bytes)

External Memory

Note 1

(1013248 Bytes)

Internal ROM

(32K Bytes)

When LOCATION 0FH

Instruction Is Executed

Special Function Registers (SFR

)

Note 1

(256 Bytes)

Internal RAM

(1K Bytes)

Note 2

Main RAM

Peripheral
RAM

H
H
H
H
H
H

0
F
F
0
0
F

0
F

D
D

0
F

0
F
F
F
F

0
F
F
F
F
F

1
0
0
0
0
0

H
H

0
F

B
A

F
F

0
0

H
H

0
F

6
5

F
F

0
0

H
H

0
F

8
7

0
0

External Memory

Note 1

(30208 Bytes)

H
H

0
F

8
7

E
E

F
F

0
0

H
H

0
F

D
C

F
F

0
0

H
H

0
F

1
0

0
0

H
H

0
F

8
7

0
0

H
H

0
F

8
7

0
0

H
H

0
F

8
7

E
E

F
F

H
H

0
F

D
C

F
F

H
H

0
F

6
5

F
F

H
H

0
F

8
7

0
0

H
H

0
F

1
0

H
H

0
F

B
A

F
F

Note 2

H
H

0
F

4
3

0
0

CHAPTER 3 CPU ARCHITECTURE

3.2 Internal ROM Area

The

PD784054 subseries products incorporate ROM which is used to store programs, table data, etc.

Table 3-1. Internal ROM Area

Product Name

Internal ROM

Address Space

Location 0 Instruction

Location 0FH Instruction

PD784054

32 K

8 bits

00000H-07FFFH

The internal ROM can be accessed at high speed. Normally, fetches are performed at the same speed as external ROM,

but if the IFCH bit of the memory extension mode register (MM) is set (1), the high-speed fetch function is used and internal

ROM fetches are performed at high speed (2-byte fetch performed in 2 system clocks).

When the instruction execution cycle equal to an external ROM fetch is selected, wait insertion is performed by the wait

function, but when high-speed fetches are used, wait insertion is not performed for internal ROM.

RESET input sets the instruction execution cycle equal to the external ROM fetch cycle.

3.3 Base Area

The space from 0 to FFFFH comprises the base area. The base area is the object for the following uses:

Reset entry address

Interrupt entry address

CALLT instruction entry address

16-bit immediate addressing mode (with instruction address addressing)

16-bit direct addressing mode

16-bit register addressing mode (with instruction address addressing)

16-bit register indirect addressing mode

Short direct 16-bit memory indirect addressing mode

The vector table area, CALLT instruction table area and CALLF instruction entry area are allocated to the base area.

When the LOCATION 0 instruction is executed, the internal data area is located in the base area. Note that, in the internal

data area, program fetches cannot be performed from the internal high-speed RAM area or special function register (SFR)

area. Also, internal RAM area data should only be used after initialization has been performed.

CHAPTER 3 CPU ARCHITECTURE

3.3.1 Vector table area

The 64-byte area from 00000H to 0003FH is reserved as the vector table area. The vector table area stores the program

start addresses used when a branch is made as the result of RESET input or generation of an interrupt request. When context

switching is used by an interrupt, the number of the register bank to be switched to is stored here.

Any portion not used as the vector table can be used as program memory or data memory.

16-bit values can be written to the vector table. Therefore, branches can only be made within the base area.

Table 3-2. Vector Table

Vector Table Address

Interrupt Cause

0003CH

Operand error

0003EH

BRK

00000H

Reset (RESET input)

00002H

NMI

00004H

INTWDT

00006H

INTOV0

00008H

INTOV1

0000AH

INTOV4

0000CH

INTP0/INTCC00

0000EH

INTP1/INTCC01

00010H

INTP2/INTCC02

00012H

INTP3/INTCC03

00014H

INTP4

00016H

INTP5

00018H

INTP6

0001AH

INTCM10

0001CH

INTCM11

00026H

INTCM40

00028H

INTCM41

0002AH

INTSER

0002CH

INTSR/INTCSI1

0002EH

INTST

00030H

INTSER2

00032H

INTSR2/INTCSI2

00034H

INTST2

00036H

INTAD

CHAPTER 3 CPU ARCHITECTURE

3.3.2 CALLT instruction table area

The 1-byte call instruction (CALLT) subroutine entry addresses can be stored in the 64-byte area from 00040H to 0007FH.

The CALLT instruction references this table, and branches to a base area address written in the table as a subroutine.

As the CALLT instruction is one byte in length, use of the CALLT instruction for subroutine calls written frequently throughout

the program enables the program object size to be reduced. The table can contain up to 32 subroutine entry addresses,

and therefore it is recommended that they be recorded in order of frequency.

If this area is not used as the CALLT instruction table, it can be used as ordinary program memory or data memory.

3.3.3 CALLF instruction entry area

A subroutine call can be made directly to the area from 00800H to 00FFFH with the 2-byte call instruction (CALLF).

As the CALLF instruction is a two-byte call instruction, it enables the object size to be reduced compared with use of

the direct subroutine call CALL instruction (3 or 4 bytes).

Writing subroutines directly in this area is an effective means of exploiting the high-speed capability of the device.

If you wish to reduce the object size, writing an unconditional branch (BR) instruction in this area and locating the

subroutine itself outside this area will result in a reduced object size for subroutines that are called from five or more points.

In this case, only the 4 bytes of the BR instruction are occupied in the CALLF entry area, enabling the object size to be reduced

with a large number of subroutines.

CHAPTER 3 CPU ARCHITECTURE

3.4 Internal Data Area

The internal data area consists of the internal RAM area and special function register area (refer to Figure 3-1).

The final address of the internal data area can be specified by means of the LOCATION instruction as either 0FFFFH

(when a LOCATION 0 instruction is executed) or FFFFFH (when a LOCATION 0FH instruction is executed). Selection of

the addresses of the internal data area by means of the LOCATION instruction must be executed once immediately after

reset release, and once the selection is made, it cannot be changed. The program after reset release must be as shown

in the example below. If the internal data area and another area are allocated to the same addresses, the internal data

area is accessed and the other area cannot be accessed.

Example

RSTVCT

CSEG

AT 0

RSTSTRT

INITSEG

CSEG

BASE

RSTSTRT: LOCATION 0H; or LOCATION 0FH

MOVG

SP, #STKBGN

Caution When the LOCATION 0 instruction is executed, it is necessary to ensure that the program after reset

release does not overlap the internal data area. It is also necessary to make sure that the entry

addresses of the processing routines for non-maskable interrupts such as NMI do not overlap the

internal data area. Also, initialization must be performed for maskable interrupt entry areas, etc.,

before the internal data area is referenced.

3.4.1 Internal RAM area

The

PD784054 incorporates general-purpose static RAM.

This area is configured as follows:

Peripheral RAM (PRAM)

Internal RAM area

Internal high-speed RAM (IRAM)

Table 3-3. Internal RAM Area

Internal RAM

Internal RAM Area

Product Name

Peripheral RAM: PRAM

Internal High-Speed RAM: IRAM

PD784054

1024 bytes

512 bytes

(0FB00H-0FEFFH)

(0FB00H-0FCFFH)

(0FD00H-0FEFFH)

Remark

The addresses in the table are the values that apply when the LOCATION 0 instruction is executed. When

the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.

CHAPTER 3 CPU ARCHITECTURE

The internal RAM memory map is shown in Figure 3-2.

Figure 3-2. Internal RAM Memory Map

Remark

The addresses in the figure are the values that apply when the LOCATION 0 instruction is executed. When

the LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown above.

00FEFFH

00FE80H

00FE37H

00FE06H

00FE00H

00FDFFH

Peripheral RAM

Internal High-Speed RAM

Macro Service
Control Word Area

General-Purpose
Register Area

Short Direct Addressing 1
Permissible Range

Short Direct Addressing 2
Permissible Range

00FD20H

00FD1FH

00FD00H

00FCFFH

00FB00H

CHAPTER 3 CPU ARCHITECTURE

(1) Internal high-speed RAM (IRAM)

The internal high-speed RAM (IRAM) allows high-speed accesses to be made. The short direct addressing mode

for high-speed accesses can be used on FD20H to FEFFH in this area. There are two kinds of short direct addressing

mode, short direct addressing 1 and short direct addressing 2, according to the target address. The function is the

same in both of these addressing modes. With some instructions, the word length is shorter with short direct

addressing 2 than with short direct addressing 1. Refer to the 78K/IV Series User's Manual - Instruction for details.

A program fetch cannot be performed from IRAM. If a program fetch is performed from an address onto which IRAM

is mapped, CPU inadvertent loop will result.

The following areas are reserved in IRAM.

General-purpose register area

: FE80H to FEFFH

Macro service control word area : FE06H to FE37H

Macro service channel area

: FE00H to FEFFH (the address is specified by the macro service control word)

If the reserved function is not used in these areas, they can be used as ordinary data memory.

Remark

The addresses in this text are those that apply when the LOCATION 0 instruction is executed. When the

LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.

(2) Peripheral RAM (PRAM)

The peripheral RAM (PRAM) is used as ordinary program memory or data memory. When used as program memory,

the program must be written to the peripheral RAM beforehand by a program.

Program fetches from peripheral RAM are fast, with a 2-byte fetch being executed in 2 clocks.

CHAPTER 3 CPU ARCHITECTURE

3.4.2 Special function register (SFR) area

The on-chip peripheral hardware special function registers (SFRs) are mapped onto the area from 0FF00H to 0FFFFH

(refer to Figure 3-1).

The area from 0FFD0H to 0FFDFH is mapped as an external SFR area, and allows externally connected peripheral I/

Os, etc., to be accessed in external memory extension mode (specified by the memory extension mode register (MM)).

Caution Addresses onto which SFRs are not mapped should not be accessed in this area. If such an address

is accessed by mistake, the CPU may become deadlocked. A deadlock can only be released by reset

input.

Remark

The addresses in this text are those that apply when the LOCATION 0 instruction is executed. When the

LOCATION 0FH instruction is executed, 0F0000H should be added to the values shown in the text.

3.4.3 External SFR area

PD784054, the 16-byte area from 0FFD0H to 0FFDFH in the SFR area (when the LOCATION 0 is executed; 0FFFD0H

to 0FFFDFH when the LOCATION 0FH instruction is executed) is mapped as an external SFR area. When the external

memory extension mode is externally connected peripheral I/Os, etc., can be accessed using the address bus or address/

data bus, etc.

As the external SFR area can be accessed by SFR addressing, peripheral I/O and similar operations can be performed

easily, the object size can be reduced, and macro service can be used.

Bus operations for accesses to the external SFR area are performed in the same way as for ordinary memory accesses.

3.5 External Memory Space

The external memory space is a memory space that can be accessed in accordance with the setting of the memory

extension mode register (MM). It can store programs, table data, etc., and can have peripheral I/O devices allocated to

it.

CHAPTER 3 CPU ARCHITECTURE

3.6 Control Registers

Control registers consist of the program counter (PC), program status word (PSW), and stack pointer (SP).

3.6.1 Program counter (PC)

This is a 20-bit binary counter that holds address information on the next program to be executed (refer to Figure 3-3).

Normally, the PC is incremented automatically by the number of bytes in the fetched instruction. When an instruction

associated with a branch is executed, the immediate data or register contents are set in the PC.

Upon RESET input, the 16-bit data in address 0 and 1 is set in the low-order 16 bits, and 0000 in the high-order 4 bits

of the PC.

Figure 3-3. Format of Program Counter (PC)

3.6.2 Program status word (PSW)

The program status word (PSW) is a 16-bit register comprising various flags that are set or reset according to the result

of instruction execution.

Read accesses and write accesses are performed in high-order 8-bit (PSWH) and low-order 8-bit (PSWL) units.

Individual flags can be manipulated by bit-manipulation instructions.

The contents of the PSW are automatically saved to the stack when a vectored interrupt request is acknowledged or

a BRK instruction is executed, and automatically restored when an RETI or RETB instruction is executed. When context

switching is used, the contents are automatically saved in RP3, and automatically restored when an RETCS or RETCSB

instruction is executed.

RESET input resets (0) all bits.

"0" must always be written to the bits written as "0" in Figure 3-4. The contents of bits written as "-" are undefined when

read.

Figure 3-4. Format of Program Status Word (PSW)

The flags are described below.

(1) Carry flag (CY)

The carry flag records a carry or borrow resulting from an operation.

This flag also records the shifted-out value when a shift/rotate instruction is executed, and functions as a bit

accumulator when a bit-manipulation instruction is executed.

The status of the CY flag can be tested with a conditional branch instruction.

PSWH

Symbol

RBS2

RBS1

RBS0

PSWL

RSS

P/V

CHAPTER 3 CPU ARCHITECTURE

(2) Parity/overflow flag (P/V)

The P/V flag performs the following two kinds of operation associated with execution of an operation instruction.

The status of the P/V flag can be tested with a conditional branch instruction.

Parity flag operation

Set (1) when the number of bits set (1) as the result of execution of a logical operation instruction, shift/rotate

instruction, or a CHKL or CHKLA instruction is even, and reset (0) if odd. When a 16-bit shift instruction is

executed, however, only the low-order 8 bits of the operation result are valid for the parity flag.

Overflow flag operation

Set (1) only when the numeric range expressed as a two's complement is exceeded as the result of execution

of a arithmetic operation instruction, and reset (0) otherwise. More specifically, the value of this flag is the

exclusive OR of the carry into the MSB and the carry out of the MSB. For example, the two's complement range

in an 8-bit arithmetic operation is 80H (128) to 7FH (+127), and the flag is set (1) if the operation result is outside

this range, and reset (0) if within this range.

Example The operation of the overflow flag when an 8-bit addition instruction is executed is shown below.

When the addition of 78H (+120) and 69H (+105) is performed, the operation result is E1H (+225), and the

two's complement limit is exceeded, with the result that the P/V flag is set (1). Expressed as a two's

complement, E1H is -31.

78H (+120)

0111

1000

69H (+105)

= +)

0110

1001

1110

0001

P/V = 1

When the following two negative numbers are added together, the operation result is within the two's

complement range, and therefore the P/V flag is reset (0).

FBH (5)

1111

1011

F0H (16)

= +)

1111

0000

1110

1011

P/V = 0

(3) Interrupt request enable flag (IE)

This flag controls CPU interrupt request acknowledgment operations.

When "0", interrupts are disabled, and only non-maskable interrupts and unmasked macro service can be

acknowledged. All other interrupts are disabled.

When "1", the interrupt enabled state is set, and enabling of interrupt request acknowledgment is controlled by the

interrupt mask flags corresponding to the individual interrupt requests and the priority of the individual interrupts.

The IE flag is set (1) by execution of an EI instruction, and reset (0) by execution of a DI instruction or acknowledgment

of an interrupt.

CHAPTER 3 CPU ARCHITECTURE

(4) Auxiliary carry flag (AC)

The AC flag is set (1) when there is a carry out of bit 3 or a borrow into bit 3 as the result of an operation, and reset

(0) otherwise.

This flag is used when the ADJBA or ADJBS instruction is executed.

(5) Register set selection flag (RSS)

The RSS flag specifies the general-purpose registers that function as X, A, C and B, and the general-purpose register

pairs (16-bit) that function as AX and BC.

This flag is provided to maintain compatibility with the 78K/III series, and must be set to 0 except when using a 78K/

III series program.

(6) Zero flag (Z)

The Z flag records the fact that the result of an operation is "0".

It is set (1) when the result of an operation is "0", and reset (0) otherwise. The status of the Z flag can be tested

with a conditional branch instruction.

(7) Sign flag (S)

The S flag records the fact that the MSB is "1" as the result of an operation.

It is set (1) when the MSB is "1" as the result of an operation, and reset (0) otherwise. The status of the S flag can

be tested with a conditional branch instruction.

(8) Register bank selection flag (RBS0 to RBS2)

This is a 3-bit flag used to select one of the 8 register banks (register bank 0 to register bank 7) (refer to Table

3-4).

It stores 3-bit information which indicates the register bank selected by execution of a SEL RBn instruction, etc.

Table 3-4. Register Bank Selection

RBS2

RBS1

RBS0

Specified Register Bank

(9) User flag (UF)

This flag can be set and reset in the user program, and used for program control.

CHAPTER 3 CPU ARCHITECTURE

3.6.3 Use of RSS bit

Basically, the RSS bit should be fixed at 0 at all times.

The following explanation refers to the case where a 78K/III series program is used, and the program used sets the RSS

bit to 1. This explanation can be skipped if the RSS bit is fixed at 0.

The RSS bit is provided to allow the functions of A (R1), X (R0), B (R3), C (R2), AX (RP0) and BC (RP1) to be used by

registers R4 to R7 (RP2, RP3) as well. Effective use of this bit enables efficient programs to be written in terms of program

size and program execution.

However, careless use can result in unforeseen problems. Therefore, the RSS bit should always be set to 0. The RSS

bit should only be set to 1 when a 78K/III series program is used.

Use of the RSS bit set to 0 in all programs will improve programming and debugging efficiency.

Even when using a program in which the RSS bit set to 1 is used, it is recommended that the program be amended if

possible so that it does not set the RSS bit to 1.

(1) RSS bit recommendations

Registers used by instructions for which the A, X, B, C and AX registers are directly entered in the operand column

of the operation list (refer to 19.2.)

Registers specified as implied by instructions that use the A, AX, B and C registers by means of implied addressing

Registers used in addressing by instructions that use the A, B and C registers in indexed addressing and based

indexed addressing

The registers used in these cases are switched as follows according to the RSS bit.

When RSS = 0

R1, X

R0, B

R3, C

R2, AX

RP0, BC

RP1

When RSS = 1

R5, X

R4, B

R7, C

R6, AX

RP2, BC

RP3

Registers used other than those mentioned above are always the same irrespective of the value of the RSS bit. With

the NEC assembler (RA78K4), the register operation code generated when the A, X, B, C, AX and BC registers are

described by those names is determined by the assembler RSS pseudo-instruction.

When the RSS bit is set or reset, an RSS pseudo-instruction must be written immediately before (or immediately

after) the relevant instruction (refer to example below).

<Program example>

When RSS is set to 0

RSS

; RSS pseudo-instruction

CLR1 PSWL.5

MOV

B, A

; This code is equivalent to "MOV R3, R1".

When RSS is set to 1

RSS

; RSS pseudo-instruction

SET1 PSWL.5

MOV

B, A

; This code is equivalent to "MOV R7, R5".

CHAPTER 3 CPU ARCHITECTURE

(2) Operation code generation method with RA78K4

With RA78K4, if there is an instruction with the same function as an instruction for which A or AX is directly entered

in the operand column of the instruction operation list, the operation code for which A or AX is directly entered

in the operand column is generated first.

Example The function is the same when B is used as r in a MOV A,r instruction, and when A is used as r and

B is used as r' in a MOVr,r' instruction, and the same code (MOV,A,B) is used in the assembler source

program. In this case, RA78K4 generates code equivalent to the MOV A, r instruction.

If A, X, B, C, AX or BC is written in an instruction for which r, r', rp and rp' are specified in the operand column,

the A, X, B, C, AX and BC instructions generate an operation code that specifies the following registers according

to the operand of the RA78K4 RSS pseudo-instruction.

RSS = 0

RSS = 1

RP0

RP2

RP1

RP3

If R0 to R7 or RP0 to RP4 is written as r, r', rp or rp' in the operand column, an operation code in accordance

with that specification is output (an operation code for which A or AX is directly entered in the operand column

is not output.)

R1, R3, R2 or R5, R7, R6 cannot be used for registers A, B and C used in indexed addressing and based indexed

addressing.

(3) Operating precautions

Switching the RSS bit has the same effect as having two register sets. However, when writing a program, care must

be taken to ensure that the static program code and dynamic RSS bit changes at the time of program execution

always coincide.

Also, a program that sets RSS to 1 cannot be used by a program that uses the context switching function, and

therefore program usability is poor. Moreover, since different registers are used with the same name, program

readability is poor and debugging is difficult. Therefore, if it is necessary to set RSS to 1, these disadvantages must

be fully taken into consideration when writing a program.

A register not specified by the RSS bit can be accessed by writing its absolute name.

CHAPTER 3 CPU ARCHITECTURE

3.6.4 Stack pointer (SP)

The stack pointer is a 24-bit register that holds the start address of the stack area (LIFO type: 00000H to FFFFFFH) (refer

to Figure 3-5). It is used to address the stack area when subroutine processing or interrupt processing is performed. Be

sure to write "0" in the high-order 4 bits.

The contents of the SP are decremented before a write to the stack area and incremented after a read from the stack

area (refer to Figures 3-6 and 3-7).

The SP is accessed by dedicated instructions.

The SP contents are undefined after RESET input, and therefore the SP must always be initialized by an initialization

program directly after reset release (before a subroutine call or interrupt acknowledgment).

Example SP initialization

MOVG SP, #0FEE0H;SP

0FEE0H (when used from FEDFH)

Figure 3-5. Format of Stack Pointer (SP)

CHAPTER 3 CPU ARCHITECTURE

Figure 3-6. Data Saved to Stack Area

PUSH sfr Instruction

Stack

PUSH sfrp Instruction

Stack

High-order Byte

Low-order Byte

High-order Byte

Undefined

PC15 to PC8

PC7 to PC0

PC15 to PC8

PC7 to PC0

PC19 to

PC16

PC19 to

PC16

PSWH

PSWL

RP3

RP2

Middle-order Byte

Low-order Byte

PUSH rg Instruction

Stack

PUSH PSW Instruction

Stack

CALL, CALLF, CALLT Instruction

Stack

Vectored Interrupt

Stack

PUSH post, PUSHU post Instruction

(In case of PUSH AX, RP2, RP3)

Stack

SP 1

SP 2

SP 1

SP 2

SP 1

SP 2

SP 3

SP 1

SP 2

SP 3

SP 1

SP 2

SP 3

SP 4

SP 1

SP 2

SP 3

SP 4

SP 5

SP 6

CHAPTER 3 CPU ARCHITECTURE

Figure 3-7. Data Restored from Stack Area

Note

This 4-bit data is ignored.

POP sfr Instruction

Stack

POP sfrp Instruction

Stack

High-order Byte

Low-order Byte

HIgh-order Byte

Note

PC15 to PC8

PC7 to PC0

PC15 to PC8

PC7 to PC0

PC19 to

PC16

PC19 to

PC16

PSWH

PSWL

RP3

RP2

Middle-order Byte

Low-order Byte

POP rg Instruction

Stack

POP PSW Instruction

Stack

RET Instruction

Stack

RETI, RETB Instruction

Stack

POP post, POPU post Instruction

(In case of POP AX, RP2, RP3)

Stack

SP+1

SP+2

SP+1

SP+3

SP+2

SP+1

SP+3

SP+2

SP+1

SP+4

SP+3

SP+2

SP+1

SP+6

SP+5

SP+4

SP+3

SP+2

SP+1

SP+2

SP+1

CHAPTER 3 CPU ARCHITECTURE

Cautions 1. With stack addressing, the entire 1 M-byte space can be accessed but a stack area cannot be

reserved in the SFR area or internal ROM area.

2. The stack pointer (SP) is undefined after RESET input. Moreover, non-maskable interrupts can

still be acknowledged when the SP is in an undefined state. An unanticipated operation may

therefore be performed if a non-maskable interrupt request is generated when the SP is in the

undefined state directly after reset release. To avoid this risk, the program after reset release must

be written as follows.

RSTVCT

CSEG

RSTSTRT

INITSEG

CSEG

BASE

RSTSTRT : LOCATION 0H ; or LOCATION 0FH

MOVG SP, #STKBGN

CHAPTER 3 CPU ARCHITECTURE

3.7 General-Purpose Registers

3.7.1 Configuration

There are sixteen 8-bit general-purpose registers, and two 8-bit general-purpose registers can be used together as a

16-bit general-purpose register. In addition, four of the 16-bit general-purpose registers can be combined with an 8-bit

General-purpose registers other than the V, U, T and W registers for address extension are mapped onto internal RAM.

These register sets are provided in 8 banks, and can be switched by means of software or the context switching function.

Upon RESET input, register bank 0 is selected. The register bank used during program execution can be checked by

reading the register bank selection flag (RBS0, RBS1, RBS2) in the PSW.

Figure 3-8. Format of General-Purpose Register

Remark

Absolute names are shown in parentheses.

0 7

A(R1)

X(R0)

AX(RP0)

B (R3)

C (R2)

BC (RP1)

RP2

RP3

VP (RP4)

VVP (RG4)

R11

R10

UP (RP5)

UUP (RG5)

D (R13)

E (R12)

DE (RP6)

TDE (RG6)

H (R15)

L (R14)

HL (RP7)

WHL (RG7)

8 Banks

CHAPTER 3 CPU ARCHITECTURE

Figure 3-9. General-Purpose Register Addresses

......

Note

When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, 0F0000H

should be added to the address values shown above.

Caution R4, R5, R6, R7, RP2 and RP3 can be used as the X, A, C, B, AX and BC registers respectively by setting

the RSS bit of the PSW to 1, but this function should only be used when using a 78K/III series program.

Remark

When the register bank is changed, and it is necessary to return to the original register bank, an SEL RBn

instruction should be executed after saving the PSW to the stack with a PUSH PSW instruction. When returning

to the original register bank, if the stack location does not change the POP PSW instruction should be used.

When the register bank is changed by a vectored interrupt processing program, etc., the PSW is automatically

saved to the stack when an interrupt is acknowledged and restored by an RETI or RETB instruction, so that,

if only one register bank is used in the interrupt service routine, only an SEL RBn instruction needs be executed,

and execution of a PUSH PSW and POP PSW instruction is not necessary.

Example When register bank 2 is specified

PUSH PSW

SEL RB2

Operations in register bank 2

POP PSW

Operations in original register bank

RBNK0

FEFFH

Note

FE80H

Note

RBNK1

RBNK2

RBNK3

RBNK4

RBNK5

RBNK6

RBNK7

H(R15)

(FH)

8-Bit Processing

16-Bit Processing

D(R13)

(DH)

R11

(BH)

(9H)

(7H)

(5H)

B(R3)

(3H)

A(R1)

(1H)

L(R14)

(EH)

E(R12)

(CH)

R10

(AH)

(8H)

(6H)

(4H)

C(R2)

(2H)

X(R0)

(0H)

HL(RP7)

(EH)

DE(RP6)

(CH)

UP(RP5)

(AH)

VP(RP4)

(8H)

RP3

(6H)

RP2

(4H)

BC(RP1)

(2H)

AX(RP0)

(0 H)

CHAPTER 3 CPU ARCHITECTURE

3.7.2 Functions

In addition to being manipulated in 8-bit units, the general-purpose registers can also be manipulated in 16-bit units by

pairing two 8-bit registers. Also, four of the 16-bit registers can be combined with an 8-bit register for address extension

and manipulated in 24-bit units.

Each register can be used in a general-purpose way for temporary storage of an operation result and as the operand

of an inter-register operation instruction.

The area from 0FE80H to 0FEFFH (when the LOCATION 0 instruction is executed; 0FFE80H to 0FFEFFH when the

LOCATION 0FH instruction is executed) can be given an address specification and accessed as ordinary data memory

irrespective of whether or not it is used as the general-purpose register area.

As 8 register banks are provided in the 78K/IV series, efficient programs can be written by using different register banks

for normal processing and processing in the event of an interrupt.

The registers have the following specific functions.

A (R1):

· Register mainly used for 8-bit data transfers and operation processing. Can be used in combination with all

addressing modes for 8-bit data.

· Can also be used for bit data storage.

· Can be used as the register that stores the offset value in indexed addressing and based indexed addressing.

X (R0):

· Can be used for bit data storage.

AX (RP0):

· Register mainly used for 16-bit data transfers and operation processing. Can be used in combination with all

addressing modes for 16-bit data.

AXDE:

· Used for 32-bit data storage when a DIVUX, MACW or MACSW instruction is executed.

B (R3):

· Has a loop counter function, and can be used by the DBNZ instruction.

· Can be used as the register that stores the offset value in indexed addressing and based indexed addressing.

· Used as the MACW and MACSW instruction data pointer.

C (R2):

· Has a loop counter function, and can be used by the DBNZ instruction.

· Can be used as the register that stores the offset value in based indexed addressing.

· Used as the counter in a string instruction and the SACW instruction.

· Used as the MACW and MACSW instruction data pointer.

RP2:

· Used to save the low-order 16 bits of the program counter (PC) when context switching is used.

RP3:

· Used to save the high-order 4 bits of the program counter (PC) and the program status word (PSW) (excluding

bit 0 to bit 3 of PSWH) when context switching is used.

CHAPTER 3 CPU ARCHITECTURE

VVP (RG4):

· Has a pointer function, and operates as the register that specifies the base address in register indirect addressing,

based addressing and based indexed addressing.

UUP (RG5):

· Has a user stack pointer function, and enables a stack separate from the system stack to be implemented by means

of the PUSHU and POPU instructions.

· Has a pointer function, and operates as the register that specifies the base address in register indirect addressing

and based addressing.

DE (RP6), HL (RP7):

· Operate as the registers that store the offset value in indexed addressing and based indexed addressing.

TDE (RG6):

· Has a pointer function, and operates as the register that specifies the base address in register indirect addressing

and based addressing.

· Used as the pointer in a string instruction and the SACW instruction.

WHL (RG7):

· Register used mainly for 24-bit data transfers and operation processing.

· Has a pointer function, and operates as the register that specifies the base address in register indirect addressing

and based addressing.

· Used as the pointer in a string instruction and the SACW instruction.

CHAPTER 3 CPU ARCHITECTURE

In addition to the function name that emphasizes the specific function of the register (X, A, C, B, E, D, L, H, AX, BC, VP,

UP, DE, HL, VVP, UUP, TDE, WHL), each register can also be written by its absolute name (R0 to R15, RP0 to RP7, RG4

to RG7). The correspondence between these names is shown in Table 3-5.

Table 3-5. Correspondence between Function Names and Absolute Names

(a) 8-bit registers

Absolute Name

Function Name

RSS = 0

RSS = 1

Note

R10

R11

R12

R13

R14

R15

(b) 16-bit registers

Absolute Name

Function Name

RSS = 0

RSS = 1

Note

RP0

RP1

RP2

RP3

RP4

RP5

RP6

RP7

(c) 24-bit registers

Absolute Name

Function Name

RG4

VVP

RG5

UUP

RG6

TDE

RG7

WHL

Note

RSS should only be set to 1 when a 78K/III series program is used.

Remark

R8 to R11 have no function name.

CHAPTER 3 CPU ARCHITECTURE

3.8 Special Function Registers (SFRs)

These are registers to which a special function is assigned, such as on-chip peripheral hardware mode registers, control

registers, etc. They are mapped onto the 256-byte space from 0FF00H to 0FFFFH

Note

When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, the area is

FFF00H to FFFFFH.

Caution Addresses onto which SFRs are not assigned should not be accessed in this area. If such an address

is as accessed by mistake, the

PD784054 may become deadlocked. A deadlock can only be released

by reset input.

A list of special function registers (SFRs) is given in Table 3-6. The meaning of the items in the table is as explained

below.

· Symbol ................................... Symbol that indicates the incorporated SFR. This is a reserved word in the NEC

assembler (RA78K4). With the C compiler (CC78K4), this symbol can be used as a sfr

variable by means of a #pragma sfr command.

· R/W ......................................... Indicates whether the corresponding SFR is read/write enabled.

R/W: Read/write enabled

: Read-only

: Write-only

· Bit Units for Manipulation ...... Indicates the applicable manipulation bit units when the corresponding SFR is manipulated.

A 16-bit-manipulable SFR can be written in the operand "sfrp", and when specified by

an address, an even address is specified.

A bit-manipulable SFR can be written in a bit manipulation instruction.

· On Reset ................................ Indicates the status of the register after RESET input.

CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Registers (SFRs) List (1/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

On Reset

1 bit

8 bits

16 bits

0FF00H

Port 0

R/W

Undefined

0FF01H

Port 1

0FF02H

Port 2

Note 2

0FF03H

Port 3

R/W

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

0FF07H

Port 7

0FF08H

Port 8

0FF09H

Port 9

R/W

0FF10H

Timer register 0

TM0

0000H

0FF11H

0FF12H

Capture/compare register 00

CC00

R/W

Undefined

0FF13H

0FF14H

Capture/compare register 01

CC01

0FF15H

0FF16H

Capture/compare register 02

CC02

0FF17H

0FF18H

Capture/compare register 03

CC03

0FF19H

0FF1AH

Timer register 1

TM1

0000H

0FF1BH

0FF1CH

Compare register 10

CM10

R/W

Undefined

0FF1DH

0FF1EH

Compare register 11

CM11

0FF1FH

0FF20H

Port 0 mode register

PM0

FFH

0FF21H

Port 1 mode register

PM1

0FF22H

Port 2 mode register

PM2

Note 3

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF29H

Port 9 mode register

PM9

0FF2FH

Port read control register

PRDC

00H

0FF30H

Timer unit mode register 0

TUM0

0FF31H

Timer mode control register

TMC

Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. Bit 0 of P2 can only be read. Bits 1 through 7 can be read/written.

3. Bit 0 of PM2 is fixed to "1" by hardware.

CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Registers (SFRs) List (2/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

On Reset

1 bit

8 bits

16 bits

0FF32H

Timer output control register 0

TOC0

R/W

00H

0FF33H

Timer output control register 1

TOC1

0FF37H

Timer mode control register 4

TMC4

0FF38H

Prescaler mode register

PRM

0FF3AH

Prescaler mode register 4

PRM4

0FF3BH

Noise protection control register

NPC

0FF3CH

External interrupt mode register 0

INTM0

0FF3DH

External interrupt mode register 1

INTM1

0FF3EH

Interrupt valid edge flag register 1

IEF1

Undefined

0FF3FH

Interrupt valid edge flag register 2

IEF2

0FF42H

Port 2 mode control register

PMC2

Note 2

00H

0FF43H

Port 3 mode control register

PMC3

0FF49H

Port 9 mode control register

PMC9

0FF4EH

Pull-up resistor option register L

PUOL

0FF4FH

Pull-up resistor option register H

PUOH

0FF60H

Timer register 4

TM4

0000H

0FF61H

0FF62H

Compare register 40

CM40

R/W

Undefined

0FF63H

0FF64H

Compare register 41

CM41

0FF65H

0FF6EH

A/D converter mode register

ADM

00H

0FF70H

A/D conversion result register 0

ADCR0

Undefined

0FF71H

A/D conversion result register 0H

ADCR0H

0FF72H

A/D conversion result register 1

ADCR1

0FF73H

A/D conversion result register 1H

ADCR1H

0FF74H

A/D conversion result register 2

ADCR2

0FF75H

A/D conversion result register 2H

ADCR2H

0FF76H

A/D conversion result register 3

ADCR3

0FF77H

A/D conversion result register 3H

ADCR3H

0FF78H

A/D conversion result register 4

ADCR4

0FF79H

A/D conversion result register 4H

ADCR4H

Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. Bits 0, and 5 through 7 of PMC2 are fixed to "0" by hardware.

CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Registers (SFRs) List (3/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

On Reset

1 bit

8 bits

16 bits

0FF7AH

A/D conversion result register 5

ADCR5

Undefined

0FF7BH

A/D conversion result register 5H

ADCR5H

0FF7CH

A/D conversion result register 6

ADCR6

0FF7DH

A/D conversion result register 6H

ADCR6H

0FF7EH

A/D conversion result register 7

ADCR7

0FF7FH

A/D conversion result register 7H

ADCR7H

0FF84H

Clocked serial interface mode register 1

CSIM1

R/W

00H

0FF85H

Clocked serial interface mode register 2

CSIM2

0FF88H

Asynchronous serial interface mode register

ASIM

0FF89H

Asynchronous serial interface mode register 2

ASIM2

0FF8AH

Asynchronous serial interface status register

ASIS

0FF8BH

Asynchronous serial interface status register 2

ASIS2

0FF8CH

Serial receive buffer: UART0

RXB

Undefined

Serial transmit shift register: UART0

TXS

Serial shift register: IOE1

SIO1

R/W

0FF8DH

Serial receive buffer: UART2

RXB2

Serial transmit shift register: UART2

TXS2

Serial shift register: IOE2

SIO2

R/W

0FF90H

Baud rate generator control register

BRGC

00H

0FF91H

Baud rate generator control register 2

BRGC2

0FFA8H

In-service priority register

ISPR

0FFAAH

Interrupt mode control register

IMC

R/W

80H

0FFACH

Interrupt mask register 0L

MK0L

FFH

0FFACH

Interrupt mask register 0

MK0

FFFFH

0FFADH

Interrupt mask register 0H

MK0H

FFH

0FFAEH

Interrupt mask register 1L

MK1L

0FFAEH

Interrupt mask register 1

MK1

FFFFH

0FFAFH

Interrupt mask register 1H

MK1H

FFH

0FFC0H

Standby control register

Note 2

STBC

30H

0FFC2H

Watchdog timer mode register

Note 2

WDM

00H

0FFC4H

Memory expansion mode register

20H

0FFC7H

Programmable wait control register 1

PWC1

AAH

Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. These registers can be written only by using dedicated instructions MOV STBC, #byte and MOV WDM,

#byte, and cannot be written by any other instructions.

CHAPTER 3 CPU ARCHITECTURE

Table 3-6. Special Function Registers (SFRs) List (4/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

On Reset

1 bit

8 bits

16 bits

0FFC8H

Programmable wait control register 2

PWC2

R/W

AAAAH

0FFC9H

0FFCAH

Bus width specification register

Note 3

0FFCBH

0FFCFH

Oscillation stabilization time specification register

OSTS

00H

0FFD0H-

External SFR area

Undefined

0FFDFH

0FFE0H

Interrupt control register (INTOV0)

OVIC0

43H

0FFE1H

Interrupt control register (INTOV1)

OVIC1

0FFE2H

Interrupt control register (INTOV4)

OVIC4

0FFE3H

Interrupt control register (INTP0)

PIC0

0FFE4H

Interrupt control register (INTP1)

PIC1

0FFE5H

Interrupt control register (INTP2)

PIC2

0FFE6H

Interrupt control register (INTP3)

PIC3

0FFE7H

Interrupt control register (INTP4)

PIC4

0FFE8H

Interrupt control register (INTP5)

PIC5

0FFE9H

Interrupt control register (INTP6)

PIC6

0FFEAH

Interrupt control register (INTCM10)

CMIC10

0FFEBH

Interrupt control register (INTCM11)

CMIC11

0FFF0H

Interrupt control register (INTCM40)

CMIC40

0FFF1H

Interrupt control register (INTCM41)

CMIC41

0FFF2H

Interrupt control register (INTSER)

SERIC

0FFF3H

Interrupt control register (INTSR)

SRIC

Interrupt control register (INTCSI1)

CSIIC1

0FFF4H

Interrupt control register (INTST)

STIC

0FFF5H

Interrupt control register (INTSER2)

SERIC2

0FFF6H

Interrupt control register (INTSR2)

SRIC2

Interrupt control register (INTCSI2)

CSIIC2

0FFF7H

Interrupt control register (INTST2)

STIC2

0FFF8H

Interrupt control register (INTAD)

ADIC

0FFFCH

Internal memory size select register

Note 2

IMS

CDH

Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. Writing to IMS is valid only with the flash memory model (

PD78F4046). When writing to IMS with mask

ROM models (

PD784054), the value is not changed and remains the same as the value on reset.

3. The value of this register on reset differs depending on the setting of the BWD pin.

BWD = 0: 0000H

BWD = 1: 00FFH

CHAPTER 3 CPU ARCHITECTURE

3.9 Cautions

(1) Program fetches cannot be performed from the internal high-speed RAM area (0FD00H to 0FEFFH when the

LOCATION 0 instruction is executed; FFD00H to FFEFFH when the LOCATION 0FH instruction is executed).

(2) Special function registers (SFRs)

Addresses onto which SFRs are not assigned should not be accessed in the area 0FF00H to 0FFFFH

Note

If such an address is accessed by mistake, the

PD784054 may become deadlocked. A deadlock can only

be released by reset input.

Note

When the LOCATION 0 instruction is executed; FFF00H to FFFFFH when the LOCATION 0FH

instruction is executed.

(3) Stack pointer (SP) operation

With stack addressing, the entire 1 M-byte space can be accessed, but a stack area cannot be reserved in

the SFR area or internal ROM area.

(4) Stack pointer (SP) initialization

The SP is undefined after RESET input, while non-maskable interrupts can be acknowledged directly after

reset release. Therefore, an unforeseen operation may be performed if a non-maskable interrupt request is

generated while the SP is in the undefined state directly after reset release. To minimize this risk, the following

program should be coded without fail after reset release.

RSTVCT

CSEG

RSTSTRT

INITSEG

CSEG

BASE

RSTSTRT :

LOCATION 0H ; or LOCATION 0FH

MOVG SP, #STKBGN

[MEMO]

CHAPTER 4 CLOCK GENERATOR

4.1 Configuration and Function

The clock generator generates and controls the internal system clock (CLK) supplied to the CPU and on-chip hardware. The

clock generator block diagram is shown in Figure 4-1.

Figure 4-1. Block Diagram of Clock Generator

Remark

: crystal/ceramic oscillation frequency

: external clock frequency

CLK

: internal system clock frequency

The clock oscillator oscillates by means of a crystal resonator/ceramic resonator connected to the X1 and X2 pins. When

standby mode (STOP) is set, oscillation stops (refer to CHAPTER 16 STANDBY FUNCTION).

An external clock can also be input. In this case, input the clock signal to the X1 pin.

The processing of the X2 pin differs depending on the setting of the EXTC bit of the oscillation stabilization time specification

EXTC bit = 1: Input a clock in reverse phase to the clock input to X1 pin to the X2 pin.

EXTC bit = 0: Leave the X2 pin unconnected.

The frequency divider circuit divides the output (f

or f

) of the clock oscillator by two, to generate an internal system clock

CLK

Internal Bus

EXTC

OSTS2 OSTS1 OSTS0

RESET

OSTS

STP

HLT

RESET

STBC

Clock

Oscillator

or f

1/2

CLK

Internal System Clock (CLK)

Frequency Divider

CHAPTER 4 CLOCK GENERATOR

Figure 4-2. Clock Oscillator External Circuitry

(a) Crystal/ceramic oscillation

(b) External clock

· EXTC bit of OSTS = 1 · EXTC bit of OSTS = 0

Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.

2. No other signal lines should pass through the area enclosed by the dotted line.

Remark

Use of crystal resonator and ceramic resonator

Generally speaking, the oscillation frequency of a crystal resonator is extremely stable. It is therefore ideal for

performing high-precision time management (in clocks, frequency meters, etc.).

A ceramic resonator is inferior to a crystal resonator in terms of oscillation frequency stability, but it has three

advantages: a fast oscillation start-up time, small size, and low price. It is therefore suitable for general use (when

high-precision time management is not required). In addition, there are products with a built-in capacitor, etc.,

which enable the number of parts and mounting area to be reduced.

PD784054

Open

PD74HC04, etc.

PD784054

CHAPTER 4 CLOCK GENERATOR

4.2 Control Registers

4.2.1 Standby control register (STBC)

STBC is a register used to set the standby mode. Refer to CHAPTER 16 STANDBY FUNCTION for details of the standby

modes.

To prevent erroneous entry into standby mode due to an inadvertent program loop, the STBC register can only be written

to by a dedicated instruction. This instruction is the MOV STBC, #byte instruction, and has a special code configuration (4 bytes).

A write is only performed if the 3rd and 4th bytes of the op code are mutual complements. If the 3rd and 4th bytes of the op code

are not mutual complements, a write is not performed, and an op error interrupt is generated. In this case, the return address

saved in the stack area is the address of the instruction which is the source of the error. The error source address can thus be

found from the return address saved on the stack area.

An endless loop will result if restore from an operand error is simply performed with an RETB instruction.

Since an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler

RA78K4, only the correct dedicated instruction is generated when the MOV STBC, #byte instruction is written), system

initialization should be performed by the program.

Other write instructions ("MOV STBC, A", "AND STBC, # byte", "SET1 STBC.7", etc.) are ignored, and no operation is

performed. That is, a write is not performed on the STBC, and an interrupt such as an operand error interrupt is not generated.

The STBC can be read at any time with a data transfer instruction.

RESET input sets the STBC register contents to 30H.

The format of the STBC is shown in Figure 4-3.

Figure 4-3. Standby Control Register (STBC) Format

Caution

If the STOP mode is used when external clock input is used, the EXTC bit of the oscillation stabilization

time specification register (OSTS) must be set (1) before setting the STOP mode. If the STOP mode is used

when the EXTC bit of the OSTS is in the cleared (0) state when external clock input is used, the

PD784054

may be damaged or suffer reduced reliability.

When setting the EXTC bit to 1, be sure to input a clock in phase reverse to that of the clock input to the

X1 pin, to the X2 pin.

STP

HLT

STP

CPU Operating Mode Control

Normal mode

HALT mode

STOP mode

IDLE mode

HLT

STBC

Address : 0FFC0H On reset : 30H R/W

CHAPTER 4 CLOCK GENERATOR

4.2.2 Oscillation stabilization time specification register (OSTS)

OSTS is a register used to specify the operation of the oscillator. The EXTC bit of the OSTS specifies whether a crystal/

ceramic resonator or an external clock is used. The STOP mode can be set during use of external clock input, only when the

EXTC bit is set (1).

The OSTS can be read/written to by an 8-bit manipulation instruction.

RESET input clears the OSTS register contents to 00H.

The format of the OSTS is shown in Figure 4-4.

Figure 4-4. Format of Oscillation Stabilization Time Specification Register (OSTS)

Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit must be cleared (0). If the EXTC bit is set (1),

oscillation will stop.

2. If the STOP mode is used with external clock input, the EXTC bit must be set (1) before setting the STOP

mode. If the STOP mode is used when the EXTC bit is in the cleared (0) state, the

PD784054 may be

damaged or suffer reduced reliability.

3. When setting the EXTC bit to 1 during external clock input, be sure to input a clock in phase reverse

to that of the clock input to the X1 pin, to the X2 pin. When the EXTC bit is set to 1, the

PD784054

operates on only the clock input to the X2 pin.

EXTC

OSTS2 OSTS1 OSTS0

EXTC

Selects External Clock

Inputs clock in reverse phase to clock input

X1 pin to X2 pin.

OSTS2

Selects oscillation stabilization time

(for details, refer to Figure 16-4).

OSTS1 OSTS0

OSTS

Address : 0FFCFH On reset : 00H R/W

Opens X2 pin when crystal/ceramic oscillation

is used or when external clock is used.

CHAPTER 4 CLOCK GENERATOR

4.3 Clock Generator Operation

4.3.1 Clock oscillator

(1) When using crystal/ceramic oscillation

The clock oscillator starts oscillating when the RESET signal is input, and stops oscillation when the STOP mode is set

by the standby control register (STBC). Oscillation is resumed when the STOP mode is released.

(2) When using external clock

The clock oscillator supplies the clock input from the X1 pin to the internal circuitry when the RESET signal is input.

The oscillator operates as follows when the EXTC bit of the oscillation stabilization time specification register (OSTS)

is set to 1.

The clock oscillator supplies the clock input to the X2 pin to the internal circuitry.

The necessary circuit stops operating during the crystal/ceramic oscillation of the clock oscillator, to reduce the power

dissipation.

The STOP mode can be used even when the external clock is input.

Cautions 1. When using a crystal/ceramic oscillation, the EXTC bit of the Oscillation stabilization time specifica-

tion register (OSTS) must be cleared (0). If the EXTC bit is set (1), oscillation will stop.

2. If the STOP mode is used with external clock input, the EXTC bit of the OSTS must be set (1) before

setting the STOP mode. If the STOP mode is used when the EXTC bit is in the cleared (0) state, not

only will the clock generator consumption current not be reduced, but the

PD784054 may also be

damaged or suffer reduced reliability.

3. When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock

input to the X1 pin, to the X2 pin.

4.3.2 Frequency divider

The frequency divider divides the output from the clock oscillator by two, and supplies the result to the CPU and peripheral

hardware.

CHAPTER 4 CLOCK GENERATOR

4.4 Cautions

The following cautions apply to the clock generator.

4.4.1 When an external clock is input

(1) If the STOP mode is used with external clock input, the EXTC bit of the oscillation stabilization time specification register

(OSTS) must be set (1). If the STOP mode is used when the EXTC bit is in the cleared (0) state, the

PD784054 may

be damaged or suffer reduced reliability.

(2) When setting the EXTC bit of the OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the

X1 pin, to the X2 pin.

(3) When an external clock is input, this should be performed with a HCMOS device, or a device with the equivalent drive

capability.

(4) A signal should not be extracted from the X1 and X2 pins. If a signal is extracted, it should be extracted from point a in

Figure 4-5.

Figure 4-5. Signal Extraction with External Clock Input

(5) The wiring connecting the X1 pin to the X2 pin via an inverter, in particular, should be made as short as possible.

PD74HC04, etc.

PD784054

CHAPTER 4 CLOCK GENERATOR

4.4.2 When crystal/ceramic oscillation is used

(1) As the oscillator is a high-frequency analog circuit, considerable care is required.

The following points, in particular, require attention.

The wiring should be kept as short as possible.

No other signal lines should be crossed.

Avoid lines carrying a high fluctuating current.

The oscillator capacitor grounding point should always be at the same potential as the V

pin. Do not ground to a

ground pattern carrying a high current.

A signal should not be taken from the oscillator.

If oscillation is not performed normally and stably, the microcontroller will not be able to operate normally and stably,

either. Also, if a high-precision oscillation frequency is required, consultation with the oscillator manufacturer is

recommended.

Figure 4-6. Cautions on Resonator Connection

Cautions 1. The oscillator should be as close as possible to the X1 and X2 pins.

2. No other signal lines should pass through the area enclosed by the dotted line.

PD784054

CHAPTER 4 CLOCK GENERATOR

Figure 4-7. Incorrect Example of Resonator Connection

(a) Wiring of conneted circuits is too long

(b) Crossed signal lines

(e) Signal extracted

(c) Wiring near high alternating current

(d) Current flowing through ground line of

oscillator

(Potentials at points A, B, and C fluctuate)

PD784054

Pnm

PD784054

High
Alternating
Current

PD784054

Pnm

High
Alternating
Current

PD784054

CHAPTER 4 CLOCK GENERATOR

(2) When the device is powered on, and when restoring from the STOP mode, sufficient time must be allowed for the

oscillation to stabilize. Generally speaking, the time required for oscillation stabilization is several milliseconds when a

crystal resonator is used, and several hundred microseconds when a ceramic resonator is used.

An adequate oscillation stabilization period should be secured by the following means:

<1>

When powering-on

: RESET input (reset period)

<2>

When returning from STOP mode :

(i) RESET input (reset period)

(ii) Time of the oscillation stabilization timer that automatically starts at the valid edge of NMI signal (set by the

oscillation stabilization time specification register (OSTS))

(3) The EXTC bit of the oscillation stabilization time specification register (OSTS) must be cleared (0). If the EXTC bit is

set (1), oscillation will stop.

[MEMO]

CHAPTER 5 PORT FUNCTIONS

5.1 Digital Input/Output Port

The

PD784054 is provided with the ports shown in Figure 5-1, enabling various kinds of control to be performed. The

function of each port is shown in Table 5-1. For port 0, ports 4 to 6, and port 9, connection of an internal pull-up resistor

can be specified by software when used as input ports.

Figure 5-1. Port Configuration

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

P00

P03

P10

P12

P20

P27

P30

P37

P40

P47

P50

P57

P60

P63

P70-P77

Port 7

Port 9

P80-P87

Port 8

P90

P94

CHAPTER 5 PORT FUNCTIONS

Table 5-1. Port Function

Port Name

Pin Name

Function

Specification of Pull-Up Resistor by Software

Port 0

P00-P03

Can be set in input or output mode bit-wise.

All pins can be set in input mode

Port 1

P10-P12

Port 2

P20-P27

Can be set in input or output mode bit-wise

(however, P20 is input-only).

Port 3

P30-P37

Can be set in input or output mode bit-wise.

Port 4

P40-P47

All pins can be set in input mode

Port 5

P50-P57

Port 6

P60-P63

Port 7

P70-P77

Input port

Port 8

P80-P87

Port 9

P90-P94

Can be set in input or output mode bit-wise.

All pins can be set in input mode

CHAPTER 5 PORT FUNCTIONS

5.2 Port 0

Port 0 is a 4-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 0 mode

When RESET is input, port 0 is set as an input port (output high-impedance state), and the output latch contents are

undefined.

5.2.1 Hardware configuration

The port 0 hardware configuration is shown in Figure 5-2.

Figure 5-2. Block Diagram of Port 0

PUO

PM0

OUT

Internal Bus

Pull-Up Resistor Option Register L

Port 0 Mode Register

PUO0

PM0n

P0n

P0n
n = 0-3

Output Latch

CHAPTER 5 PORT FUNCTIONS

5.2.2 Input/output mode/control mode setting

The port 0 input/output mode is set by means of the port 0 mode register (PM0) as shown in Figure 5-3.

Figure 5-3. Format of Port 0 Mode Register (PM0)

5.2.3 Operating status

Port 0 is an input/output port

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-4. Port Specified as Output Port

P0n
n = 0-3

OUT

PORT

Internal

Bus

Output

Latch

PM03

PM02

PM01

PM00

PM0n

Specifies I/O Mode of P0n Pin (n = 0 to 3)

Output mode (output buffer on)

Input mode (output buffer off)

PM0

Address : 0FF20H On reset : FFH R/W

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes

can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is

stored in all output latches irrespective of the port input/output specification. However, since the output buffer of

a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input

is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output

latch of a bit specified as an input port cannot be loaded into an accumulator.

Figure 5-5. Port Specified as Input Port

Output

Latch

P0n
n = 0-3

PORT

Internal

Bus

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,

the contents of the output latch of pins specified as inputs will be undefined (excluding bits

manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits

which are switched between input and output.

Caution is also required when manipulating the port with other 8-bit manipulation instructions.

CHAPTER 5 PORT FUNCTIONS

5.2.4 Internal pull-up resistors

Port 0 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of

parts and the mounting area to be reduced.

Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO0 bit of the

pull-up resistor option register L (PUOL) and the port 0 mode register (PM0).

When PUO0 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the PM0 is valid when the PUO

bit is 1.

Figure 5-6. Pull-Up Resistor Option Register L (PUOL) Format

PUO6 PUO5 PUO4

PUO0

PUO6 Specifies Pull-up Resistor of Port 6

(refer to Figure 5-44).

PUO0

Specifies Pull-up Resistor of Port 0

Not used with port 0

Used with port 0

PUOL

Address : 0FF4EH On reset : 00H R/W

PUO5 Specifies Pull-up Resistor of Port 5

(refer to Figure 5-38).

PUO4 Specifies Pull-up Resistor of Port 4

(refer to Figure 5-32).

Remark

When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.

CHAPTER 5 PORT FUNCTIONS

Figure 5-7. Pull-Up Resistor Specification (Port 0)

P01

Input

Buffer

P00

P02

P03

Port 0 Mode Register

(PM0)

PUO0

(PUOL)

Internal

Bus

100

CHAPTER 5 PORT FUNCTIONS

5.3 Port 1

Port 1 is a 3-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 1 mode

When RESET is input, port 1 is set as an input port (output high-impedance state), and the output latch contents are

undefined.

5.3.1 Hardware configuration

The port 1 hardware configuration is shown in Figure 5-8.

Figure 5-8. Block Diagram of Port 1

Internal Bus

PM1

OUT

Port 1 Mode Register

Output Latch

PM1n

P1n

P1n
n = 0-2

101

CHAPTER 5 PORT FUNCTIONS

5.3.2 Setting I/O mode/control mode

The input/output mode of port 1 is set by using the port 1 mode register (PM1) per pin, as shown in Figure 5-9.

Figure 5-9. Format of Port 1 Mode Register (PM1)

5.3.3 Operating status

Port 1 is an input/output port.

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-10. Port Specified as Output Port

PM12

PM11

PM10

PM1n

Specifies I/O mode of P1n pin (n = 0 to 2)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM1

Address : 0FF21H On reset : FFH R/W

Internal

Bus

Output

Latch

P1n
n = 0-2

OUT

PORT

102

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction, etc. In this case, too, writes

can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is

stored in all output latches irrespective of the port input/output specification. However, since the output buffer of

a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input

is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output

latch of a bit specified as an input port cannot be loaded into an accumulator.

Figure 5-11. Port Specified as Input Port

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port that has the I/O mode or port mode and

control mode, the contents of the output latch of the pin set in the input mode or control mode become

undefined (excluding bits manipulated with a SET1 or CLR1 instruction, etc.). Particular care is

required when there are bits which are switched between input and output.

Caution is also required when manipulating the port with other 8-bit manipulation instructions.

Output

Latch

P1n
n = 0-2

PORT

Internal

Bus

103

CHAPTER 5 PORT FUNCTIONS

5.4 Port 2

Port 2 is an 8-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using

port 2 mode register (PM2) (however, P20 is input-only).

In addition to the input/output port function, port 2 also has a function to input control signals such as external interrupt

signals, and output the timer signal of timer 0 (refer to Table 5-2). P21 through P24 serve as the timer output pins of timer

0 if so specified by port 2 mode control register (PMC2). The level of each pin of this port can always be read or tested

regardless of the multiplexed function.

All the eight pins are Schmitt trigger input pins to prevent malfunctioning due to noise.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output

latch are undefined.

Table 5-2. Operation Mode of Port 2

(n = 0 to 7)

Mode

Port Mode

Control Signal Output Mode

Set condition

PMC2n = 0

PMC2n = 1

PM2n = 0

PM2n = 1

PM2n =

P20

Input port/NMI input

Note

P21

Output port

Input port/INTP0 input

TO00 output

P22

Input port/INTP1 input

TO01 output

P23

Input port/INTP2 input

TO02 output

P24

Input port/INTP3 input

TO03 output

P25

Input port/INTP4 input

P26

Input port/INTP5 input

P27

Input port/INTP6 input

Note

The NMI input pin accepts an interrupt request regardless of whether interrupts are enabled or disabled.

Remark

: don't care

(1) Port mode

(a) Function as port pin

Each port pin set in the port mode by the port 2 mode control register (PMC2) can be set in the input or output

mode in 1-bit units by the port 2 mode register (PM2) (however, P20 is fixed in the input mode).

(b) Function as control signal input pins

If PMC2n (n = 0 to 7) bit of PMC2 is "0" and if PM2n (n = 0-7) bit of PM2 is "1", the pins of port 2 can be used

as the following control signal input pins.

(i) NMI (Non-maskable Interrupt)

This pin inputs an external non-maskable interrupt request. Whether the interrupt request is detected at

the rising or falling edge can be specified by using external interrupt mode register 0 (INTM0).

104

CHAPTER 5 PORT FUNCTIONS

(ii) INTP0 through INTP6 (Interrupt from Peripherals)

These pins input external interrupt requests. When the valid edge specified by external interrupt mode

registers (INTM0 and INTM1) is detected on the INTP0 to INTP6 pins, an interrupt occurs (refer to CHAPTER

13 EDGE DETECTION FUNCTION).

The INTP0 through INTP4 pins can also be used as external trigger input pins of each function, as follows:

INTP0 ... Capture trigger input pin of capture/compare register 00 (CC00) of timer 0

INTP1 ... Capture trigger input pin of capture/compare register 01 (CC01) of timer 0

INTP2 ... Capture trigger input pin of capture/compare register 02 (CC02) of timer 0

INTP3 ... Capture trigger input pin of capture/compare register 03 (CC03) of timer 0

INTP4 ... External trigger input pin of A/D converter

(2) Control signal output mode

The P21 through P24 pins can be used as the timer output pins (TO00 through TO03) of timer 0 in 1-bit units if so

specified by the port 2 mode control register (PMC2).

5.4.1 Hardware configuration

The port 2 hardware configuration is shown Figure 5-12 through 5-14.

Figure 5-12. Block Diagram of P20 (Port 2)

Internal

Bus

P20

NMI

Edge

Detection

Circuit

105

CHAPTER 5 PORT FUNCTIONS

Figure 5-13. Block Diagram of P21 to P24 (Port 2)

P2n

Output Latch

PMC2n

P2n

Internal Bus

PMC2n

Port 2 Mode Register

TO Output

PMC2n

P2n

PM2n

Selector

P2n
n = 1-4

INTP

n-1

Edge

Detection

Circuit

Figure 5-14. Block Diagram of P25 to P27 (Port 2)

Internal Bus

P2n
(n = 5-7)

P2n

PM2n

Port 2 Mode Register

Output Latch

Edge

Detection

Circuit

INTP

n-1

106

CHAPTER 5 PORT FUNCTIONS

5.4.2 Setting I/O mode/control mode

The input/output mode of P21 through P27 is set per pin by using the port 2 mode register (PM2), as shown in Figure

5-15. P20 is input-only.

P21 through P24 also functions as timer output pins of timer 0, in addition to as input/output port pins. To use these

pins as timer output pins, set them in the control mode by using the port 2 mode control register (PMC2) as shown in Figure

5-16.

Figure 5-15. Format of Port 2 Mode Register (PM2)

PM27

PM26

PM25

PM24

PM23

PM22

PM21

PM2n

Specifies input/output mode of P2n pin (n = 1 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM2

Address : 0FF22H On reset : FFH R/W

PMC24 PMC23 PMC22 PMC21

PMC24

Specifies Control Mode of P24 Pin

I/O port mode/INTP3 input mode

TO03 output mode

PMC2

Address : 0FF42H On reset : 00H R/W

PMC23

Specifies Control Mode of P23 Pin

I/O port mode/INTP2 input mode

TO02 output mode

PMC22

Specifies Control Mode of P22 Pin

I/O port mode/INTP1 input mode

TO01 output mode

PMC21

Specifies Control Mode of P21 Pin

I/O port mode/INTP0 input mode

TO00 output mode

Figure 5-16. Format of Port 2 Mode Control Register (PMC2)

Caution Even when using the P21 through P27 pins in the output port mode or timer output mode, INTPn (n

= 0 to 6) interrupt occurs depending on edge detection of the pin level. Therefore, mask the interrupt

before using the pins.

107

CHAPTER 5 PORT FUNCTIONS

5.4.3 Operating status

Port 2 is an I/O port (however, the P20 pin is input-only). The P21 through P24 pins can also be used as timer output

pins of timer 0.

(1) In output port mode

The output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction.

The contents of the output latch can be freely set by a logical operation instruction. Data that has been written to

the output latch is retained until new data is written to the output latch

Note

Including when the other bits of the same port are manipulated by a bit manipulation instruction.

Figure 5-17. Port in Output Port Mode

Internal Bus

Output

Latch

P2n
n = 1-7

OUT

PORT

108

CHAPTER 5 PORT FUNCTIONS

(2) In input port mode

The level of a port pin can be loaded to the accumulator by using a transfer instruction. Even in this case, data can

be written to the output latch. Data transferred from the accumulator by a transfer instruction is stored to all the output

latches regardless of whether the input or output mode is specified. However, because the output buffer of a bit

(pin) set in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents

of the output latch are output to the port pin when the mode of the pin is changed from input to output). The contents

of the output latch of the pin set in the input port cannot be loaded to the accumulator.

Figure 5-18. Port in Input Port Mode

Output

Latch

P2n
n = 0-7

PORT

Internal Bus

Note

P20 does not have the circuit enclosed by the dotted line in the above figure.

Caution Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses

a port in 8-bit units. If such an instruction is executed to manipulate a port with some pins set in

the input mode and the others in the control mode, the contents of the output latch are undefined

(except when a pin is manipulated by the SET1 or CLR1 instruction). Especially, care must be

exercised if the mode of some pins must be changed between input and output.

The same applies when manipulating the port by using the other 8-bit operation instructions.

109

CHAPTER 5 PORT FUNCTIONS

(3) Pin in control mode

P21 to P24 can be used to output control signals in 1-bit units regardless of the setting of the port 2 mode register

(PM2), if the corresponding bit of the port 2 mode control register (PMC2) is set (1). When using each pin as a control

signal pin, the status of the control signal can be checked by executing an instruction that reads the port.

Figure 5-19. Port in Control Mode

P2n
n = 1-4

PM2n = 0

PM2n = 1

Control
(Output)

Internal Bus

If the PM2n (n = 1 to 4) bit of PM2 is set (1), and if an instruction that reads the port is executed, the level of the

corresponding control signal pin can be read.

If the port read instruction is executed when the PM2n bit is reset (0), the status of the control signal in the

PD784054

can be read.

110

CHAPTER 5 PORT FUNCTIONS

5.5 Port 3

Port 3 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 3 mode

In addition to its function as an input/output port, port 3 also has various dual-function control signal pin functions.

The operating mode can be specified bit-wise by means of the port 3 mode control register (PMC3), as shown in

Table 5-3. The pin level of all pins can always be read or tested regardless of the dual-function pin operation.

When RESET is input, port 3 is set as an input port (output high impedance state), and the output latch contents are

undefined.

Table 5-3. Port 3 Operating Modes

(n = 0 to 7)

Mode

Port Mode

Control Signal Input/Output Mode

Setting Condition

PMC3n = 0

PMC3n = 1

P30

Input/output port

TO10 output

P31

TO11 output

P32

RxD/SI1 input

P33

TxD/SO1 output

P34

ASCK input/SCK1 input/output

P35

RxD2/SI2 input

P36

TxD2/SO2 output

P37

ASCK2 input/SCK2 input/output

(a) Port mode

Each port specified as port mode by the port 3 mode control register (PMC3) can be specified as input/output bit-

wise by means of the port 3 mode register (PM3).

(b) Control signal input/output mode

Pins can be set as control pins bit-wise by setting the port 3 mode control register (PMC3).

(i) TO10, TO11 (Timer Output)

These are timer output pins of timer 1.

(ii) RxD, RxD2 (Receive Data)

These are serial data input pins of the asynchronous serial interface.

(iii) TxD, TxD2 (Transmit Data)

These are serial data output pins of the asynchronous serial interface.

(iv) SI1, SI2 (Serial Input)

These are serial data input pins of the 3-wire serial I/O.

(v) SO1, SO2 (Serial Output)

These are serial data output pins of the 3-wire serial I/O.

(vi) ASCK, ASCK2 (Asynchronous Serial Clock)

These are external baud rate clock input pins.

(vii) SCK1, SCK2 (Serial Clock)

These are serial clock I/O pins of the 3-wire serial I/O.

111

CHAPTER 5 PORT FUNCTIONS

5.5.1 Hardware configuration

The port 3 hardware configuration is shown in Figures 5-20 to 5-22.

Figure 5-20. Block Diagram of P30, P31, P33 and P36 (Port 3)

P3n

Output Latch

PMC3n

P3n

Internal

Bus

PMC3n

Port 3 Mode Register

TO, SO, TxD
Output

PMC3n

P3n

PM3n

Selector

P3n
n = 0, 1, 3 and 6

P3n

P3n
n = 2, 5

P3n

Internal

Bus

SI, RxD Input

PM3n

Port 3 Mode Register

Output Latch

PMC3n

PM3n

P3n

PMC3n

Figure 5-21. Block Diagram of P32 and P35 (Port 3)

112

CHAPTER 5 PORT FUNCTIONS

Figure 5-22. Block Diagram of P34 and P37 (Port 3)

P3n

P3n
n = 4 and 7

P3n

Output Latch

PMC3n

P3n

Internal

Bus

ASCK, SCK Input

PMC3n

External
SCK

PM3n

Port 3 Mode Register

SCK
Output

PMC32

P32

PM32

Selector

113

CHAPTER 5 PORT FUNCTIONS

5.5.2 Input/output mode/control mode setting

The port 3 input/output mode is set for each pin by means of the port 3 mode register (PM3) as shown in Figure 5-23.

In addition to their input/output port function, port 3 pins also have a dual function as various control signal pins, and

the control mode is specified by means of the port 3 mode control register (PMC3) as shown in Figure 5-24.

Figure 5-23. Format of Port 3 Mode Register (PM3)

PM37

PM36

PM35

PM34

PM33

PM32

PM31

PM30

PM3n

Specifies I/O Mode of P3n Pin (n = 0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM3

Address : 0FF23H On reset : FFH R/W

114

CHAPTER 5 PORT FUNCTIONS

Figure 5-24. Format of Port 3 Mode Control Register (PMC3)

PMC37 PMC36 PMC35 PMC34 PMC33 PMC32 PMC31 PMC30

PMC37

Specifies Control Mode of P37 Pin

I/O port mode

ASCK2/SCK2 I/O mode

PMC3

Address : 0FF43H On reset : 00H R/W

PMC36

Specifies Control Mode of P36 Pin

I/O port mode

TxD2/SO2 output mode

PMC35

Specifies Control Mode of P35 Pin

I/O port mode

RxD2/SI2 input mode

PMC34

Specifies Control Mode of P34 Pin

I/O port mode

ASCK/SCK1 I/O mode

PMC33

Specifies Control Mode of P33 Pin

I/O port mode

TxD/SO1 output mode

PMC32

Specifies Control Mode of P32 Pin

I/O port mode

RxD/SI1 input mode

PMC31

Specifies Control Mode of P31 Pin

I/O port mode

TO11 output mode

PMC30

Specifies Control Mode of P30 Pin

I/O port mode

TO10 output mode

115

CHAPTER 5 PORT FUNCTIONS

5.5.3 Operating status

Port 3 is an input/output port, with a dual function as various control pins.

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-25. Port Specified as Output Port

Internal

Bus

Output

Latch

P3n
n = 0-7

OUT

PORT

116

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes

can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is

stored in all output latches irrespective of the port input/output specification. However, since the output buffer of

a bit specified as an input port is high impedance, the data is not output to the port pin (when a bit specified as input

is switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output

latch of a bit specified as an input port cannot be loaded into an accumulator.

Figure 5-26. Port Specified as Input Port

Output

Latch

P3n
n = 0-7

PORT

Internal

Bus

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins

or port mode and control mode, the contents of the output latch of pins specified as inputs and

pins specified as control mode will be undefined (excluding bits manipulated with a SET1 or CLR1

instruction, etc.). Particular care is required when there are bits which are switched between input

and output.

Caution is also required when manipulating the port with other 8-bit manipulation instructions.

117

CHAPTER 5 PORT FUNCTIONS

(3) When specified as control signal input/output

By setting (1) bits of the port 3 mode control register (PMC3), port 3 can be used as control signal input or output

bit-wise irrespective of the setting of the port 3 mode register (PM3). When a pin is used as a control signal, the

control signal status can be seen by executing a port read instruction.

Figure 5-27. Control Specification

P3n
n = 0-7

PM3n = 0

PM3n = 1

Control

(Output)

Internal Bus

Control (Input)

(a) When port is control signal output

When PM3n (n = 0 to 7) bits of the port 3 mode register (PM3) is set (1), the control signal pin level can be read

by executing a port read instruction.

When PM3n bit is reset (0), the

PD784054 internal control signal status can be read by executing a port read

instruction.

(b) When port is control signal input

Only the port 3 mode register (PM3) is set (1), control signal pin levels can be read by executing a port read

instruction.

Caution Pins that function as input pins in the control mode may malfunction if the corresponding bits

of the port 3 mode control register (PMC3) are rewritten while the pins are operating.

Therefore, write PMC3 on initializing the system.

CHAPTER 5 PORT FUNCTIONS

118

5.6 Port 4

Port 4 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 4 mode

In addition to its function as input/output port, port 4 also functions as the low-order multiplexed address/data bus (AD0

to AD7) when external memory or I/Os are extended.

When RESET is input, port 4 is set as an input port (output high-impedance state), and the output latch contents are

undefined.

5.6.1 Hardware configuration

The port 4 hardware configuration is shown in Figure 5-28.

Figure 5-28. Block Diagram of Port 4

PUO

PUO4

Internal
Data
Bus

P4n
n = 0-7

Input/
Output
Control
Circuit

PM4n

Internal
Address
Bus

Port 4 Mode Register

P4n

Output Latch

P4n

Pull-Up Resistor Option Register L

MM0-MM3

119

CHAPTER 5 PORT FUNCTIONS

5.6.2 Input/output mode/control mode setting

The port 4 input/output mode is set for each pin by means of the port 4 mode register (PM4) as shown in Figure 5-29.

When port 4 is used as the address/data bus, it is set by means of the memory extension mode register (MM: Refer to Figure

15-1) as shown in Table 5-4.

Figure 5-29. Format of Port 4 Mode Register (PM4)

PM47

PM46

PM45

PM44

PM43

PM42

PM41

PM40

PM4n

Specifies I/O Mode of P4n Pin (n = 0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM4

Address : 0FF24H On reset : FFH R/W

Table 5-4. Operation Mode of Port 4

Bits of MM

Operation Mode

Remark

MM3 MM2 MM1 MM0

Port (P40-P47)

Address/data bus (AD0-AD7)

Setting prohibited when

external 16-bit bus specified

CHAPTER 5 PORT FUNCTIONS

120

5.6.3 Operating status

Port 4 is an input/output port, with a dual function as the address/data bus (AD0 to AD7).

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-30. Port Specified as Output Port

Internal

Bus

Output

Latch

P4n
n = 0-7

OUT

PORT

121

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes

can be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is

stored in all output latches irrespective of the port input/output specification. However, since the output buffer of

a bit specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input

is switched to an output port, the output latch contents are output to the port pin). Also, when a bit specified as an

input port, the output latch contents cannot be loaded into an accumulator.

Figure 5-31. Port Specified as Input Port

Output

Latch

P4n
n = 0-7

PORT

Internal

Bus

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,

the contents of the output latch of pins specified as inputs will be undefined (excluding bits

manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits

which are switched between input and output.

Caution is also required when manipulating the port with other 8-bit manipulation instructions.

(3) When used as address/data bus (AD0 to AD7)

Used automatically when an external access is performed.

Input/output instructions should not be executed on port 4.

CHAPTER 5 PORT FUNCTIONS

122

5.6.4 Internal pull-up resistors

Port 4 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of

parts and the mounting area to be reduced.

Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO4 bit of the

pull-up resistor option register L (PUOL) and the port 4 mode register (PM4).

When the PUO4 bit is 1, the internal pull-up resistor of only the pin set in the input mode by the memory expansion mode

Figure 5-32. Format of Pull-up Resistor Option Register L (PUOL)

Caution When using port 4 as the address/data bus, be sure to reset the PUO4 bit to "0" to not connect the

internal pull-up resistor.

Remark

When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.

PUO6 PUO5 PUO4

PUO0

PUO6 Specifies Pull-up Resistor of Port 6

(refer to Figure 5-44).

PUOL

Address : 0FF4EH On reset : 00H R/W

PUO4

Specifies Pull-up Resistor of Port 4.

Not used with port 4

Used with port 4

PUO5 Specifies Pull-up Resistor of Port 5

(refer to Figure 5-38).

PUO0 Specifies Pull-up Resistor of Port 0

(refer to Figure 5-6).

123

CHAPTER 5 PORT FUNCTIONS

Figure 5-33. Pull-Up Resistor Specification (Port 4)

P41

Input

Buffer

P40

P42

P46

P47

Port 4 Mode Register

(PM4)

PUO4

(PUOL)

Internal

Bus

CHAPTER 5 PORT FUNCTIONS

124

5.7 Port 5

Port 5 is an 8-bit input/output port with an output latch. Input/output can be specified bit-wise by means of the port 5 mode

In addition to as an I/O port, port 5 also functions as follows when an external memory or I/O is connected:

When external 8-bit bus is specified

As the high-order address bus (AD8 through AD15)

When external 16-bit bus is specified

As the high-order multiplexed address/data bus (AD8 through AD15)

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output

latch are undefined.

5.7.1 Hardware configuration

The port 5 hardware configuration is shown in Figure 5-34.

Figure 5-34. Block Diagram of Port 5

PUO

PUO5

Internal
Data
Bus

Internal
Address
Bus

P5n
n = 0-7

PM5n

Port 5 Mode Register

P5n

Output Latch

P5n

Pull-Up Resistor Option Register L

MM0-MM3

Input/
Output
Control
Circuit

125

CHAPTER 5 PORT FUNCTIONS

5.7.2 Input/output mode/control mode setting

The port 5 input/output mode is set for each pin by means of the port 5 mode register (PM5) as shown in Figure 5-35.

When port 5 pins can be used as port or address pins in 2-bit units, the setting is performed by means of the memory extension

mode register (MM: Refer to Figure 15-1) as shown in Table 5-5.

Figure 5-35. Format of Port 5 Mode Register (PM5)

Table 5-5. Operation Mode of Port 5

Bits of MM

Operation mode

Remark

MM3 MM2 MM1 MM0

P50

P51

P52

P53

P54

P55

P56

P57

Port (P50-P57)

Setting prohibited when external

AD8

AD9

Port

16-bit bus specified. AD8-AD13

AD8

AD9 AD10 AD11 Port

used as address bus

AD8

AD9 AD10 AD11 AD12 AD13 Port

AD8

AD9 AD10 AD11 AD12 AD13 AD14 AD15

PM57

PM56

PM55

PM54

PM53

PM52

PM51

PM50

PM5n

Specifies I/O Mode of P5n Pin (n = 0 to 7)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM5

Address : 0FF25H On reset : FFH R/W

CHAPTER 5 PORT FUNCTIONS

126

5.7.3 Operating status

Port 5 is an input/output port, with a dual function as the address/data bus (AD8 to AD15).

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-36. Port Specified as Output Port

Internal

Bus

Output

Latch

P5n
n = 0-7

OUT

PORT

127

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can

be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored

in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit

specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is

switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch

of a bit specified as an input port cannot be loaded into an accumulator.

Figure 5-37. Port Specified as Input Port

Output

Latch

P5n
n = 0-7

PORT

Internal

Bus

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,

the contents of the output latch of pins specified as inputs will be undefined (excluding bits

manipulated with a SET1 or CLR1 instruction, etc.). Particular care is required when there are bits

which are switched between input and output.

Caution is also required when manipulating the port with other 8-bit operation instructions.

(3) When used as address/data bus (AD8 to AD15)

Port 5 is automatically used when an external address/data bus is accessed.

At this time, do not execute an I/O instruction to port 5.

CHAPTER 5 PORT FUNCTIONS

128

5.7.4 Internal pull-up resistors

Port 5 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of

parts and the mounting area to be reduced.

Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO5 bit of the

pull-up resistor option register L (PUOL) and the port 5 mode register (PM5).

When PUO5 bit is 1, the internal pull-up resistor of only the pin set in the input port by the memory expansion mode register

(MM) and PM5 is valid.

Figure 5-38. Format of Pull-Up Resistor Option Register L (PUOL)

Caution When port 5 is used as the address/data bus, and "0" must be set in PUO5 bit so that internal pull-up

resistor connection is not performed.

Remark

When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.

PUO6 PUO5 PUO4

PUO0

PUO6 Specifies Pull-up Resistor of Port 6

(refer to Figure 5-44).

PUOL

Address : 0FF4EH On reset : 00H R/W

PUO5

Specifies Pull-up Resistor of Port 5.

Not used with port 5

Used with port 5

PUO4 Specifies Pull-up Resistor of Port 4

(refer to Figure 5-32).

PUO0 Specifies Pull-up Resistor of Port 0

(refer to Figure 5-6).

129

CHAPTER 5 PORT FUNCTIONS

Figure 5-39. Pull-Up Resistor Specification (Port 5)

P51

Input

Buffer

P50

P52

P56

P57

Port 5 Mode Register

(PM5)

PUO5

(PUOL)

Internal

Bus

CHAPTER 5 PORT FUNCTIONS

130

5.8 Port 6

Port 6 is a 4-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using port

6 mode register (PM6). Each pin is provided with a software programmable pull-up resistor.

In addition to as an I/O port, this port also functions as the high-order address bus (A16 through A19) if so specified when

an external memory or I/O is connected.

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output

latch are undefined.

5.8.1 Hardware configuration

The port 6 hardware configuration is shown in Figures 5-40.

Figure 5-40. Block Diagram of Port 6

PUO

PUO6

P6n
n = 0-3

PM6n

P6n

PM6n

Port 6 Mode Register

P6n

Output Latch

P6n

Pull-Up Resistor Option Register L

MM0-MM3

Internal
Data
Bus

Internal
Address
Bus

Input/
Output
Control
Circuit

131

CHAPTER 5 PORT FUNCTIONS

5.8.2 Setting of I/O mode/control mode

The input/output mode of port 6 is set in 1-bit units by using the port 6 mode register (PM6) as shown in Figure 5-41.

Port 6 can be used as port pins or address pins in 2-bit units. Whether it is used as port pins or address pins is specified

by using the memory extension mode register (MM: refer to Figure 15-1), as shown in Table 5-6.

Figure 5-41. Format of Port 6 Mode Register (PM6)

PM63

PM62

PM61

PM60

PM6n

Specifies I/O Mode of P6n Pin (n = 0 to 3)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM6

Address : 0FF26H On reset : FFH R/W

Table 5-6. Operation Mode of Port 6

Bits of MM

Operation mode

Remark

MM3 MM2 MM1 MM0

P60

P61

P62

P63

Port (P60-P63)

Setting prohibited when external

16-bit bus specified.

A16

A17

Port

A16

A17

A18

A19

CHAPTER 5 PORT FUNCTIONS

132

5.8.3 Operating status

Port 6 is an input/output port, with a dual function as the address bus (A16 to A19).

(1) When set as an output port

The output latch is enabled, and data transfers between the output latch and accumulator are performed by means

of transfer instructions. The output latch contents can be freely set by means of logical operation instructions. Once

data has been written to the output latch, it is retained until data is next written to the output latch

Note

Including the case where another bit of the same port is manipulated by a bit manipulation instruction.

Figure 5-42. Port Specified as Output Port

Internal

Bus

Output

Latch

P6n
n = 0-3

OUT

PORT

133

CHAPTER 5 PORT FUNCTIONS

(2) When set as an input port

The port pin level can be loaded into an accumulator by means of a transfer instruction. In this case, too, writes can

be performed to the output latch, and data transferred from the accumulator by a transfer instruction, etc., is stored

in all output latches irrespective of the port input/output specification. However, since the output buffer of a bit

specified as an input port is high-impedance, the data is not output to the port pin (when a bit specified as input is

switched to an output port, the output latch contents are output to the port pin). Also, the contents of the output latch

of a bit specified as an input port cannot be loaded into an accumulator.

Figure 5-43. Port Specified as Input Port

Output

Latch

P6n
n = 0-3

PORT

Internal

Bus

Caution A bit manipulation instruction manipulates one bit as the result, but accesses the port in 8-bit units.

Therefore, if a bit manipulation instruction is used on a port with a mixture of input and output pins,

or port mode and control mode, the contents of the output latch of pins specified as inputs or pins

specified as in the control mode will be undefined (excluding bits manipulated with a SET1 or CLR1

instruction, etc.). Particular care is required when there are bits which are switched between input

and output.

Caution is also required when manipulating the port with other 8-bit manipulation instructions.

(3) When used as address bus (A16 to A19)

Port 6 is automatically used for external access.

At this time, do not execute an I/O instruction to port 6.

CHAPTER 5 PORT FUNCTIONS

134

5.8.4 Internal pull-up resistors

Port 6 incorporates pull-up resistors. Use of these internal resistors when pull-up is necessary enables the number of

parts and the mounting area to be reduced.

Whether or not an internal pull-up resistor is to be used can be specified for each pin by means of the PUO6 bit of the

pull-up resistor option register L (PUOL) and the port 6 mode register (PM6).

The internal pull-up resistor of only the pin set in the input mode by PM6 is valid when the PUO6 bit is 1.

Even when port 6 is specified as the address bus, specifying the use of the internal pull-up resistor is valid. To not connect

the internal pull-up resistor, either set the output mode by using the port 6 mode register (PM6) (PM6n = 0: n = 0 to 3), or

reset PUO6 to 0.

Figure 5-44. Format of Pull-Up Resistor Option Register L (PUOL)

PUO6 PUO5 PUO4

PUO0

PUO5 Specifies Pull-up Resistor of Port 5

(refer to Figure 5-38).

PUOL

Address : 0FF4EH On reset : 00H R/W

PUO6

Specifies Pull-up Resistor of Port 6

Not used with port 6

Used with port 6

PUO4 Specifies Pull-up Resistor of Port 4

(refer to Figure 5-32).

PUO0 Specifies Pull-up Resistor of Port 0

(refer to Figure 5-6).

Remark

When STOP mode is entered, setting 00H in PUOL is effective in reducing the current consumption.

135

CHAPTER 5 PORT FUNCTIONS

Figure 5-45. Pull-Up Resistor Specification (Port 6)

P61

P60

P62

P63

Port 6 Mode Register

(PM6)

PUO6

(PUOL)

Internal

Bus

Input

Buffer

CHAPTER 5 PORT FUNCTIONS

136

5.9 Port 7

Port 7 is an 8-bit input port. In addition to functioning as input port pins, its pins also function as an A/D converter analog

input (low-order 8 channels) pins (ANI0 through ANI7), and can always input analog signals. This port is set in the analog

input mode by using A/D converter mode register (ADM) (refer to Figure 11-3).

The level of each pin of this port can always be read or tested, regardless of the multiplexed function.

5.9.1 Hardware configuration

Figure 5-46 shows the hardware configuration of port 7.

Figure 5-46. Block Diagram of Port 7

5.9.2 Notes

(1) Do not apply a voltage outside the range of AV

to AV

REF

to the P70 through P77 pins when they are used as ANI0

through ANI7. For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.

(2) If some pins of port 7 are used for analog input and the others are used for digital input, and if the digital input changes

at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is necessary, do

not use analog input and digital input simultaneously.

Internal Bus

P7n
n = 0-7

A/D Converter

137

CHAPTER 5 PORT FUNCTIONS

5.10 Port 8

Port 8 is an 8-bit input port. In addition to functioning as input port pins, its pins also function as an A/D converter analog

input (high-order 8 channels) pins (ANI8 through ANI15), and can always input analog signals. This port is set in the analog

input mode by using A/D converter mode register (ADM) (refer to Figure 11-3).

The level of each pin of this port can always be read or tested, regardless of the multiplexed function.

5.10.1 Hardware configuration

Figure 5-47 shows the hardware configuration of port 8.

Figure 5-47. Block Diagram of Port 8

Internal Bus

P8n
n = 0-7

A/D Converter

5.10.2 Cautions

(1) Do not apply a voltage outside the range of AV

to AV

REF

to the P80 through P87 pins when they are used as ANI8

through ANI15. For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.

(2) If some pins of port 8 are used for analog input and the others are used for digital input, and if the digital input changes

at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is necessary, do

not use analog input and digital input simultaneously.

CHAPTER 5 PORT FUNCTIONS

138

5.11 Port 9

Port 9 is a 5-bit I/O port with an output latch. This port can be set in the input or output mode in 1-bit units by using port

9 mode register (PM9). Each pin is provided with a software programmable pull-up resistor.

In addition to the I/O port function, port 9 also functions as control signal pins (refer to Table 5-7). P90 through P93

functions as a read/write strobe signals and address strobe signal when an external memory or I/O is connected. P94

functions as a wait signal input pin if so specified by port 9 mode control register (PMC9).

When RESET is input, this port is set in the input mode (output high-impedance status), and the contents of the output

latch are undefined.

Table 5-7. Operation Mode of Port 9

Pin Name

Port Mode

Control Signal I/O Mode

Manipulation to Use Port 9 as Control Pins

P90

I/O Port

Specifying external memory expansion mode by

P91

LWR

MM0 through MM3 bits of memory expansion

P92

HWR

mode register (MM)

P93

ASTB

P94

WAIT

Setting of PMC94 bit of PMC9 to 1

Remark

For details, refer to CHAPTER 15 LOCAL BUS INTERFACE FUNCTION.

(a) Port mode

Each port pin not set in the control mode can be set in the input or output mode in 1-bit units by using the port

9 mode register (PM9).

(b) Control signal I/O mode

(i) RD (Read Strobe)

This pin outputs a strobe signal to read an external memory. The operation of this pin is specified by the

memory expansion mode register (MM).

(ii) LWR, HWR (Low/High Write Strobe)

These pins output strobe signals to write an external memory. The operations of these pins are specified

by the memory expansion mode register (MM).

(iii) ASTB (Address Strobe)

This is a timing signal output pin to latch the address information output from the AD0 through AD15 pins

to access the external memory. The operation of this pin is specified by the memory expansion mode

(iv) WAIT (Wait)

This pin inputs a wait signal. The operation of this pin is specified by the port 9 mode control register (PMC9).

139

CHAPTER 5 PORT FUNCTIONS

5.11.1 Hardware configuration

Figure 5-48 and Figure 5-49 show the hardware configuration of port 9.

Figure 5-48. Block Diagram of P90 to P93 (Port 9)

OUT

PUO

Output Latch

Pull-Up Resistor Option Register H

PUO

P9n

Port 9 Mode Register

PUO9

P9n

PM9n

Selector

Internal

Bus

P9n
n = 0-3

External Extension Mode

PM9n

RD, LWR, HWR and ASTB signals

CHAPTER 5 PORT FUNCTIONS

140

Figure 5-49. Block Diagram of P94 (Port 9)

P94

Pull-Up Resistor Option Register H

PUO

P94

Internal Bus

Wait Input

PUO

PM94

Port 9 Mode Register

PMC94

PUO9

PM94

P94

PMC94

Output Latch

141

CHAPTER 5 PORT FUNCTIONS

5.11.2 Setting of I/O mode/control mode

The input/output mode of port 9 is set per pin by using the port 9 mode register (PM9) as shown in Figure 5-50.

In addition to as an I/O port function, port 9 also has the following functions. P90 through P93 can be used as RD, LWR,

HWR, and ASTB pins, if so specified by the memory extension mode register (MM: refer to Figure 15-1), as shown in Table

5-8. P94 can be used as a WAIT pin if so specified by the port 9 mode control register (PMC9) as shown in Figure 5-51.

Figure 5-50. Format of Port 9 Mode Register (PM9)

PM94

PM93

PM92

PM91

PM90

PM9n

Specifies I/O Mode of P9n Pin (n = 0 to 4)

Output mode (output buffer ON)

Input mode (output buffer OFF)

PM9

Address : 0FF29H On reset : FFH R/W

Table 5-8. Operation Mode of P90 through P93

Bits of MM

Operation mode

Remark

MM3 MM2 MM1 MM0

P90

P91

P92

P93

Port (P90-P93)

LWR HWR ASTB

Setting prohibited when external

16-bit bus specified.

Figure 5-51. Format of Port 9 Mode Control Register (PMC9)

PMC94

Specifies Control Mode of P94 Pin

I/O port mode

WAIT input mode

PMC9

Address : 0FF49H On reset : 00H R/W

CHAPTER 5 PORT FUNCTIONS

142

5.11.3 Operating status

Port 9 is an input/output port and is multiplexed with control pins.

(1) In output port mode

The output latch is valid, and data is transferred between the output latch and accumulator by a transfer instruction.

The contents of the output latch can be freely set by a logical operation instruction. Data that has been written to

the output latch is retained until new data is written to the output latch

Note

Including when the other bits of the same port are manipulated by a bit manipulation instruction.

Figure 5-52. Port in Output Port Mode

Internal Bus

Output

Latch

P9n
n = 0-4

OUT

PORT

143

CHAPTER 5 PORT FUNCTIONS

(2) In input port mode

The level of a port pin can be loaded to the accumulator by using a transfer instruction. Even in this case, data can

be written to the output latch. Data transferred from the accumulator by a transfer instruction is stored to all the latches

regardless of whether the input or output mode is specified. However, because the output buffer of a bit (pin) set

in the input mode is in the high-impedance state, its contents are not output to the port pin (the contents of the output

latch are output to the port pin when the mode of the pin is changed from input to output). The contents of the output

latch of the pin set in the input port cannot be loaded to the accumulator.

Figure 5-53. Port in Input Port Mode

Output

Latch

P9n
n = 0-4

PORT

Internal Bus

Caution Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port

in 8-bit units. If such an instruction is executed to manipulate a port with some pins set in the input

mode and the others in the control mode, the contents of the output latch are undefined (except when

a pin is manipulated by the SET1 or CLR1 instruction). Especially, care must be exercised if the mode

of some pins must be changed between input and output.

The same applies when manipulating the port by using the other 8-bit operation instructions.

CHAPTER 5 PORT FUNCTIONS

144

(3) Pin in control mode

P90 through P93

These pins are automatically used as the RD, LWR, HWR, and ASTB pins when the external memory or I/O is

accessed.

At this time, do not execute an I/O instruction to P90 through P93.

P94

This pin can be used as the WAIT pin, regardless of the setting of the port 9 mode register (PM9), if the PMC94

bit of the port 9 mode control register (PMC9) is set (1). When using P94 as the WAIT pin, the status of the WAIT

pin can be read by executing an instruction that reads the port only when the PM94 bit of PM9 is set (1).

Caution The pin that functions as an input pin in the control mode (P94) may malfunction if the PMC94

bit of the port 9 mode control register (PMC9) is rewritten while the pin is operating. Therefore,

write PMC9 on initializing the system.

5.11.4 Internal pull-up resistor

Port 9 is provided with pull-up resistors. When the port must be pulled up, the number of components and the mounting

area can be reduced by using these internal pull-up resistor.

Whether the internal pull-up resistors are used or not is specified per pin by using the PUO9 bit of the pull-up resistor

option register H (PUOH) and port 9 mode register (PM9).

When the PUO9 bit is 1, the internal pull-up resistor of only the pin specified as follows is valid.

P90 through P93 : Set in input port mode by memory extension mode register (MM) and PM9

P94

: Set in input mode by PM9

Even when P94 is specified as the WAIT pin, specifying its use as a pull-up resistor is valid. In order not to connect the

internal pull-up resistor, either specify the output mode by using PM9 (PM94 = 0), or reset (0) in PUO9.

Figure 5-54. Format of Pull-up Resistor Option register H (PUOH)

PUO9

PUOH

Address : 0FF4FH On reset : 00H R/W

PUO9

Specifies Pull-up Resistor of Port 9

Not used with port 9

Used with port 9

Caution When using P90 through P93 as the RD, LWR, HWR, and ASTB pins, be sure to reset the PUO9 bit to

"0" in order not to connect the internal pull-up resistor.

Remark

Resetting PUOH to 00H is effective for decreasing the current consumption when the STOP mode is set.

145

CHAPTER 5 PORT FUNCTIONS

Figure 5-55. Specifying Pull-up Resistor (port 9)

P91

P90

P92

P93

P94

Port 9 Mode Register

(PM9)

PUO9

(PUOH)

Internal Bus

Input Buffer

CHAPTER 5 PORT FUNCTIONS

146

5.12 Port Output Data Check Function

The

PD784054 has a function to read the status of a port pin even in the output mode, to improve the reliability of the

system (pin access mode). Therefore, the output data and the actual pin status can be checked as necessary. If the data

does not match the pin status, countermeasures such as replacing by another system can be taken.

To read the pin status, set (1) bit 0 of the port read control register (PRDC), and then read the port.

When RESET is input, PRDC is reset to 00H.

Figure 5-56. Format of Port Read Control Register (PRDC)

PRDC0

PRDC

Address : 0FF2FH On reset : 00H R/W

PRDC0

Specifies Operation Mode

Normal mode

Pin access mode

Example

To check the output data of ports 0 (P0), 4 (P4), and 5 (P5) by using the pin access mode.

TEST:

; Disables interrupts

MOV

A, #5AH

; Test data = 5AH

MOV

P0, A

; Sets 5AH to output latch

MOV

P4, A

MOV

P5, A

SET1

PRDC.0

; Sets pin access mode (sets PRDC)

CMP

A, P0

; Compares pin level and output latch contents

BNE

$ERR0

; Error if unmatch

CMP

A, P4

BNE

$ERR4

CMP

A, P5

BNE

$ERR5

CLR1

PRDC.0

; Returns to normal mode (resets PRDC)

; Enables interrupts

147

CHAPTER 5 PORT FUNCTIONS

Cautions 1. If a bit manipulation instruction is executed to manipulate the port, it is not executed normally in

the pin access mode (PRDC0 = 1). After checking the port, be sure to reset the mode to the normal

mode (PRDC0 = 0).

2. If an interrupt occurs in the pin access mode (PRDC0 = 1), a bit manipulation instruction may be

executed with this mode maintained, causing malfunctioning. Be sure to set the DI status before

checking the port.

Do not use a macro service that manipulates the port.

3. Occurrence of the non-maskable interrupt cannot be prevented. Take the following measures in

the program, depending on the system:

Do not manipulate the port in the non-maskable interrupt routine.

Save the level of PRDC.0 at the beginning of the non-maskable interrupt routine, and restore it on

returning execution from the interrupt routine.

If PRDC.0 is set (1), the switch enclosed by the dotted line in the figure below is connected to the pin, and the pin level

is read. If a bit manipulation instruction is executed in this status, the pin level is read and the bit is manipulated, affecting

the value of the output latch.

When PRDC.0 is reset (0), the normal operation is performed.

Figure 5-57. Concept of Control (in output port mode)

Internal Bus

PORT

Output

Latch

OUT

PXn

PRDC.0 = 0

PRDC.0 = 1

Dedicated instructions (CHKL, CHKLA) that are used to frequently check the port status are available. These instructions

compare the pin status with the contents of the output latch (in port mode), or the pin status with the level of the internal

control output signal (in control mode) through exclusive OR.

CHAPTER 5 PORT FUNCTIONS

148

Example

To check the pin status and the contents of the output latch using the CHKL or CHKLA instruction.

TEST:

SET1

P0.3

; Sets bit 3 of port 0

CHKL

; Checks port 0

BNE

$ERR1

; Branches to error processing (ERR1) if contents of output

latch do not match pin status

ERR1:

CHKLA

; Checks defective bit

A.3, $BIT03

; Bit 3?

A.2, $BIT02

; Bit 2?

A.1, $BIT01

; Bit 1?

$BIT00

; Bit 0 is defective if all other bits are valid.

Cautions 1. Use the CHKL or CHKLA instruction when the PRDC0 bit of the port read control register (PRDC)

is "0" (normal mode).

2. The result of comparison by the CHKL or CHKLA instruction always matches, regardless of

whether the pin set in the input port mode is set in the port mode or control mode. Because the

input level of the input-only pin is read when the CHKL or CHKLA instruction is executed, because

this pin does not have an output latch. In other words, executing the CHKL or CHKLA instruction

to the input-only pin is practically invalid, therefore, do not use the instruction to manipulate such

a pin.

3. To check the output level of a port with some of its bits set in the control output mode and others

in the port output mode, using the CHKL or CHKLA instruction, execute the instruction after

changing the input/output mode of the control output pin to the input mode (the output level of

the control output pin changes asynchronously and therefore cannot be checked by the CHKL or

CHKLA instruction).

149

CHAPTER 5 PORT FUNCTIONS

5.13 Cautions

(1) All the port pins go into a high-impedance state when the RESET signal is input (the internal pull-up resistor is also

disconnected from the pin).

If it is necessary to prevent a pin from going into a high-impedance state during RESET input, use an external circuit.

(2) Bits 1, 3, and 7 of the pull-up resistor option register L (PUOL) that specifies connection of the internal pull-up resistor,

and bits 0 and 2 through 7 of the pull-up resistor option register H (PUOH) are fixed to "0". However, if "1" is written

to these bits, 1 can be read with an in-circuit emulator.

(3) The contents of the output latch are not initialized by RESET input. To use a port as an output port, be sure to initialize

the output latch before turning ON the output buffer. Unless the output buffer is initialized before the output buffer

is turned ON, unexpected data is output to the output port.

In the same way, when using a port as control pins, be sure to initialize the internal peripheral hardware, and then

set the port in the control mode.

(4) Although the result of a bit manipulation instruction is ultimately 1 bit manipulation, it accesses a port in 8-bit units.

If such an instruction is executed to manipulate a port with some pins set in the input/output mode and the others

in the port mode and in the control mode, the contents of the output latch are undefined (except when a pin is

manipulated by the SET1 or CLR1 instruction). Especially, care must be exercised if the mode of some pins must

be changed between input and output.

The same applies when manipulating the port by using the other 8-bit operation instructions.

(5) Even when using the P21 through P27 pins in the output port mode or timer output mode, INTPn (n = 0 to 6) interrupt

occurs depending on the edge detection of the pin level. Mask the interrupt before using these pins.

(6) The pins used as input pins in the control mode (P32, P34, P35, P37, and P94) may malfunction if the corresponding

bit of the port n mode control register (PMCn: n = 3, 9) while these pins are operating. Therefore, write PMCn on

initializing the system.

(7) When using ports 4 and 5, and P90 through P93 as pins in the external memory extension mode, be sure to reset

the corresponding bits of the pull-up resistor option registers (PUOL, PUOH) to "0", in order not to connect the internal

pull-up resistor.

(8) Do not apply a voltage outside the range of AV

to AV

REF

to P70 through P77 and P80 through P87 used as ANI0

through ANI15.

For details, refer to 11.6 Cautions in CHAPTER 11 A/D CONVERTER.

(9) If some pins of ports 7 and 8 are used for analog input and the others are used for digital input, and if the digital

input changes at analog input sampling timing, the A/D conversion accuracy is affected. When a high accuracy is

necessary, do not use analog input and digital input simultaneously.

(10) A bit manipulation instruction executed to manipulate the port is not executed normally in the pin access mode

(PRDC0 of port read control register (PRDC) = 1). After checking the port, be sure to reset the mode to the normal

mode (PRDC0 = 0).

CHAPTER 5 PORT FUNCTIONS

150

(11) If an interrupt occurs in the pin access mode (PRDC0 of PRDC = 1), a bit manipulation instruction may be executed

with this mode maintained, causing malfunctioning. Be sure to set the DI status before checking the port.

Do not use a macro service that manipulates the port.

(12) Occurrence of the non-maskable interrupt cannot be prevented in the pin access mode (PRDC0 of PRDC = 1). Take

the following measures by using the program, depending on the system:

Do not manipulate the port in the non-maskable interrupt routine.

Save the level of PRDC.0 at the beginning of the non-maskable interrupt routine, and restore it on returning

execution from the interrupt routine.

(13) Use the CHKL or CHKLA instruction when the PRDC0 bit of PRDC is "0" (normal mode).

(14) The result of comparison by the CHKL or CHKLA instruction always matches, regardless of whether the pin set in

the input port mode is set in the port mode or control mode.

Because the input level of the input-only pin is read when the CHKL or CHKLA instruction is executed, because this

pin does not have an output latch. In other words, executing the CHKL or CHKLA instruction to the input-only pin

is practically invalid, and therefore, do not use the instruction to manipulate such a pin.

(15) To check the output level of a port with some of its bits set in the control output mode and others in the port output

mode, by using the CHKL or CHKLA instruction, execute the instruction after changing the input/output mode of the

control output pin to the input mode (the output level of the control output pin changes asynchronously and therefore

cannot be checked by the CHKL or CHKLA instruction).

CHAPTER 6 OUTLINE OF TIMER

The

PD784054 incorporates three 16-bit time units.

These timer units can be used as eleven units of timers because the

PD784054 supports eleven interrupt requests.

Table 6-1. Operations of Timer

Name

Timer 0

Timer 1

Timer 4

Item

Operation mode

Interval timer

4 ch

2 ch

Function

Timer output

4 ch

2 ch

Toggle output

Set/reset output

Overflow interrupt

Number of interrupt requests

151

152

CHAPTER 6 OUTLINE OF TIMER

Figure 6-1. Block Diagram of Timer (1/2)

Timer 0

Prescaler

Timer Register 0

(TM0)

CLK

INTP0

INTP1

INTP2

INTP3

INTOV0

Edge

Detection

Capture/Compare

INTP0

INTCC00

Match

TO00

Pulse
Output
Control

Edge

Detection

Capture/Compare

INTP1

INTCC01

Match

TO01

Edge

Detection

Capture/Compare

INTP2

INTCC02

Match

TO02

Pulse
Output
Control

Edge

Detection

Capture/Compare

INTP3

INTCC03

Match

TO03

Prescaler: f

CLK

/4, f

CLK

/8, f

CLK

/16, f

CLK

/32, f

CLK

/64

Timer 1

CLK

Prescaler

Timer Register 1

(TM1)

Compare Register 10

(CM10)

INTCM10

Match

TO10

Pulse
Output
Control

Compare Register 11

(CM11)

INTCM11

Match

TO11

Clear

Control

INTOV1

Prescaler: f

CLK

/8, f

CLK

/16, f

CLK

/32, f

CLK

/64, f

CLK

/128

153

CHAPTER 6 OUTLINE OF TIMER

Figure 6-1. Block Diagram of Timer (2/2)

Timer 4

Prescaler: f

CLK

/4, f

CLK

/8, f

CLK

/16, f

CLK

/32, f

CLK

/64

CLK

Prescaler

Timer Register 4

(TM4)

Compare Register 40

(CM40)

Match

INTCM40

Compare Register 41

(CM41)

Match

INTCM41

Clear

Control

INTOV4

[MEMO]

154

CHAPTER 7 TIMER 0

7.1 Function

Timer 0 is a 16-bit free running timer.

Because this timer has four capture/compare registers and a toggle and set/reset timer output functions, it can be used

as an interval timer or to measure pulse width.

(1) Interval timer

When timer 0 is used as an interval timer, it generates an internal interrupt at interval set in advance.

Table 7-1. Interval Time of Timer 0

Minimum Interval Time

Note

Maximum Interval Time

Resolution

4/f

CLK

(0.25

4/f

CLK

(16.4 ms)

4/f

CLK

(0.25

8/f

CLK

(0.5

8/f

CLK

(32.8 ms)

8/f

CLK

(0.5

16/f

CLK

(1.0

16/f

CLK

(65.5 ms)

16/f

CLK

(1.0

32/f

CLK

(2.0

32/f

CLK

(131 ms)

32/f

CLK

(2.0

64/f

CLK

(4.0

64/f

CLK

(262 ms)

64/f

CLK

(4.0

( ): at f

CLK

= 16 MHz

Note

The minimum interval time is limited by the data transfer processing time.

Consider the interrupt processing time or macro service processing time

used (refer to Table 14-11 Interrupt Acceptance Processing Time and

Table 14-12 Macro Service Processing Time).

155

CHAPTER 7 TIMER 0

156

(2) Pulse width measurement

Timer 0 can be used to detect the pulse width of a signal input to an external interrupt request input pin (INTP0 to

INTP3).

Table 7-2. Pulse Width Measurement Range of Timer 0

Measurable Pulse Width

Note 1

Resolution

4/f

CLK

(0.25

Note 2

4/f

CLK

(16.4 ms)

4/f

CLK

(0.25

8/f

CLK

(0.5

Note 2

8/f

CLK

(32.8 ms)

8/f

CLK

(0.5

16/f

CLK

(1.0

Note 2

16/f

CLK

(65.5 ms)

16/f

CLK

(1.0

32/f

CLK

(2.0

Note 2

32/f

CLK

(131 ms)

32/f

CLK

(2.0

64/f

CLK

(4.0

Note 2

64/f

CLK

(262 ms)

64/f

CLK

(4.0

( ): at f

CLK

= 16 MHz

Notes 1. The minimum measurable pulse width changes depending on the sampling clock selected by the noise

protection control register (NPC). The minimum measurable pulse width is either of the values in the above

table and the table below, whichever greater.

Sampling Clock

Minimum Pulse Width

CLK

4/f

CLK

(0.25

CLK

16/f

CLK

(1.0

2. This value is limited by the data transfer processing time. Consider the interrupt processing time or macro

service processing time used (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-

12 Macro Service Processing Time).

7.2 Configuration

Timer 0 consists of the following registers:

Timer register (TM0)

Capture/compare register (CC0n)

4 (n = 0 to 3)

Figure 7-1 shows the block diagram of timer 0.

CHAPTER 7 TIMER 0

157

Figure 7-1. Block Diagram of Timer 0

Internal Bus

1/8

ES21 ES20 ES11 ES10 ES01 ES00

External Interrupt Mode
Register 0
(INTM0)

External Interrupt
Mode Register 1
(INTM1)

ES31 ES30

1/8

Capture/Compare
Register 00 (CC00)

Match

Capture/Compare
Register 01 (CC01)

Capture/Compare
Register 02 (CC02)

Match

Timer Output Control
Register 0
(TOC0)

ENTO03

1/8

ALV03 ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00

Edge
Detection
Circuit

INTP0

Edge
Detection
Circuit

INTP1

Edge
Detection
Circuit

INTP2

Edge
Detection
Circuit

INTP3

INTP0

INTP1

INTP2

INTP3

Capture Trigger

CLK

Prescaler

Selector

CLK

/64

CLK

/32

CLK

/16

CLK

1/8

PRM02 PRM01 PRM00

Prescaler Mode
Register (PRM)

Timer Unit Mode
Register 0 (TUM0)

TOM02 TOM00 CMS03 CMS02 CMS01 CMS00

1/8

Timer Register 0

(TM0)

Match

Capture/Compare
Register 03 (CC03)

Match

Overflow

Clear

RESET

Timer Mode
Control Register
(TMC)

1/8

CE0

TO03

INTCC03

INTOV0

Output
Control
Circuit

TO02

INTCC02

Output
Control
Circuit

TO01

INTCC01

Output
Control
Circuit

TO00

INTCC00

Output
Control
Circuit

CHAPTER 7 TIMER 0

158

(1) Timer register 0 (TM0)

TM0 is a timer register that counts up the count clock specified by the prescaler mode register (PRM).

Counting of this timer register is enabled or disabled by the timer mode control register (TMC).

The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM0 is cleared

to 0000H and stops counting.

(2) Capture/compare registers (CC00 through CC03)

CC0n (n = 0 to 3) is a 16-bit register that can be used as a compare register to detect match between its value and

the count value of TM0 or as a capture register to capture the count value of TM0. Whether CC0n is used as a

compare register or capture register is specified by the timer unit mode register 0 (TUM0).

This register can be read or written by using a 16-bit manipulation instruction.

When RESET is input, the value of this register is undefined.

When the CE0 bit of the timer mode control register (TMC) is 0 and timer 0 is stopped, the capture operation is not

performed.

(a) As compare register

When used as a compare register, CC0n functions as a 16-bit register that holds the value determining the cycle

of the interval timer operation.

When the contents of CC0n matches with the contents of TM0, an interrupt request (INTCC0n: n = 0 to 3) and

a timer output control signal are generated.

(b) As capture register

When used as a capture register, CC0n functions as a 16-bit register that captures the contents of TM0 in

synchronization with the valid edge (capture trigger) input from an external interrupt input pin (INTPn: n = 0

to 3).

The contents of CC0n are retained until the next capture trigger is generated.

(3) Edge detection circuit

The edge detection circuit detects the valid edge of an external input.

It detects the valid edge of the INTP0 through INTP3 pin inputs, and generates an external interrupt request (INTP0

to INTP3) and capture trigger. The valid edge is specified by the external interrupt mode registers (INTM0 and

INTM1) (for the details of INTM0 and INTM1, refer to Figures 13-1 and 13-2).

(4) Output control circuit

When the contents of CC0n (n = 0 to 3) and the contents of TM0 match, the timer output can be inverted. A square

wave can be output from a timer output pin (TO00 to TO03) if so specified by the timer output control register 0

(TOC0). The TO00 and TO02 pins can also output a set and reset signals if so specified by the timer unit mode

The timer output can be enabled or disabled by TOC0. When the timer output is disabled, a fixed level is output

to the TO0n (n = 0 to 3) pin (the output level is fixed by TOC0).

(5) Prescaler

The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler

is selected by the selector, and TM0 performs the count operation by using this clock as a count clock.

(6) Selector

The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM0.

CHAPTER 7 TIMER 0

159

7.3 Timer 0 Control Register

(1) Timer unit mode register 0 (TUM0)

TUM0 is a register that specifies the output mode of the timer output pins (TO00, TO02, and TO10) of timers 0 and

1, controls the clear operation of the timer register 1 (TM1), and specifies the operations of the capture/compare

registers (CC00 through CC03) of timer 0.

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

7-2 shows the format of TUM0.

When RESET is input, the value of TUM0 is cleared to 00H.

Figure 7-2. Format of Timer Unit Mode Register 0 (TUM0)

TOM10 CLR1 TOM02 TOM00 CMS03 CMS02 CMS01 CMS00

TOM10 Specifies Output Mode of TO10 Pin

(refer to Figure 8-2).

TUM0

Address : 0FF30H On reset : 00H R/W

TOM0n

Specifies Output Mode of TO0n Pin (n = 0, 2)

Toggle output

Set/reset output

CLR1 Controls Clear Operation of TM1

(refer to Figure 8-2).

CMS0n

Specifies Operation of CC0n (n = 0 to 3)

Capture register

Compare register

CHAPTER 7 TIMER 0

160

(2) Timer mode control register (TMC)

TMC is a register that controls the count operation of timer registers 0 and 1 (TM0 and TM1).

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

7-3 shows the format of TMC.

When RESET is input, the value of this register is cleared to 00H.

Figure 7-3. Format of Timer Mode Control Register (TMC)

(3) Timer output control register 0 (TOC0)

TOC0 is a register that specifies the operation and active level of the timer output pins (TO00 through TO03) of

timer 0.

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

7-4 shows the format of TOC0.

When RESET is input, the value of this register is cleared to 00H.

Figure 7-4. Format of Timer Output Control Register 0 (TOC0)

ENTO03 ALV03 ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00

TOC0

Address : 0FF32H On reset : 00H R/W

ENTO0n

Specifies Operation of TO0n Pin (n = 0 to 3)

Outputs ALV0n

Enables pulse output

ALV0n

Specifies Active Level of TO0n Pin (n = 0 to 3)

Low level

High level

CE1

CE0

CE1

Controls Count Operation of TM1

(refer to Figure 8-3).

TMC

Address : 0FF31H On reset : 00H R/W

CE0

Controls Count Operation of TM0

Clears and stops counting

Enables counting

CHAPTER 7 TIMER 0

161

(4) Prescaler mode register (PRM)

PRM is a register that specifies the count clock of timer registers 0 and 1 (TM0 and TM1).

This register can be read or written by using an 8-bit manipulation instruction. Figure 7-5 shows the format of PRM.

When RESET is input, the value of this register is cleared to 00H.

Figure 7-5. Format of Prescaler Mode Register (PRM)

PRM12 PRM11 PRM10

PRM02 PRM01 PRM00

PRM

Address : 0FF38H On reset : 00H R/W

PRM12

Specifies Count Clock of TM1

(refer to Figure 8-5).

PRM02

Specifies Count Clock of TM0.

CLK

/16

CLK

/32

CLK

/64

Setting prohibited

PRM11 PRM10

PRM01

PRM00

Count Clock [Hz] Resolution [ s]

0.25

0.5

1.0

2.0

4.0

Others

CLK

= 16 MHz )

Remark

CLK

: internal system clock

CHAPTER 7 TIMER 0

162

7.4 Operation of Timer Register 0 (TM0)

7.4.1 Basic operation

Timer 0 counts up by using the count clock specified by the prescaler mode register (PRM).

Counting is enabled or disabled by the CE0 bit of the timer mode control register (TMC). When the CE0 bit is set (1)

by software, TM0 is set to 0001H at the first count clock, and starts counting up. When the CE0 bit is cleared (0) by software,

TM0 is immediately cleared to 0000H, and stops the capture operation and generation of the match signal.

If the CE0 bit is set (1) while it has been already set (1), TM0 is not cleared but continues counting.

If a count clock is input when TM0 reaches FFFFH, TM0 is cleared to 0000H, and an overflow interrupt (INTOV0) occurs,

but TM0 continues counting.

When RESET is input TM0 is cleared to 0000H and stops counting.

CHAPTER 7 TIMER 0

163

Figure 7-6. Basic Operation of Timer Register 0 (TM0)

(a) Count started

count stopped

count started

TM0

CE0

FFH

100H

101H

Count Started

CE0

Count Stopped

CE0

Count Started

CE0

Count Clock

TM0

INTOV0

Interrupt Request

FFFEH FFFFH

Count Clock

(c) Operation when TM0 = FFFFH

TM0

CE0

Count Started

CE0

Rewritten

CE0

Count Clock

(b) When "1" is written to the CE0 bit again after the count starts

CHAPTER 7 TIMER 0

164

7.4.2 Clear operation

Timer register 0 (TM0) is cleared by clearing (0) the CE0 bit of the timer mode control register (TMC). TM0 is cleared

as soon as the CE0 bit has been cleared (0).

Figure 7-7. Clear Operation of Timer Register 0 (TM0)

(a) Basic operation

TM0

CE0

Count Clock

n-1

(c) Restart after count clock input after clearance

TM0

CE0

Count Clock

n-1

If the CE0 bit is set (1) from this count clock onward, the count starts from 1
on the count clock after the CE0 bit is set (1).

(b) Restart before count clock input after clearance

TM0

CE0

Count Clock

n-1

If the CE0 bit is set (1) before this count clock, the count starts from 1 on the count clock.

CHAPTER 7 TIMER 0

165

7.5 Operation of Capture/Compare Register

7.5.1 Compare operation

Timer 0 performs a compare operation by comparing the value set to a capture/compare register (CC00 to CC03)

specified as a compare register with the count value of a timer register 0 (TM0).

If the count value of TM0 matches with the value set in advance to CC0n (n = 0 to 3) as a result of counting by TM0,

the timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal

(INTCC0n: n = 0 to 3).

Table 7-3. Interrupt Request Signal from Compare Register (timer 0)

Compare Register

Interrupt Request Signal

CC00

INTCC00

CC01

INTCC01

CC02

INTCC02

CC03

INTCC03

Remark

CC00 through CC03 are capture/compare

registers. Whether these registers are used

as capture registers or compare registers is

specified by the timer unit mode register 0

(TUM0).

Timer 0 has four timer output pins (TO00 through TO03). Table 7-4 shows the operation mode of each of these pins

(for details, refer to 7.6 Basic Operation of Output Control Circuit).

Table 7-4. Operation Mode of Timer Output Pin (timer 0)

Timer Output Pin

Output Operation Mode

Specification of Operation Mode

TO00

Toggle

Set/reset

TOM00 bit of TUM0

TO01

Toggle

TO02

Toggle

Set/reset

TOM02 bit of TUM0

TO03

Toggle

CHAPTER 7 TIMER 0

166

Figure 7-8. Compare Operation (timer 0)

INTCC00

Interrupt Request

TM0
Count Value

FFFFH

Count Started

CE0

CC00 Value

CC01 Value

FFFFH

CC00 Value

CC01 Value

INTCC01

Interrupt Request

TO00 Pin Output

ENTO00 = 1

ALV00 = 1

INTOV0

Interrupt Request

Match

TO01 Pin Output

ENTO01 = 1

ALV01 = 0

Inactive Level

CHAPTER 7 TIMER 0

167

7.5.2 Capture operation

In synchronization with an external trigger, timer 0 also performs a capture operation that captures and retains the count

value of timer register 0 (TM0) to a capture register.

As an external trigger, the valid edge detected from an external interrupt request input pin (INTP0 to INTP3) is used

(capture trigger). In synchronization with this capture trigger, the count value of TM0 is captured to a capture/compare

The contents of CC00 through CC03 are retained until the following capture triggers each corresponding to CC00 to CC03

are generated.

Table 7-5. Capture Trigger Signal to Capture Register (timer 0)

Capture Register

Capture Trigger Signal

CC00

INTP0

CC01

INTP1

CC02

INTP2

CC03

INTP3

Remark

CC00 through CC03 are capture/compare

registers. Whether these registers are used

as capture registers or compare registers is

specified by the timer unit mode register 0

(TUM0).

The valid edge of the capture trigger is specified by external interrupt mode registers (INTM0 and INTM1) If the capture

trigger is specified so that both the rising and falling edges are valid, the width of an externally input pulse can be measured.

If the capture trigger is generated with either of the edges specified as valid, the cycle of an input pulse can be measured.

CHAPTER 7 TIMER 0

168

Figure 7-9. Capture Operation (timer 0)

TM0
Count Value

INTP1

Pin Input

INTP1

Interrupt Request

Capture Register

(CC01)

INTP0

Pin Input

INTP0

Interrupt Request

Capture Register

(CC00)

INTOV0

Interrupt Request

FFFFH

Count Started
CE0

Remark

Dn: TM0 count value (n = 0, 1, 2, ... )

CHAPTER 7 TIMER 0

169

7.6 Basic Operation of Output Control Circuit

The output control circuit controls the levels of the timer output pins (TO00 through TO03) by using the match signals

from the compare registers (CC00 through CC03). The operation of the output control circuit is determined by the timer

output control register 0 (TOC0). Note that the TO01 and TO03 pin outputs can be used for toggle operation only. The

TO00 and TO02 pin outputs can be used for toggle or set/reset operation, according to the specification by the timer unit

mode register 0 (TUM0).

To output the signals TO00 through TO03 to pins, the corresponding pins must be set in the control mode by using the

port 2 mode control register (PMC2).

Table 7-6. Toggle Signal of Timer Output Pin (timer 0)

Timer Output

Toggle Signal

TO00

INTCC00

TO01

INTCC01

TO02

INTCC02

TO03

INTCC03

Table 7-7. Set/Reset Signal of Timer Output Pin (timer 0)

Timer Output

Set Signal

Reset Signal

TO00

INTCC00

INTCC01

TO02

INTCC02

INTCC03

CHAPTER 7 TIMER 0

170

Figure 7-10. Block Diagram of Timer Output Operation of Timer 0

INTCC00

INTCC01

Selector

TO00

TO01

INTCC02

INTCC03

Selector

TO02

TO03

CHAPTER 7 TIMER 0

171

7.6.1 Basic operation

By setting (1) the ENTO0n (n = 0 to 3) bit of the timer output control register 0 (TOC0), a pulse can be output from the

TO0n (n = 0 to 3) pin.

Clearing (0) ENTO0n bit sets the TO0n to a fixed level. The fixed level is determined by the ALV0n (n = 0 to 3) bit of

the TOC0. The level is high when ALV0n bit is 0, and low when 1.

7.6.2 Toggle output

Toggle output is an operating mode in which the output level is inverted each time the compare register (CC0n: n = 0

to 3) value coincides with the timer register 0 (TM0) value. The output level of timer output (TO0n: n = 0 to 3) is inverted

by a match between CC0n and TM0.

When timer 0 is stopped by clearing (0) the CE0 bit of the timer mode control register (TMC), the output level at the time

it was stopped is retained as is.

Figure 7-11. Operation of Toggle Output

ENTO00

TM0
Count Value

FFFFH

CC00 Value

CC01 Value

FFFFH

CC00 Value

CC01 Value

FFFFH

CC00 Value

CC01 Value

FFFFH

CC00 Value

CC01 Value

FFFFH

TO00 Output

(ALV00 = 1)

ENTO01

Instruction
Execution

Instruction

Execution

Instruction
Execution

TO01 Output

(ALV01 = 0)

CHAPTER 7 TIMER 0

172

Table 7-8. Toggle Output of TO00 through TO03 (f

CLK

= 16 MHz)

Count Clock

Minimum Pulse Width

Note

Maximum Pulse Width

CLK

4/f

CLK

(0.25

4/f

CLK

(16.4 ms)

CLK

8/f

CLK

(0.5

8/f

CLK

(32.8 ms)

CLK

/16

16/f

CLK

(1.0

16/f

CLK

(65.5 ms)

CLK

/32

32/f

CLK

(2.0

32/f

CLK

(131 ms)

CLK

/64

64/f

CLK

(4.0

64/f

CLK

(262 ms)

Note

The minimum interval time is limited by the data transfer processing time.

Consider the interrupt processing time or macro service processing time

used (refer to Table 14-11 Interrupt Acceptance Processing Time and

Table 14-12 Macro Service Processing Time).

7.6.3 Set/reset output

The set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare

If CC00 = CC01 and CC02 = CC03, interrupt requests are simultaneously generated, and timer outputs (TO00 and TO02)

are used as ALV00 and ALV02.

When timer 0 is stopped by clearing (0) the CE0 bit of the timer mode control register (TMC), the output level at which

the timer stops is retained as is.

Figure 7-12. Operation of Set/Reset Output (timer 0)

TM0
Count Value

INTCC00

Interrupt Request

INTCC01

Interrupt Request

TO00 Pin

ENTO00
ALV00
TOM00

CC00

CC01

FFFFH

CC00

CC01

CC00

Count Started

CE0

CHAPTER 7 TIMER 0

173

7.7 Examples of Use

7.7.1 Operation as interval timer

When timer register 0 (TM0) is made free-running and a fixed value is added to the compare register (CC0n: n = 0 to

3) in the interrupt processing routine, TM0 operates as an interval timer with the added fixed value as the cycle (refer to

Figure 7-13).

This interval timer can count within the range shown in Table 7-1 (internal system clock f

CLK

= 16 MHz).

Since TM0 has four capture compare registers, four interval timers with different cycles can be constructed.

Taking an example where compare register CC00 is used, the control register settings are shown in Figure 7-14, the

setting procedure in Figure 7-15, and the processing in the interrupt processing routine in Figure 7-16.

Figure 7-13. Timing of Interval Timer Operation

Remark

Interval time = n

x/f

CLK

FFFFH

x = 4, 8, 16, 32, 64

y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro

service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12

Macro Service Processing Time).

MOD(2n)

INTCC00

Interrupt Request

TM0
Count Value

FFFFH

Compare Register

(CC00)

Timer Started

MOD(3n)

MOD(4n)

FFFFH

MOD(2n)

MOD(3n)

Interval

Rewritten by
Interrupt Program

CHAPTER 7 TIMER 0

174

Figure 7-14. Set Contents of Control Register for Interval Timer Operation

(a) Prescaler mode register (PRM)

(b) Timer unit mode register 0 (TUM0)

PRM02 PRM01 PRM00

PRM

Specifies count clock

CLK

/x ; x = 4, 8, 16, 32, 64)

TUM0

Specifies CC00 as compare register

Specifies TO00 for toggle output

: don't care

CHAPTER 7 TIMER 0

175

Figure 7-15. Setting Procedure of Interval Timer Operation

Interval timer

Sets count value to CC00

CC00

Count starts

CE0

INTCC00 interrupt

; Sets bit 3 of TMC to 1

Sets PRM

Sets TUM0

Figure 7-16. Interrupt Request Processing of Interval Timer Operation

INTCC00 interrupt

Calculates timer value at which

interrupt is generated next time

CC00

CC00 + n

Other interrupt processing program

RETI

CHAPTER 7 TIMER 0

176

7.7.2 Pulse width measurement operation

In pulse width measurement, the high-level or low-level width of external pulses input to the external interrupt request

input pin (INTP0 through INTP3) is measured.

When the sampling clock is f

CLK

both the high-level and low-level widths of pulses input to the INTPn (n = 0 to 3) pin must

be at least 4 system clocks (0.25

s: f

CLK

= 16 MHz); if shorter than this, the valid edge will not be detected and a capture

operation will not be performed.

When a pulse width is measured, the pulse width in a range shown in Table 7-2 can be measured (f

CLK

= 16 MHz). How

a pulse width is measured is explained below where the INTP3 pin is used as an external input pin.

As shown in Figure 7-17, the timer register 0 (TM0) value being counted is fetched into the capture register (CC03) in

synchronization with a valid edge (specified as both rising and falling edges) in the INTP3 pin input, and held there. The

pulse width is obtained from the product of the difference between the TM0 count value (Dn) fetched into and held in the

CC03 on detection of the nth valid edge and the count value (D

n-1

) fetched and held on detection of valid edge n-1, and

the number of count clocks (x/f

CLK

; x = 4, 8, 16, 32, 64).

The control register settings are shown in Figure 7-18, the setting procedure in Figure 7-19, and the processing at interrupt

processing routine in Figure 7-20.

Figure 7-17. Timing of Pulse Width Measurement

Remark

Dn: TM0 count value (n = 0, 1, 2, ...)

x = 4, 8, 16, 32, 64

INTP3

External Input Signal

INTP3

Interrupt Request

TM0
Count Value

FFFFH

Capture Register

(CC03)

INTOV0

Interrupt Request

Count Started

FFFFH

Capture

(D1_D0)

x/f

CLK

(10000H_D1+
D2)

x/f

CLK

(D3_D2)

x/f

CLK

CHAPTER 7 TIMER 0

177

Figure 7-18. Control Register Settings for Pulse Width Measurement

(a) Prescaler mode register (PRM)

(b) Timer unit mode register 0 (TUM0)

(c) External interrupt mode register 1 (INTM1)

PRM02 PRM01 PRM00

PRM

Specifies count clock

CLK

/x ; x = 4, 8, 16, 32, 64)

TUM0

Specifies CC03 as capture register

INTM1

: Don

t care

Specifies both rising & falling edges

as INTP3 input valid edges

CHAPTER 7 TIMER 0

178

Figure 7-19. Pulse Width Measurement Setting Procedure

Figure 7-20. Interrupt Request Processing that Calculates Pulse Width

INTP3 Interrupt

Calculate pulse width

= CC03 _ X

Store capture value in memory

n+1

CC03

RETI

Pulse Width Measurement

Set INTM1,
Set MK0L

Initialize capture value buffer memory

Start Count

CE0

Enable Interrupt

; Specify both edges as
INTP3 input valid edges,
release interrupt masking

INTP3 Interrupt

; Set 1 to bit 3 of TMC

Set PRM

Set TUM

CHAPTER 7 TIMER 0

179

7.8 Cautions

(1) The prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer

4). If one of the timers sets the CE bit to "1", the time base starts counting. If another timer sets the CE bit to "1"

while one timer is operating, the first count clock of the timer may be shortened because the time base has already

started counting.

For example, when using timer/counter 0 as an interval timer, the first interval time is shortened by up to 1 count

clock. The second and those that follow are at the specified interval.

Figure 7-21. Operation When Counting Is Started

Count Clock

TM0

CE0

Count Start Command (CE0

by Software

(2) While timer 0 is operating (while the CE0 bit of the timer mode control register (TMC) is set), malfunctioning may

occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence

in a contention the change in the hardware functions due to rewriting the register, or the change in the status because

of the function before rewriting.

Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following

registers.

Timer unit mode register 0 (TUM0)

Timer output control register 0 (TOC0)

Prescaler mode register (PRM)

CHAPTER 7 TIMER 0

180

(3) If the contents of the compare register (CC0n: n = 0 to 3) match with those of TM0 operation when an instruction

that stops timer register 0 (TM0) operation operation is executed, the counting operation of TM0 stops, but an

interrupt request is generated.

In order not to generate the interrupt when stopping the operation of TM0, mask the interrupt in advance by using

the interrupt mask register before stopping TM0.

Example

Program that may generate interrupt request Program that does not generate interrupt request

CLR1

CE0

Interrupt request

MK0L, #78H

Disables interrupt

MK0L, #78H

from timer 0

CLR1

CE0

from timer 0

occurs between

CLR1

PIF0

Clears interrupt request

these instructions

CLR1

PIF1

flag from timer 0

CLR1

PIF2

CLR1

PIF3

(4) Match between timer register 0 (TM0) and compare register (CC0n: n = 0 to 3) is detected only when TM0 is

incremented. Therefore, the interrupt request is not generated even if the same value as TM0 is written to CC0n,

and the timer output (TO0n: n = 0 to 3) does not change.

(5) When the compare register (CC00 to CC03) is set to 0000H, the compare operation is performed after counting by

TM0. Therefore, the match interrupt (INTCC00 to INTCC03) does not occur immediately after counting has been

started. If CC0n (n = 0 to 3) is set to 0000H, TM0 counts up to FFFFH, the timer overflows, and match interrupt

INTCC0n (n = 0 to 3) occurs.

Figure 7-22. Operation When Compare Register (CC00 to CC03) Is Set to 0000H

.
.
.

Interrupt Occurred

Count Started

FFFFH

0000H

Match

Count Clock

TM0

CE0

CC0n

INTCC0n

Remark

n = 0 to 3

CHAPTER 7 TIMER 0

181

(6) If the timer output is enabled when the active level is changed, the output level of pins may change momentarily.

To prevent this, enable the timer output after the active level have been changed.

(7) To change the active level specification (ALV0n bit (n = 0 to 3) of the timer output control register 0 (TOC0)), change

the active level specification after the timer output of the corresponding timer output pins has been disabled.

[MEMO]

182

CHAPTER 8 TIMER 1

8.1 Function

Timer 1 is a 16-bit timer.

In addition to a function as an interval timer, this timer has a toggle and set/reset function as timer output.

When used as an interval timer, timer 1 generates an internal interrupt at interval determined in advance.

Table 8-1. Interval Time of Timer 1

Minimum Interval Time

Maximum Interval Time

Resolution

8/f

CLK

(0.5

8/f

CLK

(32.8 ms)

8/f

CLK

(0.5

16/f

CLK

(1.0

16/f

CLK

(65.5 ms)

16/f

CLK

(1.0

32/f

CLK

(2.0

32/f

CLK

(131 ms)

32/f

CLK

(2.0

64/f

CLK

(4.0

64/f

CLK

(262 ms)

64/f

CLK

(4.0

128/f

CLK

(8.0

128/f

CLK

(524 ms)

128/f

CLK

(8.0

( ): at f

CLK

= 16 MHz

8.2 Configuration

Timer 1 consists of the following registers:

Timer register (TM1)

Compare register (CM1n)

2 (n = 0, 1)

Figure 8-1 shows the block diagram of timer 1.

183

CHAPTER 8 TIMER 1

184

Figure 8-1. Block Diagram of Timer 1

Internal Bus

Compare Register 10

(CM10)

Match

1/8

TOM10 CLR1

ENTO11 ALV11 ENTO10 ALV10

Timer Unit Mode
Register 0
(TUM0)

Timer Output Control
Register 1 (TOC1)

1/8

Output
Control
Circuit

TO10

INTCM10

TO11

INTCM11

RESET

INTOV1

CE1

1/8

Timer Mode Control
Register (TMC)

1/8

Compare Register 11

(CM11)

Match

Timer Register

(TM1)

Overflow

Clear

Selector

PRM12 PRM11 PRM10

CLK

/128

CLK

/64

CLK

/32

CLK

/16

CLK

Prescaler

CLK

Prescaler Mode
Register (PRM)

CHAPTER 8 TIMER 1

185

(1) Timer register 1 (TM1)

TM1 is a timer register that counts up the count clock specified by the prescaler mode register (PRM).

Counting of this timer register is enabled or disabled by the timer mode control register (TMC).

The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM1 is cleared

to 0000H and stops counting.

(2) Compare registers (CM10, CM11)

CM1n (n = 0, 1) is a 16-bit register that holds the value determining the cycle of the interval timer operation.

When the contents of CM1n matches with the contents of TM1, an interrupt request (INTCM1n: n = 0, 1) and a timer

output control signal are generated. The count value of TM1 can be cleared when its value matches with the contents

of CM10.

These compare registers can be read or written by using 16-bit manipulation instructions. When RESET is input,

their contents are undefined.

(3) Output control circuit

When the contents of CM1n (n = 0, 1) and the contents of TM1 match, the timer output can be inverted. A square

wave can be output from a timer output pin (TO10, TO11) if so specified by the timer output control register 1 (TOC1).

The TO10 pin can also output a set and reset signals if so specified by the timer unit mode register 0 (TUM0).

The timer output can be enabled or disabled by TOC1. When the timer output is disabled, a fixed level is output

to the TO1n (n = 0, 1) pin (the output level is fixed by TOC1).

(4) Prescaler

The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler

is selected by the selector, and TM1 performs the count operation by using this clock as a count clock.

(5) Selector

The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM1.

CHAPTER 8 TIMER 1

186

8.3 Timer 1 Control Register

(1) Timer unit mode register 0 (TUM0)

TUM0 is a register that specifies the output mode of the timer output pins (TO00, TO02, and TO10) of timers 0 and

1, controls the clear operation of the timer register 1 (TM1), and specifies the operations of the capture/compare

registers (CC00 through CC03) of timer 0.

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

8-2 shows the format of TUM0.

When RESET is input, the value of TUM0 is cleared to 00H.

Figure 8-2. Format of Timer Unit Mode Register 0 (TUM0)

TOM10 CLR1 TOM02 TOM00 CMS03 CMS02 CMS01 CMS00

TOM10

Specifies Output Mode of TO10 Pin

Toggle output

Set/reset output

TUM0

Address : 0FF30H On reset : 00H R/W

TOM0n Specifies Output Mode of TO0n Pin (n = 0, 2)

(refer to Figure 7-2).

CLR1

Controls Clear Operation of TM1 by match with CM10

Disabled (free running mode)

Enabled (interval timer mode)

CMS0n Specifies Operation of CC0n (n = 0 to 3)

(refer to Figure 7-2).

CHAPTER 8 TIMER 1

187

(2) Timer mode control register (TMC)

TMC is a register that controls the count operation of timer registers 0 and 1 (TM0 and TM1).

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

8-3 shows the format of TMC.

When RESET is input, the value of this register is cleared to 00H.

Figure 8-3. Format of Timer Mode Control Register (TMC)

CE1

CE0

CE1

Controls Count Operation of TM1

Clears and stops counting

Enables counting operation

TMC

Address : 0FF31H On reset : 00H R/W

CE0

Controls Count Operation of TM0

(refer to Figure 7-3).

(3) Timer output control register 1 (TOC1)

TOC1 is a register that specifies the operation and active level of the timer output pins (TO10, TO11) of timer 1.

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

8-4 shows the format of TOC1.

When RESET is input, the value of this register is cleared to 00H.

Figure 8-4. Format of Timer Output Control Register 1 (TOC1)

ENTO11 ALV11 ENTO10 ALV10

ENTO1n

Specifies Operation of TO1n Pin (n = 0, 1)

Outputs ALV1n

Enables pulse output

TOC1

Address : 0FF33H On reset : 00H R/W

ALV1n

Specifies Active Level of TO1n Pin (n = 0, 1)

Low level

High level

CHAPTER 8 TIMER 1

188

(4) Prescaler mode register (PRM)

PRM is a register that specifies the count clock of timer registers 0 and 1 (TM0, TM1).

This register can be read or written by using an 8-bit manipulation instruction. Figure 8-5 shows the format of PRM.

When RESET is input, the value of this register is cleared to 00H.

Figure 8-5. Format of Prescaler Mode Register (PRM)

Remark

CLK

: internal system clock

Address : 0FF38H On reset : 00H R/W

PRM12 PRM11 PRM10

PRM02 PRM01 PRM00

PRM

PRM02

Specifies Count Clock of TM0

(refer to Figure 7-5).

PRM12

Specifies Count Clock of TM1

CLK

/16

CLK

/32

CLK

/64

CLK

/128

Setting prohibited

PRM01 PRM00

PRM11

PRM10

Count Clock [Hz] Resolution [ s]

0.5

1.0

2.0

4.0

8.0

Others

CLK

= 16 MHz)

CHAPTER 8 TIMER 1

189

8.4 Operation of Timer Register 1 (TM1)

8.4.1 Basic operation

Timer 1 counts up by using the count clock specified by the prescaler mode register (PRM).

Counting is enabled or disabled by the CE1 bit of the timer mode control register (TMC). When the CE1 bit is set (1)

by software, TM1 is set to 0001H at the first count clock, and starts counting up. When the CE1 bit is cleared (0) by software,

TM1 is immediately cleared to 0000H, and stops the generation of the match signal.

If the CE1 bit is set (1) while it has been already set (1), TM1 is not cleared but continues counting.

If a count clock is input when TM1 reaches FFFFH, TM1 is cleared to 0000H, and an overflow interrupt (INTOV1) occurs.

When RESET is input, TM1 is cleared to 0000H and stops counting.

CHAPTER 8 TIMER 1

190

Figure 8-6. Basic Operation of Timer Register 1 (TM1)

(a) Count started

count stopped

count started

(c) Operation when TM1 = FFFFH

(b) When "1" is written to the CE1 bit again after the count starts

TM1

CE1

Count Started

CE1

Rewritten

CE1

Count Clock

TM1

CE1

FFH 100H

101H

Count Started

CE1

Count Stopped

CE1

Count Started

CE1

Count Clock

TM1

INTOV1

Interrupt Request

FFFEH FFFFH

Count Clock

CHAPTER 8 TIMER 1

191

8.4.2 Clear operation

(1) Clear operation after match with compare register

Timer register 1 (TM1) can be cleared automatically after a match with the compare register (CM10). When a

clearance source arises, TM1 is cleared to 000H on the next count clock. Therefore, even if a clearance source arises,

the value at the point at which the clearance source arose is retained until the next count clock arrives.

Figure 8-7. TM1 Clear Operation by Match with Compare Register (CM10)

TM1

Compare Register

(CM10)

Cleared Here

Count Clock

TM1 and CM10 Match

n_1

(2) Clear operation by CE1 bit of timer mode control register (TMC)

Timer register 1 (TM1) is also cleared when the CE1 bit of TMC is cleared (0) by software. The clear operation is

performed Iimmediately after the clearance (0) of the CE1 bit.

CHAPTER 8 TIMER 1

192

Figure 8-8. TM1 Clear Operation When CE1 Bit is Cleared (0)

(a) Basic operation

TM1

CE1

Count Clock

n_1

(b) Restart before count clock is input after clearance

(c) Restart after count clock is input after clearance

TM1

CE1

Count Clock

n_1

If the CE1 bit is set (1) from this count clock onward, the count clock starts counting
from 1 after the CE1 bit is set (1).

TM1

CE1

Count Clock

n_1

If the CE1 bit is set (1) before this count clock, this count clock starts counting from 1.

CHAPTER 8 TIMER 1

193

8.5 Operation of Compare Register

Timer 1 performs a compare operation by comparing the value set to a compare register (CM10, CM11) specified as

a compare register with the count value of a timer register 1 (TM1).

If the count value of TM1 matches with the value set in advance to CM1n (n = 0, 1) as a result of counting by TM1, the

timer sends a match signal to the output control circuit, and at the same time, generates an interrupt request signal

(INTCM10, INTCM11).

After the value of TM1 has matched with the value of CM10, the count value of TM1 can be cleared, so that TM1 can

be used as an interval timer that repeatedly counts the value set to CM10.

Table 8-2. Interrupt Request Signal from Compare Register (timer 1)

Compare Register

Interrupt Request Signal

CM10

INTCM10

CM11

INTCM11

Timer 1 has two timer output pins (TO10, TO11). Table 8-3 shows the operation mode of each of these pins (for details,

refer to 8.6 Basic Operation of Output Control Circuit).

Table 8-3. Operation Mode of Timer Output Pin (timer 1)

Timer Output Pin

Output Operation Mode

Specification of Operation Mode

TO10

Toggle

Set/reset

TUM10 bit of TUM0

TO11

Toggle

CHAPTER 8 TIMER 1

194

Figure 8-9. Compare Operation (timer 1)

INTCM10

Interrupt Request

TM1
Count value

FFFFH

Count Started

CE1

CM10 Value

CM11 Value

FFFFH

CM10 Value

CM11 Value

INTCM11

Interrupt Request

TO10 Pin Output

ENTO10 = 1

ALV10 = 1

INTOV1

Interrupt Request

Match

TO11 Pin Output

ENTO11 = 1

ALV11 = 0

Inactive Level

Remark

CLR1 = 0

CHAPTER 8 TIMER 1

195

Figure 8-10. Clearing TM1 after Detection of Match

INTCM11

Interrupt Request

TM1
Count Value

FFFFH

Count Started
CE1

CLR1

INTCM10

Interrupt Request

TO11 Pin Output

ENTO11

ALV11

INTOV1

Interrupt Request

TO10 Pin Output

ENTO10

ALV10

Inactive Level

CM11

CM10

Inactive Level

Count Disabled
CE1

Count
Started
CE1

CLR1

Cleared

CHAPTER 8 TIMER 1

196

8.6 Basic Operation of Output Control Circuit

The output control circuit controls the levels of the timer output pins (TO10, TO11) by using the coincidence signals from

the compare registers (CM10, CM11). The operation of the output control circuit is determined by the timer output control

for toggle or set/reset operation, according to the specification by the timer unit mode register 0 (TUM0).

To output the TO10 and TO11 signals to pins, the corresponding pins must be set in the control mode by using the port

3 mode control register (PMC3).

Table 8-4. Toggle Signal of Timer Output Pin (timer 1)

Timer Output

Toggle Signal

TO10

INTCM10

TO11

INTCM11

Table 8-5. Set/Reset Signal of Timer Output Pin (timer 1)

Timer Output

Set Signal

Reset Signal

TO10

INTCM10

INTCM11

Figure 8-11. Block Diagram of Timer Output Operation of Timer 1

INTCM10

INTCM11

Selector

TO10

TO11

CHAPTER 8 TIMER 1

197

8.6.1 Basic operation

By setting (1) the ENTO1n (n = 0, 1) bit of the timer output control register 1 (TOC1), a pulse can be output from the

TO1n (n = 0, 1) pin.

By clearing (0) the ENTO1n bit, the level of TO1n is fixed. The level to which TO1n is fixed is determined by the ALV1n

(n = 0, 1) bit of TOC1. When the ALV1n bit is 0, TO1n is fixed to the high level; when ALV1n bit is 1, it is fixed to the low

level.

8.6.2 Toggle output

Toggle output is an operation mode in which the output level is inverted each time the value of the compare register

(CM10, CM11) matches with the value of timer register 1 (TM1). The output level of the timer output TO10 is inverted when

the value of CM10 matches with TM1, and the output level of TO11 is inverted when the value of CM11 matches with the

value of TM1.

When timer 1 is stopped by clearing (0) the CE1 bit of the timer mode control register (TMC), the output level is retained

as is.

Figure 8-12. Operation of Toggle Output

ENTO10

TM1
Count Value

FFFFH

Instruction

Execution

CM10 Value

CM11 Value

FFFFH

CM10 Value

CM11 Value

FFFFH

CM10 Value

CM11 Value

FFFFH

CM10 Value

CM11 Value

FFFFH

TO10 Output

(ALV10 = 1)

ENTO11

TO11 Output

(ALV11 = 0)

Instruction

Execution

Instruction

Execution

Instruction

Execution

Table 8-6. Toggle Output of TO10 and TO11 (f

CLK

= 16 MHz)

Count Clock

Minimum Pulse Width

Maximum Pulse Width

CLK

8/f

CLK

(0.5

8/f

CLK

(32.8 ms)

CLK

/16

16/f

CLK

(1.0

16/f

CLK

(65.5 ms)

CLK

/32

32/f

CLK

(2.0

32/f

CLK

(131 ms)

CLK

/64

64/f

CLK

(4.0

64/f

CLK

(262 ms)

CLK

/128

128/f

CLK

(8.0

128/f

CLK

(524 ms)

CHAPTER 8 TIMER 1

198

8.6.3 Set/reset output

The set/reset output is an operation mode in which the timer output is set or reset each time the value of the compare

If CM10 = CM11, interrupt requests are simultaneously generated, and timer output (TO10) is used as ALV10.

When timer 1 is stopped by clearing (0) the CE1 bit of the timer mode control register (TMC), the output level at which

the timer stops is retained as is.

Figure 8-13. Operation of Set/Reset Output (timer 1)

TM1
Count Value

INTCM10

Interrupt Request

INTCM11

Interrupt Request

TO10 pin

ENTO10
ALV10
TOM10

CM10

CM11

FFFFH

CM10

CM11

CM10

Count Started

CE1

CHAPTER 8 TIMER 1

199

8.7 Examples of Use

8.7.1 Operation as interval timer (1)

When timer register 1 (TM1) is made free-running and a fixed value is added to the compare register (CM1n: n = 0, 1)

in the interrupt processing routine, TM1 operates as an interval timer with the added fixed value as the cycle (refer to Figure

8-14).

This interval timer can count in the range shown in Table 8-1 (internal system clock f

CLK

= 16 MHz).

Because TM1 has two compare registers, interval timers of two types of cycles can be created.

Figure 8-15 shows the set contents of the control registers, Figure 8-16 shows how to set the registers, and Figure 8-

17 shows the processing in an interrupt routine, where compare register CM10 is used.

Figure 8-14. Timing of Interval Timer Operation (1)

MOD(2n)

INTCM10

Interrupt Request

TM1
Count Value

FFFFH

Compare Register

(CM10)

Timer Started

MOD(3n)

MOD(4n)

FFFFH

MOD(2n)

MOD(3n)

Interval

Rewrittern by
Interrupt Program

Remark

Interval time = n

x/f

CLK

FFFFH

x = 4, 8, 16, 32, 64

y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro

service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12

Macro Service Processing Time).

CHAPTER 8 TIMER 1

200

Figure 8-15. Control Register Settings for Interval Timer Operation (1)

(a) Prescaler mode register (PRM)

(b) Timer unit mode register 0 (TUM0)

TUM0

Disables TM1 clearing by match of CM10 and TM1

Specifies TO10 for toggle output

don't care

PRM

PRM12

PRM11

PRM10

Specifies count clock

CLK

/x ; x = 8, 16, 32, 64, 128)

CHAPTER 8 TIMER 1

201

Figure 8-16. Setting Procedure of Interval Timer Operation (1)

Interval Timer (1)

Set count value to CM10

CM10

Start Count

CE1

INTCM10 Interrupt

; Set 1 to bit 7 of TMC

Set PRM

Set TUM0

Figure 8-17. Interrupt Request Processing of Interval Timer Operation (1)

INTCM10 Interrupt

Calculate timer value that will

generate next interrupt

CM10

CM10 + n

Other Interrupt Processing Program

RETI

CHAPTER 8 TIMER 1

202

8.7.2 Operation as interval timer (2)

TM1 operates as an interval timer that generates interrupts repeatedly with the preset count time as the interval (refer

to Figure 8-18).

This interval timer can count in the range shown in Table 8-1 (internal system clock f

CLK

= 16 MHz)

The control register settings are shown in Figure 8-19, and the setting procedure in Figure 8-20.

Figure 8-18. Timing of Interval Timer Operation (2)

Compare Register

(CM10)

INTCM10

Interrupt Request

TM1
Count Value

Count Started

Cleared

Interval

Match

Interrupt Acknowledged

Interval

Remark

Interval = (n+1)

x/f

CLK

FFFFH

x = 8, 16, 32, 64, 128

CHAPTER 8 TIMER 1

203

Figure 8-19. Control Register Settings for Interval Timer Operation (2)

(a) Prescaler mode register (PRM)

(b) Timer unit mode register 0 (TUM0)

Interval Timer (2)

Set count value to CM10

CM10

INTCM10 Interrupt

; Set 1 to bit 7 of TMC

Set PRM

Start Count

CE1

Set TUM0

Figure 8-20. Setting Procedure of Interval Timer Operation (2)

TUM0

Clears TM1 by match of CM10 and TM1

Specifies TO10 for toggle output

don't care

PRM

PRM12

PRM11

PRM10

Specifies count clock

CLK

/x ; x = 8, 16, 32, 64, 128)

CHAPTER 8 TIMER 1

204

8.8 Cautions

(1) The prescaler uses one time base in common with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer

4). If one of the timers sets the CE bit to "1", the time base starts counting. If another timer sets the CE bit to "1"

while one timer operates, the first count clock of the timer may be shortened because the time base has already

started counting.

For example, when using timer/counter 1 as an interval timer, the first interval time is shortened by up to 1 count

clock. The second and those that follow are at the specified interval.

Figure 8-21. Operation When Counting Is Started

Count Clock

TM1

CE1

Count Start Command (CE1

by Software

(2) While timer 1 is operating (while the CE1 bit of the timer mode control register (TMC) is set), malfunctioning may

occur if the contents of the following registers are rewritten. This is because it is undefined which takes precedence

in a contention, the change in the hardware functions due to rewriting the register, or the change in the status because

of the function before rewriting.

Therefore, be sure to stop the counter operation for the sake of safety before rewriting the contents of the following

registers.

Timer unit mode register 0 (TUM0)

Timer output control register 1 (TOC1)

Prescaler mode register (PRM)

CHAPTER 8 TIMER 1

205

(3) If the contents of the compare register (CM1n: n = 0, 1) matches with those of TM1 when an instruction that stops

timer register 1 (TM1) operation is executed, the counting operation of TM1 stops, but an interrupt request is

generated.

In order not to generate the interrupt when stopping the operation of TM1, mask the interrupt in advance by using

the interrupt mask register before stopping TM1.

Example

Program that may generate interrupt request

Program that does not generate interrupt request

CLR1 CE1

MK0H, #0CH

CLR1

CE1

CLR1

CMIF10

CLR1

CMIF11

(4) A match between the timer register 1 (TM1) and compare register (CM1n: n = 0, 1) is detected only when TM1 is

incremented. Therefore, the interrupt request is not generated even if the same value as TM1 is written to CM1n,

and the timer output (TO1n: n = 0, 1) does not change.

(5) When the compare register (CM10, CM11) is set to 0000H, the compare operation is performed after counting by

TM1. Therefore, the interrupt due to a match (INTCM10, INTCM11) does not occur immediately after counting has

been started. If CM1n (n = 0, 1) is set to 0000H, TM1 counts up to FFFFH, the timer overflows, and the interrupt

due to a match INTCM1n (n = 0, 1) occurs.

Interrupt request

from timer 1 occurs

between these

instructions

Disables interrupt

from timer 1

Clears interrupt request

flag from timer 1

···

CHAPTER 8 TIMER 1

206

Figure 8-22. Operation When Compare Register (CM10, CM11) Is Set to 0000H

(a) CM10

Interrupt Occurred

Count Started

Match

Cleared Cleared Cleared

0000H

Count Clock

TM1

CE1

CM10

INTCM10

FFFFH

(b) CM11

Interrupt Occurred

Count Started

Match

0000H

Count Clock

TM1

CE1

CM11

INTCM11

FFFFH

Interrupt Occurred

(6) If the timer output is enabled when the active level is changed, the output level of pins may change momentarily.

To prevent this, enable the timer output after the active level have been changed.

(7) To change the active level specification (ALV1n bit (n = 0, 1) of the timer output control register 1 (TOC1)), change

the active level specification after the timer output of the corresponding timer output pins has been disabled.

CHAPTER 9 TIMER 4

9.1 Function

Timer 4 is a 16-bit timer.

This timer functions as an interval timer.

When used as an interval timer, timer 4 generates an internal interrupt at a predetermined interval.

Table 9-1. Interval Time of Timer 4

Minimum Interval Time

Maximum Interval Time

Resolution

4/f

CLK

(0.25

4/f

CLK

(16.4 ms)

4/f

CLK

(0.25

8/f

CLK

(0.5

8/f

CLK

(32.8 ms)

8/f

CLK

(0.5

16/f

CLK

(1.0

16/f

CLK

(65.5 ms)

16/f

CLK

(1.0

32/f

CLK

(2.0

32/f

CLK

(131 ms)

32/f

CLK

(2.0

64/f

CLK

(4.0

64/f

CLK

(262 ms)

64/f

CLK

(4.0

( ): at f

CLK

= 16 MHz

9.2 Configuration

Timer 4 consists of the following registers:

Timer register (TM4)

Compare register (CM4n)

2 (n = 0, 1)

Figure 9-1 shows the block diagram of timer 4.

207

208

CHAPTER 9 TIMER 4

Figure 9-1. Block Diagram of Timer 4

Internal Bus

Compare Register 40

(CM40)

Match

Compare Register 41

(CM41)

Match

Timer Register 4

(TM4)

Clear

Overflow

RESET

1/8

CLR41

CE4

CLR40

Timer Mode Control
Register 4 (TMC4)

INTCM40

INTCM41

INTOV4

1/8

PRM41

PRM42

PRM40

Selector

CLK

/64

CLK

/32

CLK

/16

CLK

Prescaler

Prescaler Mode
Register 4 (PRM4)

CHAPTER 9 TIMER 4

209

(1) Timer register 4 (TM4)

TM4 is a timer register that counts up the count clock specified by the prescaler mode register 4 (PRM4).

Counting of this timer register is enabled or disabled by the timer mode control register 4 (TMC4).

The timer register can be only read by using a 16-bit manipulation instruction. When RESET is input, TM4 is cleared

to 0000H and stops counting.

(2) Compare registers (CM40, CM41)

CM4n (n = 0, 1) is a 16-bit register that holds the contents determining the cycle of the interval timer operation.

When the contents of CM4n matches with the contents of TM4, an interrupt request (INTCM4n: n = 0, 1) is generated.

The count value of TM4 can be cleared when its value matches with the contents of CM4n.

These compare registers can be read or written by using 16-bit manipulation instructions. When RESET is input,

their contents are undefined.

(3) Prescaler

The prescaler generates a count clock by dividing the internal system clock. The clock generated by the prescaler

is selected by the selector, and TM4 performs the count operation by using this clock as a count clock.

(4) Selector

The selector selects one of the five signals generated by dividing the internal system clock as the count clock of TM4.

210

CHAPTER 9 TIMER 4

9.3 Timer 4 Control Register

(1) Timer mode control register 4 (TMC4)

TMC 4 is a register that controls the count and clear operations of timer register 4 (TM4).

This register can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figure

9-2 shows the format of TMC4.

When RESET is input, the value of this register is cleared to 00H.

Figure 9-2. Format of Timer Mode Control Register 4 (TMC4)

CE4

CLR41 CLR40

CE4

Controls Count Operation of TM4

Clears and stops counting

Enables counting operation

TMC4

Address: 0FF37H On reset: 00H R/W

CLR41

Clear Operation of TM4 by Match with CM41

Disables (free running mode)

Enables (interval timer mode)

CLR40

Clear Operation of TM4 by Match with CM40

Disables (free running mode)

Enables (interval timer mode)

CHAPTER 9 TIMER 4

211

(2) Prescaler mode register 4 (PRM4)

PRM4 is a register that specifies the count clock of timer register 4 (TM4).

This register can be read or written by using an 8-bit manipulation instruction. Figure 9-3 shows the format of PRM4.

When RESET is input, the value of this register is cleared to 00H.

Figure 9-3. Format of Prescaler Mode Register 4 (PRM4)

Remark

CLK

: internal system clock

Address: 0FF3AH On reset: 00H R/W

PRM42 PRM41 PRM40

PRM4

PRM42

Specifies Count Clock of TM4.

CLK

/16

CLK

/32

CLK

/64

Setting prohibited

PRM41

PRM40

Count Clock [Hz] Resolution [ s]

0.25

0.5

1.0

2.0

4.0

Others

CLK

= 16 MHz)

212

CHAPTER 9 TIMER 4

9.4 Operation of Timer Register 4 (TM4)

9.4.1 Basic operation

Timer 4 counts up by using the count clock specified by the prescaler mode register 4 (PRM4).

Counting is enabled or disabled by the CE4 bit of the timer mode control register 4 (TMC4). When the CE4 bit is set

(1) by software, TM4 is set to 0001H at the first count clock, and starts counting up. When the CE4 bit is cleared (0) by

software, TM4 is immediately cleared to 0000H, and stops generation of the match signal.

If the CE4 bit is set (1) while it has been already set (1), TM4 is not cleared but continues counting.

If a count clock is input when TM4 reaches FFFFH, TM4 is cleared to 0000H, and an overflow interrupt (INTOV4) occurs.

When RESET is input, TM4 is cleared to 0000H and stops counting.

CHAPTER 9 TIMER 4

213

Figure 9-4. Basic Operation of Timer Register 4 (TM4)

(a) When counting starts, stops, and then starts again

(c) Operation when TM4 is FFFFH

(b) If CE4 bit is set to "1" again after counting has been started

TM4

CE4

FFH

100H 101H

Count Started

CE4

Count Stopped

CE4

Count Started

CE4

Count Clock

TM4

CE4

Count Started

CE4

Rewritten

CE4

Count Clock

TM4

INTOV4

Interrupt Request

FFFEH

FFFFH

Count Clock

214

CHAPTER 9 TIMER 4

9.4.2 Clear operation

(1) Clear operation by match with compare register

Timer register 4 (TM4) can be automatically cleared when its value matches with the value of a compare register

(CM4n: n = 0, 1). When a clearance source arises, TM3 is cleared to 0000H on the next count clock. Therefore,

even if a clearance source arises, the value at the point at which the clearance source arose is retained until the

next count clock arrives.

Figure 9-5. TM4 Clear Operation by Match with Compare Register (CM40, CM41)

Count Clock

TM4

n_1

Compare Register

(CM4n)

TM4 and CM4n Match

Cleared Here

Remark

n = 0, 1

(2) Clear operation by CE4 bit of timer mode control register 4 (TMC4)

Timer register 4 (TM4) is also cleared when the CE4 bit of TMC4 is cleared (0) by software. The clear operation

is performed following clearance (0) of the CE4 bit in the same way.

CHAPTER 9 TIMER 4

215

Figure 9-6. Clear Operation of TM4 When CE4 Bit is Cleared (0)

(a) Basic operation

Count Clock

TM4

n_1

CE4

If the CE4 bit is set (1) from this count clock onward, the count starts from 1
on the count clock after the CE4 bit is set (1).

(c) Restart when count clock is input after clearance

Count Clock

TM4

n_1

CE4

If the CE4 bit is set (1) before this count clock, the count starts from 1 on
this count clock

(b) Restart before count clock is input after clearance

Count Clock

TM4

n_1

CE4

216

CHAPTER 9 TIMER 4

9.5 Operation of Compare Register

Timer 4 performs a compare operation by comparing the value set to a compare register (CM40, CM41) with the count

value of a timer register 4 (TM4).

If the count value of TM4 matches with the value set in advance to CM4n (n = 0, 1) as a result of counting by TM4, an

interrupt request (INTCM4n: n = 0, 1) is generated.

Moreover, the contents of TM4 can be cleared after it has matched with the value of CM4n, so that TM4 can operate

as an interval timer that repeatedly counts the value set to CM4n.

Table 9-2. Interrupt Request Signal from Compare Register (timer 4)

Compare Register

Interrupt Request Signal

CM40

INTCM40

CM41

INTCM41

CHAPTER 9 TIMER 4

217

Figure 9-7. Compare Operation (timer 4)

Remark

CLR40 = 0, CLR41 = 0

Figure 9-8. TM4 Clearance after Match Detection

INTCM40

Interrupt Request

TM4
Count Value

CM41

Count Started
CE4

CLR40

CLR41

CE4

CLR40

CLR41

INTCM41

Interrupt Request

CM40

Count Disabled
CE4

Count Started

Cleared

INTCM40

Interrupt Request

TM4
Count Value

FFFFH

Count Started

CE4

CM40 Value

CM41 Value

FFFFH

CM40 Value

CM41 Value

INTCM41

Interrupt Request

INTOV4

Interrupt Request

Match

218

CHAPTER 9 TIMER 4

9.6 Example of Use

9.6.1 Operation as interval timer (1)

By setting the timer register 4 (TM4) in the free running mode and adding a specific value to a compare register (CM4n:

n = 0, 1) in an interrupt processing routine, TM4 can be used as an interval timer whose cycle is determined by the specific

value to be added (refer to Figure 9-9).

Figure 9-10 shows the set contents of the control registers, Figure 9-11 shows how to set the control registers, and Figure

9-12 shows the processing in the interrupt routine, where compare register CM40 is used.

Figure 9-9. Timing of Interval Timer Operation (1)

Remark

Interval time = n

x/f

CLK

FFFFH

x = 4, 8, 16, 32, 64

y is limited by the data transfer processing time. Consider the processing time of the interrupt used or the macro

service processing time (refer to Table 14-11 Interrupt Acceptance Processing Time and Table 14-12

Macro Service Processing Time).

MOD(2n)

INTCM40

Interrupt Request

TM4 Count Value

FFFFH

Compare Register

(CM40)

Timer Started

MOD(3n)

MOD(4n)

FFFFH

MOD(2n)

MOD(3n)

Interval Time

Rewriting by
Interrupt Program

CHAPTER 9 TIMER 4

219

Figure 9-10. Set Contents of Control Registers for Interval Timer Operation (1)

(a) Prescaler mode register 4 (PRM4)

(b) Timer mode control register 4 (TMC4)

PRM42 PRM41 PRM40

PRM4

Specifies count clock

CLK

/x ; x = 4, 8, 16, 32, 64)

TMC4

Disables TM4 clearing

Enables count operation

220

CHAPTER 9 TIMER 4

Figure 9-11. Setting Procedure of Interval Timer Operation (1)

Figure 9-12. Interrupt Request Processing of Interval Timer Operation (1)

Interval Timer (1)

Sets count value to CM40

CM40

INTCM40 Interrupt

Sets PRM4

Sets TMC4

INTCM40 Interrupt

Calculates timer value at which interrupt occurs next

CM40

CM40 + n

Other Interrupt Processing Program

RETI

CHAPTER 9 TIMER 4

221

9.6.2 Operation as interval timer (2)

TM4 can be used as an interval timer that repeatedly generates an interrupt at interval determined by the count value

set in advance (refer to Figure 9-13).

Figure 9-4 shows the set contents of the control registers, and Figure 9-15 shows how to set the control registers, where

compare register CM41 is used.

Figure 9-13. Timing of Interval Timer Operation (2)

Remark

Interval time = (n+1)

x/f

CLK

FFFFH

x = 4, 8, 16, 32, 64

Compare Register

(CM41)

INTCM41

Interrupt Request

TM4
Count Value

Count Started

Cleared

Interval Time

Interrupt Accepted

Interval Time

222

CHAPTER 9 TIMER 4

Figure 9-14. Set Contents of Control Register for Interval Timer Operation (2)

(a) Prescaler mode register 4 (PRM4)

(b) Timer mode control register 4 (TMC4)

Figure 9-15. Setting Procedure of Interval Timer Operation (2)

TMC4

TM4 clearing by match of CM41 and TM4

Enables count operation

Interval timer (2)

Sets count value to CM41

CM41

INTCM41 Interrupt

Sets PRM4

Sets TMC4

PRM42 PRM41 PRM40

PRM4

Specifies count clock

CLK

/x ; x = 4, 8, 16, 32, 64)

CHAPTER 9 TIMER 4

223

9.7 Cautions

(1) The prescaler uses one time base commonly with all the timers (timers 0 and 1, timers/counters 2 and 3, and timer

4). If one of the timers sets the CE bit to "1", the time base starts counting. If another timer sets the CE bit to "1"

while one timer operates, the first count clock of the timer may be shortened because the time base has already

started counting.

For example, if a timer/counter is used as an interval timer, the first interval will be shortened by up to one count

clock. The second and subsequent intervals will be as specified.

Figure 9-16. Operation When Count Starts

(2) There is a possibility of misoperation if the next register contents are rewritten while the timer 4 is running (when

the CE4 bit of the timer mode control register 4 (TMC4) is set). The misoperation occurs as there is no defined order

of priority in the event of contention between the timings at which the hardware function changes due to a register

rewrite and the status changes in the function prior to the rewrite.

When the contents of following registers are rewritten, counter operations must be stopped first to ensure stability.

CLR40 and CLR41 bits of timer mode control register 4 (TMC4)

Prescaler mode register 4 (PRM4)

(3) If the compare register (CM4n: n = 0, 1) and TM4 contents match when an instruction that stops timer register 4

(TM4) operation is executed, the TM4 count operation stops, but an interrupt request is generated.

If you do not want an interrupt to be generated when TM4 operation is stopped, interrupts should be masked by means

of interrupt the mask register before stopping the TM4.

Example

Program in which an interrupt request may be

Program in which an interrupt request is not generated

generated

CLR1 CE4

MK1L, #03H

CLR1 CE4
CLR1 CMIF40
CLR1 CMIF41

Count Clock

TM4

CE4

Software count start directive (CE4

.
.
.

Interrupt request gener-
ated by timer 4 here

Disables interrupts from timer 4

Clears timer 4 interrupt request flag

224

CHAPTER 9 TIMER 4

(4) Match between timer register 4 (TM4) and compare register (CM4n: n = 0, 1) is detected only when TM4 is

incremented. Therefore, the interrupt request is not generated even if the same value as TM4 is written to CM4n.

(5) If a compare register (CM40, CM41) is set to 0000H, the compare operation is performed after counting has been

completed. Therefore, the interrupt due to a match (INTCM40, INTCM41) does not occur immediately after counting

has been started. If CM4n (n = 0, 1) is set to 0000H, TM4 counts up to FFFFH, overflows, and then the interrupt

due to a match INTCM4n (n = 0, 1) occurs.

Figure 9-17. Operation When Compare Register (CM40, CM41) Is Set to 0000H

Interrupt Occured

Count Started

Match

Cleared Cleared Cleared

0000H

Count Clock

TM4

CE4

CM4n

INTCM4n

FFFFH

Remark

n = 0, 1

CHAPTER 10 WATCHDOG TIMER FUNCTION

The watchdog timer is a timer that detects inadvertent program loops.

Watchdog timer interrupts are used to detect system or program errors. For this purpose, instructions that clear the

watchdog timer (start the count) within a given period are inserted at various places in a program.

If an instruction that clears the watchdog timer is not executed within the set time and the watchdog timer overflows, a

watchdog timer interrupt (INTWDT) is generated and a program error is reported.

10.1 Configuration

The watchdog timer block diagram is shown in Figure 10-1.

Figure 10-1. Block Diagram of Watchdog Timer

Watchdog Timer

(8-bit)

Overflow

WDT CLR

CLK

INTWDT

CLK

Frequency

Divider

Selector

225

226

CHAPTER 10 WATCHDOG TIMER FUNCTION

10.2 Watchdog Timer Mode Register (WDM)

The WDM is an 8-bit register that controls the watchdog timer operation.

To prevent erroneous clearing of the watchdog timer by an inadvertent program loop, writing can only be performed by

a dedicated instruction. This dedicated instruction, MOV WDM,#byte, has a special code configuration (4 bytes), and a write

is not performed unless the 3rd and 4th bytes of the operation code are mutual complements.

If the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt

is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source

of the error, and thus the address that was the source of the error can be identified from the return address saved in the

stack area.

If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.

As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler,

RA78K/IV, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should

be performed by the program.

Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any

operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.

After a system reset (RESET input), once the watchdog timer has been started (by setting (1) the RUN bit), the WDM

contents cannot be changed. The watchdog timer can only be stopped by a reset, but can be cleared at any time with a

dedicated instruction.

The WDM can be read at any time by a data transfer instruction.

RESET input clears the WDM to 00H.

The WDM format is shown in Figure 10-2.

227

CHAPTER 10 WATCHDOG TIMER FUNCTION

Figure 10-2. Format of Watchdog Timer Mode Register (WDM)

Remark

CLK

: internal system clock

Cautions 1. The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV

WDM, #byte).

2. The same value should be written each time in writes to the WDM to set (1) the RUN bit. The

contents written the first time cannot be changed even if a different value is written.

3. Once the RUN bit has been set (1), it cannot be reset (0) by software.

RUN

PRC

WDI2

WDI1

RUN

Specifies Operation of Watchdog Timer

Stops watchdog timer

Clears watchdog timer to start counting

WDM

Address: 0FFC2H On reset: 00H R/W

PRC

Priority of Interrupt Request of Watchdog Timer

Interrupt request of watchdog timer

< interrupt request of NMI pin input

Interrupt request of watchdog timer

> interrupt request of NMI pin input

WDI2

Overflow Time [ms]

CLK

WDI1

Count

Clock

CLK

= 12.5 MHz f

CLK

= 16.0 MHz

10.5

41.9

83.9

167.8

8.2

32.8

65.5

131.1

228

CHAPTER 10 WATCHDOG TIMER FUNCTION

10.3 Operation

10.3.1 Count operation

The watchdog timer is cleared, and the count started, by setting (1) the RUN bit of the watchdog timer mode register

(WDM). When overflow time specified by the WDI2 and WDI1 bits of WDM has elapsed after the RUN bit has been set

(1), a non-maskable interrupt (INTWDT) is generated.

If the RUN bit is set (1) again before the overflow time elapses, the watchdog timer is cleared and the count operation

is started again.

10.3.2 Interrupt priorities

The watchdog timer interrupt (INTWDT) is a non-maskable interrupt. Other non-maskable interrupts are interrupts from

the NMI pin (NMI). The order of acknowledgment when an INTWDT interrupt and NMI interrupt are generated simultaneously

can be specified by the setting of bit 4 of the watchdog timer mode register (WDM).

Even if INTWDT is generated while the NMI processing program is executed when NMI acknowledgement is specified

to take precedence, INTWDT is not acknowledged until completion of execution of the NMI processing program.

229

CHAPTER 10 WATCHDOG TIMER FUNCTION

10.4 Cautions

10.4.1 General cautions on use of watchdog timer

(1) The watchdog timer is one means of detecting inadvertent program loops, but it cannot detect all inadvertent program

loops. Therefore, in equipment that requires a high level of reliability, you should not rely on the on-chip watchdog

timer alone, but should use external circuitry for early detection of inadvertent program loops, to enable processing

to be performed that will restore the normal state or establish a stable state and then stop the operation.

(2) The watchdog timer cannot detect inadvertent program loops in the following cases.

<1> If watchdog timer clearance is performed in the timer interrupt processing program

<2> If cases where an interrupt request or macro service is held pending (refer to 14.9) occur consecutively

<3> If the watchdog timer is cleared periodically when the program is looping inadvertently due to an error in the

program logic (if each module of the program functions normally but the overall program does not)

<4> If the watchdog timer is periodically cleared by a group of instructions executed when an inadvertent program

loop occurs

<5> If the STOP mode, HALT mode, or IDLE mode is entered as the result of an inadvertent program loop

<6> If an inadvertent program loop of watchdog timer also occurs in the event of CPU hang up due to external noise

In cases <1>, <2> and <3> the program can be amended to allow detection to be performed.

In case <4>, the watchdog timer can only be cleared by a 4-byte dedicated instruction. Similarly, in case <5>, the

STOP mode, HALT mode, or IDLE mode cannot be set unless a 4-byte dedicated instruction is used. For state <2>

to be entered as the result of an inadvertent program loop, 3 or more consecutive bytes of data must comprise a

specific pattern (e.g. BT PSWL. bit, $$, etc.). Therefore, the establishment of state <2> as the result of <4>, <5>

or an inadvertent program loop is likely to be extremely rare.

10.4.2 Cautions on

PD784054 watchdog timer

(1) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM, #byte).

(2) The same value should be written each time in writes to the watchdog timer mode register (WDM) to set (1) the RUN

bit. The contents written the first time cannot be changed even if a different value is written.

(3) Once the RUN bit has been set (1), it cannot be reset (0) by software.

[MEMO]

230

CHAPTER 11 A/D CONVERTER

The

PD784054 incorporates an analog/digital (A/D) converter with 16 multiplexed analog inputs (ANI0 to ANI15).

The successive approximation conversion method is used, and the conversion result is held in the 10-bit A/D conversion

result register (ADCR0-ADCR7). This allows fast, high-precision conversion to be performed (conversion time of 13

s when

CLK

= 16 MHz and high-speed conversion is used).

There are two modes for starting A/D conversion, as follows:

Hardware start : Conversion started by trigger input (INTP4).

Software start : Conversion started in accordance with A/D converter mode register (ADM) bit setting.

After start-up, there are two operating modes, as follows:

Scan mode

: Multiple analog inputs are selected in order, and conversion data is obtained from all pins.

Select mode

: One pin is used as the analog input, and conversion values are obtained in succession.

Stoppage of all the above modes and conversion operations is specified by the ADM register.

In each mode, the conversion result is held in ADCRn (n = 0 to 7) each time A/D conversion has been completed. When

A/D conversion has been completed, an A/D conversion end interrupt request (INTAD) is generated. This interrupt can start

a macro service that automatically transfers data by hardware.

11.1 Configuration

Figure 11-1 shows the block diagram of the A/D converter.

The high-order 8 channels (ANI8 through ANI15) and low-order 8 channels (ANI0 through ANI7) of the A/D converter

are selected by using the A/D converter mode register (ADM).

231

232

CHAPTER 11 A/D CONVERTER

Figure 11-1. Block Diagram of A/D Converter

Internal Bus

Input

Selector

ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7

Input

Selector

ANI8
ANI9

ANI10
ANI11
ANI12
ANI13
ANI14
ANI15

Sample & Hold Circuit

Voltage
Comparator

Edge

Detection

Circuit

INTP4

Control

Circuit

Conversion
Trigger

INTAD

Trigger Enable

A/D Converter Mode Register

(ADM)

Series Resistor String

R/2

REF

ADCR0

ADCR1

ADCR2

ADCR3

ADCR4

ADCR5

ADCR6

ADCR7

A/D Conversion Result Register

RESET

Successive

Approximation Register

(SAR)

Tap selector

233

CHAPTER 11 A/D CONVERTER

Cautions 1. A capacitor should be connected between the analog input pins (ANI0 to ANI15) and AV

and

between the reference voltage input pin (AV

REF

) and AV

to prevent misoperation due to noise.

Be sure to connect the capacitor as closely to ANI0 through ANI15 and AV

REF

as possible.

Figure 11-2. Example of Capacitor Connection on A/D Converter Pins

2. A voltage outside the range AV

to AV

REF

should not be applied to pins used as A/D converter input

pins. Refer to 11.6 Cautions for details.

(1) Input circuit

The input circuit selects the analog input in accordance with the specification of the A/D converter mode register

(ADM), and sends the analog input to the sample & hold circuit according to the operating mode,

(2) Sample & hold circuit

The sample & hold circuit samples the analog inputs arriving sequentially one by one and holds the analog input

in the process of A/D conversion.

(3) Voltage comparator

The voltage comparator determines the voltage difference between the analog input and the series resistor string

value tap.

(4) Series resistor string

The series resistor string is used to generate voltages that match the analog inputs.

The series resistor string is connected between the A/D converter reference voltage pin (AV

REF

) and the A/D

converter GND pin (AV

). To provide 1024 equal voltage steps between the two pins, it is made up of 1023 equal

resistors and two resistors with half that resistance value.

The series resistor string voltage tap is selected by a tap selector controlled by the successive approximation register

(SAR).

Analog

Input

Reference

Voltage Input

100 to
500 pF

ANI0-ANI15

REF

PD784054

234

CHAPTER 11 A/D CONVERTER

(5) SAR: Successive Approximation Register

The SAR is a 10-bit register in which the data for which the series resistor string voltage tap value matches the analog

input voltage value is set bit by bit starting from the most significant bit (MSB).

When data has been set up to the least significant bit (LSB) of the SAR (when A/D conversion is completed), the

SAR contents (conversion result) are stored in the A/D conversion result register (ADCRn: n = 0-7).

(6) Edge detection circuit

The edge detection circuit detects a valid edge from the interrupt request input pin (INTP4) input, and generates

an external interrupt request signal (INTP4) and A/D conversion operation external trigger.

The INTP4 pin input valid edge is specified by external interrupt mode register 1 (INTM1) (refer to Figure 13-2).

External trigger enabling/disabling is set by means of the A/D converter mode register (ADM) (refer to 11.2 A/D

Converter Mode Register (ADM)).

235

CHAPTER 11 A/D CONVERTER

11.2 A/D Converter Mode Register (ADM)

ADM is an 8-bit register that controls A/D converter operations.

The ADM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. Its format

is shown in Figure 11-3.

Bits 0 through 2 (ANIS0 through ANIS2) select input analog signals to be converted. Bit 3 (PS) selects whether ANI0

through ANI7 (low-order 8 channels) or ANI8 through ANI15 (high-order 8 channels) are used as analog input pins. The

low-order 8 channels and high-order 8 channels have identical functions.

Bit 5 (AM0) and bit 6 (AM1) control the operation mode of A/D conversion. If the AM0 and AM1 bits are cleared (0), all

conversion operations under execution are stopped. At this time, ADCRn (n = 0 to 7) is not updated, nor is the INTAD interrupt

request generated. Moreover, power supply to the voltage comparator is stopped to reduce the current consumption of

the A/D converter.

Bit 7 (TRG) enables external synchronization of the A/D conversion operation. If the TRG bit is set (1) when the AM0

or AM1 bits are set, the conversion operation is initialized each time the valid edge is input to the INTP4 pin as an external

trigger. If the TRG bit is cleared (0), the conversion operation is performed regardless of the INTP4 pin input.

If data is written to ADM during conversion, the conversion operation is initialized and started from the beginning again.

When RESET is input, the value of ADM is reset to 00H.

Caution When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing

(0) the AM0 bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit or AM1 bit remains

set (1), the conversion operation will be stopped by entering the STOP or IDLE mode, but the power

supply to the voltage comparator will not be stopped, and therefore the A/D converter consumption

current will not be reduced.

236

CHAPTER 11 A/D CONVERTER

Figure 11-3. Format of A/D Converter Mode Register (ADM)

Remark

CLK

: internal system clock

TRG

AM1

AM0

ANIS2 ANIS1 ANIS0

TRG

Controls External Trigger

Disables external trigger

Enables external trigger

ADM

Address: 0FF6EH On reset: 00H R/W

AM1

Specifies A/D Conversion Operation Mode

Stops conversion

Scan mode

Select mode

AM0

1-buffer mode

4-buffer mode

Selects Conversion Time

208 clocks (f

CLK

> 12.5 MHz)

169 clocks (f

CLK

12.5 MHz)

ANIS2

Selects Analog Input

ANI0/ANI8

ANI1/ANI9

ANI2/ANI10

ANI3/ANI11

ANI4/ANI12

ANI5/ANI13

ANI6/ANI14

ANI7/ANI15

ANIS1

ANIS0

In select

mode

In scan

mode

ANI0/ANI8

ANI0/ANI8,

ANI1/ANI9

ANI0/ANI8-

ANI2/ANI10

ANI0/ANI8-

ANI3/ANI11

ANI0/ANI8-

ANI4/ANI12

ANI0/ANI8-

ANI5/ANI13

ANI0/ANI8-

ANI6/ANI14

ANI0/ANI8-

ANI7/ANI15

Selects Analog Input Pin

ANI0 through ANI7 (port 7)

ANI8 through ANI15 (port 8)

237

CHAPTER 11 A/D CONVERTER

Table 11-1. Conversion Time Set by FR Bit

Internal system clock: f

CLK

(MHz)

12.5

FR bit

Conversion time (

14.9

13.5

16.9

Caution Once the A/D converter starts operating, conversion operations are performed repeatedly until the AM0

bit and AM1 bit of the A/D converter mode register (ADM) is cleared (0). Therefore, a superfluous

interrupt may be generated if ADM setting is performed after interrupt-related registers, etc., when A/

D converter mode conversion, etc., is performed. The result of this superfluous interrupt is that the

conversion result storage address appears to have been shifted when the scan mode is used. Also,

when the select mode is used, the first conversion result appears to have been an abnormal value, such

as the conversion result for the other channel. It is therefore recommended that A/D converter mode

conversion be carried out using the following procedure.

<1> Write to the ADM

<2> Interrupt request flag (ADIF) clearance (0)

<3> Interrupt mask flag setting

Operations <1> to <3> should not be divided by an interrupt or macro service.

Alternatively, the following procedure is recommended.

<1> Stop the A/D conversion operation by clearing (0) the AM0 bit and AM1 bit of the ADM.

<2> Interrupt request flag (ADIF) clearance (0).

<3> Interrupt mask flag setting

<4> Write to the ADM

238

CHAPTER 11 A/D CONVERTER

11.3 A/D Conversion Result Registers (ADCR0 through ADCR7)

The

PD784054 has eight 10-bit A/D conversion result registers (ADCR0 through ADCR7) that store the results of A/

D conversion.

Each ADCRn (n = 0 to 7) can be only read by using a 16-bit manipulation instruction or an 8-bit manipulation instruction.

The conversion result can be read from ADCRn in the following two ways:

(1) Word access (by execution of 16-bit manipulation instruction)

Of the word data read, the low-order 10 bits are valid.

The high-order 6 bits are always "0" when read.

Figure 11-4 illustrates word access to ADCRn.

Figure 11-4. Word Access to A/D Conversion Result Register

Symbol

Address

On reset

ADCR0

0FF70H

Undefined

ADCR1

0FF72H

ADCR2

0FF74H

ADCR3

0FF76H

ADCR4

0FF78H

ADCR5

0FF7AH

ADCR6

0FF7CH

ADCR7

0FF7EH

Remark

AD0-AD9: A/D conversion result

Symbol

ADCRn

(n = 0-7)

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

R/W

239

CHAPTER 11 A/D CONVERTER

(2) Byte access (by execution of 8-bit manipulation instruction)

Of the 10-bit data of the A/D conversion result, the high-order 8 bits are read.

Figure 11-5 illustrates byte access to ADCRn

Figure 11-5. Byte Access to A/D Conversion Result Register

Symbol

Address

On reset

ADCR0H

0FF71H

Undefined

ADCR1H

0FF73H

ADCR2H

0FF75H

ADCR3H

0FF77H

ADCR4H

0FF79H

ADCR5H

0FF7BH

ADCR6H

0FF7DH

ADCR7H

0FF7FH

Remark

AD2-AD9: A/D conversion result (high-order 8 bits of 10 bits)

Symbol

ADCRnH

(n = 0-7)

AD9

AD8

AD7

AD6

AD5

AD4

AD3

AD2

R/W

240

CHAPTER 11 A/D CONVERTER

11.4 Operation

11.4.1 Basic A/D converter operation

(1) A/D Conversion Operation procedure

A/D conversion is performed by means of the following procedure:

(a) Analog pin selection and operating mode specification are set with the A/D converter mode register (ADM), and

the A/D conversion is started.

(b) When conversion starts, the MSB (bit 9) of the successive approximation register (SAR) is set (1) automatically.

REF

(·=· 1/2 AV

REF

(d) The voltage difference between the series resistor string voltage tap and the analog input is determined by the

voltage comparator. If the analog input is greater than (1/2) AV

REF

, the MSB of the SAR remains set (1), and

if it is less than (1/2) AV

REF

, the MSB is cleared (0).

(e) Next, bit 8 of the SAR is set (1) automatically, and the next comparison is performed. Here, the series resistor

string voltage tap is selected according to the value of bit 9 for which the result has already been set, as shown

below.

Bit 9 = 1 ........

REF

·=·

REF

Bit 9 = 0 ........

REF

·=·

REF

This voltage tap is compared with the analog input voltage, and bit 8 of the SAR is manipulated as follows

according to the result:

Analog input voltage

voltage tap: Bit 8 = 1

Analog input voltage < voltage tap: Bit 8 = 0

(f)

The same kind of comparison is continued up to the LSB (bit 0) of the SAR (binary search method).

(g) When comparison of the 10 bits is completed, a valid digital result is left in the SAR, and that value is transferred

to the A/D conversion result register (ADCR0 through ADCR7) and latched.

An A/D conversion operation end interrupt request (INTAD) can be generated at the same time.

1023
2048

1
4

3
4

1535
2048

511

2048

241

CHAPTER 11 A/D CONVERTER

Figure 11-6. Basic Operation of A/D Converter

Conversion
Result

Undefined

Conversion Time

Sampling Time

A/D Converter
Operation

SAR

ADCRn

(n = 0 to 7)

INTAD

A/D Conversion

Sampling

200H

300H

100H

A/D conversion operations are performed successively until the AM0 bit and AM1 bit is cleared (0) by software. If

a write operation is performed on the ADM during an A/D conversion operation, the conversion operation is initialized,

and if the AM0 bit and AM1 bit is set (1), conversion will be started from the beginning.

The contents of the ADCR n (n = 0 to 7) are undefined after RESET input.

(2) Input voltage and conversion result

The relationship between the analog input voltage input to an analog input pin (ANI0 to ANI15) and the A/D conversion

result (value stored in ADCRn) is shown by the following expression:

ADCRn = INT(

1024 + 0.5)

(ADCRn 0.5)

< (ADCRn + 0.5)

Remark

INT( )

: Function that returns the integer part of the value in ( )

: Analog input voltage

REF

: AV

REF

pin voltage

ADCRn : ADCR n (n = 0 to 7) value

REF

1024

REF

1024

242

CHAPTER 11 A/D CONVERTER

Figure 11-7 shows the relationship between the analog input voltage and the A/D conversion result in graphic form.

Figure 11-7. Relationship Between Analog Input Voltage and A/D Conversion Result

1023

1022

1021

Input Voltage/AV

REF

2048

1024

2048

1024

2048

1024

2043

2048

1022

1024

2045

2048

1023

1024

2047

2048

A/D Conversion Result
(ADCRn: n = 0 to 7)

(3) A/D conversion time

The A/D conversion time is determined by the system clock frequency (f

CLK

) and the FR bit of the A/D converter mode

The A/D conversion time includes the entire time required for one A/D conversion operation, and the sampling time

is also included in the A/D conversion time.

These values are shown in Table 11-2.

Table 11-2. Time of A/D Conversion

System Clock (f

CLK

) Range

FR Bit

Conversion Time

CLK

> 12.5 MHz

208 clocks

CLK

12.5 MHz

169 clocks

(4) A/D converter operating modes

There are two A/D converter operating modes, scan mode and select mode. These modes are selected according

to the setting of bit 5 (AM0) and bit 6 (AM1) of the A/D converter mode register (ADM).

Operation in either mode continues until the ADM is rewritten.

243

CHAPTER 11 A/D CONVERTER

11.4.2 Select mode

In the select mode, one analog input pin is selected by bits 0 through 2 (ANIS0 through ANIS2) of the A/D converter mode

select register (ADM), and the specified analog input is converted. The result of the conversion is stored to the A/D

conversion result register corresponding to the analog input.

In this mode, the following two modes can be selected depending on how the A/D conversion result is stored.

1-buffer mode

4-buffer mode

(1) 1-buffer mode

One analog input is converted once, and the result is stored to one A/D conversion result register. Therefore, the

analog input and A/D conversion result register correspond on a one-to-one basis (refer to Table 11-3).

Each time the conversion has been completed once, an A/D conversion end interrupt request (INTAD) occurs.

Table 11-3. Correspondence between Analog Input and A/D Conversion Result Register

(select mode: 1-buffer mode)

Analog Input

A/D Conversion Result Register

ANI0/ANI8

ACDR0

ANI1/ANI9

ADCR1

ANI2/ANI10

ACDR2

ANI3/ANI11

ADCR3

ANI4/ANI12

ACDR4

ANI5/ANI13

ADCR5

ANI6/ANI14

ACDR6

ANI7/ANI15

ADCR7

Figure 11-8. Operating Timing in Select Mode (1-buffer mode) (1/2)

(a) TRG bit

Conversion Started Conversion Ended Conversion Ended Conversion Ended Conversion Ended Conversion Ended Conversion Ended

ANI3

AM1, AM0

ANIS2-ANIS0

011

INTAD

A/D Conversion

ADCR3

244

CHAPTER 11 A/D CONVERTER

Figure 11-8. Operation Timing in Select Mode (1-buffer mode) (2/2)

(b) TRG bit

(2) 4-buffer mode

One analog input is converted four times, and the result is stored to four A/D conversion result registers. When one

of the analog inputs of ANI0 through ANI3 (ANI8 through ANI11) is selected, the conversion result is stored to A/

D conversion result registers ADCR0 through ADCR3. If one of the analog inputs of ANI4 through ANI7 (ANI12

through ANI15) is selected, the conversion result is stored to the A/D conversion result register ADCR4 through

ADCR7 (refer to Table 11-4).

Each time A/D conversion has been completed four times, A/D conversion end interrupt request (INTAD) is

generated.

Table 11-4. Correspondence between Analog Input and A/D Conversion Result Register

(select mode: 4-buffer mode)

Analog Input

A/D Conversion Result Register

ANI0/ANI8

ADCR0-ADCR3

ANI1/ANI9

ANI2/ANI10

ANI3/ANI11

ANI4/ANI12

ADCR4-ADCR7

ANI5/ANI13

ANI6/ANI14

ANI7/ANI15

Conversion Started Conversion Ended

ANI0

AM1, AM0

ANIS2-ANIS0

000

INTAD

A/D Conversion

ADCR0

INTP4

Conversion Ended Conversion Ended

ANI0

Initialization

245

CHAPTER 11 A/D CONVERTER

Figure 11-9. Operation Timing in Select Mode (4-buffer mode)

(a) TRG bit

(b) TRG bit

11.4.3 Scan mode

In this mode, analog input pins specified by the ANIS0 through ANIS2 bits of the A/D converter mode register (ADM)

are sequentially selected, starting from ANI0 pin, and A/D conversion is executed. The result of the conversion is stored

to the A/D conversion result register that corresponds to an analog input on a one-to-one basis (refer to Table 11-5).

When all the analog inputs have been converted, the A/D conversion end interrupt request (INTAD) is generated.

ANI3

AM1, AM0

ANIS2-ANIS0

011

INTAD

A/D Conversion

ADCR0-
ADCR3

ANI3

(ADCR0)

ANI3

Conversion Ended

ANI3

(ADCR1)

ANI3

(ADCR2)

ANI3

(ADCR3)

ANI3

(ADCR0)

ANI3

(ADCR1)

ANI3

(ADCR2)

Conversion Ended

Conversion Started

ANI3

AM1, AM0

ANIS2-ANIS0

011

INTAD

A/D Conversion

ADCR0-
ADCR3

INTP4

Initialization

ANI3

(ADCR0)

ANI3

(ADCR0)

ANI3

(ADCR1)

ANI3

(ADCR2)

ANI3

(ADCR3)

ANI3

(ADCR0)

Conversion Ended

246

CHAPTER 11 A/D CONVERTER

Table 11-5. Correspondence between Analog Input and A/D Conversion Result Register (scan mode)

Analog Input

A/D Conversion Result Register

ANI0/ANI8

ADCR0

ANI1/ANI9

ADCR1

ANI2/ANI10

ADCR2

ANI3/ANI11

ADCR3

ANI4/ANI12

ADCR4

ANI5/ANI13

ADCR5

ANI6/ANI14

ADCR6

ANI7/ANI15

ADCR7

Figure 11-10. Operation Timing in Scan Mode

(a) TRG bit

ANI0

AM1, AM0

ANIS2-ANIS0

010

INTAD

A/D Conversion

ADCR0-
ADCR2

ANI0

(ADCR0)

ANI1

ANI2

ANI0

ANI1

ANI2

ANI0

ANI1

(ADCR1)

ANI2

(ADCR2)

ANI0

(ADCR0)

ANI1

(ADCR1)

ANI2

(ADCR2)

ANI0

(ADCR0)

Conversion Started

Conversion Ended

(b) TRG bit

ANI0

AM1, AM0

ANIS2-ANIS0

010

INTAD

A/D Conversion

ADCR0-
ADCR2

INTP4

Initialization

ANI1

ANI0

ANI1

ANI2

ANI0

ANI1

ANI0

ANI1

ANI0

(ADCR0)

ANI0

(ADCR0)

ANI1

(ADCR1)

ANI2

(ADCR2)

ANI0

(ADCR0)

ANI0

(ADCR0)

Conversion Started

Conversion Ended

247

CHAPTER 11 A/D CONVERTER

11.4.4 A/D conversion operation start by software

An A/D conversion operation start by software is performed by writing a value to the A/D converter mode register (ADM)

that sets the TRG bit of the ADM register to 0 and the AM0 bit or AM1 bit to 1.

If a value is written to the ADM during an A/D conversion operation (AM0 bit or AM1 bit = 1) such that the TRG bit is

set to 0 and the AM0 bit or AM1 bit to 1 again, the A/D conversion operation being performed at that time is suspended,

and A/D conversion is started immediately in accordance with the written value.

Once A/D conversion operation is started, as soon as one A/D conversion operation ends the next A/D conversion

operation is started in accordance with the operating mode set by the ADM, and conversion operations continue repeatedly

until an instruction that writes to the ADM is executed.

When A/D conversion operation is started by software (TRG bit = 0), INTP4 pin (P25 pin) input does not affect the A/

D conversion operation.

(1) A/D conversion in select mode (1-buffer mode)

A/D conversion of the analog input set by the A/D converter mode register (ADM) is started. When conversion has

been completed, the same analog input is converted again. Each time A/D conversion has been completed, the

A/D conversion end interrupt request (INTAD) is generated.

Figure 11-11. A/D Conversion in Select Mode (1-buffer mode) Started by Software

(2) A/D conversion in select mode (4- buffer mode)

The analog input set by the A/D converter mode register (ADM) is converted. One analog input is converted four

times. When A/D conversion has been executed four times, the same analog input is converted four times again.

Each time conversion has been executed four times, the A/D conversion end interrupt request (INTAD) is generated.

ADM Written

ADM Rewritten

ANI1

TRG

AM1, AM0

ANIS2-ANIS0

001

INTAD

A/D Conversion

ADCR1,
ADCR5

ANI1

(ADCR1)

TRG

AM1, AM0

ANIS2-ANIS0

101

ANI1

ANI5

ANI1

(ADCR1)

ANI1

(ADCR1)

ANI1

(ADCR1)

ANI1

(ADCR1)

ANI5

(ADCR5)

248

CHAPTER 11 A/D CONVERTER

Figure 11-12. A/D Conversion in Select Mode (4-buffer mode) Started by Software

(3) A/D conversion in scan mode

When conversion is started, analog inputs selected by the ANIS0 through ANIS2 bits of the A/D converter mode

inputs has been completed, the same operation (conversion from the ANI0 pin to the specified analog input pin) is

repeated again. When a series of A/D conversion from the ANI0 pin to the specified analog input has been completed,

the A/D conversion end interrupt request (INTAD) is generated.

Figure 11-13. A/D Conversion in Scan Mode Started by Software

ADM Written

ADM Rewritten

ANI3

TRG

AM1, AM0

ANIS2-ANIS0

011

INTAD

A/D Conversion

ADCR0-
ADCR7

ANI3

(ADCR0)

TRG

AM1, AM0

ANIS2-ANIS0

101

ANI3

ANI5

ANI3

(ADCR1)

ANI3

(ADCR2)

ANI3

(ADCR3)

ANI3

(ADCR0)

ANI5

(ADCR4)

ADM Written

ADM Rewritten

ANI0

TRG

AM1, AM0

ANIS2-ANIS0

010

INTAD

A/D Conversion

ADCR0-
ADCR2

ANI0

(ADCR0)

TRG

AM1, AM0

ANIS2-ANIS0

001

ANI1

ANI2

ANI0

ANI1

ANI0

ANI1

(ADCR1)

ANI2

(ADCR2)

ANI0

(ADCR0)

ANI0

(ADCR0)

ANI1

(ADCR1)

ANI0

ANI1

249

CHAPTER 11 A/D CONVERTER

11.4.5 A/D conversion operation start by hardware

An A/D conversion operation start by hardware is made possible by setting both the TRG bit and the AM0 bit or AM1

bit of the A/D converter mode register (ADM) to 1. When the TRG bit and the AM0 bit or AM1 bit of the ADM are both set

to 1, external signals are placed in the standby state, and an A/D conversion operation is started when a valid edge is input

to the INTP4 pin (P25 pin).

If another valid edge is input to the INTP4 pin after the A/D conversion operation has been started by a valid edge input

to the INTP4 pin, the A/D conversion operation being performed at that time is suspended, and A/D conversion is performed

from the beginning in accordance with the contents set in the ADM.

If a value is written to the ADM during an A/D conversion operation (AM0 bit or AM1 = 1) such that the TRG bit and AM0

bit or AM1 bit are both set to 1 again, the A/D conversion operation being performed at that time is suspended (the standby

state is also suspended), and a state is entered in which the A/D converter waits for input of a valid edge to the INTP4 pin

in the A/D conversion operation mode in accordance with the written value, and a conversion operation is started when

a valid edge is input.

Use of this function allows A/D conversion operations to be synchronized with external signals. Once A/D conversion

operation is started, as soon as one A/D conversion operation ends the next A/D conversion operation is started in

accordance with the operating mode set by the ADM (the A/D converter does not wait for INTP4 pin input), and conversion

operations continue repeatedly until an instruction that writes to the ADM is executed, or a valid edge is input to the INTP4

pin.

(1) A/D conversion in select mode (1-buffer mode)

A/D conversion of the analog input set by the A/D converter mode register (ADM) is started. When conversion has

been completed, the same analog input is converted again. Each time A/D conversion has been completed, the

A/D conversion end interrupt request (INTAD) is generated.

If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped

once, and then conversion is newly started.

Figure 11-14. A/D Conversion in Select Mode (1-buffer mode) Started by Hardware

ADM Written

ADM Rewritten

Standby State

INTAD

A/D Conversion

ADCR1,
ADCR5

INTP4

ANI1

(ADCR1)

ANI1

Standby State

ANI5

ANI1

(ADCR1)

ANI5

(ADCR5)

TRG

AM1, AM0

ANIS2-ANIS0

001

TRG

AM1, AM0

ANIS2-ANIS0

101

250

CHAPTER 11 A/D CONVERTER

(2) A/D conversion in select mode (4-buffer mode)

The analog input set by the A/D converter mode register (ADM) is converted. One analog input is converted four

times. When A/D conversion has been executed four times, the same analog input is converted four times again.

Each time conversion has been executed four times, the A/D conversion end interrupt request (INTAD) is generated.

If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped

once, and then conversion is newly started.

Figure 11-15. A/D Conversion in Select Mode (4-buffer mode) Started by Hardware

ADM Written

ADM Rewritten

Standby

State

INTAD

A/D Conversion

ADCR0-
ADCR7

INTP4

ANI3

(ADCR0)

TRG

AM1, AM0

ANIS2-ANIS0

011

TRG

AM1, AM0

ANIS2-ANIS0

101

ANI3

(ADCR1)

ANI3

(ADCR2)

ANI3

(ADCR3)

ANI3

(ADCR0)

ANI3

ANI5

ANI3

Standby

State

251

CHAPTER 11 A/D CONVERTER

(3) A/D conversion in scan mode

When conversion is started, analog inputs selected by the ANIS0 through ANIS2 bits of the A/D converter mode

has been completed, the same operation (conversion from the ANI0 pin to the specified analog input pin) is repeated

again. When a series of A/D conversion from the ANI0 pin to the specified analog input has been completed, the

A/D conversion end interrupt request (INTAD) is generated.

If the valid edge is input to the INTP4 pin during A/D conversion, the A/D conversion under execution is stopped

once, and then conversion is newly started.

Figure 11-16. A/D Conversion in Scan Mode Started by Hardware

ADM Written

ADM Rewritten

Standby

State

INTAD

A/D Conversion

ADCR0-
ADCR2

INTP4

ANI0

(ADCR0)

TRG

AM1, AM0

ANIS2-ANIS0

010

TRG

AM1, AM0

ANIS2-ANIS0

001

ANI0

ANI1

ANI2

ANI0

Standby State

ANI0

ANI1

(ADCR1)

ANI2

(ADCR2)

ANI0

(ADCR0)

252

CHAPTER 11 A/D CONVERTER

11.5 External Circuit of A/D Converter

The A/D converter is provided with a sample & hold circuit to stabilize its conversion operation. This sample & hold circuit

outputs sampling noise during sampling immediately after an A/D conversion channel has been changed.

To absorb this sampling noise, an external capacitor must be connected. If the impedance of the signal source is high,

an error may occur in the conversion result due to the sampling noise. Especially when the scan mode is used, the impedance

of the signal source must be kept low because the channel whose signal is to be converted changes one after another.

One way to absorb the sampling noise is to increase the capacitance of the capacitor. However, if the capacitance is

increased too much, the sampling noise is accumulated. Therefore, the most effective way is to reduce the resistance

component.

11.6 Cautions

(1) Range of voltages applied to analog input pins

The following must be noted concerning A/D converter analog input pins ANI0 to ANI15 (P70 to P77, P80 to P87).

A voltage outside the range AV

to AV

REF

should not be applied to pins subject to A/D conversion during an A/

D conversion operation.

If this restriction is not observed, the

PD784046 may be damaged.

(2) Connecting capacitor to analog input pins

A capacitor should be connected between the analog input pins (ANI0 to ANI15) and AV

and between the reference

voltage input pin (AV

REF

) and AV

to prevent misoperation due to noise.

Be sure to connect the capacitor as close to ANI0 through ANI15 and AV

REF

as possible.

Figure 11-17. Example of Capacitor Connection on A/D Converter Pins

Analog
Input

Reference
Voltage Input

100 to
500 pF

ANI0-ANI15

REF

PD784054

253

CHAPTER 11 A/D CONVERTER

(3) When the STOP mode or IDLE mode is used, the consumption current should be reduced by clearing (0) the AM0

bit and AM1 bit before entering the STOP or IDLE mode. If the AM0 bit and AM1 bit remains set (1), the conversion

operation will be stopped by entering the STOP or IDLE mode, but the power supply to the voltage comparator will

not be stopped, and therefore the A/D converter consumption current will not be reduced.

(4) Once the A/D converter starts operating, conversion operations are performed repeatedly until the AM0 bit and AM1

bit of the A/D converter mode (ADM) is cleared (0). Therefore, a superfluous interrupt may be generated if ADM

setting is performed after interrupt-related registers, etc., are set when A/D converter mode conversion, etc., is

performed. The result of this superfluous interrupt is that the conversion result storage address appears to have

been shifted when the scan mode is used. Also, when the select mode is used, the first conversion result appears

to have been an abnormal value, such as the conversion result for the other channel. It is therefore recommended

that A/D converter mode conversion be carried out using the following procedure.

<1> Write to the ADM

<2> Interrupt request flag (ADIF) clearance (0)

<3> Interrupt mask flag setting

Operations <1> to <3> should not be divided by an interrupt or macro service.

Alternatively, the following procedure is recommended.

<1> Stop the A/D conversion operation by clearing (0) the AM0 bit and AM1 bit of the ADM.

<2> Interrupt request flag (ADIF) clearance (0).

<3> Interrupt mask flag setting

<4> Write to the ADM

[MEMO]

254

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

The

PD784054 incorporates two serial interface channels for which asynchronous serial interface (UART) mode or

3-wire serial I/O (IOE) mode can be selected.

The two UART/IOE channels have completely identical functions. In this chapter, therefore, unless stated otherwise,

UART/IOE1 will be described as representative of both UART/IOEs. When used as UART2/IOE2, the UART/IOE1 register

names, bit names and pin names should be read as their UART2/IOE2 equivalents as shown in Table 12-1.

Table 12-1. Differences Between UART/IOE1 and UART2/IOE2 Names

Item

UART/IOE1

UART2/IOE2

Pin names

P32/RxD/SI1, P33/TxD/SO1,

P35/RxD2/SI2, P36/TxD2/SO2,

P34/ASCK/SCK1

P37/ASCK2/SCK2

Asynchronous serial interface mode register

ASIM

ASIM2

Asynchronous serial interface mode register bit names

TXE, RXE, PS1, PS0, CL, SL,

TXE2, RXE2, PS21, PS20, CL2,

ISRM, SCK

SL2, ISRM2, SCK2

Asynchronous serial interface status register

ASIS

ASIS2

Asynchronous serial interface status register bit names

PE, FE, OVE

PE2, FE2, OVE2

Clocked serial interface mode register

CSIM1

CSIM2

Clocked serial interface mode register bit names

CTXE1, CRXE1, DIR1, CSCK1

CTXE2, CRXE2, DIR2, CSCK2

Baud rate generator control register

BRGC

BRGC2

Baud rate generator control register bit names

TPS0-TPS3, MDL0-MDL3

TPS20-TPS23, MDL20-MDL23

Interrupt request names

INTSR/ITCSI1, INTSER, INTST

INTSR2/INTCSI2, INTSER2,

INTST2

Interrupt control registers and bit names used in this

SRIC, CSIIC1, SERIC, STIC,

SRIC2, CSIIC2, SERIC2, STIC2,

chapter

SRIF, CSIIF1, SERIF, STIF

SRIF2, CSIIF2, SERIF2, STIF2

255

256

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.1 Switching between Asynchronous Serial Interface Mode and 3-wire Serial I/O Mode

The asynchronous serial interface mode and 3-wire serial I/O mode cannot be used simultaneously. Switching between

these modes is performed in accordance with the settings of the asynchronous serial interface mode register (ASIM/ASIM2)

and the clocked serial interface mode register (CSIM1/CSIM2) as shown in Figure 12-1.

Figure 12-1. Switching Between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode

TXE

ASIM

RXE

PS1

PS0

ISRM

SCK

TXE2

RXE2

PS21

PS20

CL2

SL2

ISRM2

SCK2

Asynchronous serial interface mode operation
specification (refer to Figure 12-3)

On Reset

Address

R/W

00H

0FF88H

ASIM2

R/W

00H

0FF89H

TXE

TXE2

RXE

RXE2

CTXE1

CTXE2

CRXE1

CRXE2

Operating Mode

Setting prohibited

Other than the above

Operation-stopped
mode

3-wire serial
I/O mode

Asynchronous
serial interface
mode

CTXE1

CSIM1

CRXE1

DIR1

CSCK1

CTXE2 CRXE2

DIR2

CSCK2

On Reset

R/W

00H

0FF84H

CSIM2

R/W

00H

0FF85H

3-wire serial I/O mode operation specification
(refer to Figure 12-12)

257

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2 Asynchronous Serial Interface Mode

A UART (Universal Asynchronous Receiver Transmitter) mode is incorporated as the asynchronous serial interface. With

this method, one byte of data is transmitted following a start bit, and full-duplex operation is possible.

A baud rate generator is incorporated, enabling communication to be performed at any of a wide range of baud rates.

Also, the baud rate can be defined by scaling the clock input to the ASCK pin.

12.2.1 Configuration in asynchronous serial interface mode

The block diagram of the asynchronous serial interface is described in Figure 12-2.

Refer to 12.4 Baud Rate Generator for details of the baud rate generator.

258

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-2. Block Diagram of Asynchronous Serial Interface

Remark

m = 16 to 30, n = 0 to 11

Internal Bus

1/8

Receive Buffer

Shift Register

Reception

Control

Parity Check

FE2

PE2

OVE

OVE2

RESET

ASIS, ASIS2

TXE

TXE2

RXE

RXE2 PS21

PS0

PS20

CL2

SL2

ISRM

ISRM2

SCK

SCK2

RXB, RXB2

P32/R

P35/R

P33/T

P36/T

Transmit

Shift Register

Transmission

Control Parity

Addition

INTSER,
INTSER2

INTST,

TXS,
TXS2

INTST2

INTSR, INTSR2

Selector

P34/ASCK,
P37/ASCK2

CLK

Baud Rate Generator

RESET

ASIM, ASIM2

1/8

PS1

259

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(1) Receive buffer (RXB/RXB2)

This is the register that holds the receive data. Each time one byte of data is received, the receive data is transferred

from the shift register.

If a 7-bit data length is specified, receive data is transferred to bits 0 to 6 of RXB/RXB2, and the MSB of RXB/RXB2

is always "0".

RXB/RXB2 can be read only by an 8-bit manipulation instruction. The contents of RXB/RXB2 are undefined after

RESET input.

(2) Transmit shift register (TXS/TXS2)

This is the register in which the data to be transmitted is set. Data written to the TXS/TXS2 is transmitted as serial

data.

If a 7-bit data length is specified, bits 0 to 6 of the data written in the TXS/TXS2 are treated as transmit data. A transmit

operation starts when a write to the TXS/TXS2 is performed. The TXS/TXS2 cannot be written to during a transmit

operation.

TXS/TXS2 can be written to only by an 8-bit manipulation instruction. The contents of TXS/TXS2 are undefined after

RESET input.

(3) Shift register

This is the shift register that converts the serial data input to the RxD, and RxD2 pin to parallel data. When one byte

of data is received, the receive data is transferred to the receive buffer.

The shift register cannot be manipulated directly by the CPU.

(4) Reception control parity check

Receive operations are controlled in accordance with the contents set in the asynchronous serial interface mode

if an error is detected, a value is set in the asynchronous serial interface status register (ASIS/ASIS2) according

to the type of error.

(5) Transmission control parity addition

Transmission operation is controlled by appending a start bit, parity bit, and stop bit to the data written to the transmit

shift registers (TXS and TXS2) in accordance with the contents set to the asynchronous serial interface mode

registers (ASIM and ASIM2).

(6) Selector

Selects the baud rate clock source.

260

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.2 Asynchronous serial interface control registers

(1) Asynchronous serial interface mode register (ASIM), Asynchronous serial interface mode register 2 (ASIM2)

The ASIM and ASIM2 are 8-bit registers that specify the UART mode operation.

These registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. The

format of ASIM and ASIM is shown in Figure 12-3.

These registers are cleared to 00H by RESET input.

261

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-3. Formats of Asynchronous Serial Interface Mode Register (ASIM) and

Asynchronous Serial Interface Mode Register 2 (ASIM2)

Remark

CLK

: internal system clock

TXE

RXE

PS1

PS0

ISRM

SCK

ASIM

Address: 0FF88H, 0FF89H On reset: 00H R/W

Transmission/Reception

Disables transmission/reception,

or sets 3-wire serial I/O mode

Enables reception

Enables transmission

Enables transmission/reception

ASIM2

TXE2

RXE2

PS21

PS20

CL2

SL2

ISRM2 SCK2

TXE

TXE2

RXE

RXE2

Specifies Parity Bit

No parity

Transmission: 0 parity appended

Reception: Parity error does not occur

Odd parity

Even parity

PS1

PS21

PS0

PS20

Specifies Character Length of Data

7 bits

8 bits

CL2

Specifies Stop Bit Length (transmission only)

1 bit

2 bits

SL2

Enables or Disables Occurrence of Reception

End Interrupt in Case of Reception Error

Note

Enables

Disables

ISRM

ISRM2

Specifies Input Clock To Baud Rate Generator

External clock input (ASCK, ASCK2)

Internal clock (f

CLK

)

SCK

SCK2

262

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Note To disable the reception completion interrupt when a reception error occurs, make sure that wait time

equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse after the

reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is not inserted, the

reception completion interrupt occurs even when it is disabled.

The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can

be calculated by the following expression:

Wait time =

n+2

CLK

Remark

CLK

: Internal system clock frequency

: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-

bit prescaler (n = 0 to 11)

Caution An asynchronous serial interface mode register (ASIM/ASIM2) rewrite should not be performed

during a transmit operation. If an ASIM/ASIM2 register rewrite is performed during a transmit

operation, subsequent transmit operations may not be possible (normal operation is restored by

RESET input). Software can determine whether transmission is in progress by using a transmis-

sion completion interrupt (INTST/INTST2) or the interrupt request flag (STIF/STIF2) set by INTST/

INTST2.

(2) Asynchronous serial interface status register (ASIS), Asynchronous serial interface status register 2 (ASIS2)

The ASIS and ASIS2 contain flags that indicate the error contents when a receive error occurs. Flags are set (1)

when a receive error occurs, and cleared (0) when data is read from the receive buffer (RXB/RXB2). If the next data

is received before RXB/RXB2 is read, the overrun error flag (OVE/OVE2) is set (1), and the other error flags are

cleared (0) (if there is an error in the next data, the corresponding error flag is set (1)).

These registers can be read only by an 8-bitmanipulation instruction or bit manipulation instruction. The format of

ASIS and ASIS2 is shown in Figure 12-4.

These registers are cleared to 00H by RESET input.

263

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-4. Formats of Asynchronous Serial Interface Status Register (ASIS) and Asynchronous Serial

Interface Status Register 2 (ASIS2)

Cautions 1. The receive buffer (RXB/RXB2) must be read even if there is a receive error. If RXB/RXB2 is not

read, an overrun error will occur when the next data is received, and the receive error state will

continue indefinitely.

2. To disable the reception completion interrupt when a reception error occurs, make sure that wait

time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse

after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is

not inserted, the reception completion interrupt occurs even when it is disabled.

The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate

clock can be calculated by the following expression:

Wait time =

n+2

CLK

Remark

CLK

: Internal system clock frequency

: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-

bit prescaler (n = 0 to 11)

OVE

ASIS

Address : 0FF8AH, 0FF8BH On reset : 00H R

PE2

FE2

OVE2

Parity Error Flag

Parity error does not occur

Parity error occurs

ASIS2

PE2

Framing Error Flag

Framing error does not occur

Framing error occurs

FE2

Overrun Error Flag

Reception overrun error does not occur

Reception overrun error occurs

OVE

OVE2

264

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.3 Data format

Serial data transmission/reception is performed in full-duplex asynchronous mode.

The transmit/receive data format is shown in Figure 12-5. One data frame is made up of a start bit, character bits, parity

bit, and stop bit(s).

Character bit length specification, parity selection and stop bit length specification for one data frame are performed by

means of the asynchronous serial interface mode register (ASIM).

Figure 12-5. Data Format of Asynchronous Serial Interface Transmit/Receive

1 Data Frame

Start
Bit

Parity
Bit

Stop
Bit(s)

Start bit ................... 1 bit

Character bits ........ 7 bits/8 bits

Parity bit ................. Even parity/odd parity/0 parity/no parity

Stop bit(s) ............... 1 bit/2 bits

The serial transfer rate is selected in accordance with the asynchronous serial interface mode register and baud rate

generator settings. If a serial data receive error occurs, the nature of the receive error can be determined by reading the

asynchronous serial interface status register (ASIS) status.

265

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.4 Parity types and operations

The parity bit is used to detect a bit error in the communication data. Normally, the same kind of parity bit is used on

the transmission side and the reception side. With even parity and odd parity, 1 bit (odd number) errors can be detected.

With 0 parity and no parity, errors cannot be detected.

Even parity

If the number of bits with a value of "1" in the transmit data is odd, the parity bit is set to "1", and if the number of "1"

bits is even, the parity bit is set to "0". Control is thus performed to make the number of "1" bits in the transmit data

plus the parity bit an even number. In reception, the number of "1" bits in the receive data plus the parity bit is counted,

and if this number is odd, a parity error is generated.

Odd parity

Conversely to the case of even parity, control is performed to make the number of "1" bits in the transmit data plus

the parity bit an odd number.

In reception, a parity error is generated if the number of "1" bits in the receive data plus the parity bit is even.

0 parity

In transmission, the parity bit is set to "0" irrespective of the receive data.

In reception, parity bit detection is not performed. Therefore, no parity error is generated irrespective of whether the

parity bit is "0" or "1".

No parity

In transmission, a parity bit is not added.

In reception, reception is performed on the assumption that there is no parity bit. Since there is no parity bit, no parity

error is generated.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.5 Transmission

The

PD784054's asynchronous serial interface is set to the transmission enabled state when the TXE bit of the

asynchronous serial interface mode register (ASIM) is set (1). A transmit operation is started by writing transmit data to

the transmit shift register (TXS) when transmission is enabled. The start bit, parity bit and stop bit(s) are added automatically.

When a transmit operation is started, the data in the TXS is shifted out, and a transmission completion interrupt (INTST)

is generated when the TXS is empty.

If no more data is written to the TXS, the transmit operation is discontinued.

If the TXE bit is cleared (0) during a transmit operation, the transmit operation is discontinued immediately.

Figure 12-6. Interrupt Timing of Asynchronous Serial Interface Transmission Completion

(a) Stop bit length: 1

STOP

Parity

START

TxD (Output)

INTST

(b) Stop bit length: 2

Parity

START

TxD (Output)

INTST

STOP

Cautions 1.

After RESET input the transmit shift register (TXS) is emptied but a transmission completion

interrupt is not generated. A transmit operation can be started by writing transmit data to the TXS.

An asynchronous serial interface mode register (ASIM) rewrite should not be performed during

a transmit operation. If an ASIM rewrite is performed during a transmit operation, subsequent

transmit operations may not be possible (normal operation is restored by RESET input). Software

can determine whether transmission is in progress by using a transmission completion interrupt

(INTST) or the interrupt request flag (STIF) set by INTST.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.6 Reception

When the RXE bit of the asynchronous serial interface mode register (ASIM) is set (1), receive operations are enabled

and sampling of the RxD input pin is performed.

RxD input pin sampling is performed using the serial clock (divide-by-m counter input clock) specified by ASIM and band

rate generator control register (BRGC).

When the RxD pin input is driven low, the divide-by-m counter starts counting and a data sampling start timing signal

is output on the m'th count. If the RxD pin input is low when sampled again by this start timing signal, the input is recognized

as a start bit, the divide-by-m counter is initialized and the count is started, and data sampling is performed. When the

character data, parity bit and stop bit are detected following the start bit, reception of one data frame ends.

When reception of one data frame ends, the receive data in the shift register is transferred to the receive buffer, RXB,

and a reception completion interrupt (INTSR) is generated.

If an error occurs, the receive data in which the error occurred is still transferred to RXB. If bit 1 (ISRM) of the ASIM

was cleared (0) when the error occurred, INTSR is generated.

If the ISRM was set (1), INTSR is not generated.

If the RXE bit is cleared (0) during a receive operation, the receive operation is stopped immediately. In this case the

contents of RXB and ASIS are not changed, and no INTSR or INTSER interrupt is generated.

Figure 12-7. Interrupt Timing of Asynchronous Serial Interface Reception Completion

STOP

Parity

START

RxD (Input)

INTSR

Cautions 1. The receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun

error will occur when the next data is received, and the receive error state will continue indefinitely.

2. To disable the reception completion interrupt when a reception error occurs, make sure that wait

time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse

after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is

not inserted, the reception completion interrupt occurs even when it is disabled.

The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate

clock can be calculated by the following expression:

Wait time =

n+2

CLK

Remark

CLK

: Internal system clock frequency

: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-

bit prescaler (n = 0 to 11)

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.2.7 Receive errors

Three kinds of errors can occur in a receive operation: parity errors, framing errors and overrun errors. As the result

of data reception, an error flag is raised in the asynchronous serial interface status register (ASIS) and a receive error

interrupt (INTSER) is generated. Receive error causes are shown in Table 12-2.

It is possible to detect the occurrence of any of the above errors during reception by reading the contents of the ASIS

(refer to Figures 12-4 and 12-8).

The contents of the ASIS register are cleared (0) by reading the receive buffer (RXB) or by reception of the next data

(if there is an error in the next data, the corresponding error flag is set).

Table 12-2. Causes of Receive Error

Receive Error

Cause

Parity error

Transmit data parity specification and receive data parity do not match

Framing error

Stop bit not detected

Overrun error

Reception of next data completed before data is read from receive buffer

Figure 12-8. Timing of Receive Error

STOP

Parity

START

RxD (Input)

INTSR

Note

INTSER

Note

If a receive error occurs while the ISRM bit is set (1), INTSR is not generated.

Remark

In the

PD784054, a break signal cannot be detected by hardware. As a break signal is a low-level signal

of two characters or more, a break signal may be judged to have been input if software detects the occurrence

of two consecutive framing errors in which the receive data was 00H. The chance occurrence of two

consecutive framing errors can be distinguished from a break signal by having the RxD pin level read by

software (confirmation is possible by setting "1" in bit 2 of the port 3 mode register (PM3) and reading port 3

(P3)) and confirming that it is "0".

Cautions 1.

The contents of the asynchronous serial interface status register (ASIS) are cleared (0) by reading

the receive buffer (RXB) or by reception of the next data. If you want to find the details of an error,

therefore, ASIS must be read before reading RXB.

The RXB must be read even if there is a receive error. If RXB is not read, an overrun error will occur

when the next data is received, and the receive error state will continue indefinitely.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

3. To disable the reception completion interrupt when a reception error occurs, make sure that wait

time equivalent to two pulses of the clock that serves as the reference of the baud rate clock elapse

after the reception error occurs until the receive buffers (RXB, RXB2) are read. If the wait time is

not inserted, the reception completion interrupt occurs even when it is disabled.

The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate

clock can be calculated by the following expression:

Wait time =

n+2

CLK

Remark

CLK

: Internal system clock frequency

: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-

bit prescaler (n = 0 to 11)

12.2.8 Transmitting/receiving data with macro service

When data is transmitted using a macro service, a vectored interrupt occurs two times. On the other hand, the

interrupt occurs only once when data is received using the macro service.

Transmitting/receiving data by using macro service

Transmission is started by writing data to the transmit shift register (TXS). If this is executed by using a macro service,

data is written to TXS and transmitted the specified number of times. The transmission end interrupt (INTST) that

occurs after completion of the transmission performs the macro service processing that writes the next data. When

the last data has been written to TXS, the macro service is completed (MSC = 0), and a vectored interrupt request

is generated (refer to <1> in Figure 12-9).

When data transmission is completed after that (when one frame has been transmitted), INTST is generated again,

and the vectored interrupt request is generated again (<2> in Figure 12-9).

To start a macro service by INTST in this way, therefore, a vectored interrupt is generated two times by the same

interrupt request (INTST in this case).

When reception is executed, however, a vectored interrupt request is not generated two times. Because macro service

processing that transfers received data to memory is executed by the reception and interrupt (INTSR) that occurs after

reception has been completed, a vectored interrupt request is generated only once after the macro service has been

completed.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-9. Transmission/Reception with Macro Service

(a) Transmission

(b) Reception

Main Routine

Macro Service Request

(INTSR)

Last Macro Service Request

(INTSR)

Macro Service Processing

Vectored Interrupt Processing
after End of Macro Service
Processing

Interrupt request is generated and
accepted after end of macro service
(MSC = 0).

Main Routine

Macro Service Request

(INTST)

Last Macro Service Request

(INTST)

Transmission End Interrupt

(INTST)

Macro Service Processing

Vectored Interrupt Processing after
End of macro Service ... <1>

Vectored Interrupt Processing after
End of UART Transmission ... <2>

Interrupt request is generated
and accepted after end of macro
service (MSC = 0).

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3 3-wire Serial I/O Mode

The 3-wire serial I/O mode is used to communicate with devices that incorporate a conventional clocked serial interface.

Basically, communication is performed using three lines: the serial clock (SCK), serial data output (SO), and serial data

input (SI). Handshaking lines are required when a number of devices are connected.

Figure 12-10. Example of 3-Wire Serial I/O System Configuration

3-wire serial I/O

SCK

Port (Interrupt)

Port

SCK

Port

Interrupt (Port)

Master CPU

Note

Slave CPU

Note

Handshaking lines

12.3.1 Configuration in 3-wire serial I/O mode

The block diagram in the 3-wire serial I/O mode is shown in Figure 12-11.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-11. Block Diagram of 3-Wire Serial I/O Mode

Internal Bus

RESET

Shift Register

Direction Control Circuit

Serial Clock Counter

Interrupt Signal
Generator

INTCSI1, INTCSI2

P34/SCK1,
P37/SCK2

Serial Clock Control Circuit

Selector

Baud Rate Generator

P32/SI1,
P35/SI2

P33/SO1,
P36/SO2

N-ch Open-Drain
Output Possible

CSCK1, CSCK2

SO Latch

CSCK2

DIR2

CRXE2

CTXE2

CSCK1

DIR1

CRXE1

CTXE1

CSIM1, CSIM2

SIO1, SIO2

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(1) Shift register (SIO1/SIO2)

The SIO1 and SIO2 converts 8-bit serial data to 8-bit parallel data, and vice versa. SIO1/SIO2 is used for both

transmission and reception.

Actual transmit/receive operations are controlled by writing to/reading from SIO1/SIO2.

Reading/writing can be performed by 8-bit manipulation instruction.

The contents of SIO1/SIO2 are undefined after RESET input.

(2) SO latch

The SO latch holds the SO1/SO2 pin output level.

(3) Serial clock selector

Selects the serial clock to be used.

(4) Serial clock counter

Counts the serial clocks output or input in a transmit/receive operation, and checks that 8-bit data transmission/

reception has been performed.

(5) Interrupt signal generator

Generates an interrupt request when 8 serial clocks have been counted by the serial clock counter.

(6) Serial clock control circuit

Controls the supply of the serial clock to the shift register, and also controls the clock output to the SCK1/SCK2 pins

when the internal clock is used.

(7) Direction control circuit

Switches between MSB-first and LSB-first modes.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3.2 Clocked serial interface mode registers (CSIM1, CSIM2)

The CSIM1 and CSIM2 are 8-bit registers that specify operations in the 3-wire serial I/O mode.

These registers can be read or written to by an 8-bit manipulation instruction or bit manipulation instruction. The CSIM1

and CSIM2 format is shown in Figure 12-12.

These registers are cleared to 00H by RESET input.

Figure 12-12. Formats of Clocked Serial Interface Mode Register 1 (CSIM1) and Clocked Serial Interface

Mode Register 2 (CSIM2)

Caution Even if the DIRn (n = 1, 2) bit is changed after writing to the shift register (SIOn: n = 1, 2), data is output

with the setting before change. Therefore, set the DIRn bit before writing to SIOn.

CTXE1 CRXE1

DIR1 CSCK1

CSIM1

Address : 0FF84H, 0FF85H On reset: 00H R/W

CTXE2 CRXE2

DIR2 CSCK2

CTXEn

Transmission/Reception

Disables transmission/reception,

or asynchronous serial interface mode

Enables reception

Enables transmission

Enables transmission/reception

CSIM2

CRXEn

DIRn

Specifies Operation Mode (transfer bit sequence)

MSB first

LSB first

CSCKn

Serial Clock Select Bit

External input clock to SCKn pin

Baud rate generator output

Source Clock

SCKn

(when CTXEn,

CRXEn = 1)

Input

CMOS output

(n = 1, 2)

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3.3 Basic operation timing

In the 3-wire serial I/O mode, data transmission/reception is performed in 8-bit units. Data is transmitted/received bit

by bit in MSB-first or LSB-first order in synchronization with the serial clock.

MSB/LSB switching is specified by the DIR1 bit of the clock serial interface mode register (CSIM1).

Transmit data is output in synchronization with the fall of SCK1, and receive data is sampled on the rise of SCK1.

An interrupt request (INTCSI1) is generated on the 8th rise of SCK1.

When the internal clock is used as SCK1, SCK1 output is stopped on the 8th rise of SCK1 and SCK1 remains high until

the next data transmit or receive operation is started.

3-wire serial I/O mode timing is shown in Figure 12-13.

Figure 12-13. Timing of 3-Wire Serial I/O Mode (1/2)

(a) MSB-first

INTCSI1

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

SCK1

Note

SI1 (Input)

SO1 (Output)

DO7

DO6

DO5

DO4 DO3 DO2

DO1

DO0

Transfer End
Interrupt Generation

Start of transfer synchronized with fall of SCK1

Master CPU
Slave CPU

Execution of instruction that writes to SIO1, etc.

Note

: Output
: Input

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-13. Timing of 3-Wire Serial I/O Mode (2/2)

(b) LSB-first

INTCSI1

DI0

DI1

DI2

DI3

DI4

DI5

DI6

DI7

SCK1

Note

SI1 (Input)

SO1 (Output)

DO0

DO1

DO2

DO3 DO4 DO5

DO6

DO7

Transfer End
Interrupt Generation

Start of transfer synchronized with fall of SCK1

Master CPU
Slave CPU

Execution of instruction that writes to SIO1, etc.

: Output
: Input

Note

Remark

If the

PD784054 is connected to a 2-wire serial I/O device, a buffer should be connected to the SO1 pin as

shown in Figure 12-14. In the example shown in Figure 12-14, the output level is inverted by the buffer, and

therefore the inverse of the data to be output should be written to SIO1.

In addition, non-connection of the internal pull-up resistor should be specified for the P33/SO1 pin.

Figure 12-14. Example of Connection to 2-Wire Serial I/O

PD784054

SCK1

SI1

SO1

2-Wire Serial I/O
Device

SIO

SCK

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3.4 Operation when transmission only is enabled

A transmit operation is performed when the CTXE1 bit of clocked serial interface mode register (CSIM1) is set (1). The

transmit operation starts when a write to the shift register (SIO1) is performed while the CTXE1 bit is set (1).

When the CTXE1 bit is cleared (0), the SO1 pin is in the output high level.

(1) When the internal clock is selected as the serial clock

When transmission starts, the serial clock is output from the SCK1 pin and data is output in sequence from SIO1

to the SO1 pin in synchronization with the fall of the serial clock, and SI1 pin signals are shifted into SIO1 in

synchronization with the rise of the serial clock.

There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.

If transmission is disabled during the transmit operation (by clearing (0) the CTXE1 bit), SCK1 clock output is stopped

and the transmit operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is

not generated, and the SO1 pin becomes output high level.

(2) When an external clock is selected as the serial clock

When transmission starts, data is output in sequence from SIO1 to the SO1 pin in synchronization with the fall of

the serial clock input to the SCK1 pin after the start of transmission, and SI1 pin signals are shifted into SIO1 in

synchronization with the rise of the SCK1 pin input. If transmission has not started, shift operations are not performed

and the SO1 pin output level does not change even if the serial clock is input to the SCK1 pin.

If transmission is disabled during the transmit operation (by clearing (0) the CTXE1 bit), the transmit operation is

discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated,

and the SO1 pin becomes output high level.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3.5 Operation when reception only is enabled

A receive operation is performed when the CRXE1 bit of the clocked serial interface mode register (CSIM1) is set (1).

The receive operation starts when the CRXE1 changes from "0" to "1", or when a read from shift register (SIO1) is performed.

(1) When the internal clock is selected as the serial clock

When reception starts, the serial clock is output from the SCK1 pin and the SI1 pin data is fetched in sequence into

shift register (SIO1) in synchronization with the rise of the serial clock.

There is a delay of up to one SCK1 clock cycle between the start of reception and the first fall of SCK1.

If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), SCK1 clock output is stopped

and the receive operation is discontinued on the next rise of SCK1. In this case an interrupt request (INTCSI1) is

not generated, and the contents of the SIO1 are undefined.

(2) When an external clock is selected as the serial clock

When reception starts, the SI1 pin data is fetched into shift register (SIO1) in synchronization with the rise of the

serial clock input to the SCK1 pin after the start of reception. If reception has not started, shift operations are not

performed even if the serial clock is input to the SCK1 pin.

If reception is disabled during the receive operation (by clearing (0) the CRXE1 bit), the receive operation is

discontinued and subsequent SCK1 input is ignored. In this case an interrupt request (INTCSI1) is not generated.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.3.6 Operation when transmission/reception is enabled

When the CTXE1 bit and CRXE1 bit of the clocked serial interface mode register (CSIM1) register are both set (1), a

transmit operation and receive operation can be performed simultaneously (transmit/receive operation). The transmit/

receive operation is started when the CRXE1 bit is changed from "0" to "1", or by performing a write to shift register (SIO1).

When a transmit/receive operation is started for the first time, the CRXE1 bit always changes from "0" to "1", and there

is thus a possibility that the transmit/receive operation will start immediately, and undefined data will be output. The first

transmit data should therefore be written to SIO1 beforehand when both transmission and reception are disabled (when

the CTXE1 bit and CRXE1 bit are both cleared (0)), before enabling transmission/reception.

When transmission/reception is disabled (CTXE1 = CRXE1 = 0), the SO1 pin is in the output high level.

(1) When the internal clock is selected as the serial clock

When transmission/reception starts, the serial clock is output from the SCK1 pin, data is output in sequence from

shift register (SIO1) to the (SO1) pin in synchronization with the fall of the serial clock, and SI1 pin data is shifted

in order into SIO1 in synchronization with the rise of the serial clock.

There is a delay of up to one SCK1 clock cycle between the start of transmission and the first fall of SCK1.

If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is

discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,

the contents of the SIO1 will be undefined.

If transmission and reception are disabled simultaneously, SCK1 clock output is stopped and the transmit and receive

operations are discontinued on the next rise of SCK1. When transmission and reception are disabled simultaneously,

the contents of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output

high level.

(2) When an external clock is selected as the serial clock

When transmission/reception starts, data is output in sequence from shift register (SIO1) to the SO1 pin in

synchronization with the fall of the serial clock input to the SCK1 pin after the start of transmission/reception, and

SI1 pin data is shifted in order into SIO1 in synchronization with the rise of the serial clock. If transmission/reception

has not started, the SIO1 shift operations are not performed and the SO1 pin output level does not change even

if the serial clock is input to the SCK1 pin.

If either transmission or reception is disabled during the transmit/receive operation, only the disabled operation is

discontinued. If transmission only is disabled, the SO1 pin becomes output high level. If reception only is disabled,

the contents of the SIO1 will be undefined.

If transmission and reception are disabled simultaneously, the transmit and receive operations are disconti-nued

and subsequent SCK1 input is ignored. When transmission and reception are disabled simultaneously, the contents

of SIO1 are undefined, an interrupt request (INTCSI1) is not generated, and the SO1 pin becomes output high level.

12.3.7 Corrective action in case of slippage of serial clock and shift operations

When an external clock is selected as the serial clock, there may be slippage between the number of serial clocks and

shift operations due to noise, etc. In this case, since the serial clock counter is initialized by disabling both transmit operations

and receive operations (by clearing (0) the CTXE1 bit and CRXE1 bit), synchronization of the shift operations and the serial

clock can be restored by using the first serial clock input after reception or transmission is next enabled as the first clock.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.4 Baud Rate Generator

The baud rate generator is the circuit that generates the UART/IOE serial clock. Two independent circuits are

incorporated, one for each serial interface.

12.4.1 Baud rate generator configuration

The baud rate generator block diagram is shown in Figure 12-15.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-15. Block Diagram of Baund Rate Generator

Internal Bus

Baud Rate Generator
Control Register

BRGC, BRGC2

RESET

Asynchronous Serial
Interface Mode
Registers

ASIM, ASIM2

1/8

SCK,
SCK2

Clocked Serial
Interface Mode
Registers

CSIM1, CSIM2

1/8

CSCK1,
CSCK2

5-Bit Counter

RESET

Start Bit Detection

1/2

UART Reception
Shift Clock

Clear

Match

1/2

Selector

Shift Clock
for UART
Transmission
& IOE

Frequency

Divider

Selector

PRS

CLK

P34/ASCK/SCK1,
P37/ASCK2/SCK2

BRGC Write

CSCK1,
CSCK2

Start Bit Detection

Sampling Clock

RESET

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(1) 5-bit counter

Counter that counts the clock (f

PRS

) by which the output from the frequency divider is selected. Generates a signal

with the frequency selected by the low-order 4 bits of the baud rate generator control registers (BRGC/BRGC2).

(2) Frequency divider

Scales the internal clock (f

CLK

) or, in asynchronous serial interface mode, a clock that is twice the external baud rate

input (ASCK/ASCK2), and selects f

PRS

with the next-stage selector.

(3) Both-edge detection circuit

Detects both edges of the ASCK/ASCK2 pin input signal and generates a signal with a frequency twice that of the

ASCK/ASCK2 input clock.

12.4.2 Baud rate generator control register

The BRGC and BRGC2 are 8-bit registers that set the baud rate clock in asynchronous serial interface mode or the shift

clock in 3-wire serial I/O mode.

These registers can be read or written to with an 8-bit manipulation instruction. The BRGC and BRGC2 format is shown

in Figure 12-16.

RESET input clears the BRGC register to 00H.

Caution When a baud rate generator control register (BRGC, BRGC2) write instruction is executed, the 5-bit

counter and 1/2 frequency divider operations are reset. Consequently, if a write to the BRGC and

BRGC2 is performed during communication, the generated baud rate clock may be disrupted,

preventing normal communication from continuing. The BRGC and BRGC2 should therefore not be

written to during communication.

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

Figure 12-16. Formats of Baud Rate Generator Control Register (BRGC) and

Baud Rate Generator Control Register 2 (BRGC2)

Notes 1. This cannot be selected when k = 15 is selected by MDL3 through MDL0 (MDL23 through MDL20).

2. Only f

PRS

/16 can be selected when ASCK (ASCK2) input is used.

3. This can be used only in the 3-wire serial I/O mode.

Remark

ASCK

: ASCK (ASCK2) input clock

CLK

: internal system clock

PRS

: Selected clock of prescaler output

TPS3

TPS2

TPS1

TPS0 MDL3 MDL2 MDL1 MDL0

BRGC

TPS23 TPS22 TPS21 TPS20 MDL23 MDL22 MDL21 MDL20

Selects Prescaler
Output (f

PRS

)

BRGC2

TPS3
TPS23

TPS2
TPS22

TPS1
TPS21

TPS0
TPS20

CLK

/2, f

ASCK

Note 1

CLK

/4, f

ASCK

CLK

/8, f

ASCK

CLK

/16, f

ASCK

/16

CLK

/32, f

ASCK

/32

CLK

/64, f

ASCK

/64

CLK

/128, f

ASCK

/128

CLK

/256, f

ASCK

/256

CLK

/512, f

ASCK

/512

CLK

/1024, f

ASCK

/1024

CLK

/2048, f

ASCK

/2048

CLK

/4096, f

ASCK

/4096

Others

Input Clock of Baud
Rate Generator

Note 2

MDL3
MDL23

MDL2
MDL22

MDL1
MDL21

MDL0
MDL20

PRS

/16

PRS

/17

PRS

/18

PRS

/19

PRS

/20

PRS

/21

PRS

/22

PRS

/23

PRS

/24

PRS

/25

PRS

/26

PRS

/27

PRS

/28

PRS

/29

PRS

/30

PRS

Note 3

Address: 0FF90H, 0FF91H On reset: 00H R/W

Setting prohibited

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CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.4.3 Baud rate generator operation

The baud rate generator only operates when UART/IOE transmit/receive operations are enabled. The generated baud

rate clock is a signal scaled from the internal clock (f

CLK

) or a signal scaled from the clock input from the external baud rate

input (ASCK) pin.

Caution If a write to the baud rate generator control register (BRGC) is performed during communication, the

generated baud rate clock may be disrupted, preventing normal communication from continuing. The

BRGC should therefore not be written to during communication.

(1) Baud rate clock generation in UART mode

(a) Using internal clock (f

CLK

)

This function is selected by setting (1) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).

The internal clock (f

CLK

) is scaled by the frequency divider, this signal (f

PRS

) is scaled by the 5-bit counter, and

the signal further divided by 2 is used as the baud rate. The baud rate is given by the following expression:

(Baud rate) =

CLK

: Internal system clock frequency

: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14)

: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)

(b) Using external baud rate input

This function is selected by clearing (0) bit 0 (SCK) of the asynchronous serial interface mode register (ASIM).

When this function is used, bit MDL3 to bit MDL0 of the baud rate generator control register (BRGC) must all

be cleared (0) (k= 0).

Set P34 pin (when used with UART2, set P37 pin) in the control mode by using the port 3 mode control register

(PMC3).

The ASCK pin input clock is scaled by the frequency divider, and the signal obtained by dividing this signal by

32 (f

PRS

) (division by 16 and division by 2) is used as the baud rate. The baud rate is given by the following

expression:

(Baud rate) =

ASCK

: ASCK pin input clock frequency

: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)

When this function is used, a number of baud rates can be generated by one external input clock.

CLK

(k + 16) · 2

n + 2

285

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(3) Serial clock generation in 3-wire serial I/O mode

Selected when the CSCK1 bit of the clocked serial interface mode register 1 (CSIM1) is set (1) and SCK1 is output.

(a) Normal mode

The internal clock (f

CLK

) is scaled by the frequency divider, this signal (f

PRS

) is scaled by the 5-bit counter, and

the signal further divided by 2 is used as the serial clock. The serial clock is given by the following expression:

(Serial clock) =

CLK

: Internal system clock frequency

: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14)

: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11)

(b) High-speed mode

When this function is used, bit MDL3 to bit MDL0 of the baud rate generator control register (BRGC) are all set

(1) (k= 15).

The internal clock (f

CLK

) is scaled by the frequency divider, and this signal (f

PRS

) divided by 2 is used as the serial

clock. The serial clock is given by the following expression:

(Serial clock) =

CLK

: Internal system clock frequency

: Value set in bit TPS3 to bit TPS0 of BRGC (n = 1 to 11)

CLK

(k + 16) · 2

n + 2

CLK

n + 2

286

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.4.4 Baud rate setting in asynchronous serial interface mode

There are two methods of setting the baud rate, as shown in Table 12-3.

This table shows the range of baud rates that can be generated, the baud rate calculation expression and selection

method for each case.

Table 12-3. Methods of Baud Rate Setting

Baud Rate Clock Source

Selection Method

Baud Rate Calculation

Baud Rate Range

Expression

Baud rate generator

Internal system clock

SCK in ASIM = 1

ASCK input

SCK in ASIM = 0

CLK

: Internal system clock frequency

: Value set in bit MDL3 to bit MDL0 of BRGC (k = 0 to 14; refer to Figure 12-16)

: Value set in bit TPS3 to bit TPS0 of BRGC (n = 0 to 11; refer to Figure 12-16)

ASCK

: ASCK input clock frequency (0 )

Note

Including f

ASCK

input range: (0 )

CLK

(k + 16)·2

n + 2

CLK

245760

CLK

ASCK

131072

ASCK

n+6

Note

CLK

128

287

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(1) Examples of settings when baud rate generator is used

Examples of baud rate generator control register (BRGC) settings when the baud rate generator is used are shown

below.

When the baud rate generator is used, the SCK bit of the asynchronous serial interface mode register (ASIM) should

be set (1).

Table 12-4. Examples of BRGC Settings When Baud Rate Generator Is Used

Internal System Clock

16.0 MHz

12.5 MHz

10.0 MHz

8.0 MHz

CLK

)

Baud Rate

BRGC

Baud Rate Error

BRGC

Baud Rate Error

BRGC

Baud Rate Error

BRGC

Baud Rate Error

[bps]

Value

(%)

Value

(%)

Value

(%)

Value

(%)

BAH

0.16

B4H

1.73

B0H

1.73

AAH

0.16

110

B2H

1.36

ACH

0.92

A6H

0.88

A2H

1.36

150

AAH

0.16

A4H

1.73

A0H

1.73

9AH

0.16

300

9AH

0.16

94H

1.73

90H

1.73

8AH

0.16

600

8AH

0.16

84H

1.73

80H

1.73

7AH

0.16

1200

7AH

0.16

74H

1.73

70H

1.73

6AH

0.16

2400

6AH

0.16

64H

1.73

60H

1.73

5AH

0.16

4800

5AH

0.16

54H

1.73

50H

1.73

4AH

0.16

9600

4AH

0.16

44H

1.73

40H

1.73

3AH

0.16

19200

3AH

0.16

34H

1.73

30H

1.73

2AH

0.16

31520

30H

0.00

29H

0.00

24H

0.00

20H

0.00

38400

2AH

0.16

24H

1.73

20H

1.73

1AH

0.16

76800

1AH

0.16

14H

1.73

10H

1.73

0AH

0.16

288

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

(2) Examples of settings when external baud rate input (ASCK) is used

Table 12-5 shows an example of setting when external baud rate input (ASCK) is used. When using the ASCK input,

clear (0) the SCK bit of the asynchronous serial interface mode register (ASIM), and set P34 pin (when used with

UART2, set P37 pin) in the control mode by using port 3 mode control register (PMC3).

Table 12-5. Examples of Settings When External Baud Rate Input (ASCK) Is Used

ASCK

153.6 kHz

4.9152 MHz

(ASCK Input Frequency)

Baud Rate [bps]

BRGC Value

50H

A0H

150

40H

90H

300

30H

80H

600

20H

70H

1200

10H

60H

2400

00H

50H

4800

40H

9600

30H

19200

20H

38400

10H

76800

00H

289

CHAPTER 12 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O

12.5 Cautions

(1) An asynchronous serial interface mode register (ASIM) rewrite should not be performed during a transmit operation.

If an ASIM rewrite is performed during a transmit operation, subsequent transmit operations may not be possible

(normal operation is restored by RESET input). Software can determine whether transmission is in progress by using

a transmission completion interrupt (INTST) or the interrupt request flag (STIF) set by INTST.

(2) After RESET input the transmit shift register (TXS) is emptied but a transmission completion interrupt is not

generated. A transmit operation can be started by writing transmit data to the TXS.

(3) The receive buffer (RXB) must be read even if there is a receive error. If RXB is not read, an overrun error will occur

when the next data is received, and the receive error state will continue indefinitely.

(4) To disable the reception completion interrupt when a reception error occurs, make sure that wait time equivalent

to two pulses of the clock that serves as the reference of the baud rate clock elapse after the reception error occurs

until the receive buffers (RXB, RXB2) are read. If the wait time is not inserted, the reception completion interrupt

occurs even when it is disabled.

The wait time equivalent to two pulses of the clock that serves as the reference of the baud rate clock can be

calculated by the following expression:

Wait time =

n+2

CLK

Remark

CLK

: Internal system clock frequency

: Value of baud rate generator control registers (BRGC, BRGC2) to select tap of 12-bit

prescaler (n = 0 to 11)

(5) The contents of the asynchronous serial interface status register (ASIS) are cleared (0) by reading the receive buffer

(RXB) or by reception of the next data. If you want to find the details of an error, therefore, ASIS must be read before

reading RXB.

(6) In the 3-wire serial I/O mode, even if the DIRn (n = 1, 2) bit of the clocked serial interface mode register (CSIMn:

n = 1, 2) is changed after writing to the shift register (SIOn: n = 1, 2), data is output with the setting before change.

Therefore, set the DIRn bit before writing to SIOn.

(7) The baud rate generator control register (BRGC) should not be written to during communication. If a write instruction

is executed, the 5-bit counter and 1/2 frequency divider operations will be reset, and the generated baud rate clock

may be disrupted, preventing normal communication from continuing.

[MEMO]

290

CHAPTER 13 EDGE DETECTION FUNCTION

P20 to P27 have an edge detection function that allows a rising edge/falling edge to be set programmably, and the

detected edge is sent to internal hardware. The relation between pins P20 to P27 and the use of the detected edge is shown

in Table 13-1.

Table 13-1. Pins P20 to P27 and Use of Detected Edge

Use

Detected Edge Specification Register

P20

NMI, standby circuit control

INTM0

P21

INTP0, CC00 capture signal of timer 0

P22

INTP1, CC01 capture signal of timer 0

P23

INTP2, CC02 capture signal of timer 0

P24

INTP3, CC03 capture signal of timer 0

INTM1

P25

INTP4, conversion start signal of A/D converter

P26

INTP5

P27

INTP6

The edge detection function operates at all times except in STOP mode and IDLE mode (although the edge detection

function for pin P20 also operates in STOP mode and IDLE mode).

For pins P21 to P27, the noise elimination time when edge detection is performed can be selected by software.

13.1 Edge Detection Function Control Registers

13.1.1 External interrupt mode registers (INTM0, INTM1)

The INTMn (n = 0, 1) specify the valid edge to be detected on pins P20 to P27. The INTM0 specifies the valid edge

for pins P20 to P23, and the INTM1 specifies the valid edge for pins P24 to P27.

The INTMn can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The format

of INTM0 and INTM1 are shown in Figures 13-1 and 13-2 respectively.

RESET input clears these registers to 00H.

291

292

CHAPTER 13 EDGE DETECTION FUNCTION

Figure 13-1. Format of External Interrupt Mode Register 0 (INTM0)

ES21

ES20

ES11

ES10

ES01

ES00

ESNMI

ES21

Specifies Edge To Be Detected of P23

(INTP2, CC02 capture trigger) pin input

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

INTM0

Address: 0FF3CH On reset: 00H R/W

ES20

ES11

Specifies Edge To Be Detected of P22

(INTP1, CC01 capture trigger) Pin Input

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES10

ES01

Specifies Edge To Be Detected of P21

(INTP0, CC00 capture trigger) Pin Input

Falling edge

Rising edge

Setting prohibited

Both falling and rising edges

ES00

ESNMI

Specifies Edge To Be Detected of P20 (NMI) Pin Input

Falling edge

Rising edge

293

CHAPTER 13 EDGE DETECTION FUNCTION

Figure 13-2. Format of External Interrupt Mode Register 1 (INTM1)

Caution If the valid edge is changed by writing to the external interrupt mode register (INTMn: n = 0, 1), the valid

edge is not detected. If the edge is input while the valid edge is changed, whether the input edge is

judged as the valid edge or not is undefined.

ES61

ES60

ES51

ES50

ES41

ES40

ES31

ES30

ES61

Specifies Edge To Be Detected of P27

(INTP6) Pin Input

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

INTM1

Address : 0FF3DH On reset : 00H R/W

ES60

ES51

Specifies Edge To Be Detected of P26

(INTP5) Pin Input

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES50

ES41

Specifies Edge To Be Detected of P25 (INTP4,

A/D conversion start trigger) Pin Input

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES40

ES31

Specifies Edge To Be Detected of P24

(INTP3, CC03 capture trigger) Pin Input

Falling edge

Rising edge

Setting prohibited

Both rising and falling edges

ES30

294

CHAPTER 13 EDGE DETECTION FUNCTION

13.1.2 Interrupt valid edge flag registers (IEF1, IEF2)

IEF1 and IEF2 are flag registers that indicate which of the rising or falling edge is generated when an edge is detected

by the INPT0 through INTP6 pin. By checking these flag registers, which of the rising or falling edge is generated can be

determined if both the rising and falling edges are specified as the valid edge of an interrupt.

These registers can be read or written by using an 8-bit manipulation instruction or a bit manipulation instruction. Figures

13-3 and 13-4 show the formats of IEF1 and IEF2.

The values of these registers are undefined when RESET is input.

Figure 13-3. Format of Interrupt Valid Edge Flag Register 1 (IEF1)

IEFH3 IEFL3 IEFH2 IEFL2 IEFH1 IEFL1 IEFH0 IEFL0

IEFHn

Rising Edge Flag of INTPn Pin (n = 0 to 3)

Rising edge is not generated

Rising edge is generated

IEF1

Address : 0FF3EH On reset : undefined R/W

IEFLn

Falling Edge Flag of INTPn Pin (n = 0 to 3)

Falling edge is not generated

Falling edge is generated

295

CHAPTER 13 EDGE DETECTION FUNCTION

Figure 13-4. Format of Interrupt Valid Edge Flag Register 2 (IEF2)

Cautions 1. After checking the flag, clear the flag to "0" by software.

2. The interrupt valid edge flag register (IEFn: n = 1, 2) indicates that an edge has been generated,

and has nothing to do with specification of a valid edge. For example, if the valid edge of the INTP0

pin is specified to be the rising edge, and if the falling edge is generated, the interrupt request

signal is not generated, but the IEFL0 flag is set to "1".

3. If the INTPn (n = 0 to 6) pin is "1" after the reset signal has been deasserted, the rising edge is

recognized, and the IEFHn (n = 0 to 6) flag is set to "1". Even when the IEFHn flag is used as a

digital port (P21 to P27), it may be set to 1. Be sure to clear (0) the IEFHn flag before checking the

edge of an external interrupt.

IEFH6 IEFL6 IEFH5 IEFL5 IEFH4 IEFL4

IEFHn

Rising Edge Flag of INTPn Pin (n = 4 to 6)

Rising edge is not generated

Rising edge is generated

IEF2

Address : 0FF3FH On reset : undefined R/W

IEFLn

Falling Edge Flag of INTPn Pin (n = 4 to 6)

Falling edge is not generated

Falling edge is generated

296

CHAPTER 13 EDGE DETECTION FUNCTION

13.1.3 Noise protection control register (NPC)

NPC is a register that specifies a sampling clock used to reject the digital noise on the P21/INTP0 through P27/INTP6

pins.

This register is read or written by using an 8-bit manipulation instruction or a bit manipulation instruction.

Figure 13-5 shows the format of NPC.

The value of this register is cleared to 00H when RESET is input.

Figure 13-5. Format of Noise Protection Control Register (NPC)

Remark

CLK

: internal system clock

NI6

NI5

NI4

NI3

NI2

NI1

NI0

NIn

Specifies Sampling Clock to Reject Noise on INTPn Pin

(n = 0 to 6)

CLK

NPC

Address : 0FF3BH On reset : undefined R/W

Pulse Width

Rejected as Noise

Minimum Pulse Width

Recognized as Signal

3/f

CLK

(0.19

12/f

CLK

(0.75 s)

4/f

CLK

(0.25 s)

16/f

CLK

(1.0 s)

CLK

= 16 MHz)

297

CHAPTER 13 EDGE DETECTION FUNCTION

13.2 Edge Detection for Pin P20

On pin P20 noise elimination is performed by means of analog delay before edge detection. Therefore, an edge cannot

be detected unless the pulse width is a given time (10

s) or longer.

Figure 13-6. Edge Detection for Pin P20

Caution Since analog delay noise elimination is performed on pin P20, an edge is detected up to 10

s after it

is actually input. Also, unlike pins P21 to P27, the delay before an edge is detected is not a specific

value, because of differences in the characteristics of various devices.

P20 Input

P20 Input Signal after

Noise Elimination

Falling Edge

Rising Edge

Short Pulse
Eliminated as Noise Falling Edge Detected Since

Pulse is Sufficiently Wide

Short Pulse
Eliminated as Noise

Rising Edge Detected Since
Pulse Is Sufficiently Wide

10 s

(MIN.)

10 s
(MAX.)

298

CHAPTER 13 EDGE DETECTION FUNCTION

13.3 Pin Edge Detection for Pins P21 to P27

Edge detection for pins P21 to P27 is performed after digital noise elimination by means of clock sampling. The sampling

clock is fixed to f

CLK

In digital noise elimination, input is sampled using the f

CLK

clock, and if the input level is not the same at least four times

in succession (if it is the same only three or fewer times in succession), it is eliminated as noise. Therefore, the level must

be maintained for at least 4 f

CLK

clock cycles (0.25

s: f

CLK

= 16 MHz, f

CLK

= 1/2 f

, f

= 32 MHz) in order to be recognized

as a valid edge.

Figure 13-7. Edge Detection for Pins P21 to P27

Cautions 1.

Since digital noise elimination is performed with the f

CLK

clock, there is a delay of 4 f

CLK

clocks

between input of an edge to the pin and the point at which the edge is actually detected.

If the input pulse width is 4 f

CLK

clocks, it is uncertain whether a valid edge will be detected.

Therefore, to ensure reliable operation, the level should be held for at least 4 clocks.

If noise input to a pin is synchronized with the f

CLK

clock in the

PD784054, it may not be recognized

as noise. If there is a possibility of such noise being input, noise should be eliminated by adding

a filter to the input pins.

Pins P21 to P27

CLK

P21 to P27 Input Signal

after Noise Elimination

Rising Edge

Falling Edge

Digital Noise Elimination
with f

CLK

Clock

299

CHAPTER 13 EDGE DETECTION FUNCTION

13.4 Cautions

(1) Valid edge detection cannot be performed when the valid edge is changed by a write to the external interrupt mode

be judged to be a valid edge.

(2) After checking the flag by using the interrupt valid edge flag register (IEFn: n = 1, 2), clear the flag to "0" by software.

(3) The interrupt valid edge flag register (IEFn: n = 1, 2) indicates that an edge has been generated, and has nothing

to do with specification of a valid edge. For example, if the valid edge of the INTP0 pin is specified to be the rising

edge, and if the falling edge is generated, the interrupt request signal is not generated, but the IEFL0 flag is set to

"1".

(4) If the INTPn (n = 0 to 6) pin is "1" after the reset signal has been deasserted, the rising edge is recognized, and the

IEFHn (n = 0 to 6) flag of the interrupt valid edge flag register (IEFn: n = 1, 2) is set to "1". Even when the IEFHn

flag is used as a digital port (P21 to P27), it may be set (1). Be sure to clear (0) the IEFHn flag before checking

the edge of an external interrupt.

(5) Since analog delay noise elimination is performed on pin P20 an edge is detected up to 10

ms after it is actually

input. Also, unlike pins P21 to P27, the delay before an edge is detected is not a specific value, because of differences

in the characteristics of various devices.

(6) Since digital noise elimination is performed on pins P21 to P27 with the f

CLK

clock, there is a delay of 4 f

CLK

clocks

between input of an edge to the pin and the point at which the edge is actually detected.

(7) If the input pulse width on pins P21 to P27 is 4 f

CLK

clocks, it is uncertain whether a valid edge will be detected or

not. Therefore, to ensure reliable operation, the period of at least 4 clocks and the level must be fixed.

(8) If noise input to pins P21 to P27 is synchronized with the f

CLK

clock in the

PD784054, it may not be recognized as

noise. If there is a possibility of such noise being input, noise should be eliminated by adding a filter to the input

pins.

[MEMO]

300

CHAPTER 14 INTERRUPT FUNCTIONS

The

PD784054 is provided with three interrupt request processing modes (refer to Table 14-1). These three service

modes can be set as required in the program. However interrupt processing by macro service can only be selected for

interrupt request sources provided with the macro service processing mode shown in Table 14-2. Context switching cannot

be selected for non-maskable interrupts or operand error interrupts.

Multi-processing control using 4 priority levels can easily be performed for maskable vectored interrupts.

Table 14-1. Processing Modes of Interrupt Request

Interrupt Request

Processing Performed

PC & PSW Contents

Processing

Processing Mode

Vectored interrupts

Software

Saving to & restoration

Executed by branching to service program at

from stack

address

Note

specified by vector table

Context switching

Saving to & restoration

Executed by automatic switching to register

from fixed area in

bank specified by vector table and branching

to service program at address

Note

specified by

fixed area in register bank

Macro service

Hardware

Retained (however, PSW

Execution of pre-set processing such as data

(firmware)

is 0x00H in CPU monitor

transfers between memory and I/O

mode 0)

Note The start addresses of all interrupt service programs must be in the base area. If the body of a service program

cannot be located in the base area, a branch instruction to the service program should be written in the base area.

301

302

CHAPTER 14 INTERRUPT FUNCTIONS

14.1 Interrupt Request Sources

The

PD784054 has the 29 interrupt request sources shown in Table 14-2, with a vector table allocated to each.

Table 14-2. Sources of Interrupt Request (1/2)

Interrupt

Macro

Type of

Default

Interrupt Request

Generating

Control

Context

Macro

Service

Vector

Interrupt

Priority

Generating Source

Unit

Switching

Service

Control

Table

Request

Name

Word

Address

Software

None

BRK instruction execution

Not

3EH

possible

BRKCS instruction execution

Possible

Not

possible

Operand

None

Invalid operand in MOV STBC,

Not

3CH

error

#byte instruction or MOV WDM,

possible

#byte instruction, and LOCATION

instruction

Non-

None

NMI (pin input edge detection)

Edge

Not

maskable

detection

possible

INTWDT (watchdog timer

Watchdog

Not

overflow)

timer

possible

303

CHAPTER 14 INTERRUPT FUNCTIONS

Table 14-2. Sources of Interrupt Request (2/2)

Interrupt

Macro

Type of

Default

Interrupt Request

Generating

Control

Context

Macro

Service

Vector

Interrupt

Priority

Generating Source

Unit

Switching

Service

Control

Table

Request

Name

Word

Address

Maskable 0 (highest)

INTOV0 (overflow of timer 0)

Timer 0

OVIC0

Possible

0FE06H

INTOV1 (overflow of timer 1)

Timer 1

OVIC1

0FE08H

INTOV4 (overflow of timer 4)

Timer 4

OVIC4

0FE0AH

0AH

INTP0 (pin input edge detection)

Edge detection

PIC0

0FE0CH

0CH

INTCC00 (TM0-CC00 match signal generation)

Timer 0

INTP1 (pin input edge detection)

Edge detection

P1C1

0FE0EH

0EH

INTCC01 (TM0-CC01 match signal generation)

Timer 0

INTP2 (pin input edge detection)

Edge detection

PIC2

0FE10H

10H

INTCC002 (TM0-CC02 match signal generation)

Timer 0

INTP3 (pin input edge detection)

Edge detection

PIC3

0FE12H

12H

INTCC03 (TM0-CC03 match signal generation)

Timer 0

INTP4 (pin input edge detection)

Edge detection

PIC4

0FE14H

14H

INTP5 (pin input edge detection)

Edge detection

PIC5

0FE16H

16H

INTP6 (pin input edge detection)

Edge detection

PIC6

0FE18H

18H

INTCM10 (TM1-CM10 match signal generation)

Timer 1

CMIC10

0FE1AH

1AH

INTCM11 (TM1-CM11 match signal generation)

Timer 1

CMIC11

0FE1CH

1CH

INTCM40 (TM4-CM40 match signal generation)

Timer 4

CMIC40

0FE26H

26H

INTCM41 (TM4-CM41 match signal generation)

Timer 4

CMIC41

0FE28H

28H

INTSER (UART0 reception error)

Asynchronous

SERIC

0FE2AH

2AH

INTSR (UART0 reception end)

serial interface 0

SRIC

0FE2CH

2CH

INTCSI1 (3-wire serial I/O1 transfer end)

3-wire serial I/O1 CSIIC1

INTST (UART0 transmission end)

Asynchronous

STIC

0FE2EH

2EH

serial interface 0

INTSER2 (UART2 reception error)

Asynchronous

SERIC2

0FE30H

30H

INTSR2 (UART2 reception end)

serial interface 2

SRIC2

0FE32H

32H

INTCSI2 (3-wire serial I/O2 transfer end)

3-wire serial I/O2 CSIIC2

INTST2 (UART2 transmission end)

Asynchronous

STIC2

0FE34H

34H

serial interface 2

20 (lowest)

INTAD (A/D conversion end)

A/D converter

ADIC

0FE36H

36H

Remarks 1. Th e default priority is a fixed number. This indicates the order of priority when interrupt requests specified

as having the same priority are generated simultaneously,

2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used

simultaneously). Therefore, although the same hardware is used for the interrupts, two names are

provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.

304

CHAPTER 14 INTERRUPT FUNCTIONS

14.1.1 Software interrupts

Interrupts by software consist of the BRK instruction which generates a vectored interrupt and the BRKCS instruction

which performs context switching.

Software interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.

14.1.2 Operand error interrupts

These interrupts are generated if there is an illegal operand in an MOV STBC, #byte instruction or MOV WDM, #byte

instruction, and LOCATION instruction.

Operand error interrupts are acknowledged even in the interrupt disabled state, and are not subject to priority control.

14.1.3 Non-maskable interrupts

A non-maskable interrupt is generated by NMI pin input or the watchdog timer.

Non-maskable interrupts are acknowledged unconditionally

Note

, even in the interrupt disabled state. They are not subject

to interrupt priority control, and are of higher priority that any other interrupt.

Note Except during execution of the service program for the same non-maskable interrupt, and during execution of the

service program for a higher-priority non-maskable interrupt

14.1.4 Maskable interrupts

A maskable interrupt is one subject to masking control according to the setting of an interrupt mask flag. In addition,

acknowledgment enabling/disabling can be specified for all maskable interrupts by means of the IE flag in the program status

word (PSW).

In addition to normal vectored interruption, maskable interrupts can be acknowledged by context switching and macro

service.

The priority order for maskable interrupt requests when interrupt requests of the same priority are generated

simultaneously is predetermined (default priority) as shown in Table 14-2. Also, multi-processing control can be performed

with interrupt priorities divided into 4 levels. However, macro service requests are acknowledged without regard to priority

control or the IE flag.

305

CHAPTER 14 INTERRUPT FUNCTIONS

14.2 Interrupt Processing Modes

There are three

PD784054 interrupt processing modes, as follows:

Vectored interrupt processing

Macro service

Context switching

14.2.1 Vectored interrupt processing

When an interrupt is acknowledged, the program counter (PC) and program status word (PSW) are automatically saved

to the stack, a branch is made to the address indicated by the data stored in the vector table, and the interrupt processing

routine is executed.

14.2.2 Macro service

When an interrupt is acknowledged, CPU execution is temporarily suspended and a data transfer is performed by

hardware. Since macro service is performed without the intermediation of the CPU, it is not necessary to save or restore

CPU statuses such as the program counter (PC) and program status word (PSW) contents. This is therefore very effective

in improving the CPU service time (refer to 14.8 Macro Service Function).

14.2.3 Context switching

When an interrupt is acknowledged, the prescribed register bank is selected by hardware, a branch is made to a pre-

set vector address in the register bank, and at the same time the current program counter (PC) and program status word

(PSW) are saved in the register bank (refer to 14.4.2 BRKCS instruction software interrupt (software context switching)

acknowledgment operation and 14.7.2 Context switching).

Remark

"Context" refers to the CPU registers that can be accessed by a program while that program is being executed.

These registers include general registers, the program counter (PC), program status word (PSW), and stack

pointer (SP).

306

CHAPTER 14 INTERRUPT FUNCTIONS

14.3 Interrupt Processing Control Registers

PD784054 interrupt processing is controlled for each interrupt request by various control registers that perform interrupt

processing specification. The interrupt control registers are listed in Table 14-3.

Table 14-3. Control Registers

Symbol

Function

Interrupt control registers

OVIC0, OVIC1, OVIC4,

Registers to record generation of interrupt request, control

PIC0, PIC1, PIC2, PIC3,

masking, specify vectored interrupt processing or macro

PIC4, PIC5, PIC6, CMIC10,

service processing, enable or disable context switching

CMIC11, CMIC40, CMIC41,

function, and specify priority.

SERIC, SRIC, CSIIC1,

STIC, SERIC2, SRIC2,

CSIIC2, STIC2, ADIC

Interrupt mask registers

MK0 (MK0L, MK0H)

Control masking of maskable interrupt request. Associated

MK1 (MK1L, MK1H)

with mask control flag in interrupt control register. Can be

accessed in word or byte units.

In-service priority register

ISPR

Records priority of interrupt request currently accepted.

Interrupt mode control register

IMC

Controls nesting of maskable interrupt with priority specified

to lowest level (level 3).

Watchdog timer mode register

WDM

Specifies priorities of interrupt by NMI pin input and overflow

of watchdog timer.

Program status word

PSW

Enables or disables accepting maskable interrupt.

An interrupt control register is allocated to each interrupt source. The flags of each register perform control of the contents

corresponding to the relevant bit position in the register. The interrupt control register flag names corresponding to each

interrupt request signal are shown in Table 14-4.

307

CHAPTER 14 INTERRUPT FUNCTIONS

Table 14-4. Interrupt Control Register Flags Corresponding to Interrupt Sources

Default

Interrupt

Interrupt Control Registers

Priority

Request

Interrupt

Macro Service

Context Switching

Priority Speci-

Signal

Request Flag

Mask Flag

Enable Flag

fication Flag

0 (highest)

INTOV0

OVIC0

OVIF0

OVMK0

OVISM0

OVCSE0

OVPR00

OVPR01

INTOV1

OVIC1

OVIF1

OVMK1

OVISM1

OVCSE1

OVPR10

OVPR11

INTOV4

OVIC4

OVIF4

OVMK4

OVISM4

OVCSE4

OVPR40

OVPR41

INTP0

PIC0

PIF0

PMK0

PISM0

PCSE0

PPR00

INTCC00

PPR01

INTP1

PIC1

PIF1

PMK1

PISM1

PCSE1

PPR10

INTCC01

PPR11

INTP2

PIC2

PIF2

PMK2

PISM2

PCSE2

PPR20

INTCC02

PPR21

INTP3

PIC3

PIF3

PMK3

PISM3

PCSE3

PPR30

INTCC03

PPR31

INTP4

PIC4

PIF4

PMK4

PISM4

PCSE4

PPR40

PPR41

INTP5

PIC5

PIF5

PMK5

PISM5

PCSE5

PPR50

PPR51

INTP6

PIC6

PIF6

PMK6

PISM6

PCSE6

PPR60

PPR61

INTCM10

CMIC10

CMIF10

CMMK10

CMISM10

CMCSE10

CMPR100

CMPR101

INTCM11

CMIC11

CMIF11

CMMK11

CMISM11

CMCSE11

CMPR110

CMPR111

INTCM40

CMIC40

CMIF40

CMMK40

CMISM40

CMCSE40

CMPR400

CMPR401

INTCM41

CMIC41

CMIF41

CMMK41

CMISM41

CMCSE41

CMPR410

CMPR411

INTSER

SERIC

SERIF

SERMK

SERISM

SRCSE

SERPR0

SERPR1

INTSR

SRIC

SRIF

SRMK

SRISM

SRCSE

SRPR0

SRPR1

INTCSI1

CSIIC1

CSIIF1

CSIMK1

CSIISM1

CSICSE1

CSIPR10

CSIPR11

INTST

STIC

STIF

STMK

STISM

STCSE

STPR0

STPR1

INTSER2

SERIC2

SERIF2

SERMK2

SERISM2

SERCSE2

SERPR20

SERPR21

INTSR2

SRIC2

SRIF2

SRMK2

SRISM2

SRCSE2

SRPR20

SRPR21

INTCSI2

CSIIC2

CSIIF2

CSIMK2

CSIISM2

CSICSE2

CSIPR20

CSIPR21

INTST2

STIC2

STIF2

STMK2

STISM2

STCSE2

STPR20

STPR21

20 (lowest)

INTAD

ADIC

ADIF

ADMK

ADISM

ADCSE

ADPR0

ADPR1

308

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.1 Interrupt control registers

An interrupt control register is allocated to each interrupt source, and performs priority control, mask control, etc. for

the corresponding interrupt request. The interrupt control register format is shown in Figure 14-1.

(1) Priority specification flags (

××

PR1,

××

PR0)

The priority specification flags specify the priority on an individual interrupt source basis for the 21 maskable

interrupts.

Up to 4 priority levels can be specified, and a number of interrupt sources can be specified at the same level. Among

maskable interrupt sources, level 0 is the highest priority.

If multiple interrupt requests are generated simultaneously among interrupt source of the same priority level, they

are acknowledged in default priority order.

These flags can be manipulated bit-wise by software.

RESET input sets all bits to "1".

(2) Context switching enable flag (

××

CSE)

The context switching enable flag specifies that a maskable interrupt request is to be processed by context switching.

In context switching, the register bank specified beforehand is selected by hardware, a branch is made to a vector

address stored beforehand in the register bank, and at the same time the current contents of the program counter

(PC) and program status word (PSW) are saved in the register bank.

Context switching is suitable for real-time processing, since execution of interrupt processing can be started faster

than with normal vectored interrupt processing.

This flag can be manipulated bit-wise by software.

RESET input sets all bits to "0".

(3) Macro service enable flag (

××

ISM)

The macro service enable flag specifies whether an interrupt request corresponding to that flag is to be handled by

vectored interruption or context switching, or by macro service.

When macro service processing is selected, at the end of the macro service the macro service enable flag is

automatically cleared (0) by hardware (vectored interrupt processing/context switching processing).

This flag can be manipulated bit-wise by software.

RESET input sets all bits to "0".

(4) Interrupt mask flag (

××

MK)

An interrupt mask flag specifies enabling/disabling of vectored interrupt processing and macro service processing

for the interrupt request corresponding to that flag.

The interrupt mask flag contents are not changed by the start of interrupt processing, etc., and are the same as the

interrupt mask register contents (refer to 14.3.2 Interrupt mask registers (MK0, MK1)).

Macro service processing requests are also subject to mask control, and macro service requests can also be masked

with this flag.

This flag can be manipulated by software.

RESET input sets all bits to "1".

(5) Interrupt request flag (

××

IF)

An interrupt request flag is set (1) by generation of the interrupt request that corresponds to that flag. When the

interrupt is acknowledged, the flag is automatically cleared (0) by hardware.

This flag can be manipulated by software.

RESET input sets all bits to "0".

309

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-1. Interrupt Control Registers (

××

ICn) (1/3)

OVIF0 OVMK0 OVISM0 OVCSE0

OVPR01 OVPR00

OVIC0

Address : 0FFE0H-0FFE9H On reset : 43H R/W

OVIF1 OVMK1 OVISM1 OVCSE1

OVPR11 OVPR10

OVIC1

OVIF4 OVMK4 OVISM4 OVCSE4

OVPR41 OVPR40

OVIC4

PIF0

PMK0 PISM0 PCSE0

PPR01 PPR00

PIC0

PIC1

PIC2

PIC3

PIF1

PMK1 PISM1 PCSE1

PPR11 PPR10

PIF2

PMK2 PISM2 PCSE2

PPR21 PPR20

PIF3

PMK3 PISM3 PCSE3

PPR31 PPR30

××

IFn

Generation of Interrupt Request

No interrupt request (interrupt signal is not generated)

Interrupt request (interrupt signal is generated)

××

MKn

Enables or Disables Interrupt Processing

Enables interrupt processing

Disables interrupt processing

××

ISMn

Specifies Interrupt Processing Format

Vectored interrupt processing/context switching processing

Macro service processing

××

CSEn

Specifies Context Switching Processing

Processed by vectored interrupt

Processed by context switching

××

PRn1

Specifies Priority of Interrupt Request

Priority 0 (highest priority)

Priority 1

Priority 2

Priority 3

××

PRn0

PIF4

PMK4 PISM4 PCSE4

PPR41 PPR40

PIC4

PIC5

PIC6

PIF5

PMK5 PISM5 PCSE5

PPR51 PPR50

PIF6

PMK6 PISM6 PCSE6

PPR61 PPR60

310

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-1. Interrupt Control Registers (

××

ICn) (2/3)

Address : 0FFEAH-0FFF5H On reset : 43H R/W

CMIC10 CMIF10 CMMK10 CMISM10 CMCSE10

CMPR101 CMPR100

CMIC11 CMIF11 CMMK11 CMISM11 CMCSE11

CMPR111 CMPR110

××

IFn

Generation of Interrupt Request

No interrupt request (interrupt signal is not generated)

Interrupt request (interrupt signal is generated)

××

MKn

Enables or Disables Interrupt Processing

Enables interrupt processing

Disables interrupt processing

××

ISMn

Specifies Interrupt Processing Format

Vectored interrupt processing/context switching processing

Macro service processing

××

CSEn

Specifies Context Switching Processing

Processed by vectored interrupt

Processed by context switching

××

PRn1

Specifies Priority of Interrupt Request

Priority 0 (highest priority)

Priority 1

Priority 2

Priority 3

××

PRn0

CMIC40 CMIF40 CMMK40 CMISM40 CMCSE40

CMPR401 CMPR400

CMIC41 CMIF41 CMMK41 CMISM41 CMCSE41

CMPR411 CMPR410

SERIC SERIF SERMK SERISM SERCSE

SERPR1 SERPR0

SRIC

SRIF SRMK SRISM SRCSE

SRPR1 SRPR0

CSIIC1 CSIIF1 CSIMK1 CSIISM1 CSICSE1

CSIPR11 CSIPR10

STIC

STIF

STMK STISM STCSE

STPR1 STPR0

SERIC2 SERIF2 SERMK2 SERISM2 SERCSE2

SERPR21 SERPR20

311

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-1. Interrupt Control Registers (

××

ICn) (3/3)

Address : 0FFF6H-0FFF8H On reset : 43H R/W

SRIC2

SRIF2 SRMK2 SRISM2 SRCSE2

SRPR21 SRPR20

CSIIC2 CSIIF2 CSIMK2 CSIISM2 CSICSE2

CSIPR21 CSIPR20

STIC2

STIF2 STMK2 STISM2 STCSE2

STPR21 STPR20

ADIC

ADIF ADMK ADISM ADCSE

ADPR1 ADPR0

××

IFn

Generation of Interrupt Request

No interrupt request (interrupt signal is not generated)

Interrupt request (interrupt signal is generated)

××

MKn

Enables or Disables Interrupt Processing

Enables interrupt processing

Disables interrupt processing

××

ISMn

Specifies Interrupt Processing Format

Vectored interrupt processing/context switching processing

Macro service processing

××

CSEn

Specifies Context Switching Processing

Processed by vectored interrupt

Processed by context switching

××

PRn1

Specifies Priority of Interrupt Request

Priority 0 (highest priority)

Priority 1

Priority 2

Priority 3

××

PRn0

312

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.2 Interrupt mask registers (MK0, MK1)

The MK0 and MK1 are composed of interrupt mask flags. MK0 and MK1 are 16-bit registers which can be manipulated

as a 16-bit unit. MK0 can be manipulated in 8 bit units using MK0L and MK0H, and similarly MK1 can be manipulated using

MK1L and MK1H.

In addition, each bit of the MK0 and MK1L can be manipulated individually with a bit manipulation instruction. Each

interrupt mask flag controls enabling/disabling of the corresponding interrupt request.

When an interrupt mask flag is set (1), acknowledgment of the corresponding interrupt request is disabled.

When an interrupt mask flag is cleared (0), the corresponding interrupt request can be acknowledged as a vectored

interrupt or macro service request.

Each interrupt mask flag in the MK0 and MK1 is the same flag as the interrupt mask flag in the interrupt control register.

The MK0 and MK1 are provided for en bloc control of interrupt masking.

After RESET input, the MK0 and MK1 are set to FFFFH, and all maskable interrupts are disabled.

313

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-2. Format of Interrupt Mask Registers (MK0, MK1)

<Byte access>

<Word access>

Address : 0FFACH-0FFAFH On reset : FFH R/W

MK0L

PMK4 PMK3 PMK2 PMK1 PMK0 OVMK4 OVMK1 OVMK0

××

MKn

Enables or Disables Interrupt Request

Enables interrupt processing

Disables interrupt processing

MK0H

CMMK11 CMMK10 PMK6 PMK5

MK1L

STMK2 SRMK2 SERMK2 STMK SRMK SERMK CMMK41 CMMK40

MK1H

ADMK

Address : 0FFACH, 0FFAEH On reset : FFFFH R/W

MK0

CMMK11 CMMK10 PMK6 PMK5

××

MKn

Enables or Disables Interrupt Request

Enables interrupt processing

Disables interrupt processing

PMK4 PMK3 PMK2 PMK1 PMK0 OVMK4 OVMK1 OVMK0

MK1

ADMK

STMK2 SRMK2 SERMK2 STMK SRMK SERMK CMMK41 CMMK40

314

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.3 In-service priority register (ISPR)

The ISPR shows the priority level of the maskable interrupt currently being serviced and the non-maskable interrupt being

processed. When a maskable interrupt request is acknowledged, the bit corresponding to the priority of that interrupt request

is set (1), and remains set until the service program ends. When a non-maskable interrupt is acknowledged, the bit

corresponding to the priority of that non-maskable interrupt is set (1), and remains set until the service program ends.

When an RETI instruction or RETCS instruction is executed, the bit, among those set (1) in the ISPR, that corresponds

to the highest-priority interrupt request is automatically cleared (0) by hardware.

The contents of the ISPR are not changed by execution of an RETB or RETCSB instruction.

RESET input clears the ISPR register to 00H.

Figure 14-3. Format of In-Service Priority Register (ISPR)

Caution The in-service priority register (ISPR) is a read-only register. The microcontroller may malfunction if

this register is written.

NMIS WDTS

ISPR3 ISPR2 ISPR1 ISPR0

NMIS

NMI Processing Status

NMI interrupt is not accepted.

NMI interrupt is accepted

ISPR

Address : 0FFA8H On reset : 00H R

WDTS

Watchdog Timer Interrupt Processing Status

Watchdog timer interrupt is not accepted.

Watchdog timer interrupt is accepted.

ISPRn

Priority level (n = 0 to 3)

Interrupt of priority level n is not accepted.

Interrupt of priority level n is accepted.

315

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.4 Interrupt mode control register (IMC)

The IMC contains the PRSL flag. The PRSL flag specifies enabling/disabling of nesting of maskable interrupts for which

the lowest priority level (level 3) is specified.

When the IMC is manipulated, the interrupt disabled state (DI state) should be set first to prevent misoperation.

The IMC can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction.

RESET input sets the IMC register to 80H.

Figure 14-4. Format of Interrupt Mode Control Register (IMC)

PRSL

Controls Nesting of Maskable Interrupt

(lowest level)

Interrupts with level 3 (lowest level) can be

nested.

Nesting of interrupts with level 3 (lowest level)

is disabled.

IMC

Address : 0FFAAH On reset : 80H R

316

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.5 Watchdog timer mode register (WDM)

The PRC bit of the WDM specifies the priority of NMI pin input non-maskable interrupts and watchdog timer overflow

non-maskable interrupts.

The WDM can be written to only by a dedicated instruction. This dedicated instruction, MOV WDM, #byte, has a special

code configuration (4 bytes), and a write is not performed unless the 3rd and 4th bytes of the operation code are mutual

complements.

If the 3rd and 4th bytes of the operation code are not complements, a write is not performed and an operand error interrupt

is generated. In this case, the return address saved in the stack area is the address of the instruction that was the source

of the error, and thus the address that was the source of the error can be identified from the return address saved in the

stack area.

If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.

As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler,

RA78K4, only the correct dedicated instruction is generated when MOV WDM, #byte is written), system initialization should

be performed by the program.

Other write instructions (MOV WDM, A, AND WDM, #byte, SET1 WDM.7, etc.) are ignored and do not perform any

operation. That is, a write is not performed to the WDM, and an interrupt such as an operand error interrupt is not generated.

The WDM can be read at any time by a data transfer instruction.

RESET input clears the WDM register to 00H.

Figure 14-5. Format of Watchdog Timer Mode Register (WDM)

Caution The watchdog timer mode register (WDM) can be written only by using a dedicated instruction (MOV

WDM, #byte).

RUN

PRC

WDI2

WDI1

RUN

Specifies Operation of Watchdog Timer

(refer to Figure 10-2).

WDM

Address : 0FFC2H On reset : 00H R/W

PRC

Priority of Watchdog Timer Interrupt Request

Watchdog timer interrupt request

< NMI pin input interrupt request

Watchdog timer interrupt request

> NMI pin input interrupt request

WDI2

Specifies count clock of watchdog

timer (refer to Figure 10-2).

WDI1

317

CHAPTER 14 INTERRUPT FUNCTIONS

14.3.6 Program status word (PSW)

The PSW is a register that holds the current status regarding instruction execution results and interrupt requests. The

IE flag that sets enabling/disabling of maskable interrupts is mapped in the low-order 8 bits of the PSW (PSWL).

PSWL can be read or written to with an 8-bit manipulation instruction, and can also be manipulated with a bit manipulation

instruction or dedicated instruction (EI/DI).

When a vectored interrupt is acknowledged or a BRK instruction is executed, PSWL is saved to the stack and the IE

flag is cleared (0). PSWL is also saved to the stack by the PUSH PSW instruction, and is restored from the stack by the

RETI, RETB and POP PSW instructions.

When context switching or a BRKCS instruction is executed, PSWL is saved to a fixed area in the register bank, and

the IE flag is cleared (0). PSWL is restored from the fixed area in the register bank by an RETCSI or RETCSB instruction.

RESET input clears PSWL to 00H.

Figure 14-6. Format of Program Status Word (PSWL)

RSS

P/V

PSWL

On reset : 00H

RSS

Used when executing a normal operation

Enables or Disables Interrupt Accepting

Disables interrupt accepting

Enables interrupt accepting

P/V

Used when executing a normal operation

318

CHAPTER 14 INTERRUPT FUNCTIONS

14.4 Software Interrupt Acknowledgment Operations

A software interrupt is acknowledged in response to execution of a BRK or BRKCS instruction. Software interrupts cannot

be disabled.

14.4.1 BRK instruction software interrupt acknowledgment operation

When a BRK instruction is executed, the program status word (PSW), program counter (PC) are saved in that order to

the stack, the IE flag is cleared (0), the vector table (003EH/003FH) contents are loaded into the low-order 16 bits of the

PC, and 0000B into the high-order 4 bits, and a branch is performed (the start of the service program must be in the base

area).

The RETB instruction must be used to return from a BRK instruction software interrupt.

Caution The RETI instruction must not be used to return from a BRK instruction software interrupt.

14.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation

The context switching function can be initiated by executing a BRKCS instruction.

The register bank to be used after context switching is specified by the BRKCS instruction operand.

When a BRKCS instruction is executed, the program branches to the start address of the interrupt service program (which

must be in the base area) stored beforehand in the specified register bank, and the contents of the program status word

(PSW) and program counter (PC) are saved in the register bank.

Figure 14-7. Context Switching Operation by Execution of a BRKCS Instruction

The RETCSB instruction is used to return from a software interrupt due to a BRKCS instruction. The RETCSB instruction

must specify the start address of the interrupt service program for the next time context switching is performed by a BRKCS

instruction. This interrupt service program start address must be in the base area.

Caution The RETCS instruction must not be used to return from a BRKCS instruction software interrupt.

(0 to 7)

7 Transfer

3 Register Bank Switching
(RBS0-RBS2

4 RSS

(

)

1 Save

2 Save
(Bits 8 to 11 of
Temporary Register)

6 Exchange

5 Save

15-0

19-16

0000B

Temporary Register

PSW

319

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-8. Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation)

14.5 Operand Error Interrupt Acknowledgment Operation

An operand error interrupt is generated when the data obtained by inverting all the bits of the 3rd byte of the operand

of an MOV STBC, #byte instruction or LOCATION instruction or an MOV WDM,#byte instruction does not match the 4th

byte of the operand. Operand error interrupts cannot be disabled.

When an operand error interrupt is generated, the program status word (PSW) and the start address of the instruction

that caused the error are saved to the stack, the IE flag is cleared (0), the vector table value is loaded into the program counter

(PC), and a branch is performed (within the base area only).

As the address saved to the stack is the start address of the instruction in which the error occurred, simply writing an

RETB instruction at the end of the operand error interrupt service program will result in generation of another operand error

interrupt. You should therefore either process the address in the stack or inifialize the program by referring to 14.12

Restoring Interrupt Function To Initial State.

19-16

15-0

1 Restoration

3 Transfer

4 Restoration
(To Original
Register Bank)

2 Restoration

PSW

RETCSB Instruction Operand

320

CHAPTER 14 INTERRUPT FUNCTIONS

14.6 Non-Maskable Interrupt Acknowledgment Operation

Non-maskable interrupts are acknowledged even in the interrupt disabled state. Non-maskable interrupts can be

acknowledged at all times except during execution of the service program for an identical non-maskable interrupt or a non-

maskable interrupt of higher priority.

The relative priorities of non-maskable interrupts are set by the PRC bit of the watchdog timer mode register (WDM) (refer

to 14.3.5 Watchdog timer mode register (WDM)).

Except in the cases described in 14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending,

a non-maskable interrupt request is acknowledged immediately. When a non-maskable interrupt request is acknowledged,

the program status word (PSW) and program counter (PC) are saved in that order to the stack, the IE flag is cleared (0),

the in-service priority register (ISPR) bit corresponding to the acknowledged non-maskable interrupt is set (1), the vector

table contents are loaded into the PC, and a branch is performed. The ISPR bit that is set (1) is the NMIS bit in the case

of a non-maskable interrupt due to edge input to the NMI pin, and the WDTS bit in the case of watchdog timer overflow.

When the non-maskable interrupt service program is executed, non-maskable interrupt requests of the same priority as

the non-maskable interrupt currently being executed and non-maskable interrupts of lower priority than the non-maskable

interrupt currently being executed are held pending. A pending non-maskable interrupt is acknowledge after completion

of the non-maskable interrupt service program currently being executed (after execution of the RETI instruction). However,

even if the same non-maskable interrupt request is generated more than once during execution of the non-maskable interrupt

service program, only one non-maskable interrupt is acknowledged after completion of the non-maskable interrupt service

program.

321

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-9. Operations of Non-Maskable Interrupt Request Acknowledgment (1/2)

(a) When a new NMI request is generated during NMI service program execution

Main Routine

NMI Request

(NMIS = 1)

NMI request held pending since NMIS = 1

Pending NMI request is serviced

(b) When a watchdog timer interrupt request is generated during NMI service program execution (when the

watchdog timer interrupt priority is higher (when PRC in the WDM = 1))

Main Routine

NMI Request

Watchdog
Timer Interrupt
Request

322

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-9. Operations of Non-Maskable Interrupt Request Acknowledgment (2/2)

(c) When a watchdog timer interrupt request is generated during NMI service program execution (when the

NMI interrupt priority is higher (when PRC in the WDM = 0))

Main Routine

NMI Request

Watchdog

Timer

Interrupt

Request

Watchdog timer interrupt is kept
pending because PRC = 0

Pending watchdog timer interrupt is processed

(d) When an NMI request is generated twice during NMI service program execution

Main Routine

NMI Request

NMI

Request

Held pending since NMI service
program is being executed

NMI
Request

Held pending since NMI service
program is being executed

NMI request was generated more than
once, but is only acknowledged once

323

CHAPTER 14 INTERRUPT FUNCTIONS

Cautions 1. Macro service requests are acknowledged and serviced even during execution of a non-maskable

interrupt service program. If you do not want macro service processing to be performed during

a non-maskable interrupt service program, you should manipulate the interrupt mask register in

the non-maskable interrupt service program to prevent macro service generation.

2. The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt

acknowledgment will not be performed normally if a different instruction is used.

3. Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service

program execution (except when a high non-maskable interrupt request is generated during

execution of a low-priority non-maskable interrupt service program) and for a certain period after

execution of the special instructions shown in 14.9. Therefore, a non-maskable interrupt will be

acknowledged even when the stack pointer (SP) value is undefined, in particular after reset release,

etc. In this case, depending on the value of the SP, it may happen that the program counter (PC)

and program status word (PSW) are written to the address of a write-inhibited special function

register (SFR) (refer to Table 3-6 in 3.8 Special Function Registers (SFRs)), and the CPU becomes

deadlocked, or an unexpected signal is output from a pin, or the PC and PSW are written to an

address in which RAM is not mounted, with the result that the return from the non-maskable

interrupt processing program is not performed normally and asoftware upsets occurs.

Therefore, the program following RESET release must be as shown below.

CSEG AT 0

STRT

CSEG BASE

STRT:

LOCATION

0FH; or LOCATION 0

MOVG SP, #imm24

324

CHAPTER 14 INTERRUPT FUNCTIONS

14.7 Maskable Interrupt Acknowledgment Operation

A maskable interrupt can be acknowledged when the interrupt request flag is set (1) and the mask flag for that interrupt

is cleared (0). When processing is performed by macro service, the interrupt is acknowledged and processed by macro

service immediately. In the case of vectored interruption and context switching, an interrupt is acknowledged in the interrupt

enabled state (when the IE flag is set (1)) if the priority of that interrupt is one for which acknowledgment is permitted.

If maskable interrupt requests are generated simultaneously, the interrupt for which the highest priority is specified by

the priority specification flag is acknowledged. If the interrupts have the same priority specified, they are acknowledged

in accordance with their default priorities.

A pending interrupt is acknowledged when a state in which it can be acknowledged is established.

The interrupt acknowledgment algorithm is shown in Figure 14-10.

325

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-10. Algorithm of Interrupt Acknowledgment Processing

××

IF = 1

××

MK = 0

××

ISM = 1

××

CSE = 1

IE = 1

Higher priority

than interrupt currently

being serviced?

Higher priority

than other existing interrupt

requests?

Highest default

priority among interrupt

requests of same

priority?

Vectored interrupt

generation

Interrupt Request?

Yes

Interrupt Mask Released?

Yes

Interrupt Enabled State?

Macro Service?

Interrupt request

held pending

Yes

Context Switching?

Context switching

generation

Yes

Highest

default priority among

macro service

requests?

Macro service

processing execution

Interrupt request

held pending

Yes

326

CHAPTER 14 INTERRUPT FUNCTIONS

14.7.1 Vectored interrupt

When a vectored interrupt maskable interrupt request is acknowledged, the program status word (PSW) and program

counter (PC) are saved in that order to the stack, the IE flag is cleared (0) (the interrupt disabled state is set), and the in-

service priority register (ISPR) bit corresponding to the priority of the acknowledged interrupt is set (1). Also, data in the

vector table predetermined for each interrupt request is loaded into the PC, and a branch is performed. The return from

a vectored interrupt is performed by means of the RETI instruction.

Caution When a maskable interrupt is acknowledged by vectored interrupt, the RETI instruction must be used

to return from the interrupt. Subsequent interrupt acknowledgment will not be performed normally if

a different instruction is used.

14.7.2 Context switching

Initiation of the context switching function is enabled by setting (1) the context switching enable flag of the interrupt control

When an interrupt request for which the context switching function is enabled is acknowledged, the register bank specified

by 3 bits of the lower address (even address) of the corresponding vector table address is selected.

The vector address stored beforehand in the selected register bank is transferred to the program counter (PC), and at

the same time the contents of the PC and program status word (PSW) up to that time are saved in the register bank and

a branch is made to the interrupt service program.

Figure 14-11. Context Switching Operation by Generation of an Interrupt Request

(0 to 7)

7 Transfer

6 Exchange

2 Save
(Temporary
Register
Bit 8-11)

5 Save

1 Save

15-0

19-16

0000B

Temporary Register

PSW

3 Register Bank Switching

(RBS0-RBS2

Vector Table

RSS

(

)

327

CHAPTER 14 INTERRUPT FUNCTIONS

The RETCS instruction is used to return from an interrupt that uses the context switching function. The RETCS instruction

must specify the start address of the interrupt service program to be executed when that interrupt is acknowledged next.

This interrupt service program start address must be in the base area.

Caution The RETCS instruction must be used to return from an interrupt serviced by context switching.

Subsequent interrupt acknowledgment will not be performed normally if a different instruction is used.

Figure 14-12. Return from Interrupt that Uses Context Switching by Means of RETCS Instruction

19-16

15-0

2 Restoration

4 Restoration
(To Original
Register Bank)

PSW

RETCS Instruction Operand

3 Transfer

1 Restoration

328

CHAPTER 14 INTERRUPT FUNCTIONS

14.7.3 Maskable interrupt priority levels

The

PD784054 performs multiple interrupt processing in which an interrupt is acknowledged during processing of

another interrupt. Multiple interrupts can be controlled by priority levels.

There are two kinds of priority control, control by default priority and programmable priority control in accordance with

the setting of the priority specification flag. In priority control by means of default priority, interrupt service is performed in

accordance with the priority preassigned to each interrupt request (default priority) (refer to Table 14-2). In programmable

priority control, interrupt requests are divided into four levels according to the setting of the priority specification flag. Interrupt

requests for which multiple interruption is permitted are shown in Table 14-5.

Since the IE flag is cleared (0) automatically when an interrupt is acknowledged, when multiple interruption is used, the

IE flag should be set (1) to enable interrupts by executing an EI instruction in the interrupt processing program, etc.

Table 14-5. Multiple Interrupt Processing

Priority of Interrupt Currently

ISPR Value

IE Flag in PSW

PRSL in

Acknowledgeable Maskable Interrupts

Being Acknowledged

IMC Register

No interrupt being

00000000

All macro service only

acknowledged

All maskable interrupts

00001000

All macro service only

All maskable interrupts

All macro service

Maskable interrupts specified as

priority 0/1/2

0000

100

All macro service only

All macro service

Maskable interrupts specified as

priority 0/1

0000

××

All macro service only

All macro service

Maskable interrupts specified as

priority 0

0000

×××

All macro service only

Non-maskable interrupts

1000

××××

All macro service only

0100

××××

1100

××××

Remark

: don't care

329

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-13. Examples of Processing When Another Interrupt Request

Is Generated During Interrupt Processing (1/3)

Main routine

Interrupt Request a

(Level 3)

Interrupt

Request b

(Level 2)

Interrupt

Request d

(Level 2)

Interrupt Request e

(Level 2)

Interrupt

Request f

(Level 3)

Interrupt Request g

(Level 1)

a Processing

b Processing

c Processing

d Processing

e Processing

f Processing

g Processing

h Processing

Since interrupt request b has a higher
priority than interrupt request a, and
interrupts are enabled, interrupt
request b is acknowledged.

The priority of interrupt request d is
higher than that of interrupt request c,
but since interrupts are disabled,
interrupt request d is held pending.

Although interrupts are enabled,
interrupt request f is held pending
since it has a lower priority than
interrupt request e.

Although interrupts are enabled,
interrupt request h is held pending
since it has the same priority as
interrupt request g.

Interrupt
Request h
(Level 1)

Interrupt Request c

(Level 3)

330

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-13. Examples of Processing When Another Interrupt Request

Is Generated During Interrupt Processing (2/3)

Main routine

Interrupt Request i

(Level 1)

Interrupt Request k

(Level 2)

Interrupt Request n

(Level 2)

Macro Service
Request j
(Level 2)

i Processing

j Macro Service

k Processing

l Processing

m Processing

n Processing

o Processing

p Processing

The macro service request is
serviced irrespective of interrupt
enabling/disabling and priority.

The interrupt request is held
peding since it has a lower
priority than interrupt request k.
Interrupt request m generated
after interrupt request l has a
higher priority, and is therefore
acknowledged first.

Since processing of interrupt
request n performed in the
interrupt disabled state,
interrupt requests o and p
are held pending.
After interrupt request n
processing, the pending interrupt
requests are acknowledged.
Although interrupt request o
was generated first, interrupt
request p has a higher priority
and is therefore acknowledged
first.

Interrupt
Request l
(Level 3)

Interrupt

Request m

(Level 1)

Interrupt
Request o
(Level 3)
Interrupt
Request p
(Level 1)

331

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-13. Examples of Processing When Another Interrupt Request

Is Generated During Interrupt Processing (3/3)

Notes 1. Low default priority

2. High default priority

Remarks 1. "a" to "z" in the figure are arbitrary names used to differentiate between the interrupt requests and macro

service requests.

2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt requests.

Main routine

Interrupt Request q

Level 3)

Interrupt

Request s

(Level 1)

Interrupt Request u

(Level 0)

Interrupt
Request v
(Level 0)

w Macro Service

q Processing r Processing

s Processing

t Processing

u Processing

v Processing

x Processing

y Processing

z Processing

Interrupt Request x

(Level 1)

Interrupt
Request r
(Level 2)

Interrupt
Request t
(Level 0)

Interrupt
Request y

Note 1

(Level 2)

Interrupt

Request w

(Level 3)

Multiple acknowledgment of levels 3 to 0. If
the PRSL bit of the IMC is set (1), only
macro service requests and non-maskable
interrupts generate nesting beyond this.
If the PRSL bit of the IMC is cleared (0),
level 3 interrupts can also be nested during
level 3 interrupt processing (refer to Figure
14-15).

Even though the interrupt enabled state is
set during processing of level 0 interrupt
request u, the interrupt request is not
acknowledged but held pending even
though its priority is 0. However, the macro
service request is acknowledged and
processed irrespective of its level and even
though there is a peding interrupt with a
higher priority level.

Pending interrupt requests y and z are
acknowledged after servicing of interrupt
request x. As interrupt requests y and z
have the same priority level, interrupt
request z which has the higher default
priority is acknowledged first, irrespective
of the order in which the interrupt requests
were generated.

Interrupt

Request z

Note 2

(Level 2)

332

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-14. Examples of Processing of Simultaneously Generated Interrupts

Remark

"a" to "f" in the figure are arbitrary names used to differentiate between the interrupt requests and macro service

requests.

Main Routine

Interrupt Request a (Level 2)

(Level 3)

(Level 1)

Macro Service Request b

Macro Service Request c

Interrupt Request d

Interrupt Request e

Macro Service Request f

Default Priority Order

a > b > c > d > e > f

Macro Service Request b Processing

Macro Service Request c Processing

Macro Service Request f Processing

Interrupt Request d Processing

Interrupt Request e Processing

Interrupt Request a Processing

· When requests are generated

simultaneously, they are
acknowledged in order starting
with macro service.

· Macro service requests are

acknowledged in default priority
order (b/c/f) (not dependent
upon the programmable priority
order).

· As interrupt requests are

acknowledged in high-to-low
priority level order, d and e are
acknowledged first.

· As d and e have the same

prority level, the interrupt
request with the higher default
priority, d, is acknowledged
first.

333

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-15. Differences in Level 3 Interrupt Acknowledgment According

to Setting of Interrupt Mode Control Register (IMC)

Notes 1. Low default priority

2. High default priority

Remarks 1. "a" to "f" in the figure are arbitrary names used to differentiate between the interrupt requests and

macro service requests.

2. High/low default priorities in the figure indicate the relative priority levels of the two interrupt

requests.

Main Routine

Interrupt Request a

(Level 3)

Interrupt

Request b

(Level 3)

a Processing

b Processing

Interrupt Request c

(Level 3)

Interrupt

Request d

(Level 3)

c Processing

d Processing

Interrupt Request e

Note 1

(Level 3)

Interrupt Request f

Note 2

(Level 3)

f Processing

e Processing

IMC

80H

Main Routine

IMC

00H

Main Routine

The PRSL bit of the IMC is set to 1, and
nesting between level 3 interrupts is
disabled.

Even though interrupts are enabled, interrupt
request b is held pending since it has the
same priority as interrupt request a.

The PRSL bit of the IMC is set to 0, so that a
level 3 interrupt is acknowledged even during
level 3 interrupt processing (nesting is
possible).

Since level 3 interrupt request c is being
processed in the interrupt enabled state and
PRSL = 0, interrupt request d, which is also
level 3, is acknowledged.

As interrupt request 3 and f are both of the
same level, the one with the higher default
priority, f, is acknowledged first.
When the interrupt enabled state is set
during processing of interrupt request f,
pending interrupt request e is acknowledged
since PRSL = 0.

IMC

00H

Bit 3 (ISPR3) of the in-service priority register (ISPR)
is cleared by returning from processing d.

334

CHAPTER 14 INTERRUPT FUNCTIONS

14.8 Macro Service Function

14.8.1 Outline of macro service function

Macro service is one method of processing interrupts. With a normal interrupt, the program counter (PC) and program

status word (PSW) are saved, and the start address of the interrupt service program is loaded into the PC, but with macro

service, different processing (mainly data transfers) is performed instead of this processing. This enables interrupt requests

to be responded to quickly, and moreover, since transfer processing is faster than processing by a program, the processing

time can also be reduced.

Also, since a vectored interrupt is generated after processing has been performed the specified number of times, another

advantage is that vectored interrupt programs can be simplified.

Figure 14-16. Differences between Vectored Interrupt and Macro Service Processing

Notes 1. When register bank switching is used, and an initial value has been set in the register beforehand

2. Register bank switching by context switching, saving of PC and PSW

3. Register bank, PC and PSW restoration by context switching

4. PC and PSW saved to the stack, vector address loaded into PC

14.8.2 Types of macro service

Macro service can be used with the 21 kinds of interrupt shown in Table 14-6 (18 of which can be used simultaneously).

There are seven kinds of operation mode, which can be used to suit the application.

Macro Service

Context Switching

Note 1

Vectored Interrupt

Note 1

Vectored Interrupt

Interrupt Request Generation

Main Routine

Macro Service

Processing

Main Routine

Note 2

Note 4

Note 3

Interrupt

Processing

Main Routine

SEL

RBn

Interrupt

Processing

Restore

PC, PSW

Save

General

Registers

Initialize

General

Registers

Interrupt

Processing

Restore

General

Registers

Main Routine

Restore

PC & PSW

Main Routine

335

CHAPTER 14 INTERRUPT FUNCTIONS

Table 14-6. Interrupts for Which Macro Service Can Be Used

Default

Interrupt Request Generation Source

Generating Unit

Macro Service Control

Priority

Word Address

0 (highest)

INTOV0 (overflow of timer 0)

Timer 0

0FE06H

INTOV1 (overflow of timer 1)

Timer 1

0FE08H

INTOV4 (overflow of timer 4)

Timer 4

0FE0AH

INTP0 (pin input edge detection)

Edge detection

0FE0CH

INTCC00 (TM0-CC00 match signal generation)

Timer 0

INTP1 (pin input edge detection)

Edge detection

0FE0EH

INTCC01 (TM0-CC01 match signal generation)

Timer 0

INTP2 (pin input edge detection)

Edge detection

0FE10H

INTCC002 (TM0-CC02 match signal generation)

Timer 0

INTP3 (pin input edge detection)

Edge detection

0FE12H

INTCC03 (TM0-CC03 match signal generation)

Timer 0

INTP4 (pin input edge detection)

Edge detection

0FE14H

INTP5 (pin input edge detection)

Edge detection

0FE16H

INTP6 (pin input edge detection)

Edge detection

0FE18H

INTCM10 (TM1-CM10 match signal generation)

Timer 1

0FE1AH

INTCM11 (TM1-CM11 match signal generation)

Timer 1

0FE1CH

INTCM40 (TM4-CM40 match signal generation)

Timer 4

0FE26H

INTCM41 (TM4-CM41 match signal generation)

Timer 4

0FE28H

INTSER (UART0 reception error)

Asynchronous serial interface 0

0FE2AH

INTSR (UART0 reception end)

0FE2CH

INTCSI1 (3-wire serial I/O1 transfer end)

3-wire serial I/O1

INTST (UART0 transmission end)

Asynchronous serial interface 0

0FE2EH

INTSER2 (UART2 reception error)

Asynchronous serial interface 2

0FE30H

INTSR2 (UART2 reception end)

0FE32H

INTCSI2 (3-wire serial I/O2 transfer end)

3-wire serial I/O2

INTST2 (UART2 transmission end)

Asynchronous serial interface 2

0FE34H

20 (lowest)

INTAD (A/D conversion end)

A/D converter

0FE36H

Remarks 1. The default priority is a fixed number. This indicates the order of priority when macro service requests

are generated simultaneously,

2. The INTSR and INTCSI1 interrupts are generated by the same hardware (they cannot both be used

simultaneously). Therefore, although the same hardware is used for the interrupts, two names are

provided, for use in each of the two modes. The same applies to INTSR2 and INTCSI2.

336

CHAPTER 14 INTERRUPT FUNCTIONS

The macro service operation is performed in the following seven modes:

(1) Counter mode: EVTCNT

In this mode, each time an interrupt request has been generated, the macro service counter (MSC) is incremented

(+1) or decremented (1). When MSC reaches 00H, a vectored interrupt request is generated.

This mode is used to divide the number of times an interrupt request is generated.

(2) Block transfer mode: BLKTRS

Each time an interrupt request has been generated, 1-byte or 1-word data is transferred between a special function

number of times, a vectored interrupt request is generated.

The buffer with which data is to be transferred is limited to the addresses 0FD00H through 0FEFFH

Note

of the main

RAM.

This mode is easy to specify and is used for high-speed transfer of a small amount of data.

Note When the LOCATION 0 instruction is executed. FFD00H through FFEFFH when the LOCATION 0FH

instruction is executed.

(3) Block transfer mode (with memory pointer): BLKTRS-P

Like the block transfer mode, 1-byte or 1-word data is transferred between an SFR specified by SFR.PTR and buffer

each time an interrupt request has been generated, and a vectored interrupt request is generated when data has

been transferred the specified number of times.

The buffer with which data is to be transferred is specified by the memory pointer (MEM.PTR) (data can be transferred

with the entire 1M-byte memory).

This mode is a general-purpose type of the block transfer mode and is used to transfer a large quantity of data.

(4) Data differential mode: DTADIF

Each time an interrupt request has been generated, the difference between the current value of an SFR specified

by SFR.PRT and the "value immediately before" stored in memory is written to the buffer, and the current value is

used as the "value immediately before".

When data has been transferred the specified number of times, a vectored interrupt request is generated.

The buffer with which data is to be transferred is limited to the main RAM of the addresses 0FD00H through

0FEFFH

Note

This mode is used to measure the cycle of an input pulse, or width of a pulse by using a capture register.

Note When the LOCATION 0 instruction is executed. FFD00H through FFEFFH when the LOCATION 0FH

instruction is executed.

(5) Data differential mode (with memory pointer): DTADIF-P

Like the data differential mode, each time an interrupt request has been generated, the difference between the

current value of an SFR specified by SFR.PTR and the "value immediately before" stored in memory is written to

the buffer, and the current value is used as the "value immediately before".

When data has been transferred the specified number of times, a vectored interrupt request is generated.

The buffer with which data is to be transferred is specified by the memory pointer (MEM.PTR) (the entire 1M-byte

memory can be specified).

This mode is a general-purpose type of the data differential mode, and is used to transfer a large quantity of data.

337

CHAPTER 14 INTERRUPT FUNCTIONS

(6) CPU monitor mode 0: SELF0

Each time an interrupt request has been generated, the internal operation of the CPU is checked. If each block

operates normally, a value resulting from subtracting 10 from the initial data is transferred to an SFR specified by

SFR.PTR.

This mode is used for self-check of the CPU at initialization.

(7) CPU monitor mode 1: SELF1

Each time an interrupt request has been generated, the internal operation of the CPU is checked. If each block

operates normally, a value resulting from subtracting 8 from the initial data is transferred to an SFR specified by

SFR.PTR.

This mode is used for self-check of the CPU during normal operation.

338

CHAPTER 14 INTERRUPT FUNCTIONS

14.8.3 Basic operation of macro service (except CPU monitor modes 0 and 1)

The macro service function is to transfer data between the special function register area and memory space by hardware,

using an interrupt request.

When a macro service request is generated, the CPU temporarily stops program execution, and automatically transfers

1/2-byte data between a special function register (SFR) and memory. When data transfer has been completed, an interrupt

request flag is reset (0), and the CPU starts program execution again. Data is transferred the number of times set to the

macro service counter (MSC) and then a vectored interrupt request is generated.

Figure 14-17. Example of Macro Service Processing Sequence

Unlike other interrupt processing, processing using the macro service function is automatically performed without starting

an interrupt processing program. Therefore, operations such as branching to an interrupt service routine, saving/restoring

registers, and returning from the interrupt service routine are not performed. This means that the service time of the CPU

can be improved and that the number of program steps can be decreased.

When macro service processing is executed, the status before execution of the macro service processing, such as the

contents of the general-purpose registers and instruction queue of the CPU, are retained.

The interrupt request that specifies the macro service processing is not affected by the status of the IE flag in the program

status word (PSWL). The macro service processing can be executed even in the interrupt disabled status or while an

interrupt processing program is executed. It is disabled only when the corresponding bit in the interrupt mask registers (MK0,

MK1) is set (1).

If two or more macro service requests are issued at the same time, the sequence in which the macro service requests

are processed is determined by the default priority. Until all the macro service requests are processed, instructions are

not executed.

The

PD784054 supports macro service processing for all the internal interrupt requests.

Basically, the macro service processing executes the following two operations:

Data transfer from memory to special function register (SFR)

Data transfer from special function register (SFR) to memory

Generation of Interrupt Request

That Executes Mocro Service Processing

Executes macro service

processing

MSC

MSC _ 1

; Transfers data, controls real-time output port

; Decrements (_1) macro service counter (MSC)

YES

MSC = 0?

Macro Service Enable Flag

Interrupt Request Flag

Generation of Vectored Interrupt Request

Execution of Next Instruction

339

CHAPTER 14 INTERRUPT FUNCTIONS

14.8.4 Operation on completion of macro servicing (except CPU monitor modes 0 and 1)

The macro service performs processing the number of times specified during other program is executed. When the

processing has been performed the specified number of times (when the macro service counter (MSC) has reached 0), the

macro service is completed.

Figure 14-18. Operation on Completion of Macro Service

Caution If data is transmitted with UART by using the macro service, a vectored interrupt request is generated

two times (refer to 12.2.8 Transmitting/receiving data with macro service).

Main Routine

Macro Service Request

Last Macro Service Request

Macro Service Processing

Interrupt Request Service on
Completion of Macro Service

Other Interrupt Processing

Macro Service
Processing

Interrupt Request Processing on
Completion of Macro Service

Other Interrupt Request

Interrupt request is generated and
accepted after completion of macro
service (MSC = 0).

If last macro service is executed on
completion of macro service while
other interrupt processing is under execution,
last macro service is kept pending until
interrupt request is accepted.

Last Macro
Service Request

340

CHAPTER 14 INTERRUPT FUNCTIONS

14.8.5 Macro service control register

(1) Macro service control word

The macro service control word consists of a macro service mode register that controls the macro service function,

and a macro service channel pointer. It is located in the address space from 0FE06H through 0FE37H

Note

in the

main RAM area (refer to Figure 14-20).

Figure 14-19 shows the basic configuration of the macro service control word.

Note When the LOCATION 0 instruction is executed. FFE06H through FFE37H when the LOCATION 0FH

instruction is executed.

Figure 14-19. Basic Configuration of Macro Service Control Word

The macro service mode register sets a macro service processing mode, and the macro service channel pointer

specifies the address of the macro service channel.

To perform macro service processing, a value must be set in advance to the macro service mode register and channel

pointer corresponding to the interrupt request that can specify macro service processing.

Address MSB

LSB

(FE

××

+1)H

Macro Service Channel Pointer

××

Macro Service Mode Register

341

CHAPTER 14 INTERRUPT FUNCTIONS

Figure 14-20. Format of Macro Service Control Word

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Channel Pointer

Mode Register

Address

ADCHP

ADMMD

STCHP2

STMMD2

SRCHP2/CSICHP2

SRMMD2/CSIMMD2

SERCHP2

SERMMD2

STCHP

STMMD

SRCHP/CSICHP1

SRMMD/CSIMMD1

SERCHP

SERMMD

CMCHP41

CMMMD41

CMCHP40

CMMMD40

CMCHP11

CMMMD11

CMCHP10

CMMMD10

PCHP6

PMMD6

PCHP5

PMMD5

PCHP4

PMMD4

PCHP3

PMMD3

PCHP2

PMMD2

PCHP1

PMMD1

PCHP0

PMMD0

OVCHP4

OVMMD4

OVCHP1

OVMMD1

OVCHP0

OVMMD0

Reserved Word

INTAD

INTST2

INTSR2/INTCSI2

INTSER2

INTST

INTSR/INTCSI1

INTSER

INTCM41

INTCM40

INTCM11

INTCM10

INTP6

INTP5

INTP4

INTP3

INTP2

INTP1

INTP0

INTOV4

INTOV1

INTOV0

Cause

342

CHAPTER 14 INTERRUPT FUNCTIONS

(2) Macro service mode register

The macro service mode register is an 8-bit register that specifies the operation of the macro service. This register

is mapped to the main RAM area as a part of the macro service control word (refer to Figure 14-19)

14.8.6 Macro service mode

The operation of the macro service is specified by using the macro service mode register. The macro service mode is

specified by the low-order 6 bits of the macro service mode register, and is divided into groups 0 to 2.

Group 0 ... Type with only control word and without channel

Group 1 ... Type with both control word and channel

Group 2 ... Macro service for monitoring CPU

The high-order 2 bits of the macro service mode register of groups 0 and 1 function as a subcommand (refer to Table

14-7).

14.8.7 Operation of macro service

The operation of the macro service is performed in the following seven modes:

Table 14-7. Classification of Macro Service Mode

Group

Macro Service Mode Register

Function

Group 0

CC000001

Counter mode

EVTCNT

Group 1

CC010011

Block transfer mode

BLKTRS

CC010100

Block transfer mode (with memory pointer)

BLKTRS-P

10011001

Data differential mode

DTADIF

10011010

Data differential mode (with memory pointer)

DTADIF-P

Group 2

10101011

CPU monitor mode 0

SELF0

10001011

CPU monitor mode 1

SELF1

The most significant bit (MSB) C of the macro service mode registers for BLKTRS and BLKTRS-P indicates the length

of the data to be handled.

When C = 0: byte data

When C = 1: word data

BLKTRS and BLKTRS-P are expressed here in terms of byte buffers. When word data is specified, read byte buffer as

word buffer.

343

CHAPTER 14 INTERRUPT FUNCTIONS

(1) Counter mode: EVCNT

[Macro service control word]

[Operation]

Increments (+1) or decrements (1) the macro service counter (MSC) each time a macro service has been

generated. When the value of MSC has reached 00H (overflow), a vectored interrupt request is generated.

Table 14-8. Specifying Operation of Counter Mode

Operation

Increment

Decrement

Setting prohibited

In this mode, the macro service function serves as a counter that divides the number of times the interrupt request

is generated.

Example

To divide the number of times the INTOV0 interrupt request has been generated by five by using

the macro service

[Usage]

Event counter, measurement of number of times of capture

MSB

LSB

MSC

CC000001

High-Order Address

Low-Order Address

05H

01000001

0 F E 0 7 H

0 F E 0 6 H

344

CHAPTER 14 INTERRUPT FUNCTIONS

(2) Block transfer mode: BLKTRS

[Macro service control word]

[Operation]

Specifies an SFR pointer (SFR.PTR) by using a channel pointer (CH.PTR). Addresses a buffer by using CH.PTR

and the macro service counter (MSC).

Data is transferred between the SFR specified by SFR.PTR and buffer, starting from buffer 1.

Each time transfer has been completed, MSC is decremented (1). When MSC has reached 0, a vectored

interrupt request is generated.

Table 14-9. Specifying Operation in Block Transfer Mode

Operation

Transfer Data

Buffer Address

Buffer

SFR

Byte

(Contents of CH.PTR) (Contents of MSC) 1

SFR

buffer

Buffer

SFR

Word

(Contents of CH.PTR) (Contents of MSC

2) 1

SFR

buffer

SFR. PTR

MSC

Buffer N

Buffer 2

Buffer 1

CH. PTR

CC010011

MSC = 1

MSC = N _ 1

MSC = N

MSB

LSB

High-Order Address

Low-Order Address

345

CHAPTER 14 INTERRUPT FUNCTIONS

Example

To transfer the contents of port 1 (P1) (0FF01H) to a buffer by using the INTOV1 interrupt request

[Usage]

Data transmission/reception with serial interface

01H

03H

Buffer 3

Buffer 2

Buffer 1

51H

00010011

346

CHAPTER 14 INTERRUPT FUNCTIONS

(3) Block transfer mode (with memory pointer): BLKTRS-P

[Macro service control word]

[Operation]

An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR). Data is transferred between an

SFR specified by the SFR.PTR and the buffer addressed by the memory pointer (MEM.PTR), starting from

buffer 1.

On completion of transferring byte data, the MEM.PTR is incremented (+1). On completion of transferring word

data, the MEM.PTR is incremented (+2). Each time transfer has been completed, the macro service counter

(MSC) is decremented (1). When MSC = 0, a vectored interrupt request is generated.

Table 14-10. Specifying Operation in Block Transfer Mode (with memory pointer)

Operation

Transfer Data

Buffer

SFR

Byte

SFR

buffer

Buffer

SFR

Word

SFR

buffer

SFR. PTR

MSC

MEM. PTR

CH. PTR

CC010100

MSB

LSB

High-Order Address

Low-Order Address

Buffer N

Buffer 2

Buffer 1

MSC = 1

MSC = N _ 1

MSC = N

347

CHAPTER 14 INTERRUPT FUNCTIONS

Example

To transfer the contents of the serial receive buffer: UART0 (RXB) (0FF8CH) to a buffer by using

the INTSR interrupt request

[Usage]

Data transmission/reception with serial interface

8CH

03H

00H

FCH

80H

50H

00010100

Buffer 3

Buffer 2

Buffer 1

RXB

2nd Time

1st Time

3rd Time

348

CHAPTER 14 INTERRUPT FUNCTIONS

(4) Data differential mode: DTADIF

[Macro service control word]

[Operation]

An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR), and a buffer is addressed by the CH.PTR

and macro service counter (MSC).

The difference between the current value of the SFR (including capture registers) specified by the SFR.PTR

and the "value immediately before" is written to the buffer. This current value of the SFR is used as the "value

immediately before". Writing data is started from buffer 1.

Each time data has been written, the MSC is decremented (1). When MSC = 0, a vectored interrupt request

is generated.

The buffer address is determined as follows:

(Buffer address) = (Contents of CH.PTR) (Contents of MSC

2) 3

SFR. PTR

MSC

_ 1

MSB

LSB

High-Order Address

Low-Order Address

CH. PTR

10011001

Buffer N

Buffer 2

Buffer 1

MSC = 1

MSC = N _ 1

MSC = N

Value Immediately

Before

349

CHAPTER 14 INTERRUPT FUNCTIONS

Example

To write the difference between the capture/compare register 00 (CC00) (0FF12H) and the "value

immediately before) to the buffer by using the INTP0 input signal as a trigger. The cycle of the INTP0

input signal is measured by using the difference in the vectored interrupt processing routine.

[Usage]

To measure cycles and pulse widths by using a capture register

Cautions 1. Do not clear the macro service counter (MSC) to 00H.

2. Initialize the "value immediately before" (with dummy data) in advance.

3. Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR).

12H

03H

00H

_ 1

61H

10011001

Buffer 3

Buffer 2

Buffer 1

350

CHAPTER 14 INTERRUPT FUNCTIONS

(5) Data differential mode (with memory pointer): DTADIF-P

[Macro service control word]

[Operation]

An SFR pointer (SFR.PTR) is specified by a channel pointer (CH.PTR), and a buffer is addressed by the memory

pointer (MEM.PTR) and macro service counter (MSC).

The difference between the current value of the SFR (including capture registers) specified by the SFR.PTR

and the "value immediately before" is written to the buffer. This current value of the SFR is used as the "value

immediately before". Writing data is started from buffer 1.

Each time data has been written, the MSC is decremented (1). When MSC = 0, a vectored interrupt request

is generated.

The MEM.PTR is not affected.

The buffer address is determined as follows:

(Buffer address) = (Contents of MEM.PTR) (Contents of MSC

2) + 2

SFR. PTR

MSC

MEM. PTR

MSB

LSB

High-Order Address

Low-Order Address

CH. PTR

10011010

Buffer N

Buffer 2

Buffer 1

MSC = 1

MSC = N _ 1

MSC = N

Value Immediately

Before

351

CHAPTER 14 INTERRUPT FUNCTIONS

Example

To write the difference between the capture/compare register 00 (CC00) (0FF12H) and the "value

immediately before" to the buffer by using the INTP0 input signal as a trigger. The cycle of the INTP0

input signal is measured by using the difference in the vectored interrupt routine.

[Usage]

To measure cycles and pulse widths by using a capture register

Cautions 1. Do not clear the macro service counter (MSC) to 00H.

2. Initialize the "value immediately before" (with dummy data) in advance.

3. Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR).

12H

03H

00H

FCH

80H

61H

10011010

Buffer 3

Buffer 2

Buffer 1

352

CHAPTER 14 INTERRUPT FUNCTIONS

(6) CPU monitor mode 0: SELF0

[Macro service control word]

[Operation]

Checks the internal operation of the CPU. The items to be checked are as follows:

Writing to program status word (PSW)

Stack pointer (SP)

Main RAM

Main RAM addressing

Compare operation

If the CPU is operating normally, the value resulting from subtracting 10 from the initial data is transferred to

an SFR specified by the SFR pointer (SFR.PTR). If an abnormality of the CPU is detected, a value different

from that transferred during normal operation is transferred.

After completion of this macro service, the contents of the main RAM and the value of SP are not destroyed,

but the value of PSW is set to 0x00H.

Therefore, this macro service must be executed when initialization is performed. After that, use CPU monitor

mode 1 to be explained next.

MSB

LSB

High-Order Address

Low-Order Address

CH. PTR

10101011

Initial Data

SFR. PTR

353

CHAPTER 14 INTERRUPT FUNCTIONS

(7) CPU monitor mode 1: SELF1

[Macro service control word]

[Operation]

Checks the internal operation of the CPU. The items to be checked are as follows:

Stack pointer (SP)

Main RAM

Main RAM addressing

Compare operation

If the CPU is operating normally, the value resulting from subtracting 8 from the initial data is transferred to an

SFR specified by the SFR pointer (SFR.PTR). If an abnormality of the CPU is detected, a value different from

that transferred during normal operation is transferred.

After completion of this macro service, the contents of the main RAM and the value of SP are not destroyed.

MSB

LSB

High-Order Address

Low-Order Address

CH. PTR

10001011

Initial data

SFR. PTR

354

CHAPTER 14 INTERRUPT FUNCTIONS

14.9 When Interrupt Request and Macro Service Are Temporarily Held Pending

When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred for

8 system clock cycles. However, software interrupts are not deferred.

BRK

BRKCS

RETCS

RETCSB !addr16

RETI

RETIB

LOCATION 0H or LOCATION 0FH

POP PSW

POPU post

MOV PSWL, A

MOV PSWL, #byte

MOVG SP, #imm24

Write instruction and bit manipulation instruction to an interrupt control register

Note

, or the MK0, MK1L, IMC or ISPR

PSW bit manipulation instruction

(Excluding the BT PSWL. bit, $addr20, BF PSWL. bit, $addr20, BT PSWH. bit, $addr20, BF PSWH. bit, $addr20, SET1

CY, NOT1 CY, and CLR1 CY instructions)

Note

Interrupt control registers: OVIC0, OVIC1, OVIC4, PIC0-PIC6, CMIC10, CMIC11, CMIC40, CMIC41, SERIC,

SRIC, CSIIC1, STIC, SERIC2, SRIC2, CSIIC2, STIC2, ADIC

355

CHAPTER 14 INTERRUPT FUNCTIONS

Cautions 1. When an interrupt related register is polled using a BF instruction, etc., the branch destination of

that BR instruction, etc., should not be that instruction. If a program is written in which a branch

is made to that instruction itself, all interrupts and macro service requests will be held pending

until a condition whereby a branch is not made by that instruction arises.

Bad Example

LOOP : BF PIC0.7, $LOOP

All interrupts and macro service requests are held pending until

PIC0.7 is 1.

× × ×

Interrupts and macro service requests are not serviced until

after execution of the instruction following the BF instruction.

Good Example (1)

LOOP : NOP

BF PIC0.7, $LOOP

Interrupts and macro service requests are serviced after execu

tion of the NOP instruction, so that interrupts are never held

pending for a long period.

Good Example (2)

LOOP : BT PIC0.7, $NEXT

Using a BTCLR instruction instead of a BT instruction has the

advantage that the flag is cleared (0) automatically.

BR $LOOP

Interrupts and macro service requests are serviced after execu-

tion of the BR instruction, so that interrupts are never held

pending for a long period.

2. For a similar reason, if problems are caused by a long pending period for interrupts and macro

service when instructions to which the above applies are used in succession, a time at which

interrupts and macro service requests can be acknowledged should be provided by inserting an

NOP instruction, etc., in the series of instructions.

.
.
.

356

CHAPTER 14 INTERRUPT FUNCTIONS

14.10 Instructions Whose Execution Is Temporarily Suspended by an Interrupt or Macro Service

Execution of the following instructions is temporarily suspended by an acknowledgeable interrupt request or macro

service request, and the interrupt or macro service request is acknowledged. The suspended instruction is resumed after

completion of the interrupt service program or macro service processing.

Temporarily suspended instructions:

MOVM, XCHM, MOVBK, XCHBK

CMPME, CMPMNE, CMPMC, CMPMNC

CMPBKE, CMPBKNE, CMPBKC, CMPBKNC

SACW

14.11 Interrupt and Macro Service Operation Timing

Interrupt requests are generated by hardware. The generated interrupt request sets (1) an interrupt request flag.

When the interrupt request flag is set (1), a time of 8 clocks (0.5

s: f

CLK

= 16 MHz) is taken to determine the priority,

etc.

Following this, if acknowledgment of that interrupt or macro service is enabled, interrupt request acknowledgment

processing is performed when the instruction being executed ends. If the instruction being executed is one which temporarily

defers interrupts and macro service, the interrupt request is acknowledged after the following instruction (refer to 14.9 When

Interrupt Request and Macro Service Are Temporarily Held Pending for deferred instructions).

Figure 14-21. Interrupt Request Generation and Acknowledgment (Unit: Clocks)

Interrupt Request Flag

8 Clocks

Instruction

Interrupt Request Acknowledgment Processing/Macro Service Processing

357

CHAPTER 14 INTERRUPT FUNCTIONS

14.11.1 Interrupt acceptance processing time

To accept an interrupt, the time shown in Table 14-11 is required. After this time has elapsed, the interrupt processing

routine is executed.

Table 14-11. Interrupt Acceptance Processing Time

(unit: clock)

Interrupt Processing Mode

Vectored Interrupt

Context

Vector table

IROM, EMEM16

EMEM8

Switching

Branch Detection

Stack

IRAM

PRAM

EMEM16 EMEM8

IRAM

PRAM

EMEM16 EMEM8

IROM, PRAM

30+2n

38+4n

34+2n

42+4n

EMEM16, EMEM8

31+2n

39+4n

35+2n

43+4n

Remarks 1.

IROM

: internal ROM (with high-speed fetch specified)

IRAM

: internal high-speed RAM

PRAM

: peripheral RAM (only when the LOCATION 0 instruction is executed in the case of branch

destination)

EMEM16 : external memory and internal ROM not specified for high-speed fetch and set to 16-bit bus

width

EMEM8 : external memory and internal ROM not specified for high-speed fetch and set to 8-bit bus

width

n indicates the number of wait states per byte necessary for writing to the stack.

If the vector table is EMEM16 or EMEM8 and if wait states are inserted when reading the vector table,

the processing time is extended. Add 2m in the case of vector interrupt with EMEM8 or m in the case

of context switching with EMEM16 to the values in the above table. m is the number of wait states per

byte necessary for reading the vector table.

If the branch destination is EMEM16 or EMEM8, and if wait states are inserted when reading the

instruction at the branch destination, add the number of wait states to the value in the above table.

If the stack is in PRAM and the value of the stack pointer (SP) is odd, add 8 to the value in the above

table. If the value of SP is odd with EMEM16, add 8+2n to the value in the above table.

The number of wait states is the total number of address wait and access wait states.

358

CHAPTER 14 INTERRUPT FUNCTIONS

14.11.2 Processing time of macro service

The processing time of the macro service differs depending on the type of the macro service, as shown in Table 14-12.

Table 14-12. Macro Service Processing Time

(unit: clock)

Type of Macro Service

Processing Time

IRAM

Other

Data Area

Group 0

Counter mode: EVTCNT

Group 1

Block transfer mode: BLKTRS

Buffer

SFR

Byte

Word

SFR

buffer

Byte

Word

Block transfer mode

Buffer

SFR

Byte

(with memory pointer): BLKTRS-P

Word

SFR

buffer

Byte

Word

Data differential mode: DTADIF

Data differential mode (with memory pointer): DTADIF-P

Group 2

CPU monitor mode 0: SELF0

CPU monitor mode 1: SELF1

Remarks 1.

Add the number of clocks specified for each case in the following cases in the other data areas.

If data size is word and data is located at an odd address in IROM or PRAM: 8 clocks

If data size is byte in EMEM16 or EMEM8, or if data size is word in EMEM16 and data is located

at an even address: n (n is the number of wait states per byte)

If data size is word in EMEM8, or if data size is word in EMEM16 and data is located at an

odd address: 4 + 2n (n is the number of wait states per byte)

Data is output to an SFR in the CPU monitor modes.

IRAM

: internal high-speed RAM

IROM

: internal ROM (with high-speed fetch specified)

PRAM

: peripheral RAM

EMEM16 : external memory and internal ROM not specified for high-speed fetch and set to 16-

bit bus width

EMEM8 : external memory and internal ROM not specified for high-speed fetch and set to 8-

bit bus width

359

CHAPTER 14 INTERRUPT FUNCTIONS

14.12 Restoring Interrupt Function To Initial State

If an inadvertent program loop or system error is detected by means of an operand error interrupt, the watchdog timer,

NMI pin input, etc., the entire system must be restored to its initial state. In the

PD784054, interrupt acknowledgment related

priority control is performed by hardware. This interrupt acknowledgment related hardware must also be restored to its initial

state, otherwise subsequent interrupt acknow-ledgment control may not be performed normally.

A method of initializing interrupt acknowledgment related hardware in the program is shown below. The only way of

performing initialization by hardware is by RESET input.

Example

MOVW MK0, #0FFFFH

;

Mask all maskable interrupts

MOV

MK1, #0FFFFH

IRESL

CMP

ISPR, #0

;

No interrupt service programs running?

$NEXT

MOVG SP, #RETVAL

;

Forcibly change SP location

RETI

;

Forcibly terminate running interrupt service program, return

address = IRESL

RETVAL :

LOWW (IRESL)

;

Stack data to return to IRESL with RETI instruction

HIGHW (IRESL)

;

LOWW & HIGHW are assembler operators for calculating low-order

16 bits & high-order 16 bits respectively of symbol NEXT

· It is necessary to ensure that a non-maskable interrupt request is not generated via the NMI pin

during execution of this program.

· After this, on-chip peripheral hardware initialization and interrupt control register initialization are

performed.

· When interrupt control register initialization is performed, the interrupt request flags must be

cleared (0).

360

CHAPTER 14 INTERRUPT FUNCTIONS

14.13 Cautions

(1) The in-service priority register (ISPR) is read-only. Writing to this register may result in misoperation.

(2) The watchdog timer mode register (WDM) can only be written to with a dedicated instruction (MOV WDM/#byte).

(3) The RETI instruction must not be used to return from a software interrupt caused by a BRK instruction.

(4) The RETCS instruction must not be used to return from a software interrupt caused by a BRKCS instruction.

(5) Macro service requests are acknowledged and serviced even during execution of a non-maskable interrupt service

program. If you do not want macro service processing to be performed during a non-maskable interrupt service

program, you should manipulate the interrupt mask register in the non-maskable interrupt service program to prevent

macro service generation.

(6) The RETI instruction must be used to return from a non-maskable interrupt. Subsequent interrupt acknowledgment

will not be performed normally if a different instruction is used.

(7) Non-maskable interrupts are always acknowledged, except during non-maskable interrupt service program execu-

tion (except when a high non-maskable interrupt request is generated during execution of a low-priority non-

maskable interrupt service program) and for a certain period after execution of the special instructions shown in 14.9.

Therefore, a non-maskable interrupt will be acknowledged even when the stack pointer (SP) value is undefined, in

particular after reset release, etc. In this case, depending on the value of the SP, it may happen that the program

counter (PC) and program status word (PSW) are written to the address of a write-inhibited special function register

(SFR) (refer to Table 3-6 in 3.8 Special Function Registers (SFR)), and the CPU becomes deadlocked, or the PC

and PSW are written to an unexpected signal is output from a pin, or an address is which RAM is not mounted, with

the result that the return from the non-maskable interrupt service program is not performed normally and a software

upsets occurs.

Therefore, the program following RESET release must be as follows.

CSEG AT 0

STRT

CSEG BASE

STRT:

LOCATION 0FH; or LOCATION 0

MOVG SP, #imm24

(8) When a maskable interrupt is acknowledged by vectored interruption, the RETI instruction must be used to return

from the interrupt. Subsequent interrupt related operations will not be performed normally if a different instruction

is used.

(9) The RETCS instruction must be used to return from a context switching interrupt. Subsequent interrupt related

operations will not be performed normally if a different instruction is used.

(10) If data is transmitted with UART by using the macro service, a vectored interrupt is generated two times (refer to

12.2.8 Transmitting/receiving data with macro service).

361

CHAPTER 14 INTERRUPT FUNCTIONS

(11) Do not clear the macro service counter (MSC) to 00H in the data differential mode and data differential mode (with

memory pointer).

(12) Initialize the "value immediately before" (with dummy data) in advance in the data differential mode and data

differential mode (with memory pointer).

(13) Only a 16-bit SFR can be specified by the SFR pointer (SFR.PTR) in the data differential mode and data differential

mode (with memory pointer).

(14) When an interrupt related register is polled using a BF instruction, etc., the branch destination of that BR instruction,

etc., should not be that instruction. If a program is written in which a branch is made to that instruction itself, all

interrupts and macro service requests will be held pending until a condition whereby a branch is not made by that

instruction arises.

Bad Example

LOOP:

BF PIC0.7, $LOOP

All interrupts and macro service requests are held pending until PIC0.7 is

× × ×

Interrupts and macro service requests are not processed until after exe-

cution of the instruction following the BF instruction.

Good Example (1)

LOOP:

NOP

BF PIC0.7, $LOOP

Interrupts and macro service requests are serviced after execution of the

NOP instruction, so that interrupts are never held pending for a long period.

Good Example (2)

LOOP:

BT PIC0.7, $NEXT

Using a BTCLR instruction instead of a BT instruction has the advantage

that the flag is cleared (0) automatically.

BR $LOOP

Interrupts and macro service requests are serviced after execution of the

BR instruction, so that interrupts are never held pending for a long period.

(15) For a similar reason to that given in (14), if problems are caused by a long pending period for interrupts and macro

service when instructions to which the above applies are used in succession, a time at which interrupts and macro

service requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the series of

instructions.

.
.
.

[MEMO]

362

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

The local bus interface function is provided for the connection of external memory (ROM and RAM) and I/Os.

External memory (ROM and RAM) and I/Os are accessed using the RD, LWR, HWR and ASTB pin signals, with pins

AD0 to AD15 used as the multiplexed address/data bus and pins A16 to A19 as the address bus.

The basic bus interface timing is shown in Figures 15-3 to 15-8.

In addition, a wait function that is used to interface with a low-speed memory, and a bus sizing function that can change

the external data bus width between 8 bits and 16 bits are also provided.

15.1 Memory Extension Function

With the

PD784054, external memory and I/O extension can be performed by setting the memory extension mode

15.1.1 Memory extension mode register (MM)

The MM is an 8-bit register that performs external extension memory control, address wait number specification, and

internal fetch cycle control.

The MM register can be read or written to with an 8-bit manipulation instruction or bit manipulation instruction. The MM

format is shown in Figure 15-1.

RESET input sets the MM register to 20H.

363

364

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-1. Format of Memory Expansion Mode Register (MM)

Notes 1. Setting prohibited when external 16-bit bus is specified.

2. Used as an address bus.

IFCH

MM3

MM2

MM1

MM0

IFCH

Fetches Internal ROM

Fetches at same speed as external memory.

All setting of wait control is valid.

High-speed fetch.

Specification of wait control is invalid.

Address : 0FFC4H On reset : 20H R/W

Specifies Address Wait

Disabled

Enabled

MM3

Mode

Single-chip

mode

256-byte
extension
mode

Note 1

1K-byte
extension
mode

Note 1

4K-byte
extension
mode

Note 1

16K-byte
extension
mode

Note 1

64K-byte
extension
mode

256K-byte
extension
mode

1M-byte
extension
mode

Setting prohibited

MM2

MM1

MM0

Port 4

(P40 to P47)

Port 5

(P50 to P57)

Port 6

(P60 to P63)

P90-P93

Port

AD0-AD7

AD8,

AD9

Note2

AD8-

AD11

Note2

AD8-

AD13

Note2

AD8-AD15

Port

A16,

A17

A16-A19

Port

P90 : RD

P91 : LWR

P92 : HWR

P93 : ASTB

Others

365

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.1.2 Memory map with external memory extension

The memory map when memory extension is used is shown in Figure 15-2. External devices at the same addresses

as the internal ROM area, internal RAM area and SFR area (excluding the external SFR area (0FFD0H to 0FFDFH)) cannot

be accessed. If an access is made to these addresses, the memory or SFR in the

PD784054 has access priority and no

ASTB signal, RD signal, LWR, or HWR signal is output (these pins remain at the inactive level). The address bus output

level remains at the level output prior to this, and the address/data bus output becomes high-impedance.

Except in 1M-byte extension mode, the address output externally is output with the upper part of the address specified

by the program masked.

Example 1:

In 256-byte extension mode, when address 54321H is accessed by the program, the output address is 21H.

Example 2:

In 256-byte extension mode, when address 67821H is accessed by the program, the output address is 21H.

366

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-2. Memory Map (1/2)

(a) When LOCATION 0 instruction is executed

Notes 1. Any extension size area in unshaded part

2. External SFR area

SFR

Note 2

SFR

Internal RAM

Internal ROM

Single-Chip Mode

1 M-Byte Extension Mode

256-Byte to 256 K-Byte
Extension Modes

Internal ROM

External Memory

Note 1

External Memory

Note 2

FFFFFH

0FFFFH

0FFE0H

0FFCFH

0FB00H

07FFFH

00000H

0F600H

Use prohibited

Use Prohibited

367

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-2. Memory Map (2/2)

(b) When LOCATION 0FH instruction is executed

Notes 1. Any extension size area in unshaded part

2. External SFR area

SFR

Note 2

SFR

Internal RAM

Internal ROM

Single-Chip Mode

1 M-Byte Extension Mode

256-Byte to 256 K-Byte
Extension Modes

Internal ROM

External Memory

Note 1

External Memory

Note 2

FFFFFH
FFFE0H

FFFCFH

FFB00H

07FFFH

00000H

FF600H

Use Prohibited

368

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.1.3 Basic operation of local bus interface

The local bus interface accesses external memory using ASTB, RD, LWR, HWR, an address/data bus (AD0 to AD15)

and address bus (A8 to A19). When the local bus interface is used, port 4 and P90 to P93 automatically operate as AD0

to AD7, RD, LWR, HWR, and ASTB. In ports 5 and 6, only the pins that correspond to the extension memory size operate

as address bus pins.

An outline of the memory access timing is shown in Figures 15-3 to 15-8.

Figure 15-3. Read Timing (8 Bits)

Condition ·

Bus Size

: 8 bits

Bus Cycle : No Wait

Note

The number of address bus pins used depends on the extension mode size.

Figure 15-4. Write Timing (8 Bits)

Condition ·

Bus Size

: 8 bits

Bus Cycle : No Wait

Note

The number of address bus pins used depends on the extension mode size.

High-Order Address

Data (Input)

ASTB (Output)

RD (Output)

AD0-AD7

AD8-AD15

Note

A16-A19

Note

(Output)

Hi-Z

Low-Order Address

(Output)

High-order Address

ASTB (Output)

AD0-AD7 (Output)

AD8-AD15

Note

A16-A19

Note

(Output)

Hi-Z

LWR (Output)

Data

Low-Order Address

369

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-5. Read Timing (16 Bits, Even Address Access)

Condition ·

Bus Size

: 16 bits

Low-Order 8-Bit Data : Even Address

Bus Cycle : No Wait

High-Order 8-Bit Data : Odd Address

Note

The number of address bus pins used depends on the extension mode size.

Figure 15-6. Write Timing (16 Bits, Even Address Access)

Condition ·

Bus Size

: 16 bits

Low-Order 8-Bit Data : Even Address

Bus Cycle : No Wait

High-Order 8-Bit Data : Odd Address

Note

The number of address bus pins used depends on the extension mode size.

High-Order Address

Data (Input)

ASTB (Output)

RD (Output)

AD0-AD15

A16-A19

Note

(Output)

Hi-Z

Low-Order Address

(Output)

High-order Address

ASTB (Output)

AD0-AD15 (Output)

A16-A19

Note

(Output)

Hi-Z

LWR, HWR (Output)

Data

Low-Order Address

370

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-7. Read Timing (16 Bits, Odd Address Access)

Condition ·

Bus Size

: 16 bits

Low-Order 8-Bit Data : Odd Address

Bus Cycle : No Wait

High-Order 8-Bit Data : Even Address

Note

The number of address bus pins used depends on the extension mode size.

Note

The number of address bus pins used depends on the extension mode size.

Figure 15-8. Write Timing (16 Bits, Odd Address Access)

Condition ·

Bus Size

: 16 bits

Low-Order 8-Bit Data : Odd Address

Bus Cycle : No Wait

High-Order 8-Bit Data : Even Address

A16-A19

Note

(Output)

AD0-AD15

ASTB (Output)

RD (Output)

Hi-Z

High-Order Address

Low-Order Address :

Odd Address

(Output)

Data (Input)

Low-Order Address :

Even Address

(Output)

Data (Input)

A16-A19

Note

(Output)

AD0-AD15 (Output)

ASTB (Output)

LWR (Output)

Hi-Z

High-Order Address

Low-Order Address :

Odd Address

Data

Low-Order Address :

Even Address

Data

HWR (Output)

371

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.2 Wait Function

When a low-speed memory or I/O is connected externally to the

PD784054, waits can be inserted in the external memory

access cycle.

There are two kinds of wait cycle, an address wait for securing the address decoding time, and an access wait for securing

the access time.

15.2.1 Wait function control registers

(1) Memory extension mode register (MM)

The IFCH bit of the MM performs wait control setting for internal ROM accesses, and the AW bit performs address

wait setting.

The MM can be read or written to with an 8-bit manipulation instruction. The MM format is shown in Figure 15-9.

When RESET is input, the MM register is set to 20H, the same cycle as for external memory is used for internal ROM

accesses, and the address wait function is validated.

Figure 15-9. Format of Memory Extension Mode Register (MM)

IFCH

MM3

MM2

MM1

MM0

IFCH

Fetches Internal ROM

Fetches at same speed as external memory.

All setting of wait control is valid.

High-speed fetch.

Specification of wait control is invalid.

Address : 0FFC4H On reset : 20H R/W

Specifiess Address Wait

Disabled

Enabled

MM3

Sets memory
extension mode
(refer to Figure 15-1).

MM2

MM1

MM0

372

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

(2) Programmable wait control registers (PWC1/PWC2)

The PWC1 and PWC2 specify the number of waits.

PWC1 is an 8-bit register that divides the space from 0 to FFFFH into four, and specifies wait control for each of

these four spaces. PWC2 is a 16-bit register that divides the space from 10000H to FFFFH into four, and specifies

wait control for each of these four spaces.

The PWC1 can be read or written to with an 8-bit manipulation instruction, and the PWC2 with a 16-bit manipulation

instruction. The PWC1 and PWC2 formats are shown in Figures 15-10 and 15-11.

The high-order 8 bits of the PWC2 are fixed at AAH, and therefore ensure that the high-order 8 bits are set to AAH.

When RESET is input, the PWC1 is set to AAH, and the PWC2 to AAAAH, and 2-wait insertion is performed on the

entire space.

373

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-10. Format of Programmable Wait Control Register 1 (PWC1)

PW31 PW30 PW21 PW20 PW11 PW10 PW01 PW00

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PWC1

Address : 0FFC7H On reset : AAH R/W

PW31

PW30

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW21

PW20

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW11

PW10

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW01

PW00

Data Access
Cycle,
Fetch Cycle

H-

Note

H-

374

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Note

Except the portion overlapping the internal data area.

Cautions 1.

The above number of cycles is when no address cycle is appended. If an address cycle is

appended, one cycle must be added.

No wait cycle is inserted when fetching instructions from the internal ROM or peripheral RAM area

at high-speed.

Do not insert a wait cycle in the internal ROM area by using the WAIT pin.

375

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-11. Format of Programmable Wait Control Register 2 (PWC2)

PW71 PW70 PW61 PW60 PW51 PW50 PW41 PW40

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW71

PW70

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW61

PW60

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW51

PW50

Data Access
Cycle,
Fetch Cycle

Valid

Address

Inserted Wait

Cycle

Time of low

level input to

WAIT pin

PW41

PW40

Data Access
Cycle,
Fetch Cycle

PWC2

Address : 0FFC8H On reset : AAAAH R/W

H-

Note

H-

376

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Note

Except the portion overlapping the internal data area.

Cautions 1.

The above number of cycles is when no address cycle is appended. If an address cycle is

appended, one cycle must be added.

No wait cycle is inserted when fetching instructions from the peripheral RAM area.

377

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.2.2 Address waits

Address waits are used to secure the address decoding time. If the AW bit of the memory extension mode register (MM)

is set (1), waits are inserted in every memory access

Note

. When an address wait is inserted, the high-level period of the

ASTB signal is extended by one system clock cycle (62.5 ns: f

CLK

= 16 MHz).

Note

Except for the internal RAM, internal SFRs, and internal ROM during high-speed fetch.

If it is specified that the internal ROM is accessed in the same cycle as the external ROM, an address wait state

is inserted even when the internal ROM is accessed.

Figure 15-12. Read/Write Timing of Address Wait Function (1/3)

(a) Read timing with no address wait insertion

Note

CLK

: Internal system clock frequency. This signal is present inside the

PD784054 only.

Remark

The above figure is an example of the 8-bit bus.

CLK

Note

High-Order Address

ASTB

AD0-AD7

AD8-AD15,

A16-A19

Hi-Z

Input Data

Low-Order

Address

Hi-Z

378

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-12. Read/Write Timing of Address Wait Function (2/3)

(b) Read timing with address wait insertion

Note

CLK

: Internal system clock frequency. This signal is present inside the

PD784054 only.

Remark

The above figure is an example of the 8-bit bus.

CLK

Note

ASTB

AD0-AD7

AD8-AD15,

A16-A19

Hi-Z

Low-Order Address

Input Data

High-Order Address

379

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-12. Read/Write Timing of Address Wait Function (3/3)

(c) Write timing with no address wait insertion

Note

CLK

: Internal system clock frequency. This signal is present inside the

PD784054 only.

Remark

The above figure is an example of the 8-bit bus.

(d) Write timing with address wait insertion

CLK

Note

High-Order Address

ASTB

AD0-AD7

AD8-AD15,

A16-A19

Hi-Z

LWR

Output Data

Low-Order

Address

Hi-Z

CLK

Note

High-Order Address

ASTB

AD0-AD7

AD8-AD15,

A16-A19

Hi-Z

LWR

Output Data

Low-Order Address

Hi-Z

380

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.2.3 Access waits

Access waits are inserted in the RD, LWR, or HWR signal low-level period, and extend the low-level period by 1/f

CLK

(62.5

ns: f

CLK

= 16 MHz) per cycle.

There are two wait insertion methods, using either the programmable wait function that automatically inserts the preset

number of cycles, or the external wait function controlled by a wait signal from outside.

For wait cycle insertion control, the 1 M-byte memory space is divided into eight as shown in Figure 15-14, and control

is specified for each space by means of the programmable wait control registers (PWC1/PWC2). Waits are not inserted

in accesses to internal ROM or internal RAM using high-speed fetches. In accesses to internal SFRs, waits are inserted

at the necessary times regardless of this specification.

If access operations are specified as being performed in the same number of cycles as for external ROM, waits are

inserted also in internal ROM accesses in accordance with the PWC1 settings.

The P94 pin functions as a WAIT input pin when the PMC94 bit of the port 9 mode control register (PMC9) is set (1).

The P94 pin operates as a general-purpose I/O port pin when RESET is input (refer to Figure 15-13).

Bus timing in the case of access wait insertion is shown in Figures 15-15 to 15-17.

Caution Do not insert a wait cycle in the internal ROM area by using the WAIT pin.

Figure 15-13. Format of Port 9 Mode Control Register (PMC9)

PMC94

Specifies Control Mode of Pin P94

I/O port mode

WAIT input mode

PMC9

Address : 0FF49H On reset : 00H R/W

381

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-14. Wait Control Spaces

512K Bytes

256K Bytes

128K Bytes

64K Bytes

16K Bytes

FFFFFH

80000H

03FFFH

7FFFFH

Controlled by Bits
PW70 & PW71

Controlled by Bits
PW60 & PW61

Controlled by PWC2

Controlled by PWC1

Controlled by Bits
PW50 & PW51

Controlled by Bits
PW40 & PW41

Controlled by Bits
PW30 & PW31

Controlled by Bits
PW20 & PW21

Controlled by Bits
PW10 & PW11

Controlled by Bits
PW00 & PW01

20000H

1FFFFH

10000H

0FFFFH

0C000H

0BFFFH

08000H

07FFFH

40000H

3FFFFH

04000H

00000H

382

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-15. Read Timing of Access Wait Function (1/2)

(a) 0 wait cycles set

(b) 1 wait cycle set

Note

CLK

: Internal system clock frequency. This signal is only present inside the

PD784054.

Remark

The above figure is an example of the 8-bit bus.

CLK

Note

High-Order Address

ASTB (Output)

AD0-AD7

AD8-AD15,

A16-A19

(Output)

Hi-Z

RD (Output)

Data (Input)

Low-Order

Address

Hi-Z

CLK

Note

High-Order Address

ASTB (Output)

AD0-AD7

AD8-AD15,

A16-A19

(Output)

Hi-Z

RD (Output)

Data (Input)

Low-Order

Address

Hi-Z

383

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-15. Read Timing of Access Wait Function (2/2)

(c) 2 wait cycles set

Note

CLK

: Internal system clock frequency. This signal is only present inside the

PD784054.

Remark

The above figure is an example of the 8-bit bus.

High-Order Address

ASTB (Output)

AD0-AD7

AD8-AD15,

A16-A19

(Output)

Hi-Z

RD (Output)

Data (Input)

Low-Order

Address

Hi-Z

CLK

Note

384

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-16. Write Timing of Access Wait Function (1/2)

(a) 0 wait cycles set

(b) 1 wait cycle set

Note

CLK

: Internal system clock frequency. This signal is only present inside the

PD784054.

Remark

The above figure is an example of the 8-bit bus.

CLK

Note

High-Order Address

ASTB (Output)

AD0-AD7

(Output)

AD8-AD15,

A16-A19

(Output)

Hi-Z

LWR (Output)

Data

Low-Order

Address

Hi-Z

CLK

Note

High-Order Address

ASTB (Output)

AD0-AD7

(Output)

AD8-AD15,

A16-A19

(Output)

Hi-Z

LWR (Output)

Data

Low-Order

Address

Hi-Z

385

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-16. Write Timing of Access Wait Function (2/2)

(c) 2 wait cycles set

Note

CLK

: Internal system clock frequency. This signal is only present inside the

PD784054.

Remark

The above figure is an example of the 8-bit bus.

High-Order Address

ASTB (Output)

AD0-AD7

(Output)

AD8-AD15,

A16-A9

(Output)

Hi-Z

LWR (Output)

Data

Low-Order

Address

Hi-Z

CLK

Note

Hi-Z

386

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-17. Timing with External Wait Signal

(a) Read timing

Note

CLK

: Internal system clock frequency. This signal is only present inside the

PD784054.

Remark

The above figure is an example of the 8-bit bus.

(b) Write timing

High-Order Address

ASTB (Output)

AD0-AD7

AD8-AD15,

A16-A9

(Output)

Hi-Z

RD (Output)

Data (Input)

Low-Order

Address

Hi-Z

CLK

Note

WAIT (Input)

High-Order Address

ASTB (Output)

AD0-AD7

(Output)

AD8-AD15,

A16-A9

(Output)

Hi-Z

LWR (Output)

Data

Low-Order

Address

Hi-Z

CLK

Note

WAIT (Input)

387

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.3 Bus Sizing Function

The

PD784054 has a bus sizing function that changes the external data bus width between 8 bits and 16 bits when

an external device is connected. By using this function, the 1M-byte memory space can be divided by eight, and the external

bus width can be specified in each memory space by using the bus width specification register (BW).

15.3.1 Bus width specification register (BW)

BW is a 16-bit register that specifies the bus width when an external device is connected.

This register cannot be accessed in 8-bit units. Be sure to access it by using a 16-bit data manipulation instruction. Figure

15-18 shows the format of BW

The value of BW differs depending on the setting of the BWD pin after RESET is input. When BWD = 0, the value of

BW is 0000H; when BWD = 1, it is 00FFH.

388

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

Figure 15-18. Format of Bus Width Specification Register (BW)

Note

The value of this register on reset differs depending on the setting of the BWD pin, as follows:

BWD = 0: 0000H

BWD = 1: 00FFH

BW7

BW6

BW5

BW4

BW3

BW2

BW1

BW0

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW7

Address : 0FFCAH On reset : Note R/W

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW6

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW5

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW4

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW3

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW2

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW1

Valid
Address

Specifies external data bus width

8-bit bus

16-bit bus

BW0

H-

389

CHAPTER 15 LOCAL BUS INTERFACE FUNCTION

15.4 Cautions

(1) No wait cycle is inserted when instructions are fetched from the internal ROM or peripheral RAM area at high speeds.

(2) Do not insert a wait cycle in the internal ROM area by using the WAIT pin.

[MEMO]

390

CHAPTER 16 STANDBY FUNCTION

16.1 Configuration and Function

The

PD784054 has a standby function that enables the system power consumption to be reduced. The standby function

includes four modes as follows:

HALT mode ....................... In this mode the CPU operating clock is stopped. Intermittent operation in combination

with the normal operating mode enables the total system power consumption to be

reduced.

IDLE mode ........................ In this mode the oscillator continues operating while the entire remainder of the system

is stopped. Normal program operation can be restored at a low power consumption close

to that of the STOP mode and in a time equal to that of the HALT mode.

STOP mode ...................... In this mode the oscillator is stopped and the entire system is stopped.

...........................................

Ultra-low power consumption can be achieved, consisting of leakage current only.

Standby function mode .... In this mode the standby function (HALT/IDLE/STOP mode) can be made invalid by

inputting a high level to the MODE 1 pin.

It can be used when the standby mode must not be used for some reason in an application.

These modes are set by software. The diagram of the standby mode (STOP/IDLE/HALT mode) transition is shown in

Figure 16-1, and the block diagram of the standby function in Figure 16-2.

391

392

CHAPTER 16 STANDBY FUNCTION

Figure 16-1. Diagram of Standby Mode Transition

Wait of

Oscillation

Stabilization

Program

Operation

Macro

Service

Macro Service Request

End of 1st Service

End of Macro Service

Macro Service Request

End of 1st Service

STOP Setting

RESET Input

NMI

IDLE Setting

RESET Input

NMI

Interrupt Request

Note

RESET Input

HALT Setting

Masked Interrupt
Request

HALT

(Standby)

IDLE

(Standby)

STOP

(Standby)

End of Oscillation Stabilization Time

Standby

Function

Invalid

MODE1 = H

MODE1 = L

MODE1 = H

MODE1 = L

Note

Unmasked interrupt request only

Remark

Only external input is valid as NMI. The watchdog timer must not be used to release the standby mode (STOP,

HALT, or IDLE mode).

393

CHAPTER 16 STANDBY FUNCTION

Figure 16-2. Block Diagram of Standby Function

EXTC

System
Clock
Oscillator

Frequency

Divider

Oscillation Stabilization
Timer (19)

OSTS0
OSTS1
OSTS2

EXTC

NMI

RESET

Rising Edge
Detection

Selector

ESNMI

Interrupt

INTC

Macro Service
Request

Selector

RAM PROTECT

To Peripheral Circuit

CPU CLK

HLT F/F

IDLE F/F

STP F/F2

STP F/F1

Macro Service
Request

HLT Bit Setting
STOP Bit Setting

/2 (f

CLK

)

MODE1

394

CHAPTER 16 STANDBY FUNCTION

16.2 Control Registers

16.2.1 Standby control register (STBC)

The STBC is a register used to control the standby mode.

To prevent entry into the standby mode due to an inadvertent program loop, the STBC register can only be written to

with a dedicated instruction. This dedicated instruction, MOV STBC, #byte, has a special code configuration (4 bytes), and

a write is only performed if the 3rd and 4th bytes of the operation code are mutual complements.

If the 3rd and 4th bytes of the operation code are not mutual complements, a write is not performed and an operand error

interrupt is generated. In this case, the return address saved in the stack area is the address of the instruction that was

the source of the error, and thus the address that was the source of the error can be identified from the return address saved

in the stack area.

If recovery from an operand error is simply performed by means of an RETB instruction, an endless loop will result.

As an operand error interrupt is only generated in the event of an inadvertent program loop (with the NEC assembler,

RA78K4, only the correct dedicated instruction is generated when MOV STBC, #byte is written), system initialization should

be performed by the program.

Other write instructions (MOV STBC, A, AND STBC, #byte, SET1 STBC.7, etc.) are ignored and do not perform any

operation. That is, a write is not performed to the STBC, and an interrupt such as an operand error interrupt is not generated.

The STBC can be read at any time by a data transfer instruction.

RESET input sets the STBC register to 30H.

The format of the STBC is shown in Figure 16-3.

395

CHAPTER 16 STANDBY FUNCTION

Figure 16-3. Standby Control Register (STBC) Format

Caution If the STOP mode is used when using external clock input, the EXTC bit of the oscillation stabilization

time specification register (OSTS) must be set (1) before setting STOP mode. If the STOP mode is used

with the EXTC bit cleared (0) when using external clock input, the

PD784054 may suffer damage or

reduced reliability.

When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock

input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).

STP

HLT

STP

Controls CPU Operation Control

Normal operating mode

HALT mode

STOP mode

IDLE mode

STBC

Address : 0FFC0H On reset : 30H R/W

HLT

396

CHAPTER 16 STANDBY FUNCTION

16.2.2 Oscillation stabilization time specification register (OSTS)

The OSTS specifies the oscillator operation and the oscillation stabilization time when STOP mode is released. Set the

state of the clock oscillator operation to the EXTC bit of the OSTS. STOP mode can be set when external clock input is

used only when the EXTC bit is set (1).

Bits OSTS0 to OSTS2 of the OSTS select the oscillation stabilization time when STOP mode is released. In general,

an oscillation stabilization time of at least 40ms should be selected when a crystal resonator is used, and at least 4 ms when

a ceramic oscillator is used.

The time taken for oscillation stabilization is affected by the crystal resonator or ceramic resonator used, and the

capacitance of the connected capacitor. Therefore, if you want to set a short oscillation stabilization time, you should consult

the crystal resonator or ceramic resonator manufacturer.

The OSTS can be read/written only with an 8-bit manipulation instruction.

RESET input clears the OSTS register to 00H.

The format of the OSTS is shown in Figure 16-4.

397

CHAPTER 16 STANDBY FUNCTION

Figure 16-4. Format of Oscillation Stabilization Time Specification Register (OSTS)

EXTC

OSTS2 OSTS1 OSTS0

EXTC

Selects External Clock

X2 pin is open when crystal/ceramic oscillation

is used or when external clock is used.

Input signal in reverse phase to that input to

X1 pin to X2 pin when external clock is used.

OSTS

Address : 0FFCFH On reset : 00H R/W

EXTC

Selects Oscillation
Stabilization Time

CLK

(32.8 ms)

CLK

(16.4 ms)

CLK

(8.19 ms)

CLK

(4.10 ms)

CLK

(2.05 ms)

CLK

(1.02 ms)

CLK

(512 s)

CLK

(256 s)

CLK

(16 s)

OSTS2

OSTS1

OSTS0

CLK

= 16 MHz)

Remark

CLK

: internal system clock

: don't care

Cautions 1. When crystal/ceramic oscillation is used, the EXTC bit of the oscillation stabilization time

specification register (OSTS) must be cleared (0) before use. If the EXTC bit is set (1), oscillation

will stop.

2. If the STOP mode is used when using external clock input, the EXTC bit must be set (1) before

setting STOP mode. If the STOP mode is used with the EXTC bit cleared (0) the

PD784054 may

suffer damage or reduced reliability.

When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the

clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).

398

CHAPTER 16 STANDBY FUNCTION

16.3 HALT Mode

16.3.1 HALT mode setting and operating states

The HALT mode is selected by setting (1) the HLT bit of the standby control (STBC) register or clearing (0) the STP bit.

The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. HALT

mode setting is therefore performed by means of the "MOV STBC, #byte" instruction.

Caution If a condition that releases the HALT mode comes into effect when the HALT mode is being set, the

HALT mode is not entered, and the next instruction is executed, or a branch to a vectored interrupt

service program is performed. Before this branch execution, the instructions after the HALT mode

setting may be executed for 6 clocks. After restoring from the interrupt service, to execute an

instruction after setting the HALT mode, insert three NOP instructions before the instruction. To be

sure to set the HALT mode, take the necessary precautions such as clearing the interrupt request

before setting the HALT mode.

Table 16-1. Operating States in HALT Mode

Clock oscillator

Operating

Internal system clock

Operating

CPU

Operation stopped

Note 1

I/O lines

Retain state prior to HALT mode setting

Peripheral functions

Continue operating

Internal RAM

Retained

Bus lines

AD0 to AD7

High-impedance

AD8 to AD15

Retained

Note 2

A16 to A19

RD, LWR, HWR output

High level

ASTB output

Low level

Notes 1. Macro service processing is executed.

2. If the fetch address is in external memory with 16-bit bus width, AD8 to AD15 are made high-impedance after

the interrupt processing of the macro service is executed.

16.3.2 HALT mode release

HALT mode can be released by the following three sources.

Non-maskable interrupt request

Maskable interrupt request (vectored interrupt/context switching/macro service)

RESET input

Release sources and an outline of operations after release are shown in Table 16-2.

399

CHAPTER 16 STANDBY FUNCTION

Table 16-2. HALT Mode Release and Operations after Release

Release Source

Note 1

Note 2

State on Release

Operation after Release

Non-maskable

· Non-maskable interrupt service program

Interrupt request acknowledgment

interrupt request

not being executed

(NMI pin input

· Low-priority non-maskable interrupt

only. Excluding

service program being executed

watchdog

· Service program for same request being

Execution of instruction after MOV STBC/

timer

Note 5

executed

#byte instruction (interrupt request that

· High-priority non-maskable interrupt

released HALT mode is held pending

Note 3

)

service program being executed

Maskable

· Interrupt service program not being

Interrupt request acknowledgment

interrupt request

executed

(excluding macro

· Low-priority maskable interrupt service

service request)

program being executed

· PRSL bit

Note 4

cleared (0) during execution

of priority level 3 interrupt service program

· Same-priority maskable interrupt service

Execution of instruction after MOV STBC/

program being executed

#byte instruction (interrupt request that

(If PRSL bit

Note 4

is cleared (0), excluding

released HALT mode is held pending

Note 3

)

execution of priority level 3 interrupt

service program)

· High-priority interrupt service program

being executed

HALT mode maintained

Macro service

Macro service processing execution

request

End condition not established

HALT

mode again

End condition established

Same as

release by maskable interrupt request

HALT mode maintained

RESET input

Normal reset operation

Notes 1. Interrupt mask bit in individual interrupt request source

2. Interrupt enable flag in program status word (PSW)

3. Pending interrupt requests are acknowledged when acknowledgment becomes possible.

4. Bit in interrupt mode control register (IMC)

5. The HALT mode cannot be released by the watchdog timer.

400

CHAPTER 16 STANDBY FUNCTION

(1) Release by non-maskable interrupt

When a non-maskable interrupt is generated, the

PD784046 is released from HALT mode irrespective of whether

the interrupt acknowledgment enabled state (EI) or disabled state (DI) is in effect.

When the

PD784054 is released from HALT mode, if the non-maskable interrupt that released HALT mode can

be acknowledged, acknowledgment of that non-maskable interrupt is performed and a branch is made to the service

program. If the interrupt cannot be acknowledged, the instruction following the instruction that set the HALT mode

(the MOV STBC, #byte instruction) is executed, and the non-maskable interrupt that released the HALT mode is

acknowledged when acknowledgment becomes possible. Refer to 14.6 Non-Maskable Interrupt Acknowledg-

ment Operation for details of non-maskable interrupt acknowledgment.

(2) Release by maskable interrupt request

HALT mode release by a maskable interrupt request can only be performed by an interrupt for which the interrupt

mask flag is 0.

When HALT mode is released, if an interrupt can be acknowledged when the interrupt request enable flag (IE) is

set (1), a branch is made to the interrupt service program. If the interrupt cannot be acknowledged and if the IE flag

is cleared (0), execution is resumed from the instruction following the instruction that set the HALT mode. Refer

to 14.7 Maskable Interrupt Acknowledgment Operation for details of interrupt acknowledgment.

With macro service, HALT mode is released temporarily, service is performed once, then HALT mode is restored.

When macro service has been performed the specified number of times, HALT mode is released. The operation

after release in this case is the same as for release by a maskable interrupt described earlier.

(3) Release by RESET input

The program is executed after branching to the reset vector address, as in a normal reset operation. However,

internal RAM contents retain their value directly before HALT mode was set.

401

CHAPTER 16 STANDBY FUNCTION

16.4 STOP Mode

16.4.1 STOP mode setting and operating states

The STOP mode is selected by setting (1) the STP bit of the standby control register (STBC) register or clearing (0) the

HLT bit.

The only writes that can be performed on the STBC register are 8-bit data writes by means of a dedicated instruction.

STOP mode setting is therefore performed by means of the "MOV STBC, #byte" instruction,

Caution If a condition that releases the HALT mode comes into effect when the STOP mode is being set (refer

to 16.3.2 HALT mode release), the STOP mode is not entered, and the next instruction is executed,

or a branch to a vectored interrupt service program is performed. Before this branch execution, the

instructions after the STOP mode setting may be executed for 6 clocks. After restoring from the

interrupt service, to execute an instruction after setting the STOP mode, insert three NOP instructions

before the instruction. To be sure to set the STOP mode, take the necessary precautions such as

clearing the interrupt request before setting the STOP mode.

Table 16-3. Operating States in STOP Mode

Clock oscillator

Oscillation stopped

Internal system clock

Stopped

CPU

Operation stopped

I/O lines

Retain state prior to STOP mode setting

Peripheral functions

All operation stopped

Note

Internal RAM

Retained

Bus lines

AD0 to AD15

High-impedance

A16 to A19

High-impedance

RD, LWR, HWR output

High-impedance

ASTB output

High-impedance

Note

A/D converter operation is stopped, but if the AM0 bit or AM1 bit of the A/D converter mode register (ADM) is

set (1), the current consumption does not decrease.

Cautions 1. If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS)

register is cleared (0), the X1 pin is shorted internally to V

(GND potential) to suppress clock

generator leakage. Therefore, when the STOP mode is used in a system that uses an external clock,

the EXTC bit of the OSTS must be set (1). If STOP mode setting is performed in a system to which

an external clock is input when the EXTC bit of the OSTS is cleared (0), the

PD784054 may suffer

damage or reduced reliability.

When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the

clock input to the X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).

2. Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register

(ADM)) before setting the STOP mode.

402

CHAPTER 16 STANDBY FUNCTION

16.4.2 STOP mode release

STOP mode is released by NMI input, INTP4 input, INTP5 input, and RESET input.

Table 16-4. STOP Mode Release and Operations after Release

Release

State after Release

Operation after Release

Source

NMI pin input

· Non-maskable interrupt service

Interrupt request acknowledgment

program not being executed

· Low-priority non-maskable interrupt

service program being executed

· NMI pin input service program being

Execution of instruction after MOV STBC/

executed

#byte instruction (interrupt request that

· High-priority non-maskable interrupt

released STOP mode is held pending

Note

)

service program being executed

RESET input

Normal reset operation

Note

Pending interrupt requests are acknowledged when acknowledgment becomes possible.

(1) STOP mode release by NMI input

The oscillator resumes oscillation when the valid edge specified by external interrupt mode register 0 (INTM0) is

input to the NMI input. STOP mode is released after the oscillation stabilization time specified by the oscillation

stabilization time specification register (OSTS) elapses.

When the

PD784054 is released from STOP mode, if a non-maskable interrupt by NMI pin input can be

acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if

the STOP mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following

the instruction that set the STOP mode, and a branch is made to the NMI interrupt service program when

acknowledgment becomes possible (by execution of an RETI instruction, etc.).

Refer to 14.6 Non-Maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment.

Figure 16-5. STOP Mode Release by NMI Input

(2) STOP mode release by RESET input

When RESET input falls from high to low and the reset state is established, the oscillator resumes oscillation. The

oscillation stabilization time should be secured while RESET is active. Thereafter, normal operation is started when

RESET rises.

Unlike an ordinary reset operation, data memory retains its contents prior to STOP mode setting.

Oscillator

CLK

STP F/F1

NMI Input

Rising Edge

Specified

STP F/F2

Oscillator Stopped

STOP

Oscillation Stabilization

Count Time

403

CHAPTER 16 STANDBY FUNCTION

16.5 IDLE Mode

16.5.1 IDLE mode setting and operating states

The IDLE mode is selected by setting (1) both the STP bit and the HLT bit of the standby control (STBC) register.

The only writes that can be performed on the STBC are 8-bit data writes by means of a dedicated instruction. IDLE mode

setting is therefore performed by means of the "MOV STBC, #byte" instruction.

Caution If a condition that releases the HALT mode comes into effect when the IDLE mode is being set (refer

to 16.3.2 HALT mode release), the IDLE mode is not entered, and the next instruction is executed, or

a branch to a vectored interrupt service program is performed. Before this branch execution, the

instructions after the IDLE mode setting may be executed for 6 clocks. After restoring from the

interrupt service, to execute an instruction after setting the IDLE mode, insert three NOP instructions

before the instruction. To be sure to set the IDLE mode, take the necessary precautions such as

clearing the interrupt request before setting the IDLE mode.

Table 16-5. Operating States in IDLE Mode

Clock oscillator

Oscillation continues

Internal system clock

Stopped

CPU

Operation stopped

I/O lines

Retain state prior to IDLE mode setting

Peripheral functions

All operation stopped

Note

Internal RAM

Retained

Bus lines

AD0 to AD15

High-impedance

A16 to A19

High-impedance

RD, LWR, HWR output

High-impedance

ASTB output

High-impedance

Note

A/D converter operation is stopped, but if the AM0 bit or AM1 bit of the A/D converter mode register (ADM) is

set, the current consumption does not decrease.

Caution Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register (ADM))

before setting the IDLE mode.

404

CHAPTER 16 STANDBY FUNCTION

16.5.2 IDLE mode release

IDLE mode is released by NMI input, or RESET input.

Table 16-6. IDLE Mode Release and Operations after Release

Release

State after Release

Operation after Release

Source

NMI pin input

· Non-maskable interrupt service

Interrupt request acknowledgment

program not being executed

· Low-priority non-maskable interrupt

service program being executed

· NMI pin input service program being

Execution of instruction after MOV STBC/

executed

#byte instruction (interrupt request that

· High-priority non-maskable interrupt

released IDLE mode is held pending

Note

)

service program being executed

RESET input

Normal reset operation

Note

Pending interrupt requests are acknowledged when acknowledgment becomes possible.

(1) IDLE mode release by NMI input

IDLE mode is released when the valid edge specified by external interrupt mode register 0 (INTM0) is input to the

NMI input.

When the

PD784054 is released from IDLE mode, if a non-maskable interrupt by NMI pin input can be

acknowledged, a branch is made to the NMI interrupt service program. If the interrupt cannot be acknowledged (if

the IDLE mode is set in an NMI interrupt service program, etc.), execution is resumed from the instruction following

the instruction that set the IDLE mode, and a branch is made to the NMI interrupt service program when

acknowledgment becomes possible (by execution of an RETI instruction, etc.).

Refer to 14.6 Non-Maskable Interrupt Acknowledgment Operation for details of NMI interrupt acknowledgment.

(2) IDLE mode release by RESET input

Normal operation is started when RESET rises after RESET input falls from high to low.

Unlike an ordinary reset operation, data memory retains its contents prior to IDLE mode setting.

Caution When the execution of the IDLE mode instruction contends with the interrupt of release source of

the IDLE mode, the STOP mode is released after the STOP mode has been executed, instead of the

normal operation where the IDLE mode is released after the IDLE mode has been executed, because

of a malfunction of the

PD784054. Therefore, when the IDLE mode is released, the wait operation

for the oscillation stabilization time set by the oscillation stabilization time specification register

(OSTS) may be executed even though the IDLE mode is set in software (Usually, the

PD784054

does not wait the oscillation stabilization time when the IDLE mode is released.) If there are

problems with waiting for the oscillation stabilization time when the IDLE mode is released, set the

value of the oscillation stabilization time set by the OSTS as short as possible.

405

CHAPTER 16 STANDBY FUNCTION

16.6 Check Items When STOP Mode/IDLE Mode Is Used

Check items required to reduce the current consumption when STOP mode/IDLE mode is used are shown below.

(1) Is the output level of each output pin appropriate?

The appropriate output level for each pin varies according to the next-stage circuit. You should select the output

level that minimizes the current consumption.

If high level is output when the input impedance of the next-stage circuit is low, a current will flow from the power

supply to the port, resulting in an increased current consumption. This applies when the next-stage circuit is a

CMOS IC, etc. When the power supply is off, the input impedance of a CMOS IC is low. In order to suppress

the current consumption, or to prevent an adverse effect on the reliability of the CMOS IC, low level should be

output. If a high level is output, latchup may result when power is turned on again.

Depending on the next-stage circuit, inputting low level may increase the current consumption. In this case, high-

level or high-impedance output should be used to reduce the current consumption.

If the next-stage circuit is a CMOS IC, the current consumption of the CMOS IC may increase if the output is made

high-impedance when power is supplied to it (the CMOS IC may also be overheated and damaged). In this case

you should output an appropriate level, or pull the output high or low with a resistor.

The method of setting the output level depends on the port mode.

When a port is in control mode, the output level is determined by the status of the on-chip hardware, and therefore

the on-chip hardware status must be taken into consideration when setting the output level.

In port mode, the output level can be set by writing to the port output latch and port mode register by software.

When a port is in control mode, its output level can be set easily by changing to port mode.

(2) Is the input pin level appropriate?

The voltage level input to each pin should be in the range between V

potential and V

potential. If a voltage outside

this range is applied, the current consumption will increase and the reliability of the

PD784054 may be adversely

affected.

Also ensure that an intermediate potential is not applied.

(3) Are pull-up resistors necessary?

An unnecessary pull-up resistor will increase the current consumption and cause a latchup of other devices. A mode

should be specified in which pull-up resistors are used only for parts that require them.

If there is a mixture of parts that do and do not require pull-up resistors, for parts that do, you should connect a pull-

up resistor externally and specify a mode in which the on-chip pull-up resistor is not used.

406

CHAPTER 16 STANDBY FUNCTION

(4) Is processing of the address bus, address/data bus, etc., appropriate?

In STOP mode and IDLE mode, the address bus, address/data bus, RD and LWR, HWR pins become high-

impedance. Normally, these pins are pulled high with a pull-up resistor. If this pull-up resistor is connected to the

backed-up power supply, then if the input impedance of circuitry connected to the non-backed-up power supply is

low, a current will flow through the pull-up resistor, and the current consumption will increase. Therefore, the pull-

up resistor should be connected to the non-backed-up power supply side as shown in Figure 16-6.

Also, in STOP mode and IDLE mode the ASTB pin also becomes high impedance. Countermeasures should be

taken with reference to the points noted in (1).

Figure 16-6. Example of Address/Data Bus Processing

(5) A/D converter

The current flowing to the AV

, AV

REF1

pins can be reduced by clearing (0) the AM0 and AM1 bits of the A/D converter

mode register (ADM). The current can be further reduced, if required, by cutting the current supply to the AV

, AV

REF

pins with external circuitry.

Make sure that the AV

pin is not at the same potential as the V

pin. Unless power is supplied to the AV

in the STOP mode, not only does the current consumption increase, but the reliability is also affected.

IN/OUT

CMOS IC, etc.

Non-Backed-Up Power Supply

ADn

(n = 0-15)

PD784054

Backed-Up Power Supply

407

CHAPTER 16 STANDBY FUNCTION

16.7 Cautions

(1) If a condition that releases the HALT mode comes into effect when the HALT/STOP/IDLE mode (hereafter referred

to as standby mode) is being set (refer to 16.3.2 HALT mode release), the standby mode is not entered, and the

next instruction is executed, or a branch to a vectored interrupt service program is performed. Before this branch

execution, the instructions after the standby mode setting may be executed for 6 clocks. After restoring from the

interrupt service, to execute an instruction after setting the standby mode, insert three NOP instructions before the

instruction. To be sure to set the standby mode, take the necessary precautions such as clearing the interrupt request

before setting the standby mode.

(2) When crystal/ceramic oscillation is used, the EXTC bit must be cleared (0) before use. If the EXTC bit is set (1),

oscillation will stop.

(3) If the STOP mode is set when the EXTC bit of the oscillation stabilization time specification (OSTS) register is cleared

(0), the X1 pin is shorted internally to V

(GND potential) to suppress clock generator leakage. Therefore, when

the STOP mode is used in a system that uses an external clock, the EXTC bit of the OSTS must be set (1). If STOP

mode setting is performed in a system to which an external clock is input when the EXTC bit of the OSTS is cleared

(0), the

PD784054 may suffer damage or reduced reliability.

When setting the EXTC bit of OSTS to 1, be sure to input a clock in phase reverse to that of the clock input to the

X1 pin, to the X2 pin (refer to 4.3.1 Clock oscillator).

(4) Stop the A/D converter (by clearing (0) the AM0 and AM1 bits of the A/D converter mode register (ADM)) before

setting the STOP or IDLE mode.

(5) When the execution of the IDLE mode instruction contends with the interrupt of release source of the IDLE mode,

the STOP mode is released after the STOP mode has been executed, instead of the normal operation where the

IDLE mode is released after the IDLE mode has been executed, because of a malfunction of the

PD784054.

Therefore, when the IDLE mode is released, the wait operation for the oscillation stabilization time set by the

oscillation stabilization time specification register (OSTS) may be executed even though the IDLE mode is set in

software (Usually, the

PD784054 does not wait the oscillation stabilization time when the IDLE mode is released.)

If there are problems with waiting for the oscillation stabilization time when the IDLE mode is released, set the value

of the oscillation stabilization time set by the OSTS as short as possible.

[MEMO]

408

CHAPTER 17 RESET FUNCTION

17.1 Reset Function

When low level is input to the RESET input pin, a system reset is affected, the various hardware units are set to the states

shown in Table 17-2, and all pins except the power supply pins and the X1 and X2 CLKOUT pins are placed in the high-

impedance state. Table 17-1 shows the pin statuses on reset and after reset release.

When the RESET input changes from low to high level, the reset state is released, the contents of address 00000H of

the reset vector table are set in bits 0 to 7 of the program counter (PC), the contents of address 00001H in bits 8 to 15, and

0000B in bits 16 to 19, a branch is made, and program execution is started at the branch destination address. A reset start

can therefore be performed from any address in the base area.

The contents of the various registers should be initialized as required in the program in the base area.

To prevent misoperation due to noise, the RESET input pin incorporates an analog delay noise elimination circuit (refer

to Figure 17-1).

Figure 17-1. Acknowledgment of Reset Signal

Oscillation Stabilization Time

Delay PC Initialization, etc.

Execution of Instruction at
Reset Start Address

Internal Reset Signal

Reset End

RESET

(Input)

Delay PC Initialization, etc.

Execution of Instruction
at Reset Start Address

Reset Start

Delay

Reset End

Internal Reset Signal

RESET

(Input)

In a reset operation upon powering on and STOP mode release by reset, the RESET signal must be kept active until

the oscillation stabilization time has elapsed (approx. 40 ms, depending on the resonator used).

Figure 17-2. Power-On Reset Operation

409

410

CHAPTER 17 RESET FUNCTION

Table 17-1. Pin Status during Reset Input and after Clearing Reset

Pin Name

I/O

During Reset

Immediately after Clearing Reset

P00-P03

I/O

Hi-Z

Hi-Z (input port mode)

P10-P12

P20

Input

Hi-Z (input port)

P21-P27

I/O

Hi-Z (input port mode)

P30-P37

P40-P47

P50-P57

P60-P63

P70-P77

Input

Hi-Z (input port)

P80-P87

P90-P94

I/O

Hi-Z (input port mode)

CLKOUT

Output

Clock output

Figure 17-3. Timing on Reset Input

RESET

(Input)

CLKOUT

(output)

Other I/O Ports

Hi-Z

Reset Period

Clearing Reset - Instruction Execution Time

411

CHAPTER 17 RESET FUNCTION

Table 17-2. State of Hardware after Reset (1/2)

Hardware

State after Reset

Program counter (PC)

Contents of reset vector table

(0000H, 0001H) are set

Stack pointer (SP)

Undefined

Note

Program status word (PSW)

02H

On-chip RAM

Data memory

Undefined

Note

General-purpose register

Port

Port 0 to port 9

Undefined (high impedance)

Mode registers (PM0 to PM6, PM9)

FFH

Mode control registers (PMC2, PMC3, PMC9)

00H

Port read control register (PRDC)

Pull-up resistor option register (PUOL, PUOH)

Timer/counter

Timer registers (TM0, TM1, TM4)

0000H

Capture/compare registers (CC00 to CC03)

Undefined

Compare registers (CM10, CM11, CM40, CM41)

Timer unit mode registers (TUM0)

00H

Timer mode control registers (TMC, TMC4)

Timer output control registers (TOC0, TOC1)

Prescaler mode registers (PRM, PRM4)

Noise protection control register (NPC)

Interrupt valid edge flag registers (IEF1, IEF2)

Undefined

Watchdog timer mode register (WDM)

00H

A/D converter

A/D converter mode register (ADM)

A/D conversion result registers (ADCR0 to ADCR7, ADCR0H to ADCR7H)

Undefined

Serial interface

Asynchronous serial interface mode registers (ASIM, ASIM2)

00H

Asynchronous serial interface status registers (ASIS, ASIS2)

Serial receive buffers (RXB, RXB2)

Undefined

Serial transmit shift registers (TXS, TXS2)

Clocked serial interface mode registers (CSIM1, CSIM2)

00H

Serial shift registers (SIO1, SIO2)

Undefined

Baud rate generator control registers (BRGC, BRGC2)

00H

External interrupt mode registers (INTM0, INTM1)

Note

If the HALT, STOP, or IDLE mode is released by using the RESET input, the values immediately before each mode

has been set are retained.

412

CHAPTER 17 RESET FUNCTION

Table 17-2. State of Hardware after Reset (2/2)

Hardware

State after Reset

Interrupt

Interrupt control registers (OVIC0, OVIC1, OVIC4, PIC0 to PIC6, CMIC10,

43H

CMIC11, CMIC40, CMIC41, SERIC, SRIC, CSIIC1, STIC, SERIC2, SRIC2,

CSIIC2, STIC2, ADIC)

Interrupt mask registers

MK0, MK1

FFFFH

MK0L, MK0H, MK1L, MK1H

FFH

Interrupt mode control register (IMC)

80H

In-service priority register (ISPR)

00H

Memory extension mode register (MM)

20H

Programmable wait control register

PWC1

AAH

PWC2

AAAAH

Bus width specification register (BW)

0000H (BWD = 0)

00FFH (BWD = 1)

Standby control register (STBC)

30H

Oscillation stabilization time specification register (OSTS)

00H

Internal memory size switching register (IMS)

CDH

17.2 Caution

Reset input when powering on must remain at the low level until oscillation stabilizes after the supply voltage has reached

the prescribed voltage.

CHAPTER 18

PD78F4046

18.1 Memory Mapping of

PD78F4046

The

PD78F4046 has 64K bytes of flash memory and 2048 bytes of internal RAM.

The

PD78F4046 has a function to not use part of the internal memory (memory size select function). This function is

effected by software.

The memory size is changed by using the internal memory size select register (IMS).

This register can be read or written by using an 8-bit manipulation instruction. Data can be only written to the IMS of

the

PD78F4046, however. The IMS of the

PD784054 retains the value at reset even if data is written to it.

Therefore, the value of the IMS at RESET differs depending on the model. In the case of the

PD784054, it is CDH.

The value of the IMS of the

PD78F4046 is set to DEH at RESET.

413

414

CHAPTER 18

PD78F4046

Figure 18-1. Format of Internal Memory Size Select Register (IMS)

Note

The value at reset differs depending on the model.

PD784054 : CDH

PD78F4046 : DEH

Cautions 1. Writing to the internal memory size select register (IMS) is valid only with the

PD78F4046. The

IMS of the

PD784054 holds the value at RESET even if data is written to it.

2. To develop a program for the

PD784054 using the

PD78F4046, set the value of the IMS to CDH.

When the value of the IMS is set to CDH, the peripheral RAM capacity of the

PD78F4046 is 768

bytes, but the peripheral RAM capacity of the

PD784054 is 512 bytes. When using a mask ROM,

therefore, exercise care that addresses 0FA00H through 0FAFFH of the peripheral RAM area of the

PD78F4046 are not used (when the LOCATION 0 instruction is executed).

18.2 Programming

PD78F4046

The flash memory can be written with the

PD78F4046 mounted on the target system (on-board). Connect a Flash-

pro II (type FL-PR2) to the host machine and target system to write the flash memory.

The flash memory can also be written using the adapter for writing flash memory connected to Flashpro II.

Remark

Flashpro II is a product of Naito Densei Machida Mfg. Co., Ltd.

ROM1 ROM0

RAM1 RAM0

IMS

ROM1

Selects Internal ROM Capacity

32K bytes

Invalid

Setting prohibited

ROM0

PD784054

PD78F4046

32K bytes

64K bytes

Others

RAM1

Selects Peripheral RAM Capacity

512 bytes

Invalid

Setting prohibited

RAM0

PD784054

PD78F4046

768 bytes

1.5K bytes

Others

Address : 0FFFCH On reset : Note R/W

415

CHAPTER 18

PD78F4046

18.2.1 Selecting communication mode

The flash memory is written by using a Flashpro II and by means of serial communication. Select a communication mode

from those listed in Table 18-1. To select a communication mode, the format shown in Figure 18-2 is used. Each

communication mode is selected by the number of V

pulses shown in Table 18-1.

Table 18-1. Communication Modes

Communication Mode

Number of Channels

Pins Used

Number of V

Pulses

3-wire serial I/O

P34/ASCK/SCK1

P33/TxD/SO1

P32/RxD/SI1

P37/ASCK2/SCK2

P36/TxD2/SO2

P35/RxD2/SI2

UART

P33/TxD/SO1

P32/RxD/SI1

P36/TxD2/SO2

P35/RxD2/SI2

Caution Be sure to select the communication mode with the number of V

pulses as shown in Figure 18-1.

Figure 18-2. Selecting Format of Communication Mode

18.2.2 Function of flash memory programming

By transmitting/receiving commands and data in the selected communication mode, operations such as writing to the

flash memory are performed. Table 18-2 shows the major functions of flash memory programming.

Table 18-2. Major Functions of Flash Memory Programming.

Function

Description

Batch erase

Erases all contents of memory.

Block erase

Erases specified memory block with one block consisting of 16K bytes.

Batch blank check

Checks erased state of entire memory.

Block blank check

Checks erased state of specified block.

Data write

Writes to flash memory based on write start address and number of data written (number of bytes).

Batch verify

Compares all contents of memory with input data.

Block verify

Compares contents of specified memory block with input data.

10V

MODE/V

RESET

416

CHAPTER 18

PD78F4046

18.2.3 Connecting Flashpro II

How the Flashpro II is connected to the

PD78F4046 differs to the

PD78F4046 depending on the communication mode

(3-wire serial I/O or UART). Figures 18-3 and 18-4 show the connections in the respective modes.

Figure 18-3. Connecting Flashpro II in 3-Wire Serial I/O Mode

Figure 18-4. Connecting Flashpro II in UART Mode

18.3 Cautions

(1) Writing to the internal memory size select register (IMS) is valid only with the

PD78F4046. The IMS of the

PD784054

holds the value at RESET even if data is written to it.

(2) To develop a program for the

PD784054 using the

PD78F4046, set the value of the IMS to CDH. When the value

of the IMS is set to CDH, the peripheral RAM capacity of the

PD78F4046 is 768 bytes, but the peripheral RAM capacity

of the

PD784054 is 512 bytes. When using a mask ROM, therefore, exercise care that addresses 0FA00H through

0FAFFH of the peripheral RAM area of the

PD78F4046 are not used (when the LOCATION 0 instruction is executed).

Flashpro II

PD78F4046

RESET

SCK1 or SCK2

SI1 or SI2

SO1 or SO2

Flashpro II

PD78F4046

RESET

RxD or RxD2

TxD or TxD2

CHAPTER 19 INSTRUCTION OPERATIONS

19.1 Legend

(1) Explanation of operand identifiers (1/2)

Identifier

Explanation

r, r'

Note 1

X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7, R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)

Note 1

X(R0), A(R1), C(R2), B(R3), R4, R5, R6, R7

R8, R9, R10, R11, E(R12), D(R13), L(R14), H(R15)

V, U, T, W

rp, rp'

Note 2

AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5), DE(RP6), HL(RP7)

rp1

Note 2

AX(RP0), BC(RP1), RP2, RP3

rp2

VP(RP4), UP(RP5), DE(RP6), HL(RP7)

rg, rg'

VVP(RG4), UUP(RG5), TDE(RG6), WHL(RG7)

sfr

Special function register symbol (Refer to Special Function Register Application Table)

sfrp

Special function register symbol (register for which 16-bit operation is possible: Refer to Special

Function Register Application Table)

post

Note 2

AX(RP0), BC(RP1), RP2, RP3, VP(RP4), UP(RP5)/PSW, DE(RP6), HL(RP7)

Multiple descriptions are permissible. However, UP is only used with PUSH/POP instructions, and

PSW with PUSHU/POPU instructions.

mem

[TDE], [WHL], [TDE+], [WHL+], [TDE], [WHL], [VVP], [UUP]: Register indirect addressing

[TDE+byte], [WHL+byte], [SP+byte], [UUP+byte], [VVP+byte]: Based addressing

imm24 [A], imm24 [B], imm24 [DE], imm24 [HL]: Indexed addressing

[TDE+A], [TDE+B], [TDE+C], [WHL+A], [WHL+B], [WHL+C],

[VVP+DE], [VVP+HL]: Based indexed addressing

mem1

All mem except [WHL+] and [WHL]

mem2

[TDE], [WHL]

mem3

[AX], [BC], [RP2], [RP3], [VVP], [UUP], [TDE], [WHL]

Notes 1. Setting the RSS bit to 1 enables R4 to R7 to be used as X, A, C and B, but this function should only be used

when using a 78K/III series program.

2. Setting the RSS bit to 1 enables RP2 and RP3 to be used as AX and BC, but this function should only be used

when using a 78K/III series program.

417

418

CHAPTER 19 INSTRUCTION OPERATIONS

(1) Explanation of operand identifiers (2/2)

Identifier

Explanation

Note

saddr, saddr'

FD20H to FF1FH immediate data or label

saddr1

FE00H to FEFFH immediate data or label

saddr2

FD20H to FDFFH, FF00H to FF1FH immediate data or label

saddrp

FD20H to FF1EH immediate data or label (16-bit operation)

saddrp1

FE00H to FEFFH immediate data or label (16-bit operation)

saddrp2

FD20H to FDFFH, FF00H to FF1EH immediate data or label (16-bit operation)

saddrg

FD20H to FEFDH immediate data or label (24-bit operation)

saddrg1

FE00H to FEFDH immediate data or label (24-bit operation)

saddrg2

FD20H to FDFFH immediate data or label (24-bit operation)

addr24

0H to FFFFFFH immediate data or label

addr20

0H to FFFFFH immediate data or label

addr16

0H to FFFFH immediate data or label

addr11

800H to FFFH immediate data or label

addr8

0FE00H to 0FEFFH* immediate data or label

addr5

40H to 7EH immediate data or label

imm24

24-bit immediate data or label

word

16-bit immediate data or label

byte

8-bit immediate data or label

bit

3-bit immediate data or label

3-bit immediate data

locaddr

00H or 0FH

Note The addresses shown here apply when 00H is specified by the LOCATION instruction.

When 0FH is specified by the LOCATION instruction, F0000H should be added to the address values shown.

419

CHAPTER 19 INSTRUCTION OPERATIONS

(2) Operand column symbols

Symbol

Explanation

Auto-increment

Auto-decrement

Immediate data

16-bit absolute address

24-bit/20-bit absolute address

8-bit relative address

16-bit relative address

Bit inversion

[ ]

Indirect addressing

[%]

24-bit indirect addressing

(3) Flag column symbols

Symbol

Explanation

(Blank)

No change

Cleared to 0

Set to 1

Set or cleared depending on result

P/V flag operates as parity flag

P/V flag operates as overflow flag

Previously saved value is restored

(4) Operation column symbols

Symbol

Explanation

jdisp8

Signed two's complement data (8 bits) indicating relative address distance between start address of next

instruction and branch address

jdisp16

Signed two's complement data (16 bits) indicating relative address distance between start address of

next instruction and branch address

PC bits 16 to 19

PC bits 0 to 15

420

CHAPTER 19 INSTRUCTION OPERATIONS

(5) Number of bytes of instruction that includes mem in operands

mem Mode

Based

Indexed

Based Indexed

Addressing

Number of bytes

Note

Note One-byte instruction only when [TDE], [WHL], [TDE+], [TDE-], [WHL+] or [WHL] is written as mem in an MOV

instruction.

(6) Number of bytes of instruction that includes saddr, saddrp, r or rp in operands

For some instructions that include saddr, saddrp, r or rp in their operands, two "Bytes" entries are given, separated by

a slash ("/"). The entry that applies is shown in the table below.

Identifier

Left-Hand "Bytes" Figure

Right-Hand "Bytes" Figure

saddr

saddr2

saddr1

saddrp

saddrp2

saddrp1

rp1

rp2

(7) Code of instructions that include mem in operands and string instructions

Operands TDE, WHL, VVP and UUP (24-bit registers) can also be written as DE, HL, VP and UP respectively. However,

they are still treated as TDE, WHL, VVP and UUP (24-bit registers) when written as DE, HL, VP and UP.

421

CHAPTER 19 INSTRUCTION OPERATIONS

19.2 List of Operations

(1) 8-bit data transfer instruction: MOV

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOV

r, #byte

2/3

byte

saddr, #byte

3/4

(saddr)

byte

sfr, #byte

sfr

byte

!addr16, #byte

(saddr16)

byte

!!addr24, #byte

(addr24)

byte

r, r'

2/3

A, r

1/2

A, saddr2

(saddr2)

r, saddr

(saddr)

saddr2, A

(saddr2)

saddr, r

(saddr)

A, sfr

sfr

r, sfr

sfr

sfr, A

sfr

sfr, r

sfr

saddr, saddr'

(saddr)

(saddr')

r, !addr16

(addr16)

!addr16, r

(addr16)

r, !!addr24

(addr24)

!!addr24, r

(addr24)

A, [saddrp]

2/3

((saddrp))

A, [%saddrg]

3/4

((saddrg))

A, mem

1-5

(mem)

[saddrp], A

2/3

((saddrp))

[%saddrg], A

3/4

((saddrg))

mem, A

1-5

(mem)

PSWL, #byte

PSW

byte

PSWH, #byte

PSW

byte

PSWL, A

PSW

PSWH, A

PSW

A, PSWL

PSW

A, PSWH

PSW

r3, #byte

byte

A, r3

r3, A

422

CHAPTER 19 INSTRUCTION OPERATIONS

(2) 16-bit data transfer instruction: MOVW

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOVW

rp, #word

word

saddrp, #word

4/5

(saddrp)

word

sfrp, #word

sfrp

word

!addr16, #word

(addr16)

word

!!addr24, #word

(addr24)

word

rp, rp'

rp'

AX, saddrp2

(saddrp2)

rp, saddrp

(saddrp)

saddrp2, AX

(saddrp2)

saddrp, rp

(saddrp)

AX, sfrp

sfrp

rp, sfrp

sfrp

sfrp, AX

sfrp

sfrp, rp

sfrp

saddrp, saddrp'

(saddrp)

(saddrp')

rp, !addr16

(addr16)

!addr16, rp

(addr16)

rp, !!addr24

(addr24)

!!addr24, rp

(addr24)

AX, [saddrp]

3/4

((saddrp))

AX, [%saddrg]

3/4

((saddrg))

AX, mem

2-5

(mem)

[saddrp], AX

3/4

((saddrp))

[%saddrg], AX

3/4

((saddrg))

mem, AX

2-5

(mem)

423

CHAPTER 19 INSTRUCTION OPERATIONS

(3) 24-bit data transfer instruction: MOVG

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOVG

rg, #imm24

imm24

rg, rg'

rg'

rg, !!addr24

(addr24)

!!addr24, rg

(addr24)

rg, saddrg

(saddrg)

saddrg, rg

(saddrg)

WHL, [%saddrg]

3/4

WHL

((saddrg))

[%saddrg], WHL

3/4

((saddrg))

WHL

WHL, mem1

2-5

WHL

(mem1)

mem1, WHL

2-5

(mem1)

WHL

(4) 8-bit data exchange instruction: XCH

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

XCH

r, r'

2/3

A, r

1/2

A, saddr2

(saddr2)

r, saddr

(saddr)

r, sfr

sfr

saddr, saddr'

(saddr)

(saddr')

r, !addr16

(addr16)

r, !!addr24

(addr24)

A, [saddrp]

2/3

((saddrp))

A, [%saddrg]

3/4

((saddrg))

A, mem

2-5

(mem)

424

CHAPTER 19 INSTRUCTION OPERATIONS

(5) 16-bit data exchange instruction: XCHW

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

XCHW

rp, rp'

rp'

AX, saddrp2

(saddrp2)

rp, saddrp

(saddrp)

rp, sfrp

sfrp

AX, [saddrp]

3/4

((saddrp))

AX, [%saddrg]

3/4

((saddrg))

AX, !addr16

(addr16)

AX, !!addr24

(addr24)

saddrp, saddrp'

(saddrp)

(saddrp')

AX, mem

2-5

(mem)

(6) 8-bit operation instructions: ADD, ADDC, SUB, SUBC, CMP, AND, OR, XOR

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ADD

A, #byte

A, CY

A + byte

r, #byte

r, CY

r + byte

saddr, #byte

3/4

(saddr), CY

(saddr) + byte

sfr, #byte

sfr, CY

sfr + byte

r, r'

2/3

r, CY

r + r'

A, saddr2

A, CY

A + (saddr2)

r, saddr

r, CY

r + (saddr)

saddr, r

(saddr), CY

(saddr) + r

r, sfr

r, CY

r + sfr

sfr, r

sfr, CY

sfr + r

saddr, saddr'

(saddr), CY

(saddr) + (saddr')

A, [saddrp]

3/4

A, CY

A + ((saddrp))

A, [%saddrg]

3/4

A, CY

A + ((saddrg))

[saddrp], A

3/4

((saddrp)), CY

((saddrp)) + A

[%saddrg], A

3/4

((saddrg)), CY

((saddrg)) + A

A, !addr16

A, CY

A + (addr16)

A, !!addr24

A, CY

A + (addr24)

!addr16, A

(addr16), CY

(addr16) + A

!!addr24, A

(addr24), CY

(addr24) + A

A, mem

2-5

A, CY

A + (mem)

mem, A

2-5

(mem), CY

(mem) + A

425

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ADDC

A, #byte

A, CY

A + byte + CY

r, #byte

r, CY

r + byte + CY

saddr, #byte

3/4

(saddr), CY

(saddr) + byte + CY

sfr, #byte

sfr, CY

sfr + byte + CY

r, r'

2/3

r, CY

r + r' + CY

A, saddr2

A, CY

A + (saddr2) + CY

r, saddr

r, CY

r + (saddr) + CY

saddr, r

(saddr), CY

(saddr) + r + CY

r, sfr

r, CY

r + sfr + CY

sfr, r

sfr, CY

sfr + r + CY

saddr, saddr'

(saddr), CY

(saddr) + (saddr') + CY

A, [saddrp]

3/4

A, CY

A + ((saddrp)) + CY

A, [%saddrg]

3/4

A, CY

A + ((saddrg)) + CY

[saddrp], A

3/4

((saddrp)), CY

((saddrp)) + A + CY

[%saddrg], A

3/4

((saddrg)), CY

((saddrg)) + A + CY

A, !addr16

A, CY

A + (addr16) + CY

A, !!addr24

A, CY

A + (addr24) + CY

!addr16, A

(addr16), CY

(addr16) + A + CY

!!addr24, A

(addr24), CY

(addr24) + A + CY

A, mem

2-5

A, CY

A + (mem) + CY

mem, A

2-5

(mem), CY

(mem) + A + CY

426

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

SUB

A, #byte

A, CY

A byte

r, #byte

r, CY

r byte

saddr, #byte

3/4

(saddr), CY

(saddr) byte

sfr, #byte

sfr, CY

sfr byte

r, r'

2/3

r, CY

r r'

A, saddr2

A, CY

A (saddr2)

r, saddr

r, CY

r (saddr)

saddr, r

(saddr), CY

(saddr) r

r, sfr

r, CY

r sfr

sfr, r

sfr, CY

sfr r

saddr, saddr'

(saddr), CY

(saddr) (saddr')

A, [saddrp]

3/4

A, CY

A ((saddrp))

A, [%saddrg]

3/4

A, CY

A ((saddrg))

[saddrp], A

3/4

((saddrp)), CY

((saddrp)) A

[%saddrg], A

3/4

((saddrg)), CY

((saddrg)) A

A, !addr16

A, CY

A (addr16)

A, !!addr24

A, CY

A (addr24)

!addr16, A

(addr16), CY

(addr16) A

!!addr24, A

(addr24), CY

(addr24) A

A, mem

2-5

A, CY

A (mem)

mem, A

2-5

(mem), CY

(mem) A

427

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

SUBC

A, #byte

A, CY

A byte CY

r, #byte

r, CY

r byte CY

saddr, #byte

3/4

(saddr), CY

(saddr) byte CY

sfr, #byte

sfr, CY

sfr byte CY

r, r'

2/3

r, CY

r r' CY

A, saddr2

A, CY

A (saddr2) CY

r, saddr

r, CY

r (saddr) CY

saddr, r

(saddr), CY

(saddr) r CY

r, sfr

r, CY

r sfr CY

sfr, r

sfr, CY

sfr r CY

saddr, saddr'

(saddr), CY

(saddr) (saddr') CY

A, [saddrp]

3/4

A, CY

A ((saddrp)) CY

A, [%saddrg]

3/4

A, CY

A ((saddrg)) CY

[saddrp], A

3/4

((saddrp)), CY

((saddrp)) A CY

[%saddrg], A

3/4

((saddrg)), CY

((saddrg)) A CY

A, !addr16

A, CY

A (addr16) CY

A, !!addr24

A, CY

A (addr24) CY

!addr16, A

(addr16), CY

(addr16) A CY

!!addr24, A

(addr24), CY

(addr24) A CY

A, mem

2-5

A, CY

A (mem) CY

mem, A

2-5

(mem), CY

(mem) A CY

428

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

CMP

A, #byte

A byte

r, #byte

r byte

saddr, #byte

3/4

(saddr) byte

sfr, #byte

sfr byte

r, r'

2/3

r r'

A, saddr2

A (saddr2)

r, saddr

r (saddr)

saddr, r

(saddr) r

r, sfr

r sfr

sfr, r

sfr r

saddr, saddr'

(saddr) (saddr')

A, [saddrp]

3/4

A ((saddrp))

A, [%saddrg]

3/4

A ((saddrg))

[saddrp], A

3/4

((saddrp)) A

[%saddrg], A

3/4

((saddrg)) A

A, !addr16

A (addr16)

A, !!addr24

A (addr24)

!addr16, A

(addr16) A

!!addr24, A

(addr24) A

A, mem

2-5

A (mem)

mem, A

2-5

(mem) A

429

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

AND

A, #byte

byte

r, #byte

byte

saddr, #byte

3/4

(saddr)

byte

sfr, #byte

sfr

byte

r, r'

2/3

A, saddr2

(saddr2)

r, saddr

(saddr)

saddr, r

(saddr)

r, sfr

sfr

sfr, r

sfr

saddr, saddr'

(saddr)

(saddr')

A, [saddrp]

3/4

((saddrp))

A, [%saddrg]

3/4

((saddrg))

[saddrp], A

3/4

((saddrp))

[%saddrg], A

3/4

((saddrg))

A, !addr16

(addr16)

A, !!addr24

(addr24)

!addr16, A

(addr16)

!!addr24, A

(addr24)

A, mem

2-5

(mem)

mem, A

2-5

(mem)

430

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

A, #byte

byte

r, #byte

byte

saddr, #byte

3/4

(saddr)

byte

sfr, #byte

sfr

byte

r, r'

2/3

A, saddr2

(saddr2)

r, saddr

(saddr)

saddr, r

(saddr)

r, sfr

sfr

sfr, r

sfr

saddr, saddr'

(saddr)

(saddr')

A, [saddrp]

3/4

((saddrp))

A, [%saddrg]

3/4

((saddrg))

[saddrp], A

3/4

((saddrp))

[%saddrg], A

3/4

((saddrg))

A, !addr16

(addr16)

A, !!addr24

(addr24)

!addr16, A

(addr16)

!!addr24, A

(addr24)

A, mem

2-5

(mem)

mem, A

2-5

(mem)

431

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

XOR

A, #byte

byte

r, #byte

byte

saddr, #byte

3/4

(saddr)

byte

sfr, #byte

sfr

byte

r, r'

2/3

A, saddr2

(saddr2)

r, saddr

(saddr)

saddr, r

(saddr)

r, sfr

sfr

sfr, r

sfr

saddr, saddr'

(saddr)

(saddr')

A, [saddrp]

3/4

((saddrp))

A, [%saddrg]

3/4

((saddrg))

[saddrp], A

3/4

((saddrp))

[%saddrg], A

3/4

((saddrg))

A, !addr16

(addr16)

A, !!addr24

(addr24)

!addr16, A

(addr16)

!!addr24, A

(addr24)

A, mem

2-5

(mem)

mem, A

2-5

(mem)

432

CHAPTER 19 INSTRUCTION OPERATIONS

(7) 16-bit operation instructions: ADDW, SUBW, CMPW

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ADDW

AX, #word

AX, CY

AX + word

rp, #word

rp, CY

rp + word

rp, rp'

rp, CY

rp + rp'

AX, saddrp2

AX, CY

AX + (saddrp2)

rp, saddrp

rp, CY

rp + (saddrp)

saddrp, rp

(saddrp), CY

(saddrp) + rp

rp, sfrp

rp, CY

rp + sfrp

sfrp, rp

sfrp, CY

sfrp + rp

saddrp, #word

4/5

(saddrp), CY

(saddrp) + word

sfrp, #word

sfrp, CY

sfrp + word

saddrp, saddrp'

(saddrp), CY

(saddrp) + (saddrp')

SUBW

AX, #word

AX, CY

AX word

rp, #word

rp, CY

rp word

rp, rp'

rp, CY

rp rp'

AX, saddrp2

AX, CY

AX (saddrp2)

rp, saddrp

rp, CY

rp (saddrp)

saddrp, rp

(saddrp), CY

(saddrp) rp

rp, sfrp

rp, CY

rp sfrp

sfrp, rp

sfrp, CY

sfrp rp

saddrp, #word

4/5

(saddrp), CY

(saddrp) word

sfrp, #word

sfrp, CY

sfrp word

saddrp, saddrp'

(saddrp), CY

(saddrp) (saddrp')

CMPW

AX, #word

AX word

rp, #word

rp word

rp, rp'

rp rp'

AX, saddrp2

AX (saddrp2)

rp, saddrp

rp (saddrp)

saddrp, rp

(saddrp) rp

rp, sfrp

rp sfrp

sfrp, rp

sfrp rp

saddrp, #word

4/5

(saddrp) word

sfrp, #word

sfrp word

saddrp, saddrp'

(saddrp) (saddrp')

433

CHAPTER 19 INSTRUCTION OPERATIONS

(8) 24-bit operation instructions: ADDG, SUBG

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ADDG

rg, rg'

rg, CY

rg + rg'

rg, # imm24

rg, CY

rg + # imm24

WHL, saddrg

WHL, CY

WHL + (saddrg)

SUBG

rg, rg'

rg, CY

rg rg'

rg, # imm24

rg, CY

rg imm24

WHL, saddrg

WHL, CY

WHL (saddrg)

(9) Multiplication instructions: MULU, MULUW, MULW, DIVUW, DIVUX

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MULU

2/3

MULUW

AX (upper half), rp (lower half)

MULW

AX (upper half), rp (lower half)

DIVUW

2/3

AX (quotient), r (remainder)

Note 1

DIVUX

AXDE (quotient), rp (remainder)

AXDE

Note 2

Notes 1. When r = 0, r

X, AX

FFFFH

2. When rp = 0, pr

DE, AXDE

FFFFFFFFH

(10) Special operation instructions: MACW, MACSW, SACW

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MACW

byte

AXDE

(B)

B + 2,

C + 2, byte

byte 1

End if(byte = 0 or P/V = 1)

MACSW

byte

AXDE

(B)

B + 2,

C + 2, byte

byte 1

if byte = 0 then End

if P/V = 1 then

if overflow AXDE

7FFFFFFFH, End

if underflow AXDE

80000000H, End

SACW

[TDE + ], [WHL + ]

|(TDE) (WHL)| + AX,

TDE

TDE + 2, WHL

WHL + 2

C 1 End if(C = 0 or CY = 1)

434

CHAPTER 19 INSTRUCTION OPERATIONS

(11) Increment/decrement instructions: INC, DEC, INCW, DECW, INCG, DECG

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

INC

1/2

r + 1

saddr

2/3

(saddr)

(saddr) + 1

DEC

1/2

r 1

saddr

2/3

(saddr)

(saddr) 1

INCW

2/1

rp + 1

saddrp

3/4

(saddrp)

(saddrp) + 1

DECW

2/1

rp 1

saddrp

3/4

(saddrp)

(saddrp) 1

INCG

rg + 1

DECG

rg 1

(12) Adjustment instructions: ADJBA, ADJBS, CVTBW

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ADJBA

Decimal Adjust Accumulator after Addition

ADJBS

Decimal Adjust Accumulator after Subtract

CVTBW

A, A

00H if A

= 0

A, A

FFH if A

= 1

435

CHAPTER 19 INSTRUCTION OPERATIONS

(13) Shift/rotate instructions: ROR, ROL, RORC, ROLC, SHR, SHL, SHRW, SHLW, ROR4, ROL4

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

ROR

r, n

2/3

(CY,

rm 1

)

n times n = 0 7

ROL

r, n

2/3

(CY,

rm + 1

)

n times n = 0 7

RORC

r, n

2/3

(CY

CY,

rm 1

)

n times n = 0 7

ROLC

r, n

2/3

(CY

CY,

+ 1

)

n times n = 0 7

SHR

r, n

2/3

(CY

rm 1

)

n times n = 0 7

SHL

r, n

2/3

(CY

rm + 1

)

n times n = 0 7

SHRW

rp, n

(CY

rp0

rp15

rpm 1

rpm)

n times

n = 0 7

SHLW

rp, n

(CY

rp15

rp0

rpm + 1

rpm)

n times

n = 0 7

ROR4

mem3

3 0

(mem3)

3 0

, (mem3)

7 4

3 0

(mem3)

3 0

(mem3)

7 4

ROL4

mem3

3 0

(mem3)

7 4

, (mem3)

3 0

(mem3)

7 4

(mem3)

3 0

(14) Bit manipulation instructions: MOV1, AND1, OR1, XOR1, NOT1, SET1, CLR1

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOV1

CY, saddr. bit

3/4

(saddr. bit)

CY, sfr. bit

sfr. bit

CY, X. bit

X. bit

CY, A. bit

A. bit

CY, PSWL. bit

PSWL. bit

CY, PSWH. bit

PSWH. bit

CY, !addr16. bit

!addr16.bit

CY, !!addr24. bit

!!addr24. bit

CY, mem2. bit

mem2. bit

saddr. bit, CY

3/4

(saddr. bit)

sfr. bit, CY

sfr. bit

X. bit, CY

X.bit

A. bit, CY

A. bit

PSWL. bit, CY

PSWL. bit

PSWH. bit, CY

PSWH. bit

!addr16. bit, CY

!addr16.bit

!!addr24.bit, CY

!!addr24.bit

mem2. bit, CY

mem2. bit

436

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

AND1

CY, saddr. bit

3/4

(saddr. bit)

CY, /saddr. bit

3/4

(saddr. bit)

CY, sfr. bit

sfr. bit

CY, /sfr. bit

sfr. bit

CY, X. bit

X. bit

CY, /X. bit

X. bit

CY, A. bit

A. bit

CY, /A. bit

A. bit

CY, PSWL. bit

PSW

. bit

CY, /PSWL. bit

PSW

. bit

CY, PSWH. bit

PSW

. bit

CY, /PSWH. bit

PSW

. bit

CY, !addr16. bit

!addr16. bit

CY, /!addr16. bit

!addr16. bit

CY, !!addr24. bit

!!addr24. bit

CY, /!!addr24. bit

!!addr24. bit

CY, mem2. bit

mem2. bit

CY, /mem2. bit

mem2. bit

OR1

CY, saddr. bit

3/4

(saddr. bit)

CY, /saddr. bit

3/4

(saddr. bit)

CY, sfr. bit

sfr. bit

CY, /sfr. bit

sfr. bit

CY, X. bit

X. bit

CY, /X. bit

X. bit

CY, A. bit

A. bit

CY, /A. bit

A. bit

CY, PSWL. bit

PSW

. bit

CY, /PSWL. bit

PSW

. bit

CY, PSWH. bit

PSW

. bit

CY, /PSWH. bit

PSW

. bit

CY, !addr16. bit

!addr16. bit

CY, /!addr16. bit

!addr16. bit

CY, !!addr24. bit

!!addr24. bit

CY, /!!addr24. bit

!!addr24. bit

CY, mem2. bit

mem2. bit

CY, /mem2. bit

mem2. bit

437

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

XOR1

CY, saddr. bit

3/4

(saddr. bit)

CY, sfr. bit

sfr. bit

CY, X. bit

X. bit

CY, A. bit

A. bit

CY, PSWL. bit

PSWL. bit

CY, PSWH. bit

PSWH. bit

CY, !addr16. bit

!addr16. bit

CY, !!addr24. bit

!!addr24. bit

CY, mem2. bit

mem2. bit

NOT1

saddr. bit

3/4

(saddr. bit)

sfr. bit

X. bit

A. bit

PSWL. bit

PSW

. bit

PSWH. bit

PSW

. bit

!addr16. bit

!!addr24. bit

mem2. bit

SET1

saddr. bit

2/3

(saddr. bit)

sfr. bit

X. bit

A. bit

PSWL. bit

PSWH. bit

!addr16. bit

!!addr24. bit

mem2. bit

CLR1

saddr. bit

2/3

(saddr. bit)

sfr. bit

X. bit

A. bit

PSWL. bit

PSWH. bit

!addr16. bit

!!addr24. bit

mem2. bit

438

CHAPTER 19 INSTRUCTION OPERATIONS

(15) Stack manipulation instructions: PUSH, PUSHU, POP, POPU, MOVG, ADDWG, SUBWG, INCG, DECG

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

PUSH

PSW

(SP 2)

PSW, SP

SP 2

sfrp

(SP 2)

sfrp, SP

SP 2

sfr

(SP 1)

sfr, SP

SP 1

post

{(SP 2)

post, SP

SP 2}

m times

Note

(SP 3)

rg, SP

SP 3

PUSHU

post

{(UUP 2)

post, UUP

UUP 2}

m times

Note

POP

PSW

(SP), SP

SP + 2

sfrp

(SP), SP

SP + 2

sfr

(SP), SP

SP + 1

post

{post

(SP), SP

SP + 2}

m times

Note

(SP), SP

SP + 3

POPU

post

{post

(UUP), UUP

UUP + 2}

m times

Note

MOVG

SP, # imm24

imm24

SP, WHL

WHL

WHL, SP

WHL

ADDWG

SP, #word

SP + word

SUBWG

SP, #word

SP word

INCG

SP + 1

DECG

SP 1

Note m = number of registers specified by "post"

439

CHAPTER 19 INSTRUCTION OPERATIONS

(16) Call/return instructions: CALL, CALLF, CALLT, BRK, BRKCS, RET, RETI, RETB, RETCS, RETCSB

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

CALL

!addr16

(SP 3)

(PC + 3), SP

SP 3,

0, PC

addr16

!!addr20

(SP 3)

(PC + 4), SP

SP 3,

addr20

(SP 3)

(PC + 2), SP

SP 3,

0, PC

(SP 3)

(PC + 2), SP

SP 3,

[rp]

(SP 3)

(PC + 2), SP

SP 3,

0, PC

(rp)

[rg]

(SP 3)

(PC + 2), SP

SP 3,

(rg)

$!addr20

(SP 3)

(PC + 3), SP

SP 3,

PC + 3 + jdisp16

CALLF

!addr11

(SP 3)

(PC + 2), SP

SP 3,

19 12

0, PC11

1, PC

10 0

addr11

CALLT

[addr5]

(SP 3)

(PC + 1), SP

SP 3,

0, PC

(addr5)

BRK

(SP 2)

PSW, (SP 1)

0 3

(PC + 1)

(SP 4)

(PC + 1)

SP 4

0, PC

(003EH)

BRKCS

RBn

RP2, RP3

PSW, RBS2 0

RSS

0, IE

0, RP3

8 11

, PC

RET

(SP), SP

SP + 3

RET1

(SP), PC

(SP + 3)

0 3

PSW

(SP + 2), SP

SP + 4

Clears to 0 flag with highest priority of flags

of ISPR that are set (1)

RETB

(SP), PC

(SP + 3)

0 3

PSW

(SP + 2), SP

SP + 4

RETCS

!addr16

PSW

RP3, PC

RP2, RP2

addr16,

RP3

8 11

Clears to 0 flag with highest priority of flags

of ISPR that are set (1)

RETCSB

!addr16

PSW

RP3, PC

RP2, RP2

addr16,

RP3

8 11

440

CHAPTER 19 INSTRUCTION OPERATIONS

(17) Unconditional branch instruction: BR

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

!addr16

0, PC

addr16

!!addr20

addr20

0, PC

[rp]

0, PC

(rp)

[rg]

(rg)

$addr20

PC + 2 + jdisp8

$!addr20

PC + 3 + jdisp16

441

CHAPTER 19 INSTRUCTION OPERATIONS

(18) Conditional branch instructions: BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT,

BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

BNZ

$addr20

PC + 2 + jdisp8 if Z = 0

BNE

$addr20

PC + 2 + jdisp8 if Z = 1

BNC

$addr20

PC + 2 + jdisp8 if CY = 0

BNL

$addr20

PC + 2 + jdisp8 if CY = 1

BNV

$addr20

PC + 2 + jdisp8 if P/V = 0

BPO

$addr20

PC + 2 + jdisp8 if P/V = 1

BPE

$addr20

PC + 2 + jdisp8 if S = 0

$addr20

PC + 2 + jdisp8 if S = 1

BLT

$addr20

PC + 3 + jdisp8 if P/V

S = 1

BGE

$addr20

PC + 3 + jdisp8 if P/V

S = 0

BLE

$addr20

PC + 3 + jdisp8 if (P/V

Z = 1

BGT

$addr20

PC + 3 + jdisp8 if (P/V

Z = 0

BNH

$addr20

PC + 3 + jdisp8 if Z

CY = 1

$addr20

PC + 3 + jdisp8 if Z

CY = 0

saddr. bit, $addr20

4/5

PC + 4

Note

+ jdisp8 if (saddr. bit) = 0

sfr. bit, $addr20

PC + 4 + jdisp8 if sfr. bit = 0

X. bit, $addr20

PC + 3 + jdisp8 if X. bit = 0

A. bit, $addr20

PC + 3 + jdisp8 if A. bit = 0

PSWL. bit, $addr20

PC + 3 + jdisp8 if PSW

. bit = 0

PSWH. bit, $addr20

PC + 3 + jdisp8 if PSW

. bit = 0

!addr16. bit, $addr20

PC + 3 + jdisp8 if !addr16. bit = 0

!!addr24. bit, $addr20

PC + 3 + jdisp8 if !!addr24. bit = 0

mem2. bit, $addr20

PC + 3 + jdisp8 if mem2. bit = 0

Note When the number of bytes is 4. When 5, the operation is: PC

PC + 5 + jdisp8.

442

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

saddr. bit, $addr20

3/4

PC + 3

Note 1

+ jdisp8 if (saddr. bit) = 1

sfr. bit, $addr20

PC + 4 + jdisp8 if sfr. bit = 1

X. bit, $addr20

PC + 3 + jdisp8 if X. bit = 1

A. bit, $addr20

PC + 3 + jdisp8 if A. bit = 1

PSWL. bit, $addr20

PC + 3 + jdisp8 if PSW

. bit = 1

PSWH. bit, $addr20

PC + 3 + jdisp8 if PSW

. bit = 1

!addr16. bit, $addr20

PC + 3 + jdisp8 if !addr16. bit = 1

!!addr24. bit, $addr20

PC + 3 + jdisp8 if !!addr24. bit = 1

mem2. bit, $addr20

PC + 3 + jdisp8 if mem2. bit = 1

BTCLR

saddr. bit, $addr20

4/5

{PC

PC + 4

Note 2

+ jdisp8, (saddr. bit)

if (saddr. bit) = 1

sfr. bit, $addr20

{PC

PC + 4 + jdisp8, sfr. bit

0} if sfr. bit = 1

X. bit, $addr20

{PC

PC + 3 + jdisp8, X. bit

0} if X. bit = 1

A. bit, $addr20

{PC

PC + 3 + jdisp8, A. bit

0} if A. bit = 1

PSWL. bit, $addr20

{PC

PC + 3 + jdisp8, PSW

. bit

if PSW

. bit = 1

PSWH. bit, $addr20

{PC

PC + 3 + jdisp8, PSW

. bit

if PSW

. bit = 1

!addr16. bit, $addr20

{PC

PC + 3 + jdisp8, !addr16. bit

if !addr16. bit = 1

!!addr24. bit, $addr20

{PC

PC + 3 + jdisp8, !!addr24. bit

if !!addr24. bit = 1

mem2. bit, $addr20

{PC

PC + 3 + jdisp8, mem2. bit

if mem2. bit = 1

Notes 1. When the number of bytes is 3. When 4, the operation is: PC

PC + 4 + jdisp8.

2. When the number of bytes is 4. When 5, the operation is: PC

PC + 5 + jdisp8.

443

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

BFSET

saddr. bit, $addr20

4/5

{PC

PC + 4

Note 2

+ jdisp8, (saddr. bit)

if (saddr. bit) = 0

sfr. bit, $addr20

{PC

PC + 4 + jdisp8, sfr. bit

1} if sfr. bit = 0

X. bit, $addr20

{PC

PC + 3 + jdisp8, X. bit

1} if X. bit = 0

A. bit, $addr20

{PC

PC + 3 + jdisp8, A. bit

1} if A. bit = 0

PSWL. bit, $addr20

{PC

PC + 3 + jdisp8, PSW

. bit

if PSW

. bit = 0

PSWH. bit, $addr20

{PC

PC + 3 + jdisp8, PSW

. bit

if PSW

. bit = 0

!addr16. bit, $addr20

{PC

PC + 3 + jdisp8, !addr16. bit

if !addr16. bit = 0

!!addr24. bit, $addr20

{PC

PC + 3 + jdisp8, !!addr24. bit

if !!addr24. bit = 0

mem2. bit, $addr20

{PC

PC + 3 + jdisp8, mem2. bit

if mem2. bit = 0

DBNZ

B, $addr20

B 1, PC

PC + 2 + jdisp8 if B

C, $addr20

C 1, PC

PC + 2 + jdisp8 if C

$addr, $addr20

3/4

(saddr)

(saddr) 1,

PC + 3

Note 1

= jdisp8 if (saddr)

Notes 1. When the number of bytes is 3. When 4, the operation is: PC

PC + 4 + jdisp8.

2. When the number of bytes is 4. When 5, the operation is: PC

PC + 5 + jdisp8.

(19) CPU control instructions: MOV, LOCATION, SEL, SWRS, NOP, EI, DI

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOV

STBC, #byte

STBC

byte

WDM, #byte

WDM

byte

LOCATION

locaddr

SFR, internal data area location address

upper word specification

SEL

RBn

RSS

0, RBS2 0

RBn, ALT

RSS

1, RBS2 0

SWRS

RSS

NOP

No Operaton

1 (Enable interrupt)

0 (Disable interrupt)

444

CHAPTER 19 INSTRUCTION OPERATIONS

(20) Special instructions: CHKL, CHKLA

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

CHKL

sfr

(Pin level)

(output latch)

CHKLA

sfr

(pin level)

(output latch)

(21) String instructions:

MOVTBLW, MOVM, XCHM, MOVBK, XCHBK, CMPME, CMPMNE, CMPMC, CMPMNC,

CMPBKE, CMPBKNE, CMPBKC, CMPBKNC

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

MOVTBLW

!addr8, byte

(addr8 + 2)

(addr8), byte

byte 1,

addr8

addr8 2 End if byte = 0

MOVW

[TDE + ], A

(TDE)

A, TDE

TDE + 1, C

C 1 End if C = 0

[TDE ], A

(TDE)

A, TDE

TDE 1, C

C 1 End if C = 0

XCHM

[TDE + ], A

(TDE)

A, TDE

TDE + 1, C

C 1 End if C = 0

[TDE ], A

(TDE)

A, TDE

TDE 1, C

C 1 End if C = 0

MOVBK

[TDE + ], [WHL +]

(TDE)

(WHL), TDE

TDE + 1,

WHL

WHL + 1, C

C 1 End if C = 0

[TDE ], [WHL ]

(TDE)

(WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0

XCHBK

[TDE + ], [WHL +]

(TDE)

(WHL), TDE

TDE +1,

WHL

WHL + 1, C

C 1 End if C = 0

[TDE ], [WHL ]

(TDE)

(WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0

CMPME

[TDE + ], A

(TDE) A, TDE

TDE + 1, C

C 1 End if C = 0 or Z = 0

[TDE ], A

(TDE) A, TDE

TDE 1, C

C 1 End if C = 0 or Z = 0

CMPMNE

[TDE + ], A

(TDE) A, TDE

TDE + 1, C

C 1 End if C = 0 or Z = 1

[TDE ], A

(TDE) A, TDE

TDE 1, C

C 1 End if C = 0 or Z = 1

CMPMC

[TDE + ], A

(TDE) A, TDE

TDE + 1, C

C 1 End if C = 0 or CY = 0

[TDE ], A

(TDE) A, TDE

TDE 1, C

C 1 End if C = 0 or CY = 0

CMPMNC

[TDE + ], A

(TDE) A, TDE

TDE + 1, C

C 1 End if C = 0 or CY = 1

[TDE ], A

(TDE) A, TDE

TDE 1, C

C 1 End if C = 0 or CY = 1

CMPBKE

[TDE + ], [WHL +]

(TDE)

(WHL), TDE

TDE + 1,

WHL

WHL + 1, C

C 1 End if C = 0 or Z = 0

[TDE ], [WHL ]

(TDE)

(WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0 or Z = 0

445

CHAPTER 19 INSTRUCTION OPERATIONS

Mnemonic

Operands

Bytes

Operation

Flags

AC P/V CY

CMPBKNE

[TDE + ], [WHL +]

(TDE) (WHL), TDE

TDE + 1,

WHL

WHL + 1, C

C 1 End if C = 0 or Z = 1

[TDE ], [WHL ]

(TDE) (WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0 or Z = 1

CMPBKC

[TDE + ], [WHL +]

(TDE) (WHL), TDE

TDE + 1,

WHL

WHL + 1, C

C 1 End if C = 0 or CY = 0

[TDE ], [WHL ]

(TDE) (WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0 or CY = 0

CMPBKNC

[TDE + ], [WHL +]

(TDE) (WHL), TDE

TDE + 1,

WHL

WHL + 1, C

C 1 End if C = 0 or CY = 1

[TDE ], [WHL ]

(TDE) (WHL), TDE

TDE 1,

WHL

WHL 1, C

C 1 End if C = 0 or CY = 1

446

CHAPTER 19 INSTRUCTION OPERATIONS

19.3 Instructions Listed by Type of Addressing

(1) 8-bit instructions (combinations expressed by writing A for r are shown in parentheses)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND OR XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC,

SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK,

XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 19-1. List of Instructions by 8-Bit Addressing

2nd Operand

saddr

!addr16

mem

[WHL +]

# byte

sfr

[saddrp]

PSWL

None*

1st Operand

saddr'

!!addr24

[%saddrg]

PSWH

[WHL ]

(MOV)

MOV

(MOV)*

MOV

(MOV)

MOV

(MOV)

ADD*

(XCH)

XCH

(XCH)*

(XCH)

XCH

(XCH)

(ADD)*

1, 6

(ADD)*

ADD*

(ADD)*

MOV

(MOV)

MOV

ROR*

MULU

ADD*

(XCH)

XCH

DIVUW

(ADD)*

ADD*

INC

DEC

saddr

MOV

MOV*

MOV

INC

ADD*

(ADD)*

ADD*

XCH

DEC

ADD*

DBNZ

sfr

MOV

PUSH

ADD*

(ADD)*

ADD*

POP

CHKL

CHKLA

!addr16

MOV

(MOV)

MOV

!!addr24

(ADD)*

mem

MOV

[saddrp]

ADD*

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE +]

(MOV)

MOVBK*

[TDE ]

(ADD)*

MOVM*

* 1. ADDC, SUB, SUBC, AND, OR, XOR and CMP are the same as ADD.

2. There is no 2nd operand, or the 2nd operand is not an operand address.

3. ROL, RORC, ROLC, SHR and SHL are the same as ROR.

4. XCHM, CMPME, CMPMNE, CMPMNC and CMPMC are the same as MOVM.

5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC and CMPBKC are the same as MOVBK.

6. If saddr is saddr2 in this combination, there is a short code length instruction.

447

CHAPTER 19 INSTRUCTION OPERATIONS

(2) 16-bit instructions (combinations expressed by writing AX for rp are shown in parentheses)

MOVM, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,

ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 19-2. List of Instructions by 16-Bit Addressing

2nd Operand

saddrp

!addr16

mem

# word

sfrp

[saddrp]

[WHL +]

byte

None*

1st Operand

saddrp'

!!addr24

[%saddrg]

(MOVW)

(MOVW)*

MOVW

(MOVW)

MOVW

(MOVW)

ADDW*

(XCHW)

(XCHW)*

(XCHW)

XCHW

(XCHW)

(ADD)*

(ADDW)*

1,3

(ADDW)*

MOVW

(MOVW)

MOVW

SHRW

MULW*

ADDW*

(XCHW)

XCHW

SHLW

INCW

(ADDW)*

ADDW*

DECW

saddrp

MOVW

(MOVW)*

MOVW

INCW

ADDW*

(ADDW)*

ADDW*

XCHW

DECW

ADDW*

sfrp

MOVW

PUSH

ADDW*

(ADDW)*

ADDW*

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE +]

(MOVW)

SACW

byte

MACW

MACSW

* 1. SUBW and CMPW are the same as ADDW.

2. There is no 2nd operand, or the 2nd operand is not an operand address.

3. If saddrp is saddrp2 in this combination, there is a short code length instruction.

4. MULUW and DIVUX are the same as MULW.

448

CHAPTER 19 INSTRUCTION OPERATIONS

(3) 24-bit instructions (combinations expressed by writing WHL for rg are shown in parentheses)

MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP

Table 19-3. List of Instructions by 24-Bit Addressing

2nd Operand

# imm24

WHL

saddrg

!!addr24

mem1

[%saddrg]

None*

1st Operand

rg'

WHL

(MOVG)

MOVG

(ADDG)

ADDG

(SUBG)

SUBG

MOVG

(MOVG)

MOVG

INCG

ADDG

(ADDG)

ADDG

DECG

SUBG

(SUBG)

SUBG

PUSH

POP

saddrg

(MOVG)

MOVG

!!addr24

(MOVG)

MOVG

mem1

MOVG

[%saddrg)

MOVG

INCG

DECG

There is no 2nd operand, or the 2nd operand is not an operand address.

(4) Bit manipulation instructions

MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET

Table 19-4. List of Instructions by Bit Manipulation Instruction Addressing

2nd Operand

saddr. bit sfr. bit

/saddr.bit /sfr. bit

A.bit X. bit

/A. bit /X. bit

PSWL. bit PSWH. bit

/PSWL. bit /PSWH. bit

None*

mem2. bit

/mem2. bit

!addr16. bit

/!addr16. bit

1st Operand

!!addr24. bit

/!!addr24. bit

MOV1

AND1

NOT

AND1

OR1

SET1

OR1

CLR1

XOR1

saddr. bit

MOV1

NOT1

sfr. bit

SET1

A. bit

CLR1

X. bit

PSWL. bit

PSWH. bit

BTCLR

mem2. bit

BFSET

!addr16. bit

!!addr24. bit

There is no 2nd operand, or the 2nd operand is not an operand address.

449

CHAPTER 19 INSTRUCTION OPERATIONS

(5) Call/return instructions / branch instructions

CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC,

BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ

Table 19-5. List of Instructions by Call/Return Instruction/Branch Instruction Addressing

Instruction

Address

$addr20 $!addr20

!addr16

!!addr20

[rp]

[rg]

!addr11

[addr5]

RBn

None

Operand

Basic

BC*

CALL

CALLF

CALLT

BRKCS

BRK

instructions

RET

RETCS

RETI

RETCSB

RETB

Compound

instructions

BTCLR

BFSET

DBNZ

BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same

as BC.

(6) Other instructions

ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS

[MEMO]

450

CHAPTER 20 CAUTIONS ON USING DEVELOPMENT TOOLS

When developing a program by using in-circuit emulator IE-784000-R, note the following point.

(1) Setting of standby control register (STBC)

Include an instruction that sets the standby control register (STBC) to 00H following the LOCATION instruction and

initialization of the stack pointer (SP) in the program after reset is cleared.

Program example:

RSTVCT

CSEG

AT 0

RSTSTRT

INITSEG

CSEG

BASE

RSTSTRT:

LOCATION 0H; or LOCATION 0FH

MOVG

SP, #STKBGN

MOV

STBC, #0H

Reason: The internal system clock of the

PD784054 is fixed to f

/2. However, the internal system clock of the

in-circuit emulator is set to f

/16 after reset has been cleared. Therefore, the setting of the STBC must

be changed as described above.

Even if the instruction that sets the STBC to 00H is executed, the operation is not affected because the STBC of the real

chip is fixed to 30H. For the same reason, the value of the STBC of the real chip is always 30H when it is read. The value

of the STBC on the in-circuit emulator, however, is changed to 00H when the above setting is made. Therefore, note that

the value of the STBC of the in-circuit emulator and that of the real chip differ when they are read.

(2) Output of CLKOUT pin

The CLKOUT pin of the real chip always outputs the oscillation frequency (f

). However, in the case of the in-circuit

emulator IE-784000-R, the internal system clock (f

/2 or f

/16

Note

) is output. Note that f

is not output from the in-

circuit emulator.

Note

The CLKOUT pin output of the in-circuit emulator is set to f

/16 after the reset has been released, and set to

/2 when 00H is set to the standby control register (STBC).

451

[MEMO]

452

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for the development of systems that employ the

PD784054.

Figure A-1 shows the development tool configuration.

Figure A-1. Development Tool Configuration (1/2)

(1) When using the in-circuit emulator IE-78K4-NS

· System simulator
· Integrated debugger
· Device file

Embedded Software

· Real-time OS
· OS

Debugging Tool

· Assembler package
· C compiler package
· C library source file
· Device file

Language Processing Software

Flash memory
write adapter

In-circuit Emulator

Power supply unit

Emulation probe

Conversion socket or
conversion adapter

Target system

Host Machine (PC)

Interface adapter,
PC card interface, etc.

Emulation board

On-chip flash
memory version

Flash Memory

Write Environment

Flash programmer

453

454

APPENDIX A DEVELOPMENT TOOLS

Figure A-1. Development Tool Configuration (2/2)

(2) When using the in-circuit emulator IE-784000-R

Remark

Items in broken line boxes differ according to the development environment. Refer to A.3.1. Hardware.

· System simulator
· Integrated debugger
· Device file

Embedded Software

· Real-time OS
· OS

Debugging Tool

· Assembler package
· C compiler package
· C library source file
· Device file

Language Processing Software

Flash memory
write adapter

In-circuit Emulator

Emulation probe

Conversion socket or
conversion adapter

Target system

Host Machine (PC or EWS)

Interface board

Interface adapter

Emulation board

I/O emulation board

Probe board

Emulation probe conversion board

On-chip flash
memory version

Flash Memory

Write Environment

Flash programmer

455

APPENDIX A DEVELOPMENT TOOLS

A.1 Language Processing Software

RA78K4

Assembler Package

CC78K4

C Compiler Package

DF784046

Note

Device File

CC78K4-L

C Library Source File

Note The DF784046 can be used in common with the RA78K4, CC78K4, SM78K4, ID78K4-NS, and ID78K4.

This assembler converts programs written in mnemonics into an object codes

executable with a microcomputer.

Further, this assembler is provided with functions capable of automatically creating

symbol tables and branch instruction optimization.

This assembler should be used in combination with an optical device file (DF784046).

This assembler package is a DOS-based application. It can also be used in Windows,

however, by using the Project Manager (included in assembler package) on Win-

dows.

Part Number:

××××

RA78K4

This compiler converts programs written in C language into object codes executable

with a microcomputer.

This compiler should be used in combination with an optical assembler package and

device file.

This C compiler package is a DOS-based application. It can also be used in Win-

dows, however, by using the Project Manager (included in assembler package) on

Windows.

Part Number:

××××

CC78K4

This file contains information peculiar to the device.

This device file should be used in combination with an optional tool (RA78K4,

CC78K4, SM78K4, ID78K4-NS, and ID78K4).

Corresponding OS and host machine differ depending on the tool to be used with.

Part Number:

××××

DF780024,

××××

DF780034

This is a source file of functions configuring the object library included in the C

compiler package (CC78K/0).

This file is required to match the object library included in C compiler package to the

customer's specifications.

The operating environment does not depend on the OS because this is a source file.

Part Number:

××××

CC78K4-L

456

APPENDIX A DEVELOPMENT TOOLS

Remark

××××

in the part number differs depending on the host machine and OS used.

××××

RA78K4

××××

CC78K4

××××

DF784046

××××

CC78K4-L

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HD FD

AB13

IBM PC/AT

and its compatibles

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HC FD

BB13

Windows (English version)

Notes 1, 2

3P16

HP9000 Series 700

HP-UX (Rel. 9.05)

DAT (DDS)

3K13

SPARCstation

SunOS (Rel. 4.1.4)

3.5-inch 2HC FD

3K15

1/4-inch CGMT

3R13

NEWS

(RISC)

NEWS-OS (Rel. 6.1)

3.5-inch 2HC FD

Notes 1. Can be operated in DOS environment.

2. Not support WindowsNT

A.2 Flash Memory Writing Tools

Flashpro II (type FL-PR2)

Flash Programmer

FA-80GC

Flash Memory Writing Adapter

Remark

Flashpro II and FA-80GC are products of Naito Densei Machida Mfg. Co., Ltd.

Phone: (044) 822-3813 Naito Densei Machida Mfg. Co., Ltd.

Flash programmer dedicated to microcontrollers with on-chip flash memory.

Flash memory writing adapter used connected to the Flashpro II.

· FA-80GC : 80-pin plastic QFP (GC-3B9 type)

457

APPENDIX A DEVELOPMENT TOOLS

A.3 Debugging Tools

A.3.1 Hardware (1/2)

(1) When using the in-circuit emulator IE-78K4-NS

IE-78K4-NS

Note

In-circuit Emulator

IE-70000-MC-PS-B

Power Supply Unit

IE-70000-98-IF-C

Note

Interface Adapter

IE-70000-CD-IF

Note

PC Card Interface

IE-70000-PC-IF-C

Note

Interface Adapter

IE-784046-NS-EM1

Note

Emulation Board

NP-80GC

Emulation Probe

EV-9200GC-80

Conversion Socket

(Refer to Figures

A-2 and A-3)

Note Under development

Remarks 1. NP-80GC is a product of Naito Densei Machida Mfg. Co., Ltd.

Phone: (044) 822-3813 Naito Densei Machida Mfg. Co., Ltd.

2. EV-9200GC-80 is sold in five units.

The in-circuit emulator serves to debug hardware and software when developing

application systems using a 78K/IV Series product. It corresponds to integrated

debugger (ID78K4-NS). This emulator should be used in combination with power

supply unit, emulation probe, and interface adapter which is required to connect this

emulator to the host machine.

This adapter is used for supplying power from a receptacle of 100-V to 200-V AC.

This adapter is required when using the PC-9800 Series computer (except notebook

type) as the IE-78K4-NS host machine.

This is PC card and interface cable required when using the PC-9800 Series

notebook-type computer as the IE-78K4-NS host machine.

This adapter is required when using the IBM PC/AT and its compatible computers

as the IE-78K4-NS host machine.

This board emulates the operations of the peripheral hardware peculiar to a device.

It should be used in combination with an in-circuit emulator.

This probe is used to connect the in-circuit emulator to the target system and is

designed for 80-pin plastic QFP (GC-3B9 type).

This conversion socket connects the NP-80GC to the target system board designed

to mount a 80-pin plastic QFP (GC-3B9 type).

458

APPENDIX A DEVELOPMENT TOOLS

A.3.1 Hardware (2/2)

(2) When using the in-circuit emulator IE-784000-R

IE-784000-R

In-circuit Emulator

IE-70000-98-IF-B or

IE-7000-98-IF-C

Note

Interface Adapter

IE-70000-98N-IF

IE-70000-PC-IF-B or

IE-7000-PC-IF-C

Note

Interface Adapter

IE-78000-R-SV3

Interface Adapter

IE-784000-R-EM

IE-784046-NS-EM1

Note

IE-784046-R-EM1

Emulation Board

IE-78K4-R-EX2

Note

Emulation Probe

Conversion Board

EP-78230GC-R

Emulation Probe

EV-9200GC-80

Conversion Socket

(Refer to Figures

A-2 and A-3)

Note Under development

Remark

EV-9200GC-64 is sold in five units.

The IE-784000-R is an in-circuit emulator that can be used with the entire 78K/IV

series. It is used in combination with the optionally available IE-784000-R-EM, IE-

784046-NS-EM1, or IE-784046-R-EM1. Debugging is performed with a host

machine connected. The optionally available integrated debugger (ID78K4) and

device file are required, and in combination with these it is possible to perform

debugging at the C language or structured assembly language source program

level. More efficient debugging or program testing is possible by means of the C0

coverage function, etc. Connection to the host machine is performed by means of

Ethernet or a dedicated bus, and a optionally available interface adapter is required.

This adapter is required when using the PC-9800 Series computer (except notebook

type) as the IE-784000-R host machine.

Interface adapter and cable necessary for using when a PC-9800 series notebook

computer is used as the host machine of IE-784000-R.

This adapter is required when using the IBM PC/AT and its compatible computers as

the IE-784000-R host machine.

This is adapter and cable required when using an EWS computer as the IE-784000-

R host machine, and is used connected to the board in the IE-784000-R.

10Base-5 is supported as Ethernet. For the other methods, a commercially avail-

able conversion adapter is necessary.

Emulation board for use with the entire 78K/IV series.

This board emulates the operations of the peripheral hardware peculiar to a device.

It is common to the

PD784046 subseries.

This conversion board for 80-pin QFP is required when using the IE-784046-NS-

EM1 on the IE-784000-R.

This is not necessary when using the conventional model IE-784046-R-EM1.

This probe is used to connect the in-circuit emulator to the target system and is

designed for 80-pin plastic QFP (GC-3B9 type).

This conversion socket connects the EP-78230GC-R to the target system board

designed to mount a 80-pin plastic QFP (GC-3B9 type).

459

APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software (1/2)

SM78K4

This system simulator is used to perform debugging at C source level or assembler

System Simulator

level while simulating the operation of the target system on a host machine.

This simulator runs on Windows.

Use of the SM78K4 allows the execution of application logical testing and

performance testing on an independent basis from hardware development without

having to use an in-circuit emulator, thereby providing higher development efficiency

and software quality.

The SM78K4 should be used in combination with the optional device file (DF784046).

Part Number:

××××

SM78K4

Remark

××××

in the part number differs depending on the host machine and OS used.

××××

SM78K4

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Note

3.5-inch 2HD FD

AB13

IBM PC/AT and its compatibles

Windows (Japanese version)

Note

3.5-inch 2HC FD

BB13

Windows (English version)

Note

Note Not support WindowsNT

460

APPENDIX A DEVELOPMENT TOOLS

A.3.2 Software (2/2)

ID78K4-NS

Note

Integrated Debugger

(supporting in-circuit emulator

IE-78K4-NS)

ID78K4

Integrated Debugger

(supporting in-circuit emulator

IE-784000-R)

Note Under development

Remark

××××

in the part number differs depending on the host machine and OS used.

××××

ID78K4-NS

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Note

3.5-inch 2HD FD

AB13

IBM PC/AT and its compatibles

Windows (Japanese version)

Note

3.5-inch 2HC FD

BB13

Windows (English version)

Note

Note Not support WindowsNT

××××

ID78K4

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Note

3.5-inch 2HD FD

AB13

IBM PC/AT and its compatibles

Windows (Japanese version)

Note

3.5-inch 2HC FD

BB13

Windows (English version)

Note

3P16

HP9000 Series 700

HP-UX (Rel. 9.05)

DAT (DDS)

3K13

SPARCstation

SunOS (Rel. 4.1.4)

3.5-inch 2HC FD

3K15

1/4 inch CGMT

3R13

NEWS

(RISC)

NEWS-OS (Rel. 6.1)

3.5-inch 2HC FD

Note

Not support WindowsNT

This debugger is a control program to debug 78K/IV Series microcontrollers.

It adopts a graphical user interface, which is equivalent visually and operationally to

Windows or OSF/Motif

. It also has an enhanced debugging function for C language

programs, and thus trace results can be displayed on screen in C-language level by using

the windows integration function which links a trace result with its source program,

disassembled display, and memory display. In addition, by incorporating function

modules such as task debugger and system performance analyzer, the efficiency of

debugging programs, which run on real-time OSs can be improved.

It should be used in combination with the optional device file (DF784046).

Part Number:

××××

ID78K4-NS,

××××

ID78K4

461

APPENDIX A DEVELOPMENT TOOLS

A.4 Dimensions of Conversion Socket (EV-9200GC-80) and Recommended Board Mounting Pattern

Figure A-2. Dimensions of EV-9200GC-80 (reference)

No.1 pin index

EV-9200GC-80

EV-9200GC-80-G1E

ITEM

MILLIMETERS

INCHES

18.0

14.4

18.0

4-C 2.0

0.8

6.0

16.0

18.7

6.0

16.0

18.7

8.2

8.0

2.5

2.0

0.35

2.3

1.5

0.709

0.567

0.709

4-C 0.079

0.031

0.236

0.63

0.736

0.236

0.63

0.736

0.323

0.315

0.098

0.079

0.014

0.091

0.059

Based on EV-9200GC-80
(1) Package drawing (in mm)

462

APPENDIX A DEVELOPMENT TOOLS

Figure A-3. Recommended Board Mounting Pattern of EV-9200GC-80 (reference)

0.026

0.748=0.486

0.026

0.748=0.486

EV-9200GC-80-P1E

ITEM

MILLIMETERS

INCHES

19.7

15.0

19.7

6.0±0.05

0.35±0.02

2.36±0.03

2.3

1.57±0.03

0.776

0.591

0.776

0.236

0.014

0.093

0.091

0.062

0.65±0.02

19=12.35±0.05

0.65±0.02

19=12.35±0.05

+0.001

0.002

+0.003

0.002

+0.001

0.002

+0.003

0.002

+0.003

0.002

+0.003

0.002

+0.001

0.001

+0.001

0.002

+0.001

0.002

Based on EV-9200GC-80
(2) Pad drawing (in mm)

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (C10535E).

Caution

APPENDIX B EMBEDDED SOFTWARE

For efficient development and maintenance of the

PD784054, the following embedded products are available.

Real-Time OS (1/2)

RX78K/IV

RX 78K/IV is a real-time OS conforming to the

ITRON specifications.

Real-time OS

Tool (configurator) for generating nucleus of RX78K/0 and plural information tables

is supplied.

Used in combination with an optional assembler package (RA78K4) and device file

(DF784046).

The real-time OS is a DOS-based application. It should be used in the DOS Prompt

when using in Windows.

Part number:

××××

RX78K4

Caution

When purchasing the RX78K/IV, fill in the purchase application form in advance and sign the

User Agreement.

Remark

××××

and

in the part number differ depending on the host machine and OS used.

××××

RX78K4-

Product Outline

Maximum Number for Use in Mass Production

001

Evaluation object

Do not use for mass-produced product.

100K

Mass-production object

0.1 million units

001M

1 million units

010M

10 million units

S01

Source program

Source program for mass-produced object

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HD FD

AB13

IBM PC/AT and its compatibles

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HC FD

BB13

Windows (English version)

Notes 1, 2

3P16

HP9000 Series 700

HP-UX (Rel. 9.05)

DAT (DDS)

3K13

SPARCstation

SunOS (Rel. 4.1.4)

3.5-inch 2HC FD

3K15

1/4-inch CGMT

3R13

NEWS (RISC)

NEWS-OS (Rel. 6.1)

3.5-inch 2HC FD

Notes 1. Can also be operated in DOS environment.

2. Not support WindowsNT.

463

464

APPENDIX B EMBEDDED SOFTWARE

Real-Time OS (2/2)

MX78K4

MX78K/0 is an OS for

ITRON specification subsets. A nucleus for the MX78K4 is

also included as a companion product.

This manages tasks, events, and time. In the task management, determining the

task execution order and switching from task to the next task are performed.

The MX78K4 is a DOS-based application. It should be used in the DOS Prompt

when using in Windows.

Part number:

××××

MX78K4-

Remark

××××

and

in the part number differ depending on the host machine and OS used.

××××

MX78K4-

Product Outline

Maximum Number for Use in Mass Production

001

Evaluation object

Use in preproduction stages.

××

Mass-production object

Use in mass production stages.

S01

Source program

Only the users who purchased mass-production

objects are allowed to purchase this program.

××××

Host Machine

Supply Medium

AA13

PC-9800 Series

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HD FD

AB13

IBM PC/AT and its compatibles

Windows (Japanese version)

Notes 1, 2

3.5-inch 2HC FD

BB13

Windows (English version)

Notes 1, 2

3P16

HP9000 Series 700

HP-UX (Rel. 9.05)

DAT (DDS)

3K13

SPARCstation

SunOS (Rel. 4.1.4)

3.5-inch 2HC FD

3K15

1/4-inch CGMT

3R13

NEWS (RISC)

NEWS-OS (Rel. 6.1)

3.5-inch 2HC FD

Notes 1. Can also be operated in DOS environment.

2. Not support WindowsNT.

APPENDIX C REGISTER INDEX

[A]

ADCR0

: A/D Conversion Result Register 0 ..........................................................................................

238

ADCR0H

: A/D Conversion Result Register 0H .......................................................................................

239

ADCR1

: A/D Conversion Result Register 1 ..........................................................................................

238

ADCR1H

: A/D Conversion Result Register 1H .......................................................................................

239

ADCR2

: A/D Conversion Result Register 2 ..........................................................................................

238

ADCR2H

: A/D Conversion Result Register 2H .......................................................................................

239

ADCR3

: A/D Conversion Result Register 3 ..........................................................................................

238

ADCR3H

: A/D Conversion Result Register 3H .......................................................................................

239

ADCR4

: A/D Conversion Result Register 4 ..........................................................................................

238

ADCR4H

: A/D Conversion Result Register 4H .......................................................................................

239

ADCR5

: A/D Conversion Result Register 5 ..........................................................................................

238

ADCR5H

: A/D Conversion Result Register 5H .......................................................................................

239

ADCR6

: A/D Conversion Result Register 6 ..........................................................................................

238

ADCR6H

: A/D Conversion Result Register 6H .......................................................................................

239

ADCR7

: A/D Conversion Result Register 7 ..........................................................................................

238

ADCR7H

: A/D Conversion Result Register 7H .......................................................................................

239

ADIC

: Interrupt Control Register ........................................................................................................ 309 to 311

ADM

: A/D Converter Mode Register .................................................................................................

236

ASIM

: Asynchronous Serial Interface Mode Register .......................................................................

261

ASIM2

: Asynchronous Serial Interface Mode Register 2 ....................................................................

261

ASIS

: Asynchronous Serial Interface Status Register .....................................................................

263

ASIS2

: Asynchronous Serial Interface Status Register 2 ..................................................................

263

[B]

BRGC

: Baud Rate Generator Control Register ..................................................................................

283

BRGC2

: Baud Rate Generator Control Register 2 ...............................................................................

283

: Bus Width Specification Register ............................................................................................

388

[C]

CC00

: Capture/Compare Register 00 ................................................................................................

158

CC01

: Capture/Compare Register 01 ................................................................................................

158

CC02

: Capture/Compare Register 02 ................................................................................................

158

CC03

: Capture/Compare Register 03 ................................................................................................

158

CM10

: Compare Register 10 ..............................................................................................................

185

CM11

: Compare Register 11 ..............................................................................................................

185

CM40

: Compare Register 40 ..............................................................................................................

209

CM41

: Compare Register 41 ..............................................................................................................

209

CMIC10

: Interrupt Control Register ........................................................................................................

310

CMIC11

: Interrupt Control Register ........................................................................................................

310

CMIC40

: Interrupt Control Register ........................................................................................................

310

CMIC41

: Interrupt Control Register ........................................................................................................

310

CSIIC1

: Interrupt Control Register ........................................................................................................

310

CSIIC2

: Interrupt Control Register ........................................................................................................

311

CSIM1

: Clocked Serial Interface Mode Register 1 ..............................................................................

274

CSIM2

: Clocked Serial Interface Mode Register 2 ..............................................................................

274

465

466

APPENDIX C REGISTER INDEX

[I]

IEF1

: Interrupt Valid Edge Flag Register 1 ......................................................................................

294

IEF2

: Interrupt Valid Edge Flag Register 2 ......................................................................................

295

IMC

: Interrupt Mode Control Register ..............................................................................................

315

IMS

: Internal Memory Size Select Register ....................................................................................

414

INTM0

: External Interrupt Mode Register 0 .........................................................................................

292

INTM1

: External Interrupt Mode Register 1 .........................................................................................

293

ISPR

: In-Service Priority Register .....................................................................................................

314

[M]

MK0

: Interrupt Mask Register 0 ........................................................................................................

313

MK0H

: Interrupt Mask Register 0H .....................................................................................................

313

MK0L

: Interrupt Mask Register 0L ......................................................................................................

313

MK1

: Interrupt Mask Register 1 ........................................................................................................

313

MK1H

: Interrupt Mask Register 1H .....................................................................................................

313

MK1L

: Interrupt Mask Register 1L ......................................................................................................

313

: Memory Extension Mode Register .......................................................................................... 364, 371

[N]

NPC

: Noise Protection Control Register ..........................................................................................

296

[O]

OSTS

: Oscillation Stabilization Time Specification Register .............................................................

86, 397

OVIC0

: Interrupt Control Register ........................................................................................................

309

OVIC1

: Interrupt Control Register ........................................................................................................

309

OVIC4

: Interrupt Control Register ........................................................................................................

309

[P]

: Port 0 ........................................................................................................................................

: Port 1 ........................................................................................................................................

100

: Port 2 ........................................................................................................................................ 104, 105

: Port 3 ........................................................................................................................................ 111, 112

: Port 4 ........................................................................................................................................

118

: Port 5 ........................................................................................................................................

124

: Port 6 ........................................................................................................................................

130

: Port 7 ........................................................................................................................................

136

: Port 8 ........................................................................................................................................

137

: Port 9 ........................................................................................................................................

138

PIC0

: Interrupt Control Register ........................................................................................................

309

PIC1

: Interrupt Control Register ........................................................................................................

309

PIC2

: Interrupt Control Register ........................................................................................................

309

PIC3

: Interrupt Control Register ........................................................................................................

309

PIC4

: Interrupt Control Register ........................................................................................................

309

PIC5

: Interrupt Control Register ........................................................................................................

309

PIC6

: Interrupt Control Register ........................................................................................................

309

PM0

: Port 0 Mode Register ..............................................................................................................

PM1

: Port 1 Mode Register ..............................................................................................................

101

PM2

: Port 2 Mode Register ..............................................................................................................

106

467

APPENDIX C REGISTER INDEX

PM3

: Port 3 Mode Register ..............................................................................................................

113

PM4

: Port 4 Mode Register ..............................................................................................................

119

PM5

: Port 5 Mode Register ..............................................................................................................

125

PM6

: Port 6 Mode Register ..............................................................................................................

131

PM9

: Port 9 Mode Register ..............................................................................................................

141

PMC2

: Port 2 Mode Control Register .................................................................................................

106

PMC3

: Port 3 Mode Control Register .................................................................................................

114

PMC9

: Port 9 Mode Control Register .................................................................................................

141

PRDC

: Port Read Control Register .....................................................................................................

146

PRM

: Prescaler Mode Register ......................................................................................................... 161, 188

PRM4

: Prescaler Mode Register 4 ......................................................................................................

211

PUOH

: Pull-Up Resistor Option Register H ........................................................................................

144

PUOL

: Pull-Up Resistor Option Register L .............................................................................. 98, 122, 128, 134

PWC1

: Programmable Wait Control Register 1 ..................................................................................

373

PWC2

: Programmable Wait Control Register 2 ..................................................................................

375

[R]

RXB

: Serial Receive Buffer: UART0 ...............................................................................................

259

RXB2

: Serial Receive Buffer: UART2 ...............................................................................................

259

[S]

SERIC

: Interrupt Control Register ........................................................................................................

310

SERIC2

: Interrupt Control Register ........................................................................................................

310

SIO1

: Serial Shift Register: IOE1 .....................................................................................................

273

SIO2

: Serial Shift Register: IOE2 .....................................................................................................

273

SRIC

: Interrupt Control Register ........................................................................................................

310

SRIC2

: Interrupt Control Register ........................................................................................................

311

STBC

: Standby Control Register ........................................................................................................

85, 394

STIC

: Interrupt Control Register ........................................................................................................

310

STIC2

: Interrupt Control Register ........................................................................................................

311

[T]

TM0

: Timer Register 0 ......................................................................................................................

158

TM1

: Timer Register 1 ......................................................................................................................

185

TM4

: Timer Register 4 ......................................................................................................................

209

TMC

: Timer Mode Control Register .................................................................................................. 160, 187

TMC4

: Timer Mode Control Register 4 ...............................................................................................

210

TOC0

: Timer Output Control Register 0 .............................................................................................

160

TOC1

: Timer Output Control Register 1 .............................................................................................

187

TUM0

: Timer Unit Mode Register 0 ....................................................................................................

186

TXS

: Serial Transmit Shift Register: UART0 ..................................................................................

259

TXS2

: Serial Transmit Shift Register: UART2 ..................................................................................

259

[W]

WDM

: Watchdog Timer Mode Register ............................................................................................. 226, 316

[MEMO]

468

APPENDIX D REVISION HISTORY

The revision history is described below. The "Applied to" column indicates the chapters in each edition.

Edition

Major Revisions from Previous Edition

Applied to

2nd edition

Change of

PD784054 from "under development" to "development completed".

Addition of the following products to the relevant products:

PD784054(A), 784054(A1), 784054(A2)

Change of 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM.

Change of the minimum value of the supply voltage (V

) from 4.0 V to 4.5 V.

Addition of 1.3 Quality Grades.

Addition of 1.9 Differences between

PD784054 and

PD784054(A).

Addition of 1.10 Differences between

PD784054(A), 784054(A1), and 784054(A2).

Addition of the functional description of the CLKOUT pin.

Addition of description in (2) Capture/compare registers (CC00 through CC03).

Addition of caution when the timer output is enabled while the active level is changed.

Addition of caution when the active level of the timer output is changed.

Addition of caution when the timer output is enabled while the active level is changed.

Addition of caution when the active level of the timer output is changed.

Change of the description of <5> in (2) of 10.4.1 General cautions on use of

watchdog timer from "If the STOP mode or IDLE mode is entered as the result of

an inadvertent program loop" to "If the STOP mode, HALT mode, or IDLE mode is

entered as the result of an inadvertent program loop".

Addition of caution and calculating method of the wait time if the reception completion

interrupt is disabled when a reception error occurs.

Change of instructions in 14.9 When Interrupt Request and Macro Service Are

Temporarily Held Pending.

Change of description from "The watchdog timer must not be used to release the

standby mode (STOP or IDLE mode)" to "The watchdog timer must not be used to

release the standby mode (STOP, HALT, or IDLE mode)".

Deletion of watchdog timer of "Non-maskable interrupt request (NMI pin input/

watchdog timer)".

Addition of Caution concerning the malfunction that causes a wait for the oscillation

stabilization time when the IDLE mode is released.

Addition of note on output of CLKOUT pin.

General revision for supporting IE-78K4-NS.

Change of target host machines.

Change of versions of OSs to be supported.

Throughout

CHAPTER 1 GENERAL

CHAPTER 2 PIN FUNCTIONS

CHAPTER 7 TIMER 0

CHAPTER 8 TIMER 1

CHAPTER 10 WATCHDOG

TIMER FUNCTION

CHAPTER 12 ASYNCHRO-

NOUS SERIAL INTERFACE/3-

WIRE SERIAL I/O

CHAPTER 14 INTERRUPT

FUNCTIONS

CHAPTER 16 STANDBY

FUNCTION

CHAPTER 20 CAUTIONS ON

USING DEVELOPMENT

TOOLS

APPENDIX A DEVELOPMENT

TOOLS

APPENDIX B EMBEDDED

SOFTWARE

469

[MEMO]

470

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