1999, 2001

DATA SHEET

2001

MOS INTEGRATED CIRCUITS

16-BIT SINGLE-CHIP MICROCONTROLLER

PD78F4938A

Document No. U14118EJ1V0DS00
Date Published March 2001 N CP(K)
Printed in Japan

DESCRIPTION

The

µPD78F4938A is a product in the µPD784938A Subseries in the 78K/IV Series.

The

µPD78F4938A has flash memory in place of the internal ROM of the µPD784938A. The flash memory

incorporated enables program writing or erasing with the microcontroller mounted on the target board.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

µPD784938A Subseries User's Manual Hardware: U13570E
78K/IV Series User's Manual Instructions:

U10905E

FEATURES

Pin-compatible with mask ROM version (except V

pin)

Flash memory: 256 KB

Internal RAM: 10496 bytes

Serial interface:

4 channels

· UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)

· CSI (3-wire serial I/O):

2 channels

On-chip IEBus

controller

Supply voltage: V

= 4.0 to 5.5 V (@12.58 MHz operation)

= 3.0 to 5.5 V (@6.29 MHz operation)

APPLICATION

Car audio, etc.

ORDERING INFORMATION

Part Number

Package

Internal ROM

Internal RAM

µPD78F4938AGF-3BA

100-pin plastic QFP (14

× 20)

256 KB

10496 bytes

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

µPD78F4938A

Data Sheet U14118EJ1V0DS

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced
A/D converter,
16-bit timer, and
power management

Enhanced internal memory capacity
Pin-compatible with the PD784026

Supports I

C bus

Supports multimaster I

C bus

80-pin, ROM correction added

Supports multimaster I

C bus

Enhanced internal memory
capacity, ROM correction added

100-pin, enhanced I/O and
internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

Supports multimaster I

C bus

Enhanced functions
of the PD784915

Standard models

ASSP models

Supports multimaster I

C bus

: Products in mass-production

: Products under development

PD784976A

On-chip VFD controller/driver

PD784938A

Enhanced functions of the
PD784908, enhanced
internal memory capacity,
ROM correction added.

PD784967

Enhanced functions of the
PD784938A, enhanced I/O
and internal memory capacity.
Enhanced peripheral functions

Remark

Although VFD (Vacuum Florescent Display is generally used, in some documents, the display is described

as FIP

(Florescent Inidicator Panel). VFD and FIP are functionally equivalent.

Data Sheet U14118EJ1V0DS

µPD78F4938A

OVERVIEW OF FUNCTIONS

(1/2)

Part Number

µPD78F4938A

Item

Number of basic instructions (mnemonics) 113

General-purpose registers

8 bits

× 32 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory map)

Minimum instruction execution time

320 ns/636 ns/1.27

µs/2.54 µs (@6.29 MHz operation)

160 ns/320 ns/636 ns/1.27

µs (@12.58 MHz operation)

Internal memory

ROM

256 KB

RAM

10496 bytes

Memory space

1 MB with program and data spaces combined

I/O port

Total

80 pins

Input

8 pins

I/O

72 pins

Pins with

LED direct drive output

24 pins

ancillary

Transistor direct drive

8 pins

function

Note

N-ch open drain drive

4 pins

Real-time output port

4 bits

× 2, or 8 bits × 1

IEBus controller

Internal (simple version)

Timer/counter

Timer/event counter 0:

Timer counter

× 1

Pulse output possible

(16 bits)

Capture register

× 1

· Toggle output

Compare register

× 2

· PWM/PPG output

· One-shot pulse output

Timer/event counter 1:

Timer counter

× 1

Real-time output port

(16 bits)

Capture register

× 1

Capture/compare register

× 1

Compare register

× 1

Timer/event counter 2:

Timer counter

× 1

Pulse output possible

(16 bits)

Capture register

× 1

· Toggle output

Capture/compare register

× 1

· PWM/PPG output

Compare register

× 1

Timer 3 (16 bits):

Timer counter

× 1

Compare register

× 1

Watch timer

Generates interrupt request at 0.5-second intervals (On-chip watch clock oscillator)

Main clock (12.58 MHz) or watch clock (32.7 kHz) selectable as input clock

Clock output

Selectable from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16 (also usable as 1-bit output port)

PWM output

12-bit resolution

× 2 channels

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)

CSI (3-wire serial I/O):

2 channels

A/D converter

8-bit resolution

× 8 channels

Watchdog timer

1 channel

ROM correction function

Internal (4 points of correction addresses can be set.)

External expansion function

Provided (up to 1 MB)

Note

Pins with ancillary functions are included in the I/O pins.

Data Sheet U14118EJ1V0DS

µPD78F4938A

CONTENTS

DIFFERENCES AMONG PRODUCTS IN

µPD784938A SUBSERIES ...................................

PIN CONFIGURATION (TOP VIEW) ...........................................................................................

BLOCK DIAGRAM .........................................................................................................................

PIN FUNCTIONS ............................................................................................................................ 10

4.1

Port Pins ................................................................................................................................. 10

4.2

Non-Port Pins ........................................................................................................................ 12

4.3

Pin I/O Circuits and Recommended Connection of Unused Pins .................................

INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ..................................................

PROGRAMMING FLASH MEMORY ............................................................................................ 19

6.1

Selecting Communication Mode .........................................................................................

6.2

Flash Memory Programming Functions ............................................................................

6.3

Connecting Flashpro III ........................................................................................................ 21

ELECTRICAL SPECIFICATIONS .................................................................................................. 22

PACKAGE DRAWING .................................................................................................................... 42

RECOMMENDED SOLDERING CONDITIONS ...........................................................................

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 44

APPENDIX B. RELATED DOCUMENTS ........................................................................................... 47

µPD78F4938A

Data Sheet U14118EJ1V0DS

1. DIFFERENCES AMONG PRODUCTS IN

µPD784938A SUBSERIES

The only difference between the

µPD784935A, 784936A, 784937A, and 784938A is the internal memory capacity.

The

µPD78F4938A has a 256 KB flash memory in the place of the mask ROM of the above products. Table 1-

1 shows the differences between these products.

Table 1-1. Differences Among Products in

µPD784938A Subseries

Part Number

µPD784935A

µPD784936A

µPD784937A

µPD784938A

µPD78F4938A

Item

Internal ROM

96 KB

128 KB

192 KB

256 KB

Mask ROM

Flash memory

Internal RAM

5120 bytes

6656 bytes

8192 bytes

10496 bytes

Regulator

Provided

None

Electrical specifications

Refer to the data sheet of each product.

Internal memory size

None

Provided

switching register

Note

IC pin

Provided

None

Provided

Note

The internal flash memory capacity and internal RAM capacity can be changed by using the internal memory

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then

mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the

commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U14118EJ1V0DS

µPD78F4938A

2. PIN CONFIGURATION (TOP VIEW)

100-pin plastic QFP (14

× 20)

µPD78F4938AGF-3BA

P36/T02

P37/T03

P100

P101

P102

P103

P104

P105/SCK3

P106/SI3

P107/SO3

RESET

XT2

XT1

REGOFF

REGC

P00

P01

P02

P03

P04

P05

P06

P07

P67/REFRQ/HLDAK

P66/WAIT/HLDRQ

P65/WR

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

PWM1

PWM0

P17

P16

P15

P14/TxD2/SO2

P13/RxD2/SI2

P12/ASCK2/SCK2

P11

P10

ASTB/CLKOUT

P90

P91

P92

P93

P94

P95

P96

P97

P40/AD0

P41/AD1

P42/AD2

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

P35/TO1

P34/TO0

P33/SO0

P32/SCK0

P31/TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4/ASCK/SCK1

P24/INTP3

P23/INTP2/CI

P22/INTP1

P21/INTP0

P20/NMI

REF1

P77/ANI7

P64/RD

P63/A19

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

Cautions 1. In normal operation mode, connect V

pin directly to the V

pin, or pull it down.

In a system where the internal flash memory is rewritten while mounted on board, pull the V

pin down.
When pulling down, connection via a 470

or higher and 10 k

or lower resistor is recommended.

2. Connect the AV

pin directly to V

3. Connect the AV

pin directly to V

µPD78F4938A

Data Sheet U14118EJ1V0DS

A8 to A19:

Address bus

AD0 to AD7:

Address/data bus

ANI0 to ANI7:

Analog input

ASCK, ASCK2:

Asynchronous serial clock

ASTB:

Address strobe

Analog power supply

REF1

Reference voltage

Analog ground

CI:

Clock input

CLKOUT:

Clock output

HLDAK:

Hold acknowledge

HLDRQ:

Hold request

INTP0 to INTP5: Interrupt from peripherals

NMI:

Non-maskable interrupt

P00 to P07:

Port 0

P10 to P17:

Port 1

P20 to P27:

Port 2

P30 to P37:

Port 3

P40 to P47:

Port 4

P50 to P57:

Port 5

P60 to P67:

Port 6

P70 to P77:

Port 7

P90 to P97:

Port 9

P100 to P107:

Port 10

PWM0, PWM1:

Pulse width modulation output

RD:

Read strobe

REFRQ:

Refresh request

REGC:

Regulator capacitance

REGOFF:

Regulator off

RESET:

Reset

RX:

IEBus receive data

RxD, RxD2:

Receive data

SCK0 to SCK3: Serial clock

SI0 to SI3:

Serial input

SO0 to SO3:

Serial output

TO0 to TO3:

Timer output

TX:

IEBus transmit data

TxD, TxD2:

Transmit data

Power supply

Programming power supply

Ground

WAIT:

Wait

WR:

Write strobe

X1, X2:

Crystal (main system clock)

XT1, XT2:

Crystal (watch)

Data Sheet U14118EJ1V0DS

µPD78F4938A

3. BLOCK DIAGRAM

Programmable

interrupt controller

Timer/counter 0

(16 bits)

Timer/counter 1

(16 bits)

Timer/counter 2

(16 bits)

Timer 3

(16 bits)

Real-time

output port

PWM

A/D converter

78K/IV

CPU core

Flash

memory

RAM

Watchdog timer

UART/IOE 2

Baud-rate

generator

UART/IOE 1

Baud-rate

generator

Clocked serial

interface

Clock output

Bus I/F

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

NMI

INTP0 to INTP5

INTP3

TO0
TO1

INTP0

INTP1

INTP2/CI

TO2
TO3

P00 to P03

P04 to P07

PWM0

PWM1

IEBus controller

ANI0 to ANI7

REF1

INTP5

RxD/SI1
TxD/SO1

ASCK/SCK1

RxD2/SI2
TxD2/SO2

ASCK2/SCK2

SCK0

SO0

SI0

Clocked serial

interface 3

SCK3

SO3

SI3

ASTB/CLKOUT

AD0 to AD7

A8 to A15

A16 to A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK

P00 to P07

P10 to P17

P20 to P27

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

Port 9

Port 10

P90 to P97

P100 to P107

Watch timer

XT1

XT2

RESET

X1
X2

REGC

REGOFF

System control

(regulator)

µPD78F4938A

Data Sheet U14118EJ1V0DS

4. PIN FUNCTIONS

4.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00 to P07

I/O

P10

I/O

P11

P12

ASCK2/SCK2

P13

RxD2/SI2

P14

TxD2/SO2

P15 to 17

P20

Input

NMI

P21

INTP0

P22

INTP1

P23

INTP2/CI

P24

INTP3

P25

INTP4/ASCK/SCK1

P26

INTP5

P27

SI0

P30

I/O

RxD/SI1

P31

TxD/SO1

P32

SCK0

P33

SO0

P34 to P37

TO0 to TO3

P40 to P47

I/O

AD0 to AD7

P50 to P57

I/O

A8 to A15

P60 to P63

I/O

A16 to A19

P64

P65

P66

WAIT/HLDRQ

P67

REFRQ/HLDAK

Port 0 (P0):

· 8-bit I/O port.

· Can be used as real-time output port (4 bits

× 2).

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for

pins in input mode.

· Can drive transistor.

Port 1 (P1):

· 8-bit I/O port.

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for pins

in input mode.

· Can drive LED.

Port 2 (P2):

· 8-bit input port.

· P20 cannot be used as general-purpose port pin (non-maskable interrupt).

However, input level can be checked by interrupt routine.

· An on-chip pull-up resistor can be specified for P22 to P27 by means of

software in 6-bit units.

· P25/INTP4/ASCK/SCK1 pin operates as SCK1 I/O pin if so specified by

CSIM1.

Port 3 (P3):

· 8-bit I/O port.

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for pins

in input mode.

· P32 and P33 can be specified for N-ch open-drain connection.

Port 5 (P5):

· 8-bit I/O port.

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for pins

in input mode.

· Can drive LED.

Port 4 (P4):

· 8-bit I/O port.

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for pins in

input mode.

· Can drive LED.

Port 6 (P6):

· 8-bit I/O port.

· Input/output can be specified in 1-bit units.

· An on-chip pull-up resistor can be specified by means of software for pins

in input mode.

µPD78F4938A

Data Sheet U14118EJ1V0DS

4.2 Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TO0 to TO3

Output

P34 to P37

Timer output

Input

P23/INTP2

Count clock input to timer/counter 2

RxD

Input

P30/SI1

Serial data input (UART0)

RxD2

P13/SI2

Serial data input (UART2)

TxD

Output

P31/SO1

Serial data output (UART0)

TxD2

P14/SO2

Serial data output (UART2)

ASCK

Input

P25/INTP4/SCK1

Baud rate clock input (UART0)

ASCK2

P12/SCK2

Baud rate clock input (UART2)

SI0

Input

P27

Serial data input (3-wire serial I/O0)

SI1

P30/RxD

Serial data input (3-wire serial I/O1)

SI2

P13/RxD2

Serial data input (3-wire serial I/O2)

SI3

P106

Serial data input (3-wire serial I/O3)

SO0

Output

P33

Serial data output (3-wire serial I/O0)

SO1

P31/TxD

Serial data output (3-wire serial I/O1)

SO2

P14/TxD2

Serial data output (3-wire serial I/O2)

SO3

P107

Serial data output (3-wire serial I/O3)

SCK0

I/O

P32

Serial clock input/output (3-wire serial I/O0)

SCK1

P25/INTP4/ASCK

Serial clock input/output (3-wire serial I/O1)

SCK2

P12/ASCK2

Serial clock input/output (3-wire serial I/O2)

SCK3

P105

Serial clock input/output (3-wire serial I/O3)

NMI

Input

P20

External interrupt requests

INTP0

P21

· Count clock input to timer/counter 1

· Capture trigger signal of CR11 or CR12

INTP1

P22

· Count clock input to timer/counter 2

· Capture trigger signal of CR22

INTP2

P23/CI

· Count clock input to timer/counter 2

· Capture trigger signal of CR21

INTP3

P24

· Count clock input to timer/counter 0

· Capture trigger signal of CR02

INTP4

P25/ASCK/SCK1

INTP5

P26

Conversion start trigger input of A/D converter

AD0 to AD7

I/O

P40 to P47

Time-division address/data bus (external memory connection)

A8 to A15

Output

P50 to P57

Higher address bus (external memory connection)

A16 to A19

Output

P60 to P63

Higher address for address extension (external memory connection)

Output

P64

Read strobe to external memory

Output

P65

Write strobe to external memory

WAIT

Input

P66/HLDRQ

Wait insertion

REFRQ

Output

P67/HLDAK

Refresh pulse output to external pseudo-static memory

HLDRQ

Input

P66/WAIT

Bus hold request input

HLDAK

Output

P67/REFRQ

Bus hold acknowledge output

ASTB

Output

CLKOUT

Latch timing output of time-division address (A0 to A7) (when external

memory is accessed)

Data Sheet U14118EJ1V0DS

µPD78F4938A

4.2 Non-Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

CLKOUT

Output

ASTB

Clock output

PWM0

Output

PWM output 0

PWM1

Output

PWM output 1

Input

Data input (IEBus)

Output

Data output (IEBus)

REGC

Connecting capacitor for regulation output stabilization/power supply when

regulator is stopped

REGOFF

Regulator operation specification signal

RESET

Input

Chip reset

Input

Connecting crystal resonator for system clock oscillation (clock can be also

input to X1.)

XT1

Input

Watch clock connection

XT2

ANI0 to ANI7

Input

P70 to P77

Analog voltage input for A/D converter

REF1

Application of reference voltage for A/D converter

Positive power supply for A/D converter

GND for A/D converter

Positive power supply

GND

Input

Sets flash memory programming mode.

For high voltage application when program is written or verified. In normal

operation mode, connect V

pin directly to the V

pin, or pull it down. In a

system where the internal flash memory is rewritten while mounted on

board, pull the V

pin down. When pulling down, connection via a 470

or higher and 10 k

or lower resistor is recommended.

µPD78F4938A

Data Sheet U14118EJ1V0DS

4.3 Pin I/O Circuits and Recommended Connection of Unused Pins

The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 4-1.

For the I/O circuit configuration of each type, refer to Figure 4-1.

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

P00 to P07

5-A

I/O

Input: Connect to V

P10, P11

Output: Leave open.

P12/ASCK2/SCK2

8-A

P13/RxD2/SI2

5-A

P14/TxD2/SO2

P15 to P17

P20/NMI

Input

Connect to V

or V

P21/INTP0

P22/INTP1

2-A

Connect to V

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1

8-A

I/O

Input: Connect to V

Output: Leave open.

P26/INTP5

2-A

Input

Connect to V

P27/SI0

P30/RxD/SI1

5-A

I/O

Input: Connect to V

P31/TxD/SO1

Output: Leave open.

P32/SCK0

10-A

P33/SO0

P34/TO0 to P37/TO3

5-A

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0 to P77/ANI7

I/O

Input: Connect to V

or V

P90 to P97

5-A

Output: Leave open.

P100 to P104

P105/SCK3

10-A

P106/SI3

8-A

P107/SO3

10-A

ASTB/CLKOUT

Output

Leave open.

RESET

Input

Connect directly to V

XT2

Leave open.

XT1

Input

Connect directly to V

Data Sheet U14118EJ1V0DS

µPD78F4938A

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

REGOFF

Connect directly to V

REGC

Connect to V

PWM0, PWM1

Output

Leave open.

Input

Connect to V

or V

Output

Leave open.

REF1

Connect to V

Caution Connect an I/O pin to V

via a resistor of several 10 k

if the I/O mode of the pin is unstable

(especially if the voltage on the reset pin is higher than the low-level input voltage on power application

or if the mode is changed between input and output by software).

Remark

The circuit type numbers are common for the 78K Series and are not always sequential for one product

(some circuits are not provided).

µPD78F4938A

Data Sheet U14118EJ1V0DS

Figure 4-1. Pin I/O Circuits (1/2)

Type 2

Schmitt-triggered input with hysteresis characteristics

Type 1

Type 4

Push-pull output that can go into a high-impedance state

(both P-ch and N-ch are off).

Type 5-A

Data

Output

disable

OUT

Data

Output

disable

IN/OUT

Input

enable

Pull-up

enable

Type 2-A

Schmitt-triggered input with hysteresis characteristics

Pull-up
enable

Type 8-A

Type 10-A

Data

Output

disable

IN/OUT

Pull-up

enable

Data

Output disable

IN/OUT

Pull-up

enable

Open-drain

Type 3

P-ch

OUT

Data

N-ch

µPD78F4938A

Data Sheet U14118EJ1V0DS

5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)

IMS is a register to prevent a certain part of the internal memory from being used by software. By setting the IMS,

it is possible to establish a memory map that is the same as that of mask ROM version with a different internal memory

(ROM, RAM) capacity.

IMS is set with an 8-bit memory manipulation instruction.

RESET input sets IMS to FFH.

Figure 5-1. Internal Memory Size Switching Register (IMS) Format

IMS

ROM1

ROM0

RAM1

RAM0

Address 0FFFCH

After reset FFH

Symbol

ROM1

ROM0

256 KB

96 KB

128 KB

192 KB

Internal ROM Capacity Selection

RAM1

RAM0

10496 bytes

5120 bytes

8192 bytes

6656 bytes

Internal RAM Capacity Selection

Caution IMS is not available for mask ROM versions (

µPD784935A, 784936A, 784937A, and 784938A).

The IMS settings to create the same memory map as mask ROM versions are shown in Table 5-1.

Table 5-1. Internal Memory Size Switching Register (IMS) Settings

Relevant Mask ROM Version

IMS Setting

µPD784935A

DDH

µPD784936A

EEH

µPD784937A

FFH

µPD784938A

CCH

Note

Shifting to the flash memory programming mode sets all pins not used for flash memory programming to

the same state as immediately after reset. Therefore, if the external devices do not acknowledge the port

state immediately after reset, handling such as connecting to V

via a resistor or connecting to V

via

a resistor is required.

Data Sheet U14118EJ1V0DS

µPD78F4938A

6. PROGRAMMING FLASH MEMORY

Flash memory can be written while mounted on the target system (on-board writing). Connect the dedicated flash

programmer (Flashpro III (part No.: FL-PR3, PG-FP3)) to the host machine and target system for programming.

Moreover, writing to flash memory can also be performed using a flash memory writing adapter connected to Flashpro

III.

Remark

FL-PR3 is a product of Naito Densei Machida Mfg. Co., Ltd.

6.1 Selecting Communication Mode

The Flashpro III is used to write data into a flash memory by serial communications. Select the communication

mode for writing from Table 6-1. Figure 6-1 shows the format used to select the communication mode. Each

communication mode is selected with the number of V

pulses shown in Table 6-1.

Table 6-1. Communication Mode

Communication Mode Number of Channels

Pins Used

Number of V

Pulses

3-wire serial I/O 3

SCK3/P105

SI3/P106

SO3/P107

SCK0/P32

SI0/P27

SO0/P33

SCK3/P105

SI3/P106

SO3/P107

P104 (for handshake)

UART 1

RxD/P30

TxD/P31

Caution Always select the communication mode using the number of V

pulses shown in Table 6-1.

Figure 6-1. Communication Mode Selection Format

10 V

RESET

pulses

Flash memory write mode

µPD78F4938A

Data Sheet U14118EJ1V0DS

6.2 Flash Memory Programming Functions

By transmitting and receiving various commands and data by the selected communication mode, operations such

as writing to the flash memory are performed. Table 6-2 shows the major functions.

Table 6-2. Flash Memory Programming Functions

Function

Description

Area erase

Erase the contents of the specified memory area where one memory block is 16 KB.

Area blank check

Checks the erase state of the specified area.

Data write

Writes to the flash memory based on the start write address and the number of data written (number

of bytes).

Area verify

Compares the data input with the contents of the specified memory area.

Verification for the flash memory entails supplying the data to be verified from an external source via a serial

interface, and then outputting the existence of unmatched data to the external source after referencing the areas or

all of the data. Consequently, the flash memory is not equipped with a read function, and it is not possible for third

parties to read the contents of the flash memory with the use of the verification function.

Data Sheet U14118EJ1V0DS

µPD78F4938A

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

0.3 to +6.5

0.3 to V

+ 0.3

0.3 to V

+ 0.3

REF1

A/D converter reference voltage input

0.3 to V

+ 0.3

Input voltage

0.3 to +10.5

Analog input voltage

IAN

Analog input voltage

0.3 to AV

REF1

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, low

Per pin

Total for all pins of ports 0, 3, 6, 10 and

P54 to P57

Total for all pins of ports 1, 4, 7, 9,

P50 to P53, PWM0, PWM1, and TX pins

Output current, high

Per pin

Total for all pins of ports 0, 3, 6, 10,and

P54 to P57

Total for all pins of ports 1, 4, 7, 9,

P50 to P53, PWM0, PWM1, and TX pins

Operating ambient temperature

40 to +85

°C

Storage temperature

stg

40 to +150

°C

Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any

parameter. That is, the absolute maximum ratings are rated values at which the product is on the

verge of suffering physical damage, and therefore the product must be used under conditions that

ensure that the absolute maximum ratings are not exceeded.

Remark

Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.

Data Sheet U14118EJ1V0DS

µPD78F4938A

Operating Conditions

Clock frequency

Clock Frequency

Supply Voltage

4 MHz

12.58 MHz

4.0

5.5 V

4 MHz

6.29 MHz

3.0

5.5 V

Operating ambient temperature (T

): 40 to +85

°C

Power supply voltage and clock cycle time: Refer to Figure 7-1

Selection of internal regulator operation (REGOFF pin: low-level input)

Figure 7-1. Power Supply Voltage and Clock Cycle Time

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input capacitance

f = 1 MHz

Output capacitance

OUT

Unmeasured pins returned to 0 V.

I/O capacitance

Guaranteed operation range

10000

2000

1000

500

200

159

100

Power supply voltage [V]

Clock cycle time t

CYK

[ns]

1/8 of f

= 2 MHz

= 6.29 MHz undivided

= 12.58 MHz undivided

Data Sheet U14118EJ1V0DS

µPD78F4938A

Main Oscillator Characteristics (T

= 40 to +85

C, V

= 3.0 to 5.5 V, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

Oscillator frequency

Ceramic resonator or

4.0

5.5 V

4.0

12.58

MHz

recommended resonator

3.0

5.5 V

4.0

6.29

MHz

Caution When using the main clock oscillator, wire as follows to avoid an adverse effect from wiring capacitance.

· Keep the wiring length as short as possible.

· Do not cross the wiring with the other signal lines.

· Do not route the wiring near a signal line through which a high fluctuating current flows.

· Always make the ground point of the oscillator capacitor the same potential as V

· Do not ground the capacitor to a ground pattern through which a high current flows.

· Do not fetch signals from the oscillator.

Remarks 1. Connect a 12.582912 MHz or 6.291456 MHz oscillator to operate the internal clock timer with the main

clock.

2. For the resonator selection and oscillator constant, customers are requested to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

Clock Oscillator Characteristics (T

= 40 to +85

C, V

= 3.0 to 5.5 V, V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Oscillator frequency

Ceramic resonator or crystal resonator

32.768

kHz

Oscillation stabilization time

sxt

4.5

5.5 V

1.2

Oscillation hold voltage

DDXT

3.0

5.5

Watch timer operating voltage

DDW

3.0

5.5

Data Sheet U14118EJ1V0DS

µPD78F4938A

DC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, low

Note

IL1

P10, P11, P13 to P17, P30, P31,

0.3

0.3V

P34 to P37, P70 to P77, P90 to P97,

P100 to P104, X1, X2, XT1, XT2

IL2

P12, P20 to P27, P32, P33, P105 to P107

0.3

0.2V

RESET

IL3

P00 to P07, P40 to P47, 4.5

5.5 V

0.3

0.8

IL4

P50 to P57, P60 to P67

0.3

0.2V

Input voltage, high

IH1

P10, P11, P13 to P17, P30, P31,

0.7V

+0.3

P34 to P37, P70 to P77, P90 to P97,

P100 to P104, X1, X2, XT1, XT2

IH2

P12, P20 to P27, P32, P33, P105 to P107

0.8V

+0.3

RESET

IH3

P00 to P07, P40 to P47, 4.5

5.5 V

2.2

+0.3

IH4

P50 to P57, P60 to P67

0.7V

0.3V

Output voltage, low

OL1

= 20

µA

0.1

= 100

µA

0.2

= 2 mA

0.4

OL2

= 8 mA, P10 to P17,

4.5

5.5 V

1.0

P40 to P47, P50 to P57

Output voltage, high

OH1

= 20

µA

0.1

= 100

µA

0.2

= 2 mA

1.0

OH2

= 5 mA,

4.5 V

5.5 V V

2.4

P10 to P17, P40 to P47,

P50 to P57

Input leakage current, low

LIL1

= 0 V

For pins other than

µA

X1, X2, XT1, and XT2

LIL2

X1, X2, XT1, XT2

µA

Input leakage current, high

LIH1

= V

For pins other than

µA

X1, X2, XT1, and XT2

LIH2

X1, X2, XT1, XT2

µA

Output leakage current, low

LOL1

OUT

= 0 V

µA

Output leakage current, high

LOH1

OUT

= V

µA

Note

These values are valid when the pull-up resistor is off.

Data Sheet U14118EJ1V0DS

µPD78F4938A

DC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Power supply current

DD1

Operating

= 12.58 MHz,

mode

4.0 V

5.5 V

= 6.29 MHz,

3.0 V

5.5 V

DD2

HALT mode

= 12.58 MHz, when

peripheral clock stops

Note

4.0 V

5.5 V

= 6.29 MHz, when

1.8

3.6

peripheral clock stops

Note

3.0 V

5.5 V

DD3

IDLE mode

= 12.58 MHz,

4.0

5.5 V

= 6.29 MHz,

3.0 V

5.5 V

Data hold voltage

DDDR

STOP mode

2.5

5.5

Data hold current

DDDR

STOP mode

= 2.5 V, subsystem

µA

clock stops

= 5.5 V, subsystem

100

µA

clock stops

Pull-up resistor

= 0 V

Note

When the main system clock: f

CLK

= f

/8 is selected (set by the standby control register (STBC)) and the watch

timer is operating.

Remark

These values are valid when the internal regulator is on (REGOFF pin = low-level input).

Data Sheet U14118EJ1V0DS

PD78F4938A

AC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Cycle time

CYK

4.0

5.5 V

= 3.0 V

159

Address setup time

SAST

= 5.0 V

(0.5+a) T11

(to ASTB

)

= 3.0 V

(0.5+a) T15

Address hold time

HSTLA

= 5.0 V

0.5T19

(from ASTB

)

= 3.0 V

0.5T24

ASTB high-level width

WSTH

= 5.0 V

(0.5+a) T17

= 3.0 V

(0.5+a) T40

Address hold time (from RD

)

HRA

= 5.0 V

0.5T14

= 3.0 V

0.5T14

Delay time from address to

DAR

= 5.0 V

(1+a) T5

= 3.0 V

(1+a) T10

Address float time (from RD

)

FAR

Data input time from address

DAID

= 5.0 V

(2.5+a+n) T37

= 3.0 V

(2.5+a+n) T52

Data input time from ASTB

DSTID

= 5.0 V

(2+n) T35

= 3.0 V

(2+n) T50

Data input time from RD

DRID

= 5.0 V

(1.5+n) T40

= 3.0 V

(1.5+n) T50

Delay time from ASTB

DSTR

= 5.0 V

0.5T9

= 3.0 V

0.5T9

Data hold time (from RD

)

HRID

Address active time from RD

DRA

= 5.0 V

0.5T2

= 3.0 V

0.5T12

Delay time from RD

DRST

= 5.0 V

0.5T9

ASTB

= 3.0 V

0.5T9

RD low-level width

WRL

= 5.0 V

(1.5+n) T25

= 3.0 V

(1.5+n) T30

Remarks 1. T: t

CYK

= 1/f

CLK

: internal system clock)

2. a: 1 during address wait; otherwise 0

3. n: Number of wait states (n

4. Calculated as T = 79 ns (min.) @ V

= 5.0 V

5. Calculated as T = 159 ns (min.) @ V

= 3.0 V

Data Sheet U14118EJ1V0DS

PD78F4938A

AC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Delay time from address to

DAW

= 5.0 V

(1+a) T5

= 3.0 V

(1+a) T10

Address hold time (from WR

)

HWA

= 5.0 V

0.5T14

= 3.0 V

0.5T14

Delay time from ASTB

DSTOD

= 5.0 V

0.5T+15

data output

= 3.0 V

0.5T+20

Data output time from WR

DWOD

Delay time from ASTB

DSTW

= 5.0 V

0.5T9

= 3.0 V

0.5T9

Data setup time (to WR

)

SODWR

= 5.0 V

(1.5+n) T20

= 3.0 V

(1.5+n) T25

Data hold time (from WR

)

HWOD

= 5.0 V

0.5T14

= 3.0 V

0.5T14

Delay time from WR

DWST

= 5.0 V

0.5T9

ASTB

= 3.0 V

0.5T9

WR low-level width

WWL

= 5.0 V

(1.5+n) T25

= 3.0 V

(1.5+n) T30

Remarks 1. T: t

CYK

= 1/f

CLK

: internal system clock)

2. a: 1 during address wait; otherwise 0

3. n: Number of wait states (n

4. Calculated as T = 79 ns (min.) @ V

= 5.0 V

5. Calculated as T = 159 ns (min.) @ V

= 3.0 V

Data Sheet U14118EJ1V0DS

PD78F4938A

AC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(2) External wait timing

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

WAIT

input time from

DAWT

= 5.0 V

(2+a) T40

address

= 3.0 V

(2+a) T60

WAIT

input time from ASTB

DSTWT

= 5.0 V

1.5T40

= 3.0 V

1.5T60

WAIT hold time from ASTB

HSTWTH

= 5.0 V

(0.5+n) T+5

= 3.0 V

(0.5+n) T+10

Delay time from ASTB

DSTWTH

= 5.0 V

(1.5+a) T40

WAIT

= 3.0 V

(1.5+a) T60

WAIT

input time from RD

DRWTL

= 5.0 V

T40

= 3.0 V

T60

WAIT hold time from RD

HRWT

= 5.0 V

nT+5

= 3.0 V

nT+10

Delay time from RD

DRWTH

= 5.0 V

(1+n) T40

WAIT

= 3.0 V

(1+n) T60

Data input time from WAIT

DWTID

= 5.0 V

0.5T5

= 3.0 V

0.5T10

Delay time from WAIT

DWTR

= 5.0 V

0.5T

= 3.0 V

0.5T

Delay time from WAIT

DWTW

= 5.0 V

0.5T

= 3.0 V

0.5T

WAIT

input time from WR

DWWTL

= 5.0 V

T40

= 3.0 V

T60

WAIT hold time from WR

HWWT

= 5.0 V

nT+5

= 3.0 V

nT+10

Delay time from WR

DWWTH

= 5.0 V

(1+n) T40

WAIT

= 3.0 V

(1+n) T60

Remarks 1. T: t

CYK

= 1/f

CLK

: internal system clock)

2. a: 1 during address wait; otherwise 0

3. n: Number of wait states (n

4. Calculated as T = 79 ns (min.) @ V

= 5.0 V

5. Calculated as T = 159 ns (min.) @ V

= 3.0 V

Data Sheet U14118EJ1V0DS

PD78F4938A

AC Characteristics (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(3) Bus hold/refresh timing

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Delay time from HLDRQ

FHQC

= 5.0 V

(2+4+a+n) T+50

to float

= 3.0 V

(2+4+a+n) T+50

Delay time from HLDRQ

DHQHHAH

= 5.0 V

(3+4+a+n) T+30

HLDAK

= 3.0 V

(3+4+a+n) T+40

Delay time from float to

DCFHA

= 5.0 V

T+30

HLDAK

= 3.0 V

T+30

Delay time from HLDRQ

DHQLHAL

= 5.0 V

2T+40

HLDAK

= 3.0 V

2T+60

Delay time from HLDAK

DHAC

= 5.0 V

T20

active

= 3.0 V

T30

Random read/write cycle time

= 5.0 V

= 3.0 V

REFRQ low-level pulse width

WRFQL

= 5.0 V

1.5T25

= 3.0 V

1.5T30

Delay time from ASTB

DSTRFQ

= 5.0 V

0.5T9

REFRQ

= 3.0 V

0.5T9

Delay time from RD

DRRFQ

= 5.0 V

1.5T9

REFRQ

= 3.0 V

1.5T9

Delay time from WR

DWRFQ

= 5.0 V

1.5T9

REFRQ

= 3.0 V

1.5T9

Delay time from REFRQ

DRFQST

= 5.0 V

0.5T9

ASTB

= 3.0 V

0.5T9

REFRQ high-level pulse width

WRFQH

= 5.0 V

1.5T25

= 3.0 V

1.5T30

Remarks 1. T: t

CYK

= 1/f

CLK

: internal system clock)

2. a: 1 during address wait; otherwise 0

3. n: Number of wait states (n

4. Calculated as T = 79 ns (min.) @ V

= 5.0 V

5. Calculated as T = 159 ns (min.) @ V

= 3.0 V

Data Sheet U14118EJ1V0DS

µPD78F4938A

Serial Operation (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(a) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... External clock input)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCK cycle time

CYSK0

SO0 and SO3 are

CLK

= f

8/f

(SCK0, SCK3)

CYSK3

CMOS outputs

Except f

CLK

= f

4/f

CLK

SCK low-level width

WSKL0

SO0 and SO3 are

CLK

= f

4/f

(SCK0, SCK3)

WSKL3

CMOS outputs

Except f

CLK

= f

2/f

CLK

SCK high-level width

WSKH0

SO0 and SO3 are

CLK

= f

4/f

(SCK0, SCK3)

WSKH3

CMOS outputs

Except f

CLK

= f

2/f

CLK

SI0, SI3 setup time

SSSK0

(to SCK0, SCK3

)

SSSK3

SI0, SI3 hold time

HSSK0

1/f

CLK

+ 80

(from SCK0, SCK3

)

HSSK3

Delay time from SCK0,

DBSK0

CMOS output

1/f

CLK

+ 150

SCK3

to output

DBSK3

N-ch open-drain output (R

= 1 k

)

1/f

CLK

+ 400

SO0, SO3 output hold time

HSBSK0

When data is transferred

0.5t

CYSK0

40,

(from SCK0, SCK3

)

HSBSK3

0.5t

CYSK3

Remarks 1. The values in this table are those when CL = 100 pF.

2. f

: External oscillator frequency (f

= 12.58 MHz or f

= 6.29 MHz)

3. f

CLK

: System clock oscillation frequency (selectable from f

, f

/2, f

/4, and f

/8 by the standby control

(b) CSI0, CSI3 3-wire serial I/O mode (SCK0, SCK3 ... Internal clock output)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCK cycle time

CYSK0

SO0 and SO3 are

Except f

CLK

= f

8/f

(SCK0, SCK3)

CYSK3

CMOS outputs

CLK

= f

16/f

SCK low-level width

WSKL0

SO0 and SO3 are

Except f

CLK

= f

4/f

(SCK0, SCK3)

WSKL3

CMOS outputs

CLK

= f

8/f

SCK high-level width

WSKH0

SO0 and SO3 are

Except f

CLK

= f

4/f

(SCK0, SCK3)

WSKH3

CMOS outputs

CLK

= f

8/f

SI0, SI3 setup time

SSSK0

(to SCK0, SCK3

)

SSSK3

SI0, SI3 hold time

HSSK0

(from SCK0, SCK3

)

HSSK3

Delay time from SCK0,

DBSK0

CMOS output

150

SCK3

to output

DBSK3

N-ch open-drain output (R

= 1 k

)

400

SO0, SO3 output hold time

HSBSK0

When data is transferred

0.5t

CYSK0

40,

(from SCK0, SCK3

)

HSBSK3

0.5t

CYSK3

Remarks 1. The values in this table are those when CL = 100 pF.

2. f

: External oscillator frequency (f

= 12.58 MHz or f

= 6.29 MHz)

3. f

CLK

: System clock oscillation frequency (selectable from f

, f

/2, f

/4, and f

/8 by the standby control

Data Sheet U14118EJ1V0DS

µPD78F4938A

Serial Operation (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

(d) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... External clock input)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCK cycle time (SCK1, SCK2)

CYSK1

4.0

5.5 V

640

CYSK2

1280

SCK low-level width

WSKL1

4.0

5.5 V

280

(SCK1, SCK2)

WSKL2

600

SCK high-level width

WSKH1

4.0

5.5 V

280

(SCK1, SCK2)

WSKH2

600

SI1, SI2 setup time

SSSK1

(to SCK1, SCK2

)

SSSK2

SI1, SI2 hold time

HSSK1

(from SCK1, SCK2

)

HSSK2

Delay time from SCK1, SCK2

DSOSK1

to output

DSOSK2

SO1, SO2 output hold time

HSOSK1

When data is transferred

0.5t

CYSK1

40,

(from SCK1, SCK2

)

HSOSK2

0.5t

CYSK2

Remarks 1. The values in this table are those when CL = 100 pF.

2. T: Selected serial clock cycle. The minimum value is 8/f

(e) IOE1, IOE2 3-wire serial I/O mode (SCK1, SCK2 ... Internal clock output)

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

SCK cycle time (SCK1, SCK2)

CYSK1

CYSK2

SCK low-level width

WSKL1

0.5T 40

(SCK1, SCK2)

WSKL2

SCK high-level width

WSKH1

0.5T 40

(SCK1, SCK2)

WSKH2

SI1, SI2 setup time

SSSK1

(to SCK1, SCK2

)

SSSK2

SI1, SI2 hold time

HSSK1

(from SCK1, SCK2

)

HSSK2

Delay time from SCK1, SCK2

DSOSK1

to output

DSOSK2

SO1, SO2 output hold time

HSOSK1

When data is transferred

0.5t

CYSK1

40,

(from SCK1, SCK2

)

HSOSK2

0.5t

CYSK2

Remarks 1. The values in this table are those when CL = 100 pF.

2. T: Selected serial clock cycle. The minimum value is 8/f

Data Sheet U14118EJ1V0DS

µPD78F4938A

Other Operations (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

NMI high-/low-level width

WNIL

µs

WNIH

INTP0 high-/low-level width

WIT0L

CYSMP

WIT0H

INTP1 to INTP3, CI high-/

WIT1L

CYCPU

low-level width

WIT1H

INTP4, INTP5 high-/

WIT2L

µs

low-level width

WIT2H

RESET high-/low-level

WRSL

µs

width

Note

WRSH

Note

When the power is turned on or when STOP mode is released by reset, secure the oscillation stabilization wait

time while the RESET is at a low-level width.

When the power is applied, be sure to activate V

in the RESET = low-level state.

Remark

CYSMP

: Sampling clock set by software

CYCPU

: CPU clock set by software in the CPU

Clock Output Operation (T

= 40 to +85

C, V

= AV

= 3.0 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

CLKOUT cycle time

CYCL

32000

CLKOUT low-level width

CLL

4.5

5.5 V

0.5T 10

0.5T 20

CLKOUT high-level width

CLH

4.5

5.5 V

0.5T 10

0.5T 20

CLKOUT rise time

CLR

4.5

5.5 V

3.0

4.5 V

CLKOUT fall time

CLF

4.5

5.5 V

3.0

4.5 V

Remark

n: Division ratio of clock output frequency, T: t

CYK

= 1/f

CLK

(system clock cycle time)

IEBus Controller Characteristics (T

= 40 to +85

C, V

= AV

= 4.5 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

IEBus system clock frequency

Mode 1

6.29

MHz

Remark

Although the system clock frequency in the IEBus specifications is 6.0 MHz, in the

µPD784938A, operation

at 6.29 MHz is also guaranteed. Note, however, that operation at 6.0 MHz and 6.29 MHz cannot be used

together.

Data Sheet U14118EJ1V0DS

µPD78F4938A

A/D Converter Characteristics (T

= 40 to +85

C, V

= AV

REF1

= 3.0 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note 1

IEAD = 00H 6.29 MHz

12.58 MHz

±0.6

%FSR

Note 2

and other than FR = 1

6.29 MHz

12.58 MHz

±1.5

%FSR

Note 2

and FR = 1

IEAD = 01H 4.5

5.5 V

±1

±2.2

%FSR

Note 2

3.0

< 5.5 V

±1.4

±2.6

%FSR

Note 2

Quantization error

±1/2

LSB

Conversion time

CONV

FR = 1: 120t

CYK

9.5

480

µs

FR = 0: 240t

CYK

19.1

960

µs

Sampling time

SAMP

FR = 1: 18t

CYK

1.4

µs

FR = 0: 36t

CYK

2.9

144

µs

Analog input voltage

IAN

REF1

Analog input impedance

1000

Reference voltage

REF1

3.0

REF1

resistor

AVREF1

3.0

REF1

current

REF1

0.5

1.5

current

DD1

2.0

5.0

DD2

Notes 1. Excludes quantization error (

±1/2 LSB).

2. It is indicated as a ratio (%FSR) to the full-scale value.

Caution The analog input pins of the

µPD78F4938A function alternately as the port 7 pins (I/O port pins).

However when using the A/D converter, it is necessary to set all the pins of port 7 to input mode

in order to prevent data from being inverted by the output port operation, thus degrading the A/D

conversion accuracy. At this time, pins cannot be used as output ports even though they are not

used as A/D analog input port.

Data Sheet U14118EJ1V0DS

PD78F4938A

8. PACKAGE DRAWING

Remark

The external dimensions and material of the ES version are the same as those of the mass-produced

version.

100PIN PLASTIC QFP (14x20)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.

P100GF-65-3BA1-3

20.0

0.2

0.795+0.009

0.008

14.0

0.2

0.551+0.009

0.008

17.6

0.4

0.693

0.016

0.8

0.031

0.6

0.024

0.30

0.10

0.012

0.15

0.006

0.65 (T.P.)

0.026 (T.P.)

1.8

0.2

0.071+0.008

0.009

0.8

0.2

0.031

0.10

0.004

0.1

0.004

3.0 MAX.

0.119 MAX.

detail of lead end

2.7

0.1

0.106+0.005

0.004

100

C D

23.6

0.4

0.929

0.016

0.15

0.006

+0.10

0.05

°±

+0.004

0.005

+0.009

0.008

+0.004

0.003

Data Sheet U14118EJ1V0DS

PD78F4938A

9. RECOMMENDED SOLDERING CONDITIONS

The

PD78F4938A should be soldered and mounted under the following recommended conditions.

For details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact an NEC sales representative.

Table 9-1. Surface Mounting Type Soldering Conditions

PD78F4938AGF-3BA: 100-pin plastic QFP (14

20)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or higher),

IR35-207-2

Count: two times or less, Exposure limit: 7 days

Note

(after that, prebake at

125

C for 20 hours)

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or higher),

VP15-207-2

Count: two times or less, Exposure limit: 7 days

Note

(after that, prebake at 125

for 20 hours)

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: once,

WS60-207-1

Preheating temperature: 120

C max. (package surface temperature),

Exposure limit: 7 days

Note

(after that, prebake at 125

C for 20 hours)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Note

After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Data Sheet U14118EJ1V0DS

PD78F4938A

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78F4938A.

Also refer to (5) Cautions on using development tools.

(1) Language processing software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784937

Device file for

PD784938A Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) Flash memory writing tools

Flashpro III

Flash programmer for microcontroller with on-chip flash memory

(PG-FP3)

FA-100GF

Flash memory writing adapter for 100-pin plastic QFP (GF-3BA type). Wiring must be performed

according to the product used.

(3) Debugging tools

When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter used when PC-9800 series (except notebook type) is used as host machine

IE-70000-CD-IF-C

PC card and cable used when PC-9800 series notebook type PC is used as host machine

IE-70000-PC-IF-C

Interface adapter used when IBM PC/AT

or compatible is used as host machine

IE-784937-NS-EM1

Emulation board to emulate

PD784938A Subseries

NP-100GF

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784937

Device file for

PD784938A Subseries

Data Sheet U14118EJ1V0DS

PD78F4938A

When IE-784000-R in-circuit emulator is used

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-B

Interface adapter used when PC-9800 series (except notebook type) is used as host machine

IE-70000-98-IF-C

IE-70000-98N-IF

Interface adapter and cable used when PC-9800 series notebook type PC is used as host machine

IE-70000-PC-IF-B

Interface adapter used when IBM PC/AT or compatible is used as host machine

IE-70000-PC-IF-C

IE-78000-R-SV3

Interface adapter and cable used when EWS is used as host machine

IE-784937-NS-EM1

Emulation board to emulate

PD784938A Subseries

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX2

Emulation probe conversion board necessary when using IE-784937-NS-EM1 on IE-784000-R.

Not necessary when using IE-784937-R-EM1

EP-78064GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784937

Device file for

PD784938A Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

Data Sheet U14118EJ1V0DS

PD78F4938A

(5) Cautions on using development tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784937.

The CC78K4 and RX78K/IV are used in combination with the RA78K4 or DF784937.

The Flashpro III, FA-100GF, and NP-100GF are products made by Naito Densei Machida Mfg. Co, Ltd (TEL

+81-44-822-3813).

The host machine and OS suitable for each software are as follows:

Host Machine [OS]

EWS

PC-9800 series [Windows]

HP9000 series 700

[HP-UX

]

IBM PC/AT and compatibles

SPARCstation

[SunOS

, Solaris

]

Software

[Japanese/English Windows]

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

DOS-based software

Data Sheet U14118EJ1V0DS

µPD78F4938A

APPENDIX B. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Documents related to devices

Document Name

Document No.

µPD784935A, 784936A, 784937A, 784938A Data Sheet

Under preparation

µPD78F4938A Data Sheet

This document

µPD784938 Subseries User's Manual Hardware

U13987E

78K/IV Series User's Manual Instructions

U10905E

78K/IV Series Application Note Software Basics

U10095E

Documents related to development tools (user's manuals)

Document Name

Document No.

RA78K4 Assembler Package

Language

U11162E

Operation

U11334E

Structured Assembler

U11743E

Preprocessor

CC78K4 C Compiler

Language

U11571E

Operation

U11572E

PG-FP3 Flash Memory Programmer

U13502E

IE-78K4-NS

U13556E

IE-784000-R

U12903E

IE-784937-R-EM1

To be prepared

IE-784937-NS-EM1

To be prepared

EP-78064

EEU-1469

SM78K4 System Simulator Windows Based

Reference

U10093E

SM78K Series System Simulator

External Part User Open

U10092E

Interface Specifications

ID78K4 Integrated Debugger Windows Based

Reference

U10440E

ID78K4-NS Integrated Debugger Windows Based

Reference

U12796E

Project Manager Ver. 3.12 or Later Windows Based

U14610E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

Data Sheet U14118EJ1V0DS

µPD78F4938A

Documents related to embedded software (user's manuals)

Document Name

Document No.

78K/IV Series Real-Time OS

Fundamental

U10603E

Installation

U10604E

Other documents

Document Name

Document No.

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)

X13769X

Semiconductor Device Mounting Technology Manual

C10535E

Quality Grades on NEC Semiconductor Devices

C11531E

NEC Semiconductor Device Reliability/Quality Control System

U10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892E

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

version of each document for designing.

Data Sheet U14118EJ1V0DS

µPD78F4938A

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/

or other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

EEPROM, FIP, and IEBus are trademarks of NEC Corporation.

Data Sheet U14118EJ1V0DS

µPD78F4938A

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-3067-5800
Fax: 01-3067-5899

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

Novena Square, Singapore
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP, Brasil
Tel: 11-6462-6810
Fax: 11-6462-6829

J01.2

PD78F4938A

M8E 00.4

The information in this document is current as of December, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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