Document Outline

COVER
DESCRIPTION
FEATURES
APPLICATIONS
ORDERING INFORMATION
78K/IV SERIES LINEUP
OVERVIEW OF FUNCTIONS
1. DIFFERENCES AMONG MODELS IN uPD784216A, 784216AY/784218A, 784218AY SUBSERIES
2. MAJOR DIFFERENCES FROM uPD78078Y SUBSERIES
3. PIN CONFIGURATION (TOP VIEW)
4. BLOCK DIAGRAM
5. PIN FUNCTIONS
- 5.1 Port Pins
- 5.2 Non-Port Pins
- 5.3 Pin I/O Circuits and Recommended Connections of Unused Pins
6. CPU ARCHITECTURE
- 6.1 Memory Space
- 6.2 CPU Registers
  - 6.2.1 General-purpose registers
  - 6.2.2 Control registers
  - 6.2.3 Special function registers (SFRs)
7. PERIPHERAL HARDWARE FUNCTIONS
- 7.1 Ports
- 7.2 Clock Generator
- 7.3 Real-Time Output Port
- 7.4 Timer/Event Counter
- 7.5 A/D Converter
- 7.6 D/A Converter
- 7.7 Serial Interface
  - 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
  - 7.7.2 Clocked serial interface (CSI)
- 7.8 Clock Output Function
- 7.9 Buzzer Output Function
- 7.10 Edge Detection Function
- 7.11 Watch Timer
- 7.12 Watchdog Timer
8. INTERRUPT FUNCTIONS
- 8.1 Interrupt Sources
- 8.2 Vectored Interrupt
- 8.3 Context Switching
- 8.4 Macro Service
- 8.5 Application Example of Macro Service
9. LOCAL BUS INTERFACE
- 9.1 Memory Expansion
- 9.2 Programmable Wait
10. STANDBY FUNCTION
11. RESET FUNCTION
12. INSTRUCTION SET
13. ELECTRICAL SPECIFICATIONS
14. PACKAGE DRAWINGS
15. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. DEVELOPMENT TOOLS
APPENDIX B. RELATED DOCUMENTS

MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

16-BIT SINGLE-CHIP MICROCONTROLLERS

Document No. U14121EJ2V0DS00 (2nd edition)
Date Published August 2000 N CP(K)
Printed in Japan

DATA SHEET

DESCRIPTION

The

PD784214A, 784215A, 784216A, 784217A, and 784218A are products of the

PD784216A/784218A

Subseries in the 78K/IV Series. Besides a high-speed and high performance CPU, these controllers have ROM,

RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interfaces, a real-time output port, interrupt

functions, and various other peripheral hardware.

The

PD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are based on the

PD784216Y/784218Y

Subseries with the addition of a multimaster-supporting I

C bus interface.

The

PD78F4218A and 78F4218AY, products with a flash memory instead of the internal ROM of mask ROM

versions, and various development tools are also available.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

µ
µ
µ
µ

PD784216A, 784216AY Subseries User's Manual Hardware: U13570E

µ
µ
µ
µ

PD784218A, 784218AY Subseries User's Manual Hardware: U12970E

78K/IV Series User's Manual Instructions:

U10905E

FEATURES

78K/IV Series

Supply voltage: V

= 1.8 to 5.5 V

Standby function

Inherits peripheral functions of

PD78078, 78078Y

Subseries

HALT/STOP/IDLE mode

Minimum instruction execution time

160 ns

In low-power consumption mode: HALT/IDLE mode
(with subsystem clock)

(@f

= 12.5 MHz operation with main system clock)

Clock division function

Watch timer: 1 channel

(@f

= 32.768 kHz operation with subsystem clock)

Watchdog timer: 1 channel

I/O port: 86 pins

Clock output function

Timer/event counter:

16-bit timer/event counter

1 unit

Selectable from f

, f

/2, f

, f

8-bit timer/event counter

6 units

Buzzer output function

Serial interface: 3 channels

Selectable from f

, f

UART/IOE (3-wire serial I/O): 2 channels

A/D converter: 8-bit resolution

8 channels

CSI (3-wire serial I/O, I

C bus supporting

multimaster

Note

): 2 channels

D/A converter: 8-bit resolution

2 channels

Note

PD784216AY/784218AY Subseries only

APPLICATIONS

Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment

Unless otherwise specified, references in this document to the

µ
µ
µ
µ

PD784218A, 784218AY refer to the

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, and

784218AY.

The mark shows major revised points.

2000

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

ORDERING INFORMATION

Part Number

Package

Internal ROM (Bytes)

Internal RAM (Bytes)

PD784214AGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

96 K

3,584

PD784214AGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

96 K

3,584

PD784215AGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

128 K

5,120

PD784215AGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

128 K

5,120

PD784216AGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

128 K

8,192

PD784216AGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

128 K

8,192

PD784217AGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

192 K

12,800

PD784217AGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

192 K

12,800

PD784218AGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

256 K

12,800

PD784218AGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

256 K

12,800

PD784214AYGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

96 K

3,584

PD784214AYGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

96 K

3,584

PD784215AYGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

128 K

5,120

PD784215AYGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

128 K

5,120

PD784216AYGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

128 K

8,192

PD784216AYGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

128 K

8,192

PD784217AYGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

192 K

12,800

PD784217AYGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

192 K

12,800

PD784218AYGC-

×××

-8EU

100-pin plastic LQFP
(fine pitch) (14

14 mm)

256 K

12,800

PD784218AYGF-

×××

-3BA

100-pin plastic QFP
(14

20 mm)

256 K

12,800

Remark

×××

indicates ROM code suffix.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced
A/D converter,
16-bit timer, and
power management

Enhanced internal memory capacity
Pin-compatible with the PD784026

Supports I

C bus

Supports multimaster I

C bus

80-pin, ROM correction added

Supports multimaster I

C bus

Enhanced internal memory
capacity, ROM correction added

100-pin, enhanced I/O and
internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

Supports multimaster I

C bus

Enhanced functions
of the PD784915

Standard models

ASSP models

Supports multimaster I

C bus

: Products in mass-production

: Products under development

PD784976A

On-chip VFD controller/driver

PD784938A

Enhanced functions of the
PD784908, enhanced
internal memory capacity,
ROM correction added.

PD784967

Enhanced functions of the
PD784938A, enhanced
I/O and internal memory
capacity.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

OVERVIEW OF FUNCTIONS (1/2)

Part Number

Item

PD784214A,

PD784214AY

PD784215A,

PD784215AY

PD784216A,

PD784216AY

PD784217A,

PD784217AY

PD784218A,

PD784218AY

Number of basic instructions (mnemonics)

113

General-purpose registers

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory

mapping)

Minimum instruction execution time

160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@f

= 12.5 MHz operation with

main system clock)

s (@f

= 32.768 kHz operation with subsystem clock)

ROM

96 KB

128 KB

192 KB

256 KB

Internal

memory

RAM

3,584 bytes

5,120 bytes

8,192 bytes

12,800 bytes

Memory space

1 MB with program and data spaces combined

Total

CMOS input

CMOS I/O

I/O ports

N-ch open-drain I/O

Pins with pull-up resistor

LED direct drive output

Pins with

additional

functions

Note 1

Middle-voltage pin

Real-time output port

4 bits

2 or 8 bits

Timer/event counter:

Timer counter

Pulse output

(16-bit)

Capture/compare register

PPG output

Square wave output

One-shot pulse output

Timer/event counter 1: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 2: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 5: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 6: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 7: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter

Timer/event counter 8: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)

CSI (3-wire serial I/O, multimaster supporting I

C bus

Note 2

): 1 channel

A/D converter

8-bit resolution

8 channels

D/A converter

8-bit resolution

2 channels

Notes 1. Pins with additional functions are included with the I/O pins.

PD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

OVERVIEW OF FUNCTIONS (2/2)

Part Number

Item

PD784214A,

PD784214AY

PD784215A,

PD784215AY

PD784216A,

PD784216AY

PD784217A,

PD784217AY

PD784218A,

PD784218AY

Clock output

Selectable from f

, f

/2, f

, f

Buzzer output

Selectable from f

, f

Watch timer

1 channel

Watchdog timer

1 channel

Standby

HALT/STOP/IDLE modes

In low power consumption mode (with subsystem clock): HALT/IDLE modes

Hardware sources

29 (internal: 20, external: 9)

Software sources

BRK instruction, BRKCS instruction, operand error

Non-maskable

Internal: 1, external: 1

Interrupt

Maskable

Internal: 19, external: 8

4 programmable priority levels

3 service modes: Vectored interrupt/macro service/context switching

Supply voltage

= 1.8 to 5.5 V

Package

100-pin plastic LQFP (fine pitch) (14

14 mm)

100-pin plastic QFP (14

20 mm)

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

CONTENTS

1. DIFFERENCES AMONG MODELS IN

µ
µ
µ
µ

PD784216A, 784216AY/784218A, 784218AY SUBSERIES....... 8

2. MAJOR DIFFERENCES FROM

µ
µ
µ
µ

PD78078Y SUBSERIES ................................................................ 9

3. PIN CONFIGURATION (TOP VIEW).................................................................................................. 10

4. BLOCK DIAGRAM ............................................................................................................................... 13

5. PIN FUNCTIONS .................................................................................................................................. 14

5.1 Port Pins ...................................................................................................................................... 14

5.2 Non-Port Pins .............................................................................................................................. 16

5.3 Pin I/O Circuits and Recommended Connections of Unused Pins ........................................ 18

6. CPU ARCHITECTURE ......................................................................................................................... 22

6.1 Memory Space ............................................................................................................................. 22

6.2 CPU Registers.............................................................................................................................. 29

6.2.1 General-purpose registers ..............................................................................................................29

6.2.2 Control registers..............................................................................................................................30

6.2.3 Special function registers (SFRs)....................................................................................................31

7. PERIPHERAL HARDWARE FUNCTIONS.......................................................................................... 36

7.1 Ports ............................................................................................................................................. 36

7.2 Clock Generator........................................................................................................................... 37

7.3 Real-Time Output Port ................................................................................................................ 39

7.4 Timer/Event Counter ................................................................................................................... 40

7.5 A/D Converter .............................................................................................................................. 42

7.6 D/A Converter .............................................................................................................................. 43

7.7 Serial Interface............................................................................................................................. 44

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE) ..........................................................45

7.7.2 Clocked serial interface (CSI) .........................................................................................................47

7.8 Clock Output Function................................................................................................................ 49

7.9 Buzzer Output Function.............................................................................................................. 49

7.10 Edge Detection Function .......................................................................................................... 50

7.11 Watch Timer ............................................................................................................................... 50

7.12 Watchdog Timer ........................................................................................................................ 51

8. INTERRUPT FUNCTIONS.................................................................................................................... 52

8.1 Interrupt Sources......................................................................................................................... 52

8.2 Vectored Interrupt ....................................................................................................................... 54

8.3 Context Switching ....................................................................................................................... 55

8.4 Macro Service .............................................................................................................................. 56

8.5 Application Example of Macro Service ..................................................................................... 57

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

9. LOCAL BUS INTERFACE................................................................................................................. 58

9.1 Memory Expansion ..................................................................................................................... 59

9.2 Programmable Wait .................................................................................................................... 59

10. STANDBY FUNCTION ....................................................................................................................... 60

11. RESET FUNCTION ............................................................................................................................ 62

12. INSTRUCTION SET ........................................................................................................................... 63

13. ELECTRICAL SPECIFICATIONS ...................................................................................................... 68

14. PACKAGE DRAWINGS ..................................................................................................................... 88

15. RECOMMENDED SOLDERING CONDITIONS................................................................................ 90

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 92

APPENDIX B. RELATED DOCUMENTS................................................................................................ 95

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

1. DIFFERENCES AMONG MODELS IN

µ
µ
µ
µ

PD784216A, 784216AY/784218A, 784218AY

SUBSERIES

The only difference among the

PD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal

memory capacity.

The

PD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I

C bus

control function.

The

PD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory

instead of the mask ROM of the above models.

These differences are summarized in Table 1-1.

Table 1-1. Differences Among Models in

µ
µ
µ
µ

PD784216A, 784216AY/784218A, 784218AY Subseries

Part Number

Item

PD784214A,

PD784214AY

PD784215A,

PD784215AY

PD784216A,

PD784216AY

PD784217A,

PD784217AY

PD784218A,

PD784218AY

PD78F4216A,

PD78F4216AY

PD78F4218A,

PD78F4218AY

Internal ROM

96 KB

(Mask

ROM)

128 KB (Mask ROM)

192 KB

(Mask

ROM)

256 KB

(Mask

ROM)

128 KB

(Flash

memory)

256 KB

(Flash

memory)

Internal RAM

3,584 bytes

5,120 bytes

8,192 bytes

12,800 bytes

5,120 bytes

12,800

bytes

Internal memory size

switching register

(IMS)

Not provided

Provided

Note

ROM correction

Not provided

Provided

Not

provided

Provided

External access status

function

Not provided

Provided

Not

provided

Provided

Supply voltage

= 1.8 to 5.5 V

= 1.9 to 5.5 V

Electrical

specifications

Recommended

soldering conditions

Refer to the data sheet for each device.

EXA pin

Not provided

Provided

Not

provided

Provided

TEST pin

Provided

Not provided

Provided

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then

mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the

commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

2. MAJOR DIFFERENCES FROM

µ
µ
µ
µ

PD78078Y SUBSERIES

Series Name

Item

PD784216A, 784216AY/784218A,

784218AY Subseries

PD78078Y Subseries

CPU

16-bit CPU

8-bit CPU

With main system

clock

160 ns (@12.5 MHz operation)

400 ns (@5.0 MHz operation)

Minimum instruction

execution time

With subsystem clock

s (@32.768 kHz operation)

122

s (@32.768 kHz operation)

Memory space

1 MB

64 KB

Total

CMOS input

CMOS I/O

I/O ports

N-ch open-drain I/O

Pins with pull-up

resistor

LED direct drive

output

Pins with

additional

functions

Note 1

Middle-voltage pin

Timer/counter

16-bit timer/event counter

1 unit

8-bit timer/event counter

6 units

16-bit timer/event counter

1 unit

8-bit timer/event counter

4 units

Serial interface

UART/IOE (3-wire serial I/O)

channels

CSI (3-wire serial I/O, multimaster

supporting I

C bus

Note 2

)

1 channel

UART/IOE (3-wire serial I/O)

channel

CSI (3-wire serial I/O, 2-wire serial

I/O, I

C bus)

1 channel

CSI (3-wire serial I/O, 3-wire serial

I/O with automatic transmit/receive

function)

1 channel

NMI pin

Provided

Not provided

Macro service

Provided

Not provided

Context switching

Provided

Not provided

Interrupts

Programmable priority

4 levels

Not provided

Standby function

HALT/STOP/IDLE modes

In low power consumption mode:

HALT/IDLE modes

HALT/STOP modes

Package

100-pin plastic LQFP (fine pitch)

(14

14 mm)

100-pin plastic QFP (14

20 mm)

100-pin plastic LQFP (fine pitch)

(14

14 mm)

100-pin plastic QFP (14

20 mm)

100-pin ceramic WQFN

(14

20 mm) (

PD78P078Y only)

Notes 1. Pins with additional functions are included with the I/O pins.

PD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

3. PIN CONFIGURATION (TOP VIEW)

·
·
·
·

100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784214AGC-

×××

-8EU,

µ
µ
µ
µ

PD784215AGC-

×××

-8EU,

µ
µ
µ
µ

PD784216AGC-

×××

-8EU,

µ
µ
µ
µ

PD784217AGC-

×××

-8EU,

µ
µ
µ
µ

PD784218AGC-

×××

-8EU,

µ
µ
µ
µ

PD784214AYGC-

×××

-8EU,

µ
µ
µ
µ

PD784215AYGC-

×××

-8EU,

µ
µ
µ
µ

PD784216AYGC-

×××

-8EU,

µ
µ
µ
µ

PD784217AYGC-

×××

-8EU,

µ
µ
µ
µ

PD784218AYGC-

×××

-8EU

100

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Note 2

REF0

P10/ANI0

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P95

P94

P93

P92

P91

P90

TEST

Note 1

P37/EXA

Note 5

P36/TI01

P35/TI00

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P103/TI8/TO8

P102/TI7/TO7

P101/TI6/TO6

P100/TI5/TO5

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P63/A19

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

Note 3

P130/ANO0

P131/ANO1

REF1

P70/RxD2/SI2

P71/TxD2/SO2

P72/ASCK2/SCK2

P20/RxD1/SI1

P21/TxD1/SO1

P22/ASCK1/SCK1

P23/PCL

P24/BUZ

P25/SI0/SDA0

Note 4

P26/SO0

P27/SCK0/SCL0

Note 4

P80/A0

P81/A1

P82/A2

Notes 1. Connect the TEST pin to V

directly or via a pull-down resistor. For the pull-down connection, it is

recommended to use a resistor with a resistance ranging from 470

to 10 k

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are available in

PD784216AY/784218AY Subseries products only.

5. The EXA pin is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

·
·
·
·

100-pin plastic QFP (14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784214AGF-

×××

-3BA,

µ
µ
µ
µ

PD784215AGF-

×××

-3BA,

µ
µ
µ
µ

PD784216AGF-

×××

-3BA,

µ
µ
µ
µ

PD784217AGF-

×××

-3BA,

µ
µ
µ
µ

PD784218AGF-

×××

-3BA,

µ
µ
µ
µ

PD784214AYGF-

×××

-3BA,

µ
µ
µ
µ

PD784215AYGF-

×××

-3BA,

µ
µ
µ
µ

PD784216AYGF-

×××

-3BA,

µ
µ
µ
µ

PD784217AYGF-

×××

-3BA,

µ
µ
µ
µ

PD784218AYGF-

×××

-3BA

100

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P82/A2

P81/A1

P80/A0

P27/SCK0/SCL0

Note 4

P26/SO0

P25/SI0/SDA0

Note 4

P24/BUZ

P23/PCL

P22/ASCK1/SCK1

P21/TxD1/SO1

P20/RxD1/SI1

P72/ASCK2/SCK2

P71/TxD2/SO2

P70/RxD2/SI2

REF1

P131/ANO1

P130/ANO0

Note 3

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

REF0

Note 2

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P100/TI5/TO5

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/TI00

P36/TI01

P37/EXA

Note 5

TEST

Note 1

P90

P91

P92

P93

P94

P95

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Notes 1. Connect the TEST pin to V

directly or via a pull-down resistor. For the pull-down connection, it is

recommended to use a resistor with a resistance ranging from 470

to 10 k

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are available in

PD784216AY/784218AY Subseries products only.

5. The EXA pin is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

A0 to A19:

Address Bus

P120 to P127:

Port 12

AD0 to AD7:

Address/Data Bus

P130, P131:

Port 13

ANI0 to ANI7:

Analog Input

PCL:

Programmable Clock

ANO0, ANO1:

Analog Output

RD:

Read Strobe

ASCK1, ASCK2:

Asynchronous Serial Clock

RESET:

Reset

ASTB:

Address Strobe

RTP0 to RTP7:

Real-time Output Port

Analog Power Supply

RxD1, RxD2:

Receive Data

REF0

, AV

REF1

Analog Reference Voltage

SCK0 to SCK2:

Serial Clock

Analog Ground

SCL0

Note 1

Serial Clock

BUZ:

Buzzer Clock

SDA0

Note 1

Serial Data

EXA

Note 2

External Access Status Output

SI0 to SI2:

Serial Input

INTP0 to INTP6:

Interrupt from Peripherals

SO0 to SO2:

Serial Output

NMI:

Non-maskable Interrupt

TEST:

Test

P00 to P06:

Port 0

TI00, TI01,

P10 to P17:

Port 1

TI1, TI2, TI5 to TI8:

Timer Input

P20 to P27:

Port 2

TO0 to TO2, TO5 to TO8: Timer Output

P30 to P37:

Port 3

TxD1, TxD2:

Transmit Data

P40 to P47:

Port 4

Power Supply

P50 to P57:

Port 5

Ground

P60 to P67:

Port 6

WAIT:

Wait

P70 to P72:

Port 7

WR:

Write Strobe

P80 to P87:

Port 8

X1, X2:

Crystal (Main System Clock)

P90 to P95:

Port 9

XT1, XT2:

Crystal (Subsystem Clock)

P100 to P103:

Port 10

Notes 1. The SCL0 and SDA0 pins are available in

PD784216AY/784218AY Subseries products only.

2. The EXA pin is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

4. BLOCK DIAGRAM

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP6

Programmable
interrupt
controller

Real-time
output port

Timer/event

counter 7

(8 bits)

Timer/event

counter 6

(8 bits)

Timer/event

counter 5

(8 bits)

Timer/event

counter 2

(8 bits)

Timer/event

counter 1

(8 bits)

Timer/event

counter

(16 bits)

Watch timer

Timer/event

counter 8

(8 bits)

Watchdog timer

TI00
TI01

TO0

TI1

TO1

TI2

TO2

TI5/TO5

TI6/TO6

TI7/TO7

TI8/TO8

NMI/INTP2

RTP0 to RTP7

Clock output
control

A/D
converter

PCL

BUZ

REF0

ANI0 to ANI7

D/A
converter

ANO0

P03/INTP3

REF1

ANO1

78K/IV

CPU Core

ROM

RAM

Baud-rate
generator

RxD1/SI1

TxD1/SO1

ASCK1/SCK1

RxD2/SI2

TxD2/SO2

ASCK2/SCK2

SI0/SDA0
SO0
SCK0/SCL0

Bus I/F

UART/IOE1

ASTB

WR
WAIT

A0 to A7

AD0 to AD7

A8 to A15

A16 to A19

Port 1

P10 to P17

Port 0

P00 to P06

Port 2

P20 to P27

Port 3

P30 to P37

Port 4

P40 to P47

Port 5

P50 to P57

Port 6

P60 to P67

Port 7

P70 to P72

Port 8

P80 to P87

Port 9

P90 to P95

Port 10

P100 to P103

Port 12

P120 to P127

Port 13

P130, P131

Buzzer output

System control

RESET

XT2

XT1

TEST

Clocked
serial
interface

Note 1

Baud-rate
generator

UART/IOE2

EXA

Note 2

Notes 1. This function supports the I

C bus interface and is available in

PD784216AY/784218AY Subseries

products only.

2. The EXA pin is available in

PD784218A, 784218AY Subseries products only.

Remark The internal ROM and RAM capacities differ depending on the product.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5. PIN FUNCTIONS

5.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00

INTP0

P01

INTP1

P02

INTP2/NMI

P03

INTP3

P04

INTP4

P05

INTP5

P06

I/O

INTP6

Port 0 (P0):

7-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P10 to P17

Input

ANI0 to ANI7

Port 1 (P1):

8-bit input only port

P20

RxD1/SI1

P21

TxD1/SO1

P22

ASCK1/SCK1

P23

PCL

P24

BUZ

P25

SI0/SDA0

Note 1

P26

SO0

P27

I/O

SCK0/SCL0

Note 1

Port 2 (P2):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P30

TO0

P31

TO1

P32

TO2

P33

TI1

P34

TI2

P35

TI00

P36

TI01

P37

I/O

EXA

Note 2

Port 3 (P3):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

8-bit I/O port

Input/output can be specified in 1-bit units.

All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

LEDs can be driven directly.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

8-bit I/O port

Input/output can be specified in 1-bit units.

All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

LEDs can be driven directly.

Notes 1. This function is available in

PD784216AY/784218AY Subseries products only.

2. This function is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.1 Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

P60

A16

P61

A17

P62

A18

P63

A19

P64

P65

P66

WAIT

P67

I/O

ASTB

Port 6 (P6):

8-bit I/O port

Input/output can be specified in 1-bit units.

All pins set in input mode can be connected to on-chip pull-up

resistors by means of software.

P70

RxD2/SI2

P71

TxD2/SO2

P72

I/O

ASCK2/SCK2

Port 7 (P7):

3-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P80 to P87

I/O

A0 to A7

Port 8 (P8):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

The interrupt control flag (KRIF) is set to 1 when a falling edge is

detected at a pin of this port.

P90 to P95

I/O

Port 9 (P9):

N-ch open-drain middle-voltage I/O port

6-bit I/O port

Input/output can be specified in 1-bit units.

LEDs can be driven directly.

P100

TI5/TO5

P101

TI6/TO6

P102

TI7/TO7

P103

I/O

TI8/TO8

Port 10 (P10):

4-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P120 to P127

I/O

RTP0 to RTP7

Port 12 (P12):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, use of an on-chip

pull-up resistor can be specified in 1-bit units by means of

software.

P130, P131

I/O

ANO0, ANO1

Port 13 (P13):

2-bit I/O port

Input/output can be specified in 1-bit units.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.2

Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

P35

External count clock input to 16-bit timer counter

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer counter 1

TI2

P34

External count clock input to 8-bit timer counter 2

TI5

P100/TO5

External count clock input to 8-bit timer counter 5

TI6

P101/TO6

External count clock input to 8-bit timer counter 6

TI7

P102/TO7

External count clock input to 8-bit timer counter 7

TI8

Input

P103/TO8

External count clock input to 8-bit timer counter 8

TO0

P30

16-bit timer output (shared by 14-bit PWM output)

TO1

P31

TO2

P32

TO5

P100/TI5

TO6

P101/TI6

TO7

P102/TI7

TO8

Output

P103/TI8

8-bit timer output (shared by 8-bit PWM output)

RxD1

P20/SI1

Serial data input (UART1)

RxD2

Input

P70/SI2

Serial data input (UART2)

TxD1

P21/SO1

Serial data output (UART1)

TxD2

Output

P71/SO2

Serial data output (UART2)

ASCK1

P22/SCK1

Baud rate clock input (UART1)

ASCK2

Input

P72/SCK2

Baud rate clock input (UART2)

SI0

P25/SDA0

Note

Serial data input (3-wire serial I/O 0)

SI1

P20/RxD1

Serial data input (3-wire serial I/O 1)

SI2

Input

P70/RxD2

Serial data input (3-wire serial I/O 2)

SO0

P26

Serial data output (3-wire serial I/O 0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O 1)

SO2

Output

P71/TxD2

Serial data output (3-wire serial I/O 2)

SDA0

P25/SI0

Serial data input/output (I

C bus)

SCK0

P27/SCL0

Note

Serial clock input/output (3-wire serial I/O 0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O 1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O 2)

SCL0

I/O

P27/SCK0

Serial clock input/output (I

C bus)

NMI

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

INTP6

Input

P06

External interrupt request input

Note This function is available in

PD784216AY/784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.2 Non-Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0 to RTP7

Output

P120 to P127

Real-time output port that outputs data in synchronization with

trigger

AD0 to AD7

I/O

P40 to P47

Lower address/data bus for expanding memory externally

A0 to A7

P80 to P87

Lower address bus for expanding memory externally

A8 to A15

P50 to P57

Middle address bus for expanding memory externally

A16 to A19

Output

P60 to P63

Higher address bus for expanding memory externally

P64

Strobe signal output for reading from external memory

Output

P65

Strobe signal output for writing to external memory

WAIT

Input

P66

Wait insertion at external memory access

ASTB

Output

P67

Strobe output that externally latches address information output to

ports 4 through 6 and 8 to access external memory

EXA

Note

Output

P37

Status signal output at external memory access

RESET

Input

System reset input

Input

Connecting crystal resonator for main system clock oscillation

XT1

Input

XT2

Connecting crystal resonator for subsystem clock oscillation

ANI0 to ANI7

Input

P10 to P17

A/D converter analog input

ANO0, ANO1

Output

P130, P131

D/A converter analog output

REF0

A/D converter reference voltage input

REF1

D/A converter reference voltage input

A/D converter positive power supply. Connect to V

GND for A/D converter and D/A converter. Connect to V

Positive power supply

GND

TEST

Connect this pin to V

directly or via a pull-down resistor. For the

pull-down connection, it is recommended to use a resistor with a

resistance ranging from 470

to 10 k

(this pin is for IC test).

Note This function is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

5.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The input/output circuit type of each pin and recommended connections of unused pins are shown in Table 5-1.
For each type of input/output circuit, refer to Figure 5-1.

Table 5-1. Types of Pin Input/Output Circuits and Recommended Connection of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3 to P06/INTP6

8-N

I/O

Input:

Independently connect to V

via a resistor

Output: Leave open

P10/ANI0 to P17/ANI7

Input

Connect to V

or V

P20/RxD1/SI1

10-K

P21/TxD1/SO1

10-L

P22/ASCK1/SCK1

10-K

P23/PCL

P24/BUZ

10-L

P25/SI0/SDA0

Note 1

10-K

P26/SO0

10-L

P27/SCK0/SCL0

Note 1

10-K

P30/TO0 to P32/TO2

12-E

P33/TI1, P34/TI2

8-N

P35/TI00, P36/TI01

10-M

P37/EXA

Note 2

12-E

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

5-A

P70/RxD2/SI2

8-N

P71/TxD2/SO2

10-M

P72/ASCK2/SCK2

8-N

P80/A0 to P87/A7

12-E

P90 to P95

13-D

P100/TI5/TO5

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

8-N

P120/RTP0 to P127/RTP7

12-E

P130/ANO0, P131/ANO1

12-F

I/O

Input:

Independently connect to V

via a resistor

Output: Leave open

Notes 1. This function is available in

PD784216AY/784218AY Subseries products only.

2. This function is available in

PD784218A, 784218AY Subseries products only.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 MB can be accessed. Mapping of the internal data area (special function registers and

internal RAM) can be specified by the LOCATION instruction. The LOCATION instruction must always be executed

after reset cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

·
·
·
·

Internal memory

The internal data area and internal ROM area are mapped as follows.

Part Number

Internal Data Area

Internal ROM Area

PD784214A,

PD784214AY

0F100H to 0FFFFH

00000H to 0F0FFH

10000H to 17FFFH

PD784215A,

PD784215AY

0EB00H to 0FFFFH

00000H to 0EAFFH

10000H to 1FFFFH

PD784216A,

PD784216AY

0DF00H to 0FFFFH

00000H to 0DEFFH

10000H to 1FFFFH

PD784217A,

PD784217AY

00000H to 0CCFFH

10000H to 2FFFFH

PD784218A,

PD784218AY

0CD00H to 0FFFFH

00000H to 0CCFFH

10000H to 3FFFFH

Caution The following areas that overlap the internal data area of the internal ROM cannot be used

when the LOCATION 0H instruction is executed.

Part Number

Unusable Area

PD784214A,

PD784214AY

0F100H to 0FFFFH (3,840 bytes)

PD784215A,

PD784215AY

0EB00H to 0FFFFH (5,376 bytes)

PD784216A,

PD784216AY

0DF00H to 0FFFFH (8,448 bytes)

PD784217A,

PD784217AY

PD784218A,

PD784218AY

0CD00H to 0FFFFH (13,056 bytes)

·
·
·
·

External memory

The external memory is accessed in external memory expansion mode.

ta S

heet U

14121E

J2V

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 6-1. Memory Map of

µ
µ
µ
µ

PD784214A, 784214AY

Internal ROM
(61,696 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM
(3,584 bytes)

External memory

Note 1

(928 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(3,072 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(3,584 bytes)

External memory

Note 1

(980,736 bytes)

(256 bytes)

Internal ROM
(96 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Note 2

Internal ROM

(32,768 bytes)

Notes 1. Accessed in external memory expansion mode.

2. This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

ta S

heet U

14121E

J2V

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 6-2. Memory Map of

µ
µ
µ
µ

PD784215A, 784215AY

Internal ROM
(60,160 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM
(5,120 bytes)

External memory

Note 1

(896 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(4,608 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(5,120 bytes)

External memory

Note 1

(912,128 bytes)

(256 bytes)

Internal ROM
(128 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM
(65,536 bytes)

Note 2

Notes 1. Accessed in external memory expansion mode.

2. This 5,376-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 125,696 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

ta S

heet U

14121E

J2V

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 6-3. Memory Map of

µ
µ
µ
µ

PD784216A,

784216AY

Internal ROM
(57,088 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM
(8,192 bytes)

External memory

Note 1

(896 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(7,680 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(8,192 bytes)

External memory

Note 1

(909,056 bytes)

(256 bytes)

Internal ROM
(128 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM
(65,536 bytes)

Note 2

Notes 1. Accessed in external memory expansion mode.

2. This 8,448-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 122,624 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

ta S

heet U

14121E

J2V

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 6- 4. Memory Map of

µ
µ
µ
µ

PD784217A, 784217AY

Notes 1. Accessed in external memory expansion mode.

2. This 13,056-byte area can be used as internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 183,552 bytes, on execution of LOCATION 0FH instruction: 196,608 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Internal ROM
(52,480 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM
(12,800 bytes)

External memory

Note 1

(928 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(12,288 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(12,800 bytes)

External memory

Note 1

(838,912 bytes)

(256 bytes)

Internal ROM
(192 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Note 2

Internal ROM

(32,768 bytes)

ta S

heet U

14121E

J2V

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 6-5. Memory Map of

µ
µ
µ
µ

PD784218A, 784218AY

Notes 1. Accessed in external memory expansion mode.

2. This 13,056-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0H instruction: 249,088 bytes, on execution of LOCATION 0FH instruction: 262,144 bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Internal ROM
(52,480 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM
(12,800 bytes)

External memory

Note 1

(768 KB)

Note 1

General-purpose
registers (128 bytes)

Macro service control word
area (54 bytes)

Data area (512 bytes)

Program/data area
(12,288 bytes)

CALLF entry
area (2 KB)

Program/data area

Note 3

CALLT table
area (64 bytes)

Vector table area
(64 bytes)

Internal RAM
(12,800 bytes)

External memory

Note 1

(773,376 bytes)

(256 bytes)

Internal ROM
(256 KB)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM
(196,608 bytes)

Note 2

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can also be used in pairs as a 16-bit

bit address specification registers.

Eight banks of these register sets are available and can be selected by using software or the context switching

function.

The general-purpose registers except the V, U, T, and W registers for address expansion are mapped to the

internal RAM.

Figure 6-6. General-Purpose Register Format

Caution Registers R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for

recycling the program of the 78K/III Series.

A (R1)

B (R3)

R11

D (R13)

H (R15)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

X (R0)

C (R2)

R10

E (R12)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

Names in parentheses indicate absolute names.

8 banks

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2.2 Control registers

(1) Program counter (PC)

The program counter is a 20-bit register whose contents are automatically updated when the program is

executed.

Figure 6-7. Format of Program Counter (PC)

(2) Program status word (PSW)

This register holds the statuses of the CPU. Its contents are automatically updated when the program is

executed.

Figure 6-8. Format of Program Status Word (PSW)

Note This flag is provided to maintain compatibility with the 78K/III Series. Be sure to clear this flag to 0,

except when the software for the 78K/III Series is used.

(3) Stack pointer (SP)

This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the higher 4 bits of this

pointer.

Figure 6-9. Format of Stack Pointer (SP)

RBS2

RBS1

RBS0

PSWH

RSS

Note

P/V

PSWL

PSW

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are assigned. These registers are mapped to the 256-byte space

of addresses 0FF00H to 0FFFFH

Note

Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH

instruction.

Caution Do not access an address in this area to which no SFR is assigned. If such an address is

accessed by mistake, the

µ
µ
µ
µ

PD784218A may enter a deadlocked state. This deadlock state can be

cleared only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows.

Symbol ................................ Symbol indicating an SFR. This symbol is reserved for NEC's assembler

(RA78K4). It can be used as an sfr variable by means of the #pragma sfr command

in the C compiler (CC78K4).

R/W ..................................... Indicates whether the SFR is read-only, write-only, or read/write.

R/W: Read/write

R: Read-only

W: Write-only

Bit units for manipulation ..... Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the operand sfrp

of an instruction. To specify the address of this SFR, describe an even address.

SFRs that can be manipulated in 1-bit units can be described as the operand of a

bit manipulation instruction.

After reset ............................ Indicates the status of the register when the RESET signal has been input.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 6-1. Special Function Register (SFR) List (1/4)

Bit Units for Manipulation

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

1 Bit

8 Bits

16 Bits

After Reset

0FF00H

Port 0

R/W

0FF01H

Port 1

0FF02H

Port 2

0FF03H

Port 3

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

0FF07H

Port 7

0FF08H

Port 8

0FF09H

Port 9

0FF0AH

Port 10

P10

0FF0CH

Port 12

P12

0FF0DH

Port 13

P13

R/W

00H

Note 2

0FF10H

0FF11H

16-bit timer counter

TM0

0FF12H

0FF13H

Capture/compare register 00

(16-bit timer/event counter)

CR00

0FF14H

0FF15H

Capture/compare register 01

(16-bit timer/event counter)

CR01

0000H

0FF16H

Capture/compare control register 0

CRC0

0FF18H

16-bit timer mode control register

TMC0

0FF1AH

16-bit timer output control register

TOC0

0FF1CH

Prescaler mode register 0

PRM0

00H

0FF20H

Port 0 mode register

PM0

0FF22H

Port 2 mode register

PM2

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF27H

Port 7 mode register

PM7

0FF28H

Port 8 mode register

PM8

0FF29H

Port 9 mode register

PM9

0FF2AH

Port 10 mode register

PM10

0FF2CH

Port 12 mode register

PM12

0FF2DH

Port 13 mode register

PM13

R/W

FFH

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION

0FH instruction is executed.

2. Because each port is initialized to input mode after reset, "00H" is not actually read. The output latch is

initialized to "0".

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 6-1. Special Function Register (SFR) List (2/4)

Bit Units for Manipulation

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

1 Bit

8 Bits

16 Bits

After Reset

0FF30H

Pull-up resistor option register 0

PU0

0FF32H

Pull-up resistor option register 2

PU2

0FF33H

Pull-up resistor option register 3

PU3

0FF37H

Pull-up resistor option register 7

PU7

0FF38H

Pull-up resistor option register 8

PU8

0FF3AH

Pull-up resistor option register 10

PU10

0FF3CH

Pull-up resistor option register 12

PU12

0FF40H

Clock output control register

CKS

0FF42H

Port function control register

PF2

0FF4EH

Pull-up resistor option register

PUO

R/W

00H

0FF50H

8-bit timer counter 1

TM1

0FF51H

8-bit timer counter 2

TM2

TM1W

0FF52H

Compare register 10 (8-bit timer/event counter 1) CR10

0FF53H

Compare register 20 (8-bit timer/event counter 2) CR20

CR1W

0FF54H

8-bit timer mode control register 1

TMC1

0FF55H

8-bit timer mode control register 2

TMC2

TMC1W

0FF56H

Prescaler mode register 1

PRM1

0FF57H

Prescaler mode register 2

PRM2

PRM1W

R/W

0FF60H

8-bit timer counter 5

TM5

0FF61H

8-bit timer counter 6

TM6

TM5W

0FF62H

8-bit timer counter 7

TM7

0FF63H

8-bit timer counter 8

TM8

TM7W

0FF64H

Compare register 50 (8-bit timer/event counter 5) CR50

0FF65H

Compare register 60 (8-bit timer/event counter 6) CR60

CR5W

0FF66H

Compare register 70 (8-bit timer/event counter 7) CR70

0FF67H

Compare register 80 (8-bit timer/event counter 8) CR80

CR7W

0FF68H

8-bit timer mode control register 5

TMC5

0FF69H

8-bit timer mode control register 6

TMC6

TMC5W

0FF6AH

8-bit timer mode control register 7

TMC7

0FF6BH

8-bit timer mode control register 8

TMC8

TMC7W

0FF6CH

Prescaler mode register 5

PRM5

0FF6DH

Prescaler mode register 6

PRM6

PRM5W

0FF6EH

Prescaler mode register 7

PRM7

0FF6FH

Prescaler mode register 8

PRM8

PRM7W

0000H

0FF70H

Asynchronous serial interface mode register 1

ASIM1

0FF71H

Asynchronous serial interface mode register 2

ASIM2

R/W

0FF72H

Asynchronous serial interface status register 1

ASIS1

0FF73H

Asynchronous serial interface status register 2

ASIS2

00H

Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 6-1. Special Function Register (SFR) List (3/4)

Bit Units for Manipulation

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

1 Bit

8 Bits

16 Bits

After Reset

Transmit shift register 1

TXS1

0FF74H

Receive buffer register 1

RXB1

Transmit shift register 2

TXS2

0FF75H

Receive buffer register 2

RXB2

FFH

0FF76H

Baud rate generator control register 1

BRGC1

0FF77H

Baud rate generator control register 2

BRGC2

0FF7AH

Oscillation mode select register

0FF80H

A/D converter mode register

ADM

0FF81H

A/D converter input select register

ADIS

R/W

00H

0FF83H

A/D conversion result register

ADCR

Undefined

0FF84H

D/A conversion value setting register 0

DACS0

0FF85H

D/A conversion value setting register 1

DACS1

0FF86H

D/A converter mode register 0

DAM0

0FF87H

D/A converter mode register 1

DAM1

0FF8CH

External bus type select register

EBTS

0FF90H

Serial operation mode register 0

CSIM0

0FF91H

Serial operation mode register 1

CSIM1

0FF92H

Serial operation mode register 2

CSIM2

0FF94H

Serial I/O shift register 0

SIO0

0FF95H

Serial I/O shift register 1

SIO1

0FF96H

Serial I/O shift register 2

SIO2

0FF98H

Real-time output buffer register L

RTBL

0FF99H

Real-time output buffer register H

RTBH

0FF9AH

Real-time output port mode register

RTPM

0FF9BH

Real-time output port control register

RTPC

0FF9CH

Watch timer mode control register

WTM

0FFA0H

External interrupt rising edge enable register

EGP0

0FFA2H

External interrupt falling edge enable register

EGN0

R/W

0FFA8H

In-service priority register

ISPR

0FFA9H

Interrupt select control register

SNMI

00H

0FFAAH

Interrupt mode control register

IMC

80H

0FFACH

Interrupt mask flag register 0L

MK0L

0FFADH

Interrupt mask flag register 0H

MK0H

MK0

0FFAEH

Interrupt mask flag register 1L

MK1L

0FFAFH

Interrupt mask flag register 1H

MK1H

MK1

FFFFH

0FFB0H

C bus control register

Note 2

IICC0

0FFB2H

Prescaler mode register for serial clock

SPRM0

0FFB4H

Slave address register

SVA0

R/W

00H

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION

0FH instruction is executed.

PD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 6-1. Special Function Register (SFR) List (4/4)

Bit Units for Manipulation

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

1 Bit

8 Bits

16 Bits

After Reset

0FFB6H

C bus status register

Note 2

IICS0

0FFB8H

Serial shift register

IIC0

00H

0FFC0H

Standby control register

STBC

30H

0FFC2H

Watchdog timer mode register

WDM

00H

0FFC4H

Memory expansion mode register

20H

0FFC7H

Programmable wait control register 1

PWC1

R/W

AAH

0FFCEH

Clock status register

PCS

32H

0FFCFH

Oscillation stabilization time specification register

OSTS

00H

0FFD0H to

0FFDFH

External SFR area

0FFE0H

Interrupt control register (INTWDTM)

WDTIC

0FFE1H

Interrupt control register (INTP0)

PIC0

0FFE2H

Interrupt control register (INTP1)

PIC1

0FFE3H

Interrupt control register (INTP2)

PIC2

0FFE4H

Interrupt control register (INTP3)

PIC3

0FFE5H

Interrupt control register (INTP4)

PIC4

0FFE6H

Interrupt control register (INTP5)

PIC5

0FFE7H

Interrupt control register (INTP6)

PIC6

0FFE8H

Interrupt control register (INTIIC0/INTCSI0)

CSIIC0

0FFE9H

Interrupt control register (INTSER1)

SERIC1

0FFEAH

Interrupt control register (INTSR1/INTCSI1)

SRIC1

0FFEBH

Interrupt control register (INTST1)

STIC1

0FFECH

Interrupt control register (INTSER2)

SERIC2

0FFEDH

Interrupt control register (INTSR2/INTCSI2)

SRIC2

0FFEEH

Interrupt control register (INTST2)

STIC2

0FFEFH

Interrupt control register (INTTM3)

TMIC3

0FFF0H

Interrupt control register (INTTM00)

TMIC00

0FFF1H

Interrupt control register (INTTM01)

TMIC01

0FFF2H

Interrupt control register (INTTM1)

TMIC1

0FFF3H

Interrupt control register (INTTM2)

TMIC2

0FFF4H

Interrupt control register (INTAD)

ADIC

0FFF5H

Interrupt control register (INTTM5)

TMIC5

0FFF6H

Interrupt control register (INTTM6)

TMIC6

0FFF7H

Interrupt control register (INTTM7)

TMIC7

0FFF8H

Interrupt control register (INTTM8)

TMIC8

0FFF9H

Interrupt control register (INTWT)

WTIC

0FFFAH

Interrupt control register (INTKR)

KRIC

R/W

43H

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION

0FH instruction is executed.

PD784216AY/784218AY Subseries only

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 7-1. Port Functions

Port Name

Pin Name

Function

Specification of Pull-up Resistor

Connection by Software

Port 0

P00 to P06

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 1

P10 to P17

Input port

Port 2

P20 to P27

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 3

P30 to P37

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 4

P40 to P47

Input/output can be specified in 1-bit units

LEDs can be driven directly

Can be specified in 1-port units

Port 5

P50 to P57

Input/output can be specified in 1-bit units

LEDs can be driven directly

Can be specified in 1-port units

Port 6

P60 to P67

Input/output can be specified in 1-bit units

Can be specified in 1-port units

Port 7

P70 to P72

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 8

P80 to P87

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 9

P90 to P95

N-ch open-drain I/O port

Input/output can be specified in 1-bit units

LEDs can be driven directly

Port 10

P100 to P103

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 12

P120 to P127

Input/output can be specified in 1-bit units

Can be specified in 1-bit units

Port 13

P130, P131

Input/output can be specified in 1-bit units

7.2 Clock Generator

An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider. If

high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider to

reduce the current consumption.

Figure 7-2. Block Diagram of Clock Generator

XT2

XT1

STOP or bit 2 (MCK)
of the standby control
register (STBC) is set
to 1 when the subclock
is selected as the CPU
clock

Main system

clock

oscillator

Subsystem

clock

oscillator

Watch timer,
clock output function

Clock to
peripheral hardware

CPU
clock
(f

CPU

)

Frequency

divider

IDLE

controller

Prescaler

STOP, IDLE

controller

HALT

controller

Selector

Internal system
clock
(f

CLK

)

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 7-3. Example of Using Main System Clock Oscillator

Figure 7-4. Example of Using Subsystem Clock Oscillator

Caution

When using the main system clock and subsystem clock oscillator, wire as follows in the area

enclosed by the broken lines in Figures 7-3 and 7-4 to avoid an adverse effect from wiring

capacitance.

·
·
·
·

Keep the wiring length as short as possible.

·
·
·
·

Do not cross the wiring with other signal lines.

·
·
·
·

Do not route the wiring near a signal line through which a high fluctuating current flows.

·
·
·
·

Always make the ground point of the oscillator capacitor the same potential as V

. Do not

ground the capacitor to a ground pattern through which a high current flows.

·
·
·
·

Do not fetch signals from the oscillator.

Note that the subsystem clock oscillator has a low amplification factor to reduce the current

consumption.

External
clock

PD74HCU04

Crystal resonator
or
ceramic resonator

(1) Crystal/ceramic oscillation

(2) External clock

32.768

kHz

XT2

XT1

XT2

XT1

External
clock

PD74HCU04

(1) Crystal oscillation

(2) External clock

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.3 Real-Time Output Port

The real-time output function is to transfer data set in advance to the real-time output buffer register to the output

latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device.

The pins that output the data to the external device constitute a port called a real-time output port.

Because the real-time output port can output signals without jitter, it is ideal for controlling a stepper motor.

Figure 7-5. Block Diagram of Real-Time Output Port

Internal bus

RTPOE

BYTE

EXTR

Output trigger

Controller

Real-time output port
control register (RTPC)

Real-time output

port mode register

(RTPM)

Real-time output port output latch

RTP7······································ RTP0

High-order 4 bits of

real-time output

buffer register

(RTBH)

Low-order 4 bits of

real-time output

buffer register

(RTBL)

INTP2TRG

INTTM1

INTTM2

Port 12 output latch

P127······································ P120

P12n/RTPn pin output (n = 0 to 7)

P127/ P120/
RTP7 RTP0

······································

RTPOE bit

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.4 Timer/Event Counter

One unit of 16-bit timer/event counter and six 8-bit timer/event counters are provided.

Because a total of eight interrupt requests are supported, these timer/event counters can be used as eight

timer/counters.

Table 7-2. Operations of Timers

Name

Item

16-Bit

Timer/

Event

Counter

8-Bit

Timer/

Event

Counter 1

8-Bit

Timer/

Event

Counter 2

8-Bit

Timer/

Event

Counter 5

8-Bit

Timer/

Event

Counter 6

8-Bit

Timer/

Event

Counter 7

8-Bit

Timer/

Event

Counter 8

8 bits

Count width

16 bits

Interval timer

1 ch

Operation mode

External event counter

Timer output

1 ch

PPG output

PWM output

Square wave output

One-shot pulse output

Pulse width measurement

2 inputs

Function

Number of interrupt requests

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 7-6. Block Diagram of Timer/Event Counters

16-bit timer/event counter

8-bit timer/event counter 1, 5, 7

Remarks 1. n = 1, 5, 7

2. OVF: Overflow flag

8-bit timer/event counter 2, 6, 8

Remarks 1. n = 2, 6, 8

2. OVF: Overflow flag

/16

INTTM3

TI01

TI00

Edge

detector

Edge

detector

16-bit timer counter (TM0)

16-bit capture/compare register 00

(CR00)

16-bit capture/compare register 01

(CR01)

Clear

INTTM00

INTTM01

TO0

Selector

Output controller

TIn

8-bit timer counter n

(TMn)

8-bit compare register n0

(CRn0)

Clear

OVF

INTTMn + 1

INTTMn

TOn

Edge

detector

Output

controller

Selector

TIn

TMn 1

8-bit timer counter n

(TMn)

8-bit compare register n0

(CRn0)

Clear

OVF

INTTMn

TOn

Edge detector

Output

controller

Selector

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.5 A/D Converter

An A/D converter converts an analog signal input into a digital signal. This microcontroller is provided with an A/D

converter with a resolution of 8 bits and eight channels (ANI0 to ANI7).

This A/D converter is of successive approximation type and the result of conversion is stored in an 8-bit A/D

conversion result register (ADCR).

The A/D converter can be started in the following two ways:

Hardware start

Conversion is started by trigger input (P03).

Software start

Conversion is started by setting the A/D converter mode register (ADM).

One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started by

means of hardware start, conversion is stopped after it has been completed. When conversion is started by means

of software start, A/D conversion is repeatedly executed. Each time conversion has been completed, an interrupt

request (INTAD) is generated.

Figure 7-7. Block Diagram of A/D Converter

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Sample & hold circuit

Series resistor string

Voltage comparator

Successive approximation

A/D conversion result register

(ADCR)

Controller

Edge

detector

INTP3/P03

INTAD

INTP3

REF0

Internal bus

Selector

Tap selector

Edge

detector

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.7 Serial Interface

Three independent serial interface channels are provided.

Asynchronous serial interface (UART)/3-wire serial I/O (IOE)

Clocked serial interface (CSI)

3-wire serial I/O (IOE)

C bus interface (I

C) (

PD784216AY/784218AY Subseries only)

Therefore, communication with an external system and local communication within the system can be

simultaneously executed (refer to Figure 7-9).

Figure 7-9. Example of Serial Interface

(a) UART + I

(b)

[UART]

RS-232-C

driver/receiver

RxD1

TxD1

RS-232-C

driver/receiver

Port

RxD2

TxD2

Port

SDA0

SCL0

SDA

SCL

SDA

SCL

LCD

PD4711A

PD784218AY (master)

PD780078Y (slave)

PD780308Y (slave)

(b) UART + 3-wire serial I/O

PD784218AY (master)

RS-232-C

driver/receiver

[UART]

Port

RxD2

TxD2

PD753106 (slave)

SCK

Port

INT

[3-wire serial I/O]

Note

SO1

SI1

SCK1

INTPm

Port

PD4711A

Note Handshake

line

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces for which an asynchronous serial interface mode and a 3-wire serial I/O mode

can be selected are provided.

(1) Asynchronous serial interface mode

In this mode, data of 1 byte following the start bit is transmitted or received.

Because an on-chip baud rate generator is provided, a wide range of baud rates can be set.

Moreover, the clock input to the ASCK pin can be divided to define a baud rate.

When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can also be

obtained.

Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode

Internal bus

Receive buffer register

1, 2 (RXB1, RXB2)

Receive shift register

1, 2 (RX1, RX2)

Transmit shift register

1, 2 (TXS1, TXS2)

Receive control

parity check

Transmit control

parity addition

5-bit counter

2 transmit/

receive clock generation

RxD1, RxD2

TxD1, TxD2

ASCK1, ASCK2

Baud rate generator

INTSR1,
INTSR2

INTST1,
INTST2

Selector

to f

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

(2) I

C bus (Inter IC) bus mode (supporting multimaster) (

µ
µ
µ
µ

PD784216AY/784218AY Subseries only)

This mode is for communication with devices conforming to the I

C bus format.

This mode is for transferring 8-bit data between two or more devices by using two lines: serial clock (SCL0)

and serial data bus (SDA0) lines.

During transmission, a "start condition", "data", and "stop condition" can be output onto the serial data bus.

During reception, these data are automatically detected by hardware.

Figure 7-13. Block Diagram of I

C Bus Mode

Internal bus

Direction controller

Slave address register

(SVA0)

SDA0

SCL0

Serial I/O shift

Output latch

Wake-up

controller

Start condition/acknowledge

detector

Stop condition

detector

Serial clock counter

Serial clock

controller

Acknowledge

generator

Interrupt

generator

Selector

INTIIC0

TO2/18 to TO2/68

/24 to f

/178

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

7.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP6) are used not only to input interrupt requests

but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input

signal, they have a function to detect an edge. Moreover, a noise elimination function is also provided to prevent

erroneous detection due to noise.

Pin Name

Detectable Edge

Noise Elimination

NMI

By analog delay

INTP0 to INTP6

Either or both of rising and falling edges

7.11 Watch Timer

The watch timer has the following functions:

Watch timer

Interval timer

The watch timer and interval timer functions can be used at the same time.

(1) Watch timer

The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds by

using the 32.768 kHz subsystem clock.

(2) Interval timer

The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.

Figure 7-16. Block Diagram of Watch Timer

Prescaler

5-bit counter

INTWT

INTTM3

To 16-bit timer/counter

Selector

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8. INTERRUPT FUNCTIONS

The three types of interrupt request servicing shown in Table 8-1 can be selected by program.

Table 8-1. Servicing of Interrupt Request

Servicing Mode

Entity of Servicing

Servicing

Contents of PC and PSW

Vectored interrupt

Branches and executes servicing routine

(servicing is arbitrary)

Saves to and restores from

stack

Context switching

Software

Automatically switches register bank,

branches and executes servicing routine

(servicing is arbitrary)

Saves to or restores from

fixed area in register bank

Macro service

Firmware

Executes data transfer between memory

and I/O (servicing is fixed)

Retained

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 29 types of sources,

execution of the BRK instruction, BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt

servicing and so that which of the two or more interrupts that simultaneously occur should be serviced first can be

determined. When the macro service function is used, however, nesting always proceeds.

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having

the same priority, are simultaneously generated (refer to Table 8-2).

Table 8-2. Interrupt Sources (1/2)

Source

Type

Default

Priority

Name

Trigger

Internal/

External

Macro

Service

BRK instruction

Instruction execution

BRKCS instruction

Instruction execution

Software

Operand error

If result of exclusive OR between operands byte

and byte is not FFH when "MOV STBC, #byte"

instruction, "MOV WDM, #byte" instruction, or

LOCATION instruction is executed

NMI

Pin input edge detection

External

Non-maskable

INTWDT

Overflow of watchdog timer

Internal

0 (highest)

INTWDTM

Overflow of watchdog timer

Internal

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

Pin input edge detection

External

INTIIC0

End of I

C bus transfer by CSI0

INTCSI0

End of 3-wire transfer by CSI0

Maskable

INTSER1

Occurrence of UART reception error in ASI1

Internal

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 8-2. Interrupt Sources (2/2)

Source

Type

Default

Priority

Name

Trigger

Internal/

External

Macro

Service

INTSR1

End of UART reception by ASI1

INTCSI1

End of 3-wire transfer by CSI1

INTST1

End of UART transmission by ASI1

INTSER2

Occurrence of UART reception error in ASI2

INTSR2

End of UART reception by ASI2

INTCSI2

End of 3-wire transfer by CSI2

INTST2

End of UART transmission by ASI2

INTTM3

Reference time interval signal from watch timer

INTTM00

Signal indicating match between 16-bit timer

counter and capture/compare register (CR00)

INTTM01

Signal indicating match between 16-bit timer

counter and capture/compare register (CR01)

INTTM1

Occurrence of match signal of 8-bit timer/event

counter 1

INTTM2

Occurrence of match signal of 8-bit timer/event

counter 2

INTAD

End of conversion by A/D converter

INTTM5

Occurrence of match signal of 8-bit timer/event

counter 5

INTTM6

Occurrence of match signal of 8-bit timer/event

counter 6

INTTM7

Occurrence of match signal of 8-bit timer/event

counter 7

INTTM8

Occurrence of match signal of 8-bit timer/event

counter 8

INTWT

Overflow of watch timer

Internal

Maskable

26 (lowest)

INTKR

Detection of falling edge of port 8

External

Remarks 1. ASI: Asynchronous Serial Interface

CSI: Clocked Serial Interface

2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and

maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.2 Vectored Interrupt

Execution branches to a servicing routine by using the memory contents of a vector table address corresponding

to the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

On branching: Saves the status of the CPU (contents of PC and PSW) to stack

On returning: Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used.

The branch destination address is in a range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt Source

Vector Table Address

Interrupt Source

Vector Table Address

BRK instruction

003EH

INTST1

001CH

TRAP0 (operand error)

003CH

INTSER2

001EH

NMI

0002H

INSR2

INTWDT (non-maskable)

0004H

INTCSI2

0020H

INTWDTM (maskable)

0006H

INTST2

0022H

INTP0

0008H

INTTM3

0024H

INTP1

000AH

INTTM00

0026H

INTP2

000CH

INTTM01

0028H

INTP3

000EH

INTTM1

002AH

INTP4

0010H

INTTM2

002CH

INTP5

0012H

INTAD

002EH

INTP6

0014H

INTTM5

0030H

INTIIC0

INTTM6

0032H

INTCSI0

0016H

INTTM7

0034H

INTSER1

0018H

INTTM8

0036H

INTSR1

INTWT

0038H

INTCSI1

001AH

INTKR

003AH

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

8.5 Application Example of Macro Service

(1) Serial interface transmission

Each time macro service requests INTST1 and INTST2 are generated, the next transmit data is transferred

from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the

transmit data storage buffer has become empty), vectored interrupt requests INTST1 and INTST2 are

generated.

(2) Serial interface reception

Each time macro service requests INTSR1 and INTSR2 are generated, the receive data is transferred from

RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data

storage buffer has become full), vectored interrupt requests INTSR1 and INTSR2 are generated.

Transmit data storage buffer (memory)

Data n

Data n 1

Data 1

Data 2

Internal bus

Transmit shift register

TXS1, TXS2 (SFR)

Transmit control

TxD1, TxD2

INTST1, INTST2

Receive data storage buffer (memory)

Data n

Data n 1

Data 1

Data 2

Internal bus

Receive shift register

RXB1, RXB2 (SFR)

Receive control

INTSR1, INTSR2

RxD1, RxD2

Receive buffer register

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

9.1 Memory Expansion

External program memory and data memory can be connected in two stages: 256 KB and 1 MB.

To connect the external memory, ports 4 through 6 and port 8 are used.

The external memory can be connected in the following two modes:

Multiplexed bus mode: The external memory is connected by using a time-division address/data bus. The

number of ports used when the external memory is connected can be reduced in this

mode.

Separate bus mode:

The external memory is connected by using an address bus and data bus independent

of each other. Because an external latch circuit is not necessary, this mode is useful for

reducing the number of components and mounting area on the printed wiring board.

9.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active.

In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address

decode time.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

10. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

HALT mode:

Stops supply of the operating clock to the CPU. This mode is used in

combination with the normal operation mode for intermittent operation to

reduce the average power consumption.

IDLE mode:

Stops the entire system except for the oscillator, which continues

operating. The power consumption in this mode is close to that in the

STOP mode.

However, the time required to restore the normal program operation

from this mode is almost the same as that from the HALT mode.

STOP

mode:

Stops the main system clock and thereby stops all the internal

operations of the chip. Consequently, the power consumption is

minimized with only leakage current flowing.

Low power consumption mode:

The main system clock is stopped and the subsystem clock is used as

the system clock. The CPU can operate on the subsystem clock to

reduce the current consumption.

Low power consumption HALT mode: This is a standby function in the low power consumption mode and

stops the operation clock of the CPU, to reduce the power consumption

of the entire system.

Low power consumption IDLE mode: This is a standby function in the low power consumption mode and

stops the entire system except the oscillator, to reduce the power

consumption of the entire system.

These modes are programmable.

The macro service can be started from the HALT mode or low power consumption HALT mode. After macro

service processing is executed, the system returns to the HALT mode again.

The transition of the standby status is shown in Figure 10-1.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Figure 10-1. Standby Function State Transitions

Notes 1. Only unmasked interrupt requests

2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87)

Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby

(HALT mode/STOP mode/IDLE mode).

Wait for

stable

oscillation

Normal

operation

(Main system

clock

operation)

Macro

service

HALT

(Standby)

IDLE

(Standby)

Low power

consumption

mode

(Subsystem

clock operation)

Low

power

consumption

HALT mode

(Standby)

Low power

consumption

IDLE mode

(Standby)

STOP

(Standby)

RESET input

Macro service request

One-time processing ends

Macro service ends

Macro service request

One-time processing ends

Interrupt request

RESET input

HALT set

IDLE set

RESET input

NMI, INTP0 to INTP6 input, INTWT,

key return interrupt

Note 2

NMI, INTP0 to INTP6 input,

INTWT, key return interrupt

Note 2

STOP set

Low power consumption
IDLE mode set

RESET input

Low power

consumption mode set

Return to normal operation

NMI, INTP0 to INTP6 input,
INTWT, key return interrupt

Note 2

Low power consumption HALT mode set

RESET input

Interrupt request

Note 1

Interrupt
request for
masked interrupt

Interrupt
request for
masked
interrupt

RESET input

Macro

service

Macro service request

One-time processing ends

Macro service ends

One-time processing ends

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

11. RESET FUNCTION

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized

(reset). During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the

current consumption of the entire system can be reduced.

When the RESET signal goes high, the reset status is cleared. And after the oscillation stabilization time (84.0 ms

at 12.5 MHz operation) elapses, the contents of the reset vector table are set to the program counter (PC), execution

branches to an address set to the PC, and program execution is started from that branch address. Therefore, the

program can be reset and started from any address.

Figure 11-1. Oscillation of Main System Clock During Reset Period

The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise.

Figure 11-2. Acknowledgement of Reset Signal

Oscillation is unconditionally
stopped during reset period

Oscillation stabilization time

Main system clock
oscillator

CLK

RESET input

Analog delay

Analog
delay

Oscillation
stabilization
time

Time until clock
starts oscillating

RESET input

Internal reset signal

Internal clock

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

12. INSTRUCTION SET

(1) 8-bit instructions (instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,

CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC

Table 12-1. Instruction List by 8-Bit Addressing

Second Operand

First Operand

#byte

saddr

saddr'

sfr

!addr16

!!addr24

mem

[saddrp]

[%saddrg]

PSWL

PSWH

[WHL+]

[WHL

]

None

Note 2

(MOV)

ADD

Note 1

(MOV)

(XCH)

(ADD)

Note 1

MOV

XCH

(ADD)

Note 1

(MOV)

Note 6

(XCH)

Note 6

(ADD)

Notes 1, 6

MOV

(XCH)

(ADD)

Note 1

(MOV)

(XCH)

ADD

Note 1

MOV

XCH

ADD

Note 1

MOV

(MOV)

(XCH)

(ADD)

Note 1

MOV

ADD

Note 1

(MOV)

(XCH)

(ADD)

Note 1

MOV

XCH

ADD

Note 1

MOV

XCH

ADD

Note 1

MOV

XCH

ADD

Note 1

MOV

XCH

ROR

Note 3

MULU

DIVUW

INC

DEC

saddr

MOV

ADD

Note 1

(MOV)

Note 6

(ADD)

Note 1

MOV

ADD

Note 1

MOV

XCH

ADD

Note 1

INC

DEC

DBNZ

sfr

MOV

ADD

Note 1

MOV

(ADD)

Note 1

MOV

ADD

Note 1

PUSH

POP

!addr16

!!addr24

MOV

(MOV)

ADD

Note 1

MOV

mem

[saddrp]

[%saddrg]

MOV

ADD

Note 1

mem3

ROR4

ROL4

PSWL

PSWH

MOV

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

[TDE

]

(MOV)

Note 6

(ADD)

Note 1

MOVM

Note 4

MOVBK

Note 5

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of

MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of

MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

(2) 16-bit instructions (instructions in parentheses are combinations realized by describing AX as rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,

POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 12-2. Instruction List by 16-Bit Addressing

Second Operand

First Operand

#word

rp'

saddrp

saddrp'

sfrp

!addr16

!!addr24

mem

[saddrp]

[%saddrg]

[WHL+]

byte

None

Note 2

(MOVW)

ADDW

Note 1

(MOVW)

(XCHW)

(ADD)

Note 1

(MOVW)

(XCHW)

(ADDW)

Note 1

(MOVW)

Note 3

(XCHW)

Note 3

(ADDW)

Notes 1, 3

MOVW

(XCHW)

(ADDW)

Note 1

(MOVW)

XCHW

MOVW

XCHW

(MOVW)

(XCHW)

MOVW

ADDW

Note 1

(MOVW)

(XCHW)

(ADDW)

Note 1

MOVW

XCHW

ADDW

Note 1

MOVW

XCHW

ADDW

Note 1

MOVW

XCHW

ADDW

Note 1

MOVW

SHRW

SHLW

MULU

Note 4

INCW

DECW

saddrp

MOVW

ADDW

Note 1

(MOVW)

Note 3

(ADDW)

Note 1

MOVW

ADDW

Note 1

MOVW

XCHW

ADDW

Note 1

INCW

DECW

sfrp

MOVW

ADDW

Note 1

MOVW

(ADDW)

Note 1

MOVW

ADDW

Note 1

PUSH

POP

!addr16

!!addr24

MOVW

(MOVW)

MOVW

MOVTBLW

mem

[saddrp]

[%saddrg]

MOVW

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as that of MULW.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

13. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

°
°
°
°

Parameter

Symbol

Conditions

Ratings

Unit

0.3 to +6.5

0.3 to V

+ 0.3

0.3 to V

+ 0.3

REF0

A/D converter reference voltage input

0.3 to V

+ 0.3

Supply voltage

REF1

D/A converter reference voltage input

0.3 to V

+ 0.3

Other than P90 to P95

0.3 to V

+ 0.3

Input voltage

P90 to P95

N-ch open drain

0.3 to +12

Analog input voltage

Analog input pin

0.3 to AV

REF0

+ 0.3

Output voltage

0.3 to V

+ 0.3

Per pin

Total of P2, P4 to P8

Total of P0, P3, P9, P10, P12, P13

Output current, low

Total of all pins

100

Per pin

Output current, high

Total of all pins

Operating ambient

temperature

40 to +85

Storage temperature

stg

65 to +150

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Main System Clock Oscillator Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

12.5

2.7 V

< 4.5 V

6.25

2.0 V

< 2.7 V

3.125

Ceramic

resonator

or crystal

resonator

X1 V

Oscillation frequency

)

1.8 V

< 2.0 V

MHz

4.5 V

5.5 V

12.5

2.7 V

< 4.5 V

6.25

2.0 V

< 2.7 V

3.125

X1 input frequency (f

)

1.8 V

< 2.0 V

MHz

X1 input high-/low-

level width (t

WXH

, t

WXL

)

250

4.5 V

5.5 V

2.7 V

< 4.5 V

2.0 V

< 2.7 V

External

clock

PD74HCU04

X1 input rising/falling

time (t

, t

)

1.8 V

< 2.0 V

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

·
·
·
·

Keep the wiring length as short as possible.

·
·
·
·

Do not cross the wiring with other signal lines.

·
·
·
·

Do not route the wiring near a signal line through which a high fluctuating current flows.

·
·
·
·

Always make the ground point of the oscillator capacitor the same potential as V

·
·
·
·

Do not ground the capacitor to a ground pattern through which a high current flows.

·
·
·
·

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock,

the subsystem clock should be switched back to the main system clock after the oscillation

stabilization time is secured by the program.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Subsystem Clock Oscillator Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Oscillation frequency

)

32.768

kHz

4.5 V

5.5 V

1.2

Crystal

resonator

XT2

XT1

Oscillation

stabilization time

Note

1.8 V

< 4.5 V

XT1 input frequency

)

kHz

External

clock

XT2

XT1

PD74HCU04

XT1 input high-/low-

level width (t

XTH

, t

XTL

)

14.3

15.6

Note Time required to stabilize oscillation after applying supply voltage (V

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

·
·
·
·

Keep the wiring length as short as possible.

·
·
·
·

Do not cross the wiring with other signal lines.

·
·
·
·

Do not route the wiring near a signal line through which a high fluctuating current flows.

·
·
·
·

Always make the ground point of the oscillator capacitor the same potential as V

·
·
·
·

Do not ground the capacitor to a ground pattern through which a high current flows.

·
·
·
·

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V) (1/3)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.2 V

5.5 V

0.3V

IL1

Note 1

1.8 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.2V

IL2

P00 to P06, P20, P22, P33,

P34, P70, P72,

P100 to P103, RESET

1.8 V

< 2.2 V

0.15V

2.2 V

5.5 V

0.3V

IL3

P90 to P95

(N-ch open drain)

1.8 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.3V

IL4

P10 to P17, P130, P131

1.8 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.2V

IL5

X1, X2, XT1, XT2

1.8 V

< 2.2 V

0.1V

2.2 V

5.5 V

0.3V

Input voltage, low

IL6

P25, P27

1.8 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.7V

IH1

Note 1

1.8 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.8V

IH2

P00 to P06, P20, P22, P33,

P34, P70, P72,

P100 to P103, RESET

1.8 V

< 2.2 V

0.85V

2.2 V

5.5 V

0.7V

IH3

P90 to P95

(N-ch open drain)

1.8 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.7V

IH4

P10 to P17, P130, P131

1.8 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.8V

IH5

X1, X2, XT1, XT2

1.8 V

< 2.2 V

0.85V

2.2 V

5.5 V

0.7V

Input voltage, high

IH6

P25, P27

1.8 V

< 2.2 V

0.8V

For pins other than

P40 to P47, P50 to P57,

P90 to P95 I

= 1.6 mA

Note 1

4.5 V

5.5 V

0.4

P40 to P47, P50 to P57

= 8 mA

Note 2

4.5 V

5.5 V

1.0

OL1

P90 to P95 I

= 15 mA

Note 2

4.5 V

5.5 V

0.8

2.0

Output voltage, low

OL2

= 400

Note 2

0.5

1 mA

Note 2

4.5 V

5.5 V

1.0

Output voltage, high

OH1

100

Note 2

0.5

LIL1

Except X1, X2, XT1,
XT2

Input leakage current, low

LIL2

= 0 V

X1, X2, XT1, XT2

LIH1

Except X1, X2, XT1,
XT2

LIH2

= V

X1, X2, XT1, XT2

Input leakage current, high

LIH3

= 12 V (N-ch open drain) P90 to P95

Output leakage current, low

LOL1

OUT

= 0 V

Output leakage current, high

LOH1

OUT

= V

Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127

2. Per pin

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V) (2/3)

(1)

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784214AY, 784215AY, 784216AY

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD1

Operation

mode

= 2 MHz, V

= 2.0 V

10%

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD2

HALT mode

= 2 MHz, V

= 2.0 V

10%

0.3

3.5

= 12.5 MHz, V

= 5.0 V

10%

2.5

= 6 MHz, V

= 3.0 V

10%

0.4

1.3

DD3

IDLE mode

= 2 MHz, V

= 2.0 V

10%

0.2

0.9

= 32 kHz, V

= 5.0 V

10%

200

= 32 kHz, V

= 3.0 V

10%

110

DD4

Operation

mode

Note

= 32 kHz, V

= 2.0 V

10%

100

= 32 kHz, V

= 5.0 V

10%

160

= 32 kHz, V

= 3.0 V

10%

DD5

HALT

mode

Note

= 32 kHz, V

= 2.0 V

10%

= 32 kHz, V

= 5.0 V

10%

150

= 32 kHz, V

= 3.0 V

10%

Supply current

DD6

IDLE

mode

Note

= 32 kHz, V

= 2.0 V

10%

Data retention voltage

DDDR

HALT, IDLE modes

1.8

5.5

= 2.0 V

10%

Data retention current

DDDR

STOP mode

= 5.0 V

10%

Pull-up resistor

= 0 V

100

Note When main system clock is stopped and subsystem clock is operating.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V) (3/3)

(2)

µ
µ
µ
µ

PD784217A, 784218A, 784217AY, 784218AY

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD1

Operation

mode

= 2 MHz, V

= 2.0 V

10%

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD2

HALT mode

= 2 MHz, V

= 2.0 V

10%

0.4

3.5

= 12.5 MHz, V

= 5.0 V

10%

2.5

= 6 MHz, V

= 3.0 V

10%

0.4

1.3

DD3

IDLE mode

= 2 MHz, V

= 2.0 V

10%

0.2

0.9

= 32 kHz, V

= 5.0 V

10%

200

= 32 kHz, V

= 3.0 V

10%

110

DD4

Operation

mode

Note

= 32 kHz, V

= 2.0 V

10%

100

= 32 kHz, V

= 5.0 V

10%

160

= 32 kHz, V

= 3.0 V

10%

DD5

HALT

mode

Note

= 32 kHz, V

= 2.0 V

10%

= 32 kHz, V

= 5.0 V

10%

150

= 32 kHz, V

= 3.0 V

10%

Supply current

DD6

IDLE

mode

Note

= 32 kHz, V

= 2.0 V

10%

Data retention voltage

DDDR

HALT, IDLE modes

1.8

5.5

= 2.0 V

10%

Data retention current

DDDR

STOP mode

= 5.0 V

10%

Pull-up resistor

= 0 V

100

Note When main system clock is stopped and subsystem clock is operating.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

AC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

2.7 V

4.5 V

160

2.0 V

2.7 V

320

Cycle time

CYK

1.8 V

2.0 V

500

= 5.0 V

10%

(0.5

a)T

= 3.0 V

10%

(0.5

a)T

Address setup time (to ASTB

)

SAST

= 2.0 V

10%

(0.5

a)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from ASTB

) t

HSTLA

= 2.0 V

10%

0.5T

= 5.0 V

10%

(0.5

a)T

= 3.0 V

10%

(0.5

a)T

ASTB high-level width

WSTH

= 2.0 V

10%

(0.5

a)T

110

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from RD

)

HRA

= 2.0 V

10%

0.5T

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Delay time from address to RD

DAR

= 2.0 V

10%

a)T

= 5.0 V

10%

= 3.0 V

10%

Address float time (from RD

)

FAR

= 2.0 V

10%

= 5.0 V

10%

(2.5

n)T

= 3.0 V

10%

(2.5

n)T

Data input time from address

DAID

= 2.0 V

10%

(2.5

n)T

120

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Data input time from ASTB

DSTID

= 2.0 V

10%

n)T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Data input time from RD

DRID

= 2.0 V

10%

(1.5

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to RD

DSTR

= 2.0 V

10%

0.5T

= 5.0 V

10%

= 3.0 V

10%

Data hold time (from RD

)

HRID

= 2.0 V

10%

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of waits (n

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

AC Characteristics

(1) Read/write operation (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address active time from RD

DRA

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from RD

to ASTB

DRST

= 2.0 V

10%

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

RD low-level width

WRL

= 2.0 V

10%

(1.5

n)T

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Delay time from address to WR

DAW

= 2.0 V

10%

a)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from WR

)

HRD

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to data

output

DSTOD

= 2.0 V

10%

0.5T

240

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WR

to data

output

DWOD

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to WR

DSTW

= 2.0 V

10%

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Data setup time (to WR

)

SODWR

= 2.0 V

10%

(1.5

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Data hold time (from WR

)

HWOD

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WR

to ASTB

DWST

= 2.0 V

10%

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

WR low-level width

WWL

= 2.0 V

10%

(1.5

n)T

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

AC Characteristics

(2) External wait timing

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Input time from address to

WAIT

DAWT

= 2.0 V

10%

a)T

300

= 5.0 V

10%

1.5T

= 3.0 V

10%

1.5T

Input time from ASTB

WAIT

DSTWT

= 2.0 V

10%

1.5T

260

= 5.0 V

10%

(0.5

n)T

= 3.0 V

10%

(0.5

n)T

Hold time from ASTB

to WAIT

HSTWT

= 2.0 V

10%

(0.5

n)T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Delay time from ASTB

WAIT

DSTWTH

= 2.0 V

10%

(1.5

n)T

= 5.0 V

10%

= 3.0 V

10%

Input time from RD

to WAIT

DRWTL

= 2.0 V

10%

= 5.0 V

10%

= 3.0 V

10%

Hold time from RD

to WAIT

HRWT

= 2.0 V

10%

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Delay time from RD

to WAIT

DRWTH

= 2.0 V

10%

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Data input time from WAIT

DWTID

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WAIT

to RD

DWTR

= 2.0 V

10%

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WAIT

to WR

DWTW

= 2.0 V

10%

0.5T

= 5.0 V

10%

= 3.0 V

10%

Input time from WR

to WAIT

DWWTL

= 2.0 V

10%

= 5.0 V

10%

= 3.0 V

10%

Hold time from WR

to WAIT

HWWT

= 2.0 V

10%

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Delay time from WR

to WAIT

DWWTH

= 2.0 V

10%

n)T

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Serial Operation (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

5.5 V

800

SCK cycle time

KCY1

3,200

2.7 V

5.5 V

350

SCK high-/low-level width

KH1

KL1

1,500

2.7 V

5.5 V

SI setup time (to SCK

)

SIK1

SI hold time (from SCK

)

KSI1

SO output delay time

(from SCK

)

KSO1

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

5.5 V

800

SCK cycle time

KCY2

3,200

2.7 V

5.5 V

400

SCK high-/low-level width

KH2

KL2

1,600

2.7 V

5.5 V

SI setup time (to SCK

)

SIK2

SI hold time (from SCK

)

KSI2

SO output delay time

(from SCK

)

KSO2

(c) UART mode

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

417

2.7 V

< 4.5 V

833

ASCK cycle time

KCY3

1,667

4.5 V

5.5 V

208

2.7 V

< 4.5 V

416

ASCK high-/low-level width

KH3

KL3

833

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

(d) I

C bus mode

Standard Mode

High-Speed Mode

Parameter

Symbol

MIN.

MAX.

MIN.

MAX.

Unit

SCL0 clock frequency

CLK

100

400

kHz

Bus free time (between stop

and start conditions)

BUF

4.7

1.3

Hold time

Note1

HD : STA

4.0

0.6

Low-level width of SCL0 clock

LOW

4.7

1.3

High-level width of SCL0 clock

HIGH

4.0

0.6

Setup time of start/restart

conditions

SU : STA

4.7

0.6

When using CBUS-

compatible master

5.0

Data hold

time

When using I

C bus

HD : DAT

Note 2

0.9

Note 3

Data setup time

SU : DAT

250

100

Note 4

Rise time of SDA0 and SCL0

signals

1,000

20 + 0.1Cb

Note 5

300

Fall time of SDA0 and SCL0

signals

300

20 + 0.1Cb

Note 5

300

Setup time of stop condition

SU : STO

4.0

0.6

Pulse width of spike restricted

by input filter

Load capacitance of each bus

line

400

Notes 1. For the start condition, the first clock pulse is generated after the hold time.

2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

SDA0 signal (on V

IHmin.

) with at least 300 ns of hold time.

3. If the device does not extend the SCL0 signal low-level hold time (t

LOW

), only the maximum data hold

time

HD : DAT

needs to be satisfied.

4. The high-speed mode I

C bus can be used in a standard mode I

C bus system. In this case, the

conditions described below must be satisfied.

If the device does not extend the SCL0 signal low-level hold time

SU : DAT

250 ns

If the device extends the SCL0 signal low-level hold time

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t

Rmax.

+ t

SU :

DAT

= 1,000 + 250 = 1,250 ns by standard mode I

C bus specification)

5. Cb: Total capacitance per bus line (unit: pF)

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Other Operations (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

NMI high-/low-level width

WNIL

WNIH

INTP input high-/low-level width

WITL

WITH

INTP0 to INTP6

100

RESET high-/low-level width

WRSL

WRSH

Clock Output Operation (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

PCL cycle time

CYCL

4.5 V

5.5 V, nT

31,250

PCL high-/low-level width

CLL

CLH

4.5 V

5.5 V, 0.5T

15,615

4.5 V

5.5 V

2.7 V

< 4.5 V

PCL rise/fall time

CLR

CLF

1.8 V

< 2.7 V

Remark T: t

CYK

= 1/f

: Main system clock frequency)

n: Divided frequency ratio set by software in the CPU

When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

When using the subsystem clock: n = 1

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

A/D Converter Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bits

2.7 V

5.5 V

2.2 V

REF0

1.2

%FSR

Overall error

Notes 1, 2

1.8 V

< 2.7 V

1.8 V

REF0

1.6

%FSR

Conversion time

CONV

144

Sampling time

SAMP

24/f

Analog input voltage

IAN

REF0

Reference voltage

REF0

1.8

Resistance between AV

REF0

and AV

AVREF0

When not A/D converting

Notes 1. Quantization error (

1/2 LSB) is not included.

2. Overall error is indicated as a ratio to the full-scale value.

Remark f

: Main system clock frequency

D/A Converter Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

Bits

R = 10 M

, 2.0 V

REF1

2.0 V

5.5 V

0.6

%FSR

Overall error

Notes 1, 2

R = 10 M

, 1.8 V

REF1

1.8 V

2.0 V

1.2

%FSR

4.5 V

REF1

5.5 V

2.7 V

REF1

< 4.5 V

Settling time

Load conditions:

C = 30 pF

1.8 V

REF1

< 2.7 V

Output resistance

DACS0, 1 = 55H

Reference voltage

REF1

1.8

REF1

current

REF1

For only 1 channel

2.5

Notes 1. Quantization error (

1/2 LSB) is not included.

2. Overall error is indicated as a ratio to the full-scale value.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Data Retention Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.8 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention voltage

DDDR

STOP mode

1.8

5.5

DDDR

= 5.0 V

10%

Data retention current

DDDR

= 2.0 V

10%

rise time

RVD

200

fall time

FVD

200

hold time

(from STOP mode setting)

HVD

STOP release signal input time

DREL

Crystal resonator

Oscillation stabilization wait time

WAIT

Ceramic resonator

Low-level input voltage

0.1V

DDDR

High-level input voltage

RESET, P00/INTP0 to P06/INTP6

0.9V

DDDR

AC Timing Test Points

0.8V

or 1.8 V

0.8 V

0.8V

or 1.8 V

0.8 V

Test points

1 V

0.45 V

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

15. RECOMMENDED SOLDERING CONDITIONS

The

PD784218A should be soldered and mounted under the following recommended conditions. For the details

of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology

Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 15-1. Surface Mounting Type Soldering Conditions (1/2)

(1)

µ
µ
µ
µ

PD784214AGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784215AGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784216AGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784217AGC-

×××

-8EU: 100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784218AGC-

×××

-8EU: 100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784214AYGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784215AYGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784216AYGC-

×××

-8EU:100-pin plastic LQFP(fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784217AYGC-

×××

-8EU: 100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14 mm)

µ
µ
µ
µ

PD784218AYGC-

×××

-8EU: 100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or higher),

Count: Two times or less, Exposure limit: 7 days

Note

(after that, prebake at 125

for 10 hours)

IR35-107-2

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or higher),

Count: Two times or less, Exposure limit: 7 days

Note

(after that, prebake at 125

for 10 hours)

VP15-107-2

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Table 15-1. Surface Mounting Type Soldering Conditions (2/2)

(2)

µ
µ
µ
µ

PD784214AGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784215AGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784216AGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784217AGF-

×××

-3BA: 100-pin plastic QFP (14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784218AGF-

×××

-3BA: 100-pin plastic QFP (14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784214AYGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784215AYGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784216AYGF-

×××

-3BA:100-pin plastic QFP(14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784217AYGF-

×××

-3BA: 100-pin plastic QFP (14

×
×
×
×

20 mm)

µ
µ
µ
µ

PD784218AYGF-

×××

-3BA: 100-pin plastic QFP (14

×
×
×
×

20 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or higher),

Count: Two times or less

IR35-00-2

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or higher),

Count: Two times or less

VP15-00-2

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120

C max. (package surface temperature)

WS60-00-1

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD784218A. Also refer to (5)

Cautions on using development tools.

(1) Language processing software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) Flash memory writing tools

Flashpro II

(Model number: FL-PR2),

Flashpro III

(Model number: FL-PR3, PG-FP3)

Dedicated flash programmer for microcontroller incorporating flash memory

FA-100GF

Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be

performed in accordance with the target product.

FA-100GC

Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be

performed in accordance with the target product.

Flashpro II controller,

Flashpro III controller

Control program that runs on a personal computer and is attached to Flashpro II, Flashpro III.

Operates on Windows

95, etc.

(3) Debugging tools

·
·
·
·

When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter required when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-CD-IF-A

PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA

socket supported)

IE-70000-PC-IF-C

Interface adapter required when using IBM PC/AT

compatibles as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter required when using PC that incorporates PCI bus as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784216A, 784216AY, 784218A, 784218AY Subseries

NP-100GF

Emulation probe for 100-pin plastic QFP (GF-3BA type)

NP-100GC

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin

plastic LQFP (GC-8EU type) can be mounted

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

·
·
·
·

When IE-784000-R in-circuit emulator is used

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-C

Interface adapter required when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-PC-IF-C

Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter required when using PC that incorporates PCI bus as host machine

IE-78000-R-SV3

Interface adapter and cable required when EWS is used as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784216A, 784216AY, 784218A, 784218AY Subseries

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX3

Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R.

EP-784218GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EP-78064GC-R

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the EP-78064GC-R and a target system board on which a

100-pin plastic LQFP (GC-8EU type) can be mounted

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

(5) Cautions on using development tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.

The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito

Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).

The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

For further information, contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (TEL: +81-3-3820-7112)

Osaka Electronic Division (TEL: +81-6-6244-6672)

For third party development tools, see the Single-Chip Microcontroller Development Tool Selection Guide

(U11069E).

The host machine and OS suitable for each software are as follows:

EWS

Host Machine

[OS]

Software

PC-9800 series [Windows]

IBM PC/AT and compatibles

[Japanese/English Windows]

HP9000 Series 700

[HP-UX

]

SPARCstation

[SunOS

, Solaris

]

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

Note DOS-based software

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

APPENDIX B. RELATED DOCUMENTS

Documents related to devices

Document No.

Document Name

English

Japanese

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY,

784217AY, 784218AY Data Sheet

This document

U14121J

PD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet

To be prepared

PD784216A, 784216AY Subseries User's Manual Hardware

U13570E

U13570J

PD784218A, 784218AY Subseries User's Manual Hardware

U12970E

U12970J

78K/IV Series User's Manual Instructions

U10905E

U10905J

78K/IV Series Instruction Table

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note Software Basics

U10095J

Documents related to development tools (user's manuals)

Document No.

Document Name

English

Japanese

Language

U11162E

U11162J

RA78K4 Assembler Package

Operation

U11334E

U11334J

RA78K Structured Assembler Preprocessor

U11743E

U11743J

Language

U11571E

U11571J

CC78K4 C Compiler

Operation

U11572E

U11572J

IE-78K4-NS

U13356E

U13356J

IE-784000-R

U12903E

U12903J

IE-784218-R-EM1

U12155E

U12155J

IE-784225-NS-EM1

U13742E

U13742J

EP-78064

EEU-1469

EEU-934

SM78K4 System Simulator Windows Based

Reference

U10093E

U10093J

SM78K Series System Simulator

External Part User Open

Interface Specifications

U10092E

U10092J

ID78K4-NS Integrated Debugger PC Based

Reference

U12796E

U12796J

ID78K4 Integrated Debugger Windows Based

Reference

U10440E

U10440J

ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS based

Reference

U11960E

U11960J

Caution

The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Documents related to embedded software (user's manuals)

Document No.

Document Name

English

Japanese

Fundamental

U10603E

U10603J

Installation

U10604E

U10604J

78K/IV Series Real-Time OS

Debugger

U10364J

78K/IV Series OS MX78K4

Fundamental

U11779J

Other documents

Document No.

Document Name

English

Japanese

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)

X13769X

Semiconductor Device Mounting Technology Manual

C10535E

C10535J

Quality Grades on NEC Semiconductor Devices

C11531E

C11531J

NEC Semiconductor Device Reliability/Quality Control System

C10983E

C10983J

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892E

C11892J

Guide to Microcomputer-Related Products by Third Party

U11416J

Caution

The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet U14121EJ2V0DS00

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829

J00.7

µ
µ
µ
µ

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY, 784218AY

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conforms to the I

C Standard Specification as defined by Philips.

M8E 00. 4

The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

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