Document Outline

Cover
FEATURES
APPLICATION FIELD
ORDERING INFORMATION
78K/IV SERIES LINEUP
FUNCTIONS
1. DIFFERENCES AMONG MODELS IN uPD784225, 784225Y SUBSERIES
2. MAJOR DIFFERENCES BETWEEN uPD784216Y SUBSERIES AND uPD780058Y SUBSERIES
3. PIN CONFIGURATION (Top View)
4. BLOCK DIAGRAM
5. PIN FUNCTION
- 5.1 Port Pins
- 5.2 Pins Other Than Port Pins
- 5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
6. CPU ARCHITECTURE
- 6.1 Memory Space
- 6.2 CPU Registers
  - 6.2.1 General-purpose registers
  - 6.2.2 Control registers
  - 6.2.3 Special function registers (SFRs)
7. PERIPHERAL HARDWARE FUNCTIONS
- 7.1 Ports
- 7.2 Clock Generator
- 7.3 Real-Time Output Port
- 7.4 Timer
- 7.5 A/D Converter
- 7.6 D/A Converter
- 7.7 Serial Interface
  - 7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)
  - 7.7.2 Clocked serial interface (CSI)
- 7.8 Clock Output Function
- 7.9 Buzzer Output Function
- 7.10 Edge Detection Function
- 7.11 Watch Timer
- 7.12 Watchdog Timer
8. INTERRUPT FUNCTION
- 8.1 Interrupt Sources
- 8.2 Vectored Interrupt
- 8.3 Context Switching
- 8.4 Macro Service
- 8.5 Application Example of Macro Service
9. LOCAL BUS INTERFACE
- 9.1 Memory Expansion
- 9.2 Programmable Wait
- 9.3 External Access Status Function
10. STANDBY FUNCTION
11. RESET FUNCTION
12. ROM CORRECTION
13. INSTRUCTION SET
14. ELECTRICAL SPECIFICATIONS
15. PACKAGE DRAWINGS
16. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. DEVELOPMENT TOOLS
APPENDIX B. RELATED DOCUMENTS

DATA SHEET

1997, 2000

MOS INTEGRATED CIRCUIT

PD784224, 784225, 784224Y, 784225Y

16/8-BIT SINGLE-CHIP MICROCONTROLLERS

The

PD784224 and 784225 are products of the

PD784225 Subseries in the 78K/IV Series. Besides a high-

speed and high performance CPU, these controllers have ROM, RAM, I/O ports, 8-bit resolution A/D and D/A

converters, timers, serial interfaces, a real-time output port, interrupt functions, and various other peripheral

hardware.

The

PD784224Y and 784225Y are based on the

PD784225 Subseries with the addition of a multimaster-

supporting I

C bus interface.

Flash memory versions, the

PD78F4225 and 78F4225Y, which replace the internal ROM of the mask ROM

version with flash memory, and various development tools are also available.

The functions are explained in detail in the following user's manuals. Be sure to read this manual when

designing your system.

PD784225, 784225Y Subseries User's Manual - Hardware : U12697E

78K/IV Series User's Manual - Instruction

: U10905E

FEATURES

· I

C bus

· ROM correction

· Inherits peripheral functions of

PD780058Y

Subseries

· Minimum instruction execution time

160 ns (main system clock f

= 12.5 MHz)

s (subsystem clock f

= 32.768 kHz)

· I/O port: 67 pins

· Timer/counter: 16-bit timer/counter

1 unit

8-bit timer/counter

4 units

· Serial interface: 3 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O, multi-master supporting I

bus

Note

): 1 channel

Note

PD784225Y Subseries only

· Standby function

HALT/STOP/IDLE mode

In power-saving mode: HALT/IDLE mode (with

subsystem clock)

· Clock division function

· Watch timer: 1 channel

· Watchdog timer: 1 channel

· Clock output function

, f

/2, f

, f

selectable

· Buzzer output function

, f

selectable

· A/D converter: 8-bit resolution

8 channels

· D/A converter: 8-bit resolution

2 channels

· Supply voltage: V

= 1.8 to 5.5 V

Document No. U12376EJ1V0DS00 (1st edition)
Date Published May 2000 J CP(K)
Printed in Japan

APPLICATION FIELD

Car audio, portable audio, telephones, etc.

Unless contextually excluded, references in this document to

PD784225 mean

PD784224, 784225, 784224Y,

and 784225Y.

The mark shows major revised points.

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced
A/D converter,
16-bit timer, and
power management

Enhanced internal memory capacity
Pin-compatible with the PD784026

Supports I

C bus

Supports multi-master I

C bus

80-pin, ROM correction added

Supports multi-master I

C bus

Enhanced internal memory
capacity, ROM correction added

100-pin, enhanced I/O and
internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

Supports multi-master I

C bus

Enhanced functions
of the PD784915

Standard models

ASSP models

Supports multi-master I

C bus

: In mass production

: Under development

PD784967

On-chip FIP controller/driver

PD784938A

Enhanced functions of the
PD784908, enhanced
internal memory capacity,
ROM correction added.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

FUNCTIONS

Part Number

PD784224,

PD784225,

Item

PD784224Y

PD784225Y

Number of basic instructions

113

(mnemonics)

General-purpose register

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

Minimum instruction execution

· 160 ns/320 ns/640 ns/1,280 ns/2,560 ns (main system clock: f

= 12.5 MHz)

time

· 61

s (subsystem clock: f

= 32.768 kHz)

Internal

ROM

96 Kbytes

128 Kbytes

memory

RAM

3,584 bytes

4,352 bytes

Memory space

1 MB with program and data spaces combined

I/O port

Total

CMOS Input

CMOS I/O

Pins with pull-up

resistor

LEDs direct

drive output

Real-time output port

4 bits

2, or 8 bits

Timer

Timer/event counter

: Timer counter

Pulse output

(16-bit)

Capture/compare register

· PWM/PPG output
· Square wave output
· One-shot pulse output

Timer/event counter 1 : Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer/event counter 2 : Timer counter

Pulse output

(8-bit)

Compare register

· PWM output
· Square wave output

Timer 5

: Timer counter

(8-bit)

Compare register

Timer 6

: Timer counter

(8-bit)

Compare register

Serial interface

· UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
· CSI (3-wire serial I/O, I

C bus

Note 2

supporting multi master): 1 channel

A/D converter

8-bit resolution

8 channels

D/A converter

8-bit resolution

2 channels

Clock output

Selectable from f

, f

/2, f

, f

Buzzer output

Selectable from f

, f

Watch timer

1 channel

Watchdog timer

1 channel

Standby

· HALT/STOP/IDLE mode
· In power-saving mode (with subsystem clock): HALT/IDLE mode

Interrupt

Hardware

25 (internal: 18, external: 7)

Software

BRK instruction, BRKCS instruction, operand error

Non-maskable

Internal: 1, external: 1

Maskable

Internal: 17, external: 6

· 4 programmable priority levels
· 3 service modes: vectored interrupt/macro service/context switching

Supply voltage

= 1.8 to 5.5 V

Package

· 80-pin plastic QFP(14

14 mm)

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

Notes 1. The pins with ancillary functions are included in the I/O pins.

PD784225Y Subseries only

Pins with

ancillary

functions

Note 1

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

CONTENTS

DIFFERENCES AMONG MODELS IN

PD784225, 784225Y SUBSERIES .............................. 7

MAJOR DIFFERENCES BETWEEN

PD784216Y SUBSERIES AND

PD780058Y SUBSERIES ............................................................................................................. 8

PIN CONFIGURATION (Top View) ............................................................................................... 9

BLOCK DIAGRAM ........................................................................................................................ 11

PIN FUNCTION ............................................................................................................................... 12

5.1

Port Pins ................................................................................................................................................ 12

5.2

Pins Other Than Port Pins .................................................................................................................. 14

5.3

I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 16

CPU ARCHITECTURE ................................................................................................................... 20

6.1

Memory Space ...................................................................................................................................... 20

6.2

CPU Registers ...................................................................................................................................... 23

6.2.1

General-purpose registers .......................................................................................................... 23

6.2.2

Control registers .......................................................................................................................... 24

6.2.3

Special function registers (SFRs) ............................................................................................... 25

PERIPHERAL HARDWARE FUNCTIONS .................................................................................... 30

7.1

Ports ....................................................................................................................................................... 30

7.2

Clock Generator ................................................................................................................................... 31

7.3

Real-Time Output Port ......................................................................................................................... 33

7.4

Timer ...................................................................................................................................................... 34

7.5

A/D Converter ....................................................................................................................................... 37

7.6

D/A Converter ....................................................................................................................................... 38

7.7

Serial Interface ..................................................................................................................................... 39

7.7.1

Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 40

7.7.2

Clocked serial interface (CSI) ..................................................................................................... 42

7.8

Clock Output Function ........................................................................................................................ 43

7.9

Buzzer Output Function ...................................................................................................................... 44

7.10 Edge Detection Function .................................................................................................................... 44

7.11 Watch Timer .......................................................................................................................................... 44

7.12 Watchdog Timer ................................................................................................................................... 45

INTERRUPT FUNCTION ................................................................................................................ 46

8.1

Interrupt Sources ................................................................................................................................. 46

8.2

Vectored Interrupt ................................................................................................................................ 48

8.3

Context Switching ................................................................................................................................ 49

8.4

Macro Service ....................................................................................................................................... 49

8.5

Application Example of Macro Service ............................................................................................. 50

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

LOCAL BUS INTERFACE ............................................................................................................. 51

9.1

Memory Expansion .............................................................................................................................. 51

9.2

Programmable Wait ............................................................................................................................. 51

9.3

External Access Status Function ...................................................................................................... 51

10. STANDBY FUNCTION ................................................................................................................... 52

11. RESET FUNCTION ......................................................................................................................... 54

12. ROM CORRECTION ...................................................................................................................... 55

13. INSTRUCTION SET ........................................................................................................................ 56

14. ELECTRICAL SPECIFICATIONS ................................................................................................. 61

15. PACKAGE DRAWINGS ................................................................................................................. 82

16. RECOMMENDED SOLDERING CONDITIONS ............................................................................ 84

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 85

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 88

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

1. DIFFERENCES AMONG MODELS IN

PD784225, 784225Y SUBSERIES

The only difference among the

PD784224 and 784225 lies in the internal memory capacity.

The

PD784224Y and 784225Y are based on the

PD784224 and 784225 respectively, with the addition of an

C bus control function.

The

PD78F4225 and 78F4225Y are provided with a 128-Kbyte flash memory instead of the mask ROM of the

above models. These differences are summarized in Table 1-1.

Table 1-1. Differences among Models in

PD784225, 784225Y Subseries

Part Number

PD784224,

PD784225,

PD78F4225,

Item

PD784224Y

PD784225Y

PD78F4225Y

Internal ROM

96 Kbytes

128 Kbytes

(mask ROM)

(Flash memory)

Internal RAM

3,584 bytes

4,352 bytes

Internal memory

None

Provided

size switching

Note

Supply voltage

= 1.8 to 5.5 V

= 1.9 to 5.5 V

Electrical

Refer to the data sheet for each device.

specifications

Recommended

soldering

conditions

TEST pin

Provided

None

Provided

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

size switching register (IMS).

Caution

There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then

mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the

commercial samples (not engineering samples) of the mask ROM version.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

2. MAJOR DIFFERENCES BETWEEN

PD784216Y SUBSERIES AND

PD780058Y SUBSERIES

Series Name

PD784225, 784225Y

PD784216Y Subseries

PD780058Y Subseries

Item

Subseries

CPU

16-bit CPU

8-bit CPU

Minimum

With main system

160 ns (at 12.5 MHz)

400 ns (at 5.0 MHz)

instruction

clock selected

execution time

With subsystem

s (at 32.768 kHz)

122

s (at 32.768 kHz)

clock

Memory space

1 Mbytes

64 Kbytes

I/O port

Total

67 pins

86 pins

68 pins

CMOS input

8 pins

2 pins

CMOS I/O

59 pins

72 pins

62 pins

N-ch open-drain I/O

6 pins

4 pins

Pins with

Pins with pull-up

57 pins

70 pins

66 pins (flash memory

ancillary

resistor

model: 62 pins)

function

Note 1

LED direct drive

16 pins

22 pins

12 pins

output

Medium-voltage pin

6 pins

4 pins

Timer/counter

· 16-bit timer/event counter

1 unit

· 8-bit timer/event counter

4 units

6 units

2 units

Serial interface

· UART/IOE (3-wire serial I/O)

2 channels

· UART (time-division transfer

· CSI (3-wire serial I/O, multi-master supporting I

function)/IOE (3-wire

bus

Note 2

)

1 channel

serial I/O)

2 channels

· CSI (3-wire serial I/O,

2-wire serial I/O,

C bus)

1 channel

· CSI (3-wire serial I/O

with automatic

transmission/reception

function)

1 channel

Interrupt

NMI pin

Provided

None

Macro service

Provided

None

Context switching

Provided

None

Programmable priority 4 levels

2 levels

Standby function

· HALT/STOP/IDLE mode

HALT/STOP mode

· Power-saving mode: HALT/IDLE Mode

ROM correction

Provided

None

Provided

Package

· 80-pin plastic QFP

· 100-pin plastic QFP

· 80-pin plastic QFP

(14

14 mm)

(fine pitch) (14

14 mm)

(14

14 mm)

· 80-pin plastic TQFP

· 100-pin plastic QFP

· 80-pin plastic TQFP

(fine pitch) (12

12 mm)

(14

20 mm)

(fine pitch) (12

12 mm)

Notes 1. Pins with ancillary function are included in the I/O pins.

PD784225Y and 784216Y Subseries only

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

3. PIN CONFIGURATION (Top View)

· 80-pin plastic QFP (14

14 mm)

PD784224GC-

×××

-8BT,

PD784224YGC-

×××

-8BT,

PD784225GC-

×××

-8BT,

PD784225YGC-

×××

-8BT

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784224GK-

×××

-BE9,

PD784224YGK-

×××

-BE9,

PD784225GK-

×××

-BE9,

PD784225YGK-

×××

-BE9

P15/ANI5

P16/ANI6

P17/ANI7

P130/ANO0

P131/ANO1

REF1

P70/SI2/RxD2

P71/SO2/TxD2

P72/SCK2/ASCK2

P20/SI1/RxD1

P21/SO1/TxD1

P22/SCK1/ASCK1

P23/PCL

P24/BUZ

P25/SI0/SDA0

Note 1

P26/SO0

P27/SCK0/SCL0

Note 1

P40/AD0

P41/AD1

RESET

P127/RTP7

P126/RTP6

P125/RTP5

P124/RTP4

P123/RTP3

P122/RPT2

P121/RTP1

P120/RTP0

P37/EXA

P36/TI01

P35/TI00

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P67/ASTB

P66/WAIT

P65/WR

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

SS1

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

A14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

DD0

XT1

XT2

TEST

Note 2

DD1

SS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2/NMI

P01/INTP1

P00/INTP0

Notes 1. The SCL0 and SDA0 pins are available in

PD784225Y Subseries only.

2. Connect the TEST pin to V

SS0

directly or via a pull-down resistor. For the pull-down connection, use

of a resistor with a resistance ranging from 470

to 10 k

is recommended.

Caution Connect the AV

pin to V

SS0

Remark When using in applications where noise from inside the microcomputer has to be reduced, it is

recommended to take countermeasures against noise such as supplying power to V

DD0

and V

DD1

independently, and connecting V

SS0

and V

SS1

to different ground lines.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

A8 to A19

: Address Bus

AD0 to AD7

: Address/Data Bus

ANI0 to ANI7

: Analog Input

ANO0, ANO1

: Analog Output

ASCK1, ASCK2

: Asynchronous Serial Clock

ASTB

: Address Strobe

: Analog Power Supply

REF1

: Analog Reference Voltage

: Analog Ground

BUZ

: Buzzer Clock

EXA

: External Access Status Output

INTP0 to INTP5

: Interrupt from Peripherals

NMI

: Non-maskable Interrupt

P00 to P05

: Port0

P10 to P17

: Port1

P20 to P27

: Port2

P30 to P37

: Port3

P40 to P47

: Port4

P50 to P57

: Port5

P60 to P67

: Port6

P70 to P72

: Port7

P120 to P127

: Port12

P130, P131

: Port13

PCL

: Programmable Clock

: Read Strobe

RESET

: Reset

RTP0 to RTP7

: Real-time Output Port

RxD1, RxD2

: Receive Data

SCK0 to SCK2

: Serial Clock

SCL0

Note

: Serial Clock

SDA0

Note

: Serial Data

SI0 to SI2

: Serial Input

SO0 to SO2

: Serial Output

TEST

: Test

TI00, TI01, TI1, TI2 : Timer Input

TO0 to TO2

: Timer Output

TxD1, TxD2

: Transmit Data

DD0

, V

DD1

: Power Supply

SS0

, V

SS1

: Ground

WAIT

: Wait

: Write Strobe

X1, X2

: Crystal (Main System Clock)

XT1, XT2

: Crystal (Subsystem Clock)

Note The SCL0 and SDA0 pins are available in

PD784225Y Subseries only.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

4. BLOCK DIAGRAM

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP5

PROGRAMMABLE
INTERRUPT
CONTROLLER

REAL-TIME
OUTPUT PORT

TIMER/COUNTER6

(8 BITS)

TIMER/COUNTER5

(8 BITS)

TIMER/EVENT

COUNTER2

(8 BITS)

TIMER/EVENT

COUNTER1

(8 BITS)

TIMER/EVENT

COUNTER

(16 BITS)

WATCH TIMER

WATCHDOG TIMER

TI00
TI01

TO0

TI1

TO1

TI2

TO2

RTP0 to RTP7

CLOCK OUTPUT
CONTROL

A/D
CONVERTER

PCL

BUZ

ANI0 to ANI7

D/A
CONVERTER

ANO0

REF1

ANO1

78K/IV

CPU CORE

ROM

RAM

BAUD-RATE
GENERATOR

RxD1/SI1

TxD1/SO1

ASCK1/SCK1

RxD2/SI2

TxD2/SO2

ASCK2/SCK2

SI0/SDA0

Note

SO0
SCK0/SCL0

Note

BUS I/F

UART/IOE1

ASTB

WR
WAIT

AD0 to AD7

A8 to A15

A16 to A19

PORT1

P10 to P17

PORT0

PORT2

P20 to P27

PORT3

P30 to P37

PORT4

P40 to P47

PORT5

P50 to P57

PORT6

P60 to P67

PORT7

P70 to P72

PORT12

P120 to P127

PORT13

P130, P131

BUZZER OUTPUT

SYSTEM CONTROL

RESET

XT2

XT1

SS0

, V

SS1

DD0

, V

DD1

TEST

CLOCKED
SERIAL
INTERFACE

BAUD-RATE
GENERATOR

UART/IOE2

EXA

P00 to P05

NMI/INTP2

P03/INTP3

Note This function supports the I

C bus interface and is available in

PD784225Y Subseries only.

Remark The internal ROM and RAM capacities differ depending on the model.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

5. PIN FUNCTION

5.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00

I/O

INTP0

P01

INTP1

P02

INTP2/NM1

P03

INTP3

P04

INTP4

P05

INTP5

P10 to P17

Input

ANI0 to ANI7

P20

I/O

RxD1/SI1

P21

TxD1/SO1

P22

ASCK1/SCK1

P23

PCL

P24

BUZ

P25

SI0/SDA0

Note

P26

SO0

P27

SCK0/SCL0

Note

P30

I/O

TO0

P31

TO1

P32

TO2

P33

TI1

P34

TI2

P35

TI00

P36

TI01

P37

EXA

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· All pins set in input mode can be connected to internal pull-up

resistors by software.

· Can drive LEDs.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· All pins set in input mode can be connected to internal pull-up

resistors by software.

· Can drive LEDs.

Note This function is available in

PD784255Y Subseries only.

Port 1 (P1):

· 8-bit input port

Port 0 (P0):

· 6-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

Port 2 (P2):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

Port 3 (P3):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

5.2 Pins Other Than Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

Input

P35

External count clock input to 16-bit timer register

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer register 1

TI2

P34

External count clock input to 8-bit timer register 2

TO0

Output

P30

16-bit timer output (shared by 14-bit PWM output)

TO1

P31

8-bit timer output (shared by 8-bit PWM output)

TO2

P32

RxD1

Input

P20/SI1

Serial data input (UART1)

RxD2

P70/SI2

Serial data input (UART2)

TxD1

Output

P21/SO1

Serial data output (UART1)

TxD2

P71/SO2

Serial data output (UART2)

ASCK1

Intput

P22/SCK1

Baud rate clock input (UART1)

ASCK2

P72/SCK2

Baud rate clock input (UART2)

SI0

Input

P25/SDA0

Note

Serial data input (3-wire serial clock I/O0)

SI1

P20/RxD1

Serial data input (3-wire serial clock I/O1)

SI2

P70/RxD2

Serial data input (3-wire serial clock I/O2)

SO0

Output

P26

Serial data output (3-wire serial I/O0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O1)

SO2

P71/TxD2

Serial data output (3-wire serial I/O2)

SDA0

Note

I/O

P25/SI0

Serial data input/output (I

C bus)

SCK0

I/O

P27/SCL0

Note

Serial clock input/output (3-wire serial I/O0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O2)

SCL0

Note

P27/SCK0

Serial clock input/output (I

C bus)

NMI

Input

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

External interrupt request input

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0 to RTP7

Output

P120 to P127

Real-time output port that outputs data in synchronization with

trigger

AD0 to AD7

I/O

P40 to P47

Low-order address/data bus when external memory is connected

A8 to A15

Output

P50 to P57

Middle-order address bus when external memory is connected

A16 to A19

P60 to P63

High-order address bus when external memory is connected

Note This function is available in

PD784255Y Subseries only.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

5.2 Pins Other Than Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

Output

P64

Strobe signal output for read operation of external memory

P65

Strobe signal output for write operation of external memory

WAIT

Input

P66

To insert wait state(s) when external memory is accessed

ASTB

Output

P67

Strobe output to externally latch address information output to ports

4 to 6 to access external memory

EXA

Output

P37

External access status output

RESET

Input

System reset input

Input

To connect main system clock oscillation crystal

XT1

Input

To connect subsystem clock oscillation crystal

XT2

ANI0 to ANI7

Input

P10 to P17

Analog voltage input for A/D converter

ANO0, ANO1

Output

P130, P131

Analog voltage output for D/A converter

REF1

To apply reference voltage for D/A converter

Positive power supply for A/D converter. Connected to V

DD0

GND for A/D converter and D/A converter. Connected to V

SS0

DD0

Positive power supply for port block

SS0

GND potential for port block

DD1

Positive power supply (except port block)

SS1

GND potential (except port block)

TEST

Connect this pin to V

SS0

directly or via pull-down resistor. For the

pull-down connection, use of a resistor with a resistance ranging

from 470

to 10 k

is recommended.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection

of unused pins.

For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00/INTP0

8-K

I/O

Input : Individually connected to V

SS0

via resistor

P01/INTP1

Output: Open

P02/INTP2/NMI

P03/INTP3 to P05/INTP5

P10/ANI0 to P17/ANI7

Input

Connected to V

SS0

or V

DD0

P20/RxD1/SI1

10-I

I/O

Input : Individually connected to V

SS0

via resistor

P21/TxD1/SO1

10-J

Output: Open

P22/ASCK1/SCK1

10-I

P23/PCL

10-J

P24/BUZ

P25/SDA0

Note

/SI0

10-I

P26/SO0

10-J

P27/SCL0

Note

/SCK0

10-I

P30/TO0 to P32/TO2

8-M

P33/TI1, P34/TI2

8-K

P35/TI00, P36/TI01

8-L

P37/EXA

8-M

P40/AD0 to P47/AD7

5-H

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P70/RxD2/SI2

8-K

P71/TxD2/SO2

8-L

P72/ASCK2/SCK2

8-K

Note This function is available in

PD784255Y Subseries only.

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 Mbyte can be accessed. Mapping of the internal data area (special function registers and

internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed

after RESET cancellation, and must not be used more than once.

(1) When LOCATION 0H instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784224,

0F100H to 0FFFFH

00000H to 0F0FFH

PD784224Y

10000H to 17FFFH

PD784225,

0EE00H to 0FFFFH

00000H to 0EDFFH

PD784225Y

10000H to 1FFFFH

Caution

The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0H instruction is executed.

Part Number

Unusable Area

PD784224,

0F100H to 0FFFFH (3,840 bytes)

PD784224Y

PD784225,

0EE00H to 0FFFFH (4,608 bytes)

PD784225Y

· External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784224,

FF100H to FFFFFH

00000H to 17FFFH

PD784224Y

PD784225,

FEE00H to FFFFFH

00000H to 1FFFFH

PD784225Y

· External memory

The external memory is accessed in external memory expansion mode.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Figure 6-1. Memory Map of

PD784224, 784224Y

Notes

Accessed in external memory expansion mode.

This 3,840-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

On execution of LOCATION 0H instruction: 94,464 bytes, on execution of LOCATION 0FH instruction: 98,304 bytes

Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Internal ROM

(61,696 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM

(3,584 bytes)

External memory

Note 1

(928 Kbytes)

Note 1

General-purpose

registers (128 bytes)

Macro service control word

area (52 bytes)

Data area (512 bytes)

Program/data area

(3,072 bytes)

CALLF entry

area (2 Kbytes)

Program/data area

Note 3

CALLT table

area (64 bytes)

Vector table area

(64 bytes)

Internal RAM

(3,584 bytes)

External memory

Note 1

(980,736 bytes)

(256 bytes)

Internal ROM

(96 Kbytes)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Note 2

Internal ROM

(32,768 bytes)

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Figure 6-2. Memory Map of

PD784225, 784225Y

Notes

Accessed in external memory expansion mode.

This 4,608-byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

On execution of LOCATION 0H instruction: 126,464 bytes, on execution of LOCATION 0FH instruction: 131,072 bytes

Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Internal ROM

(60,928 bytes)

(256 bytes)

Special function registers (SFR)

Internal RAM

(4,352 bytes)

External memory

Note 1

(896 Kbytes)

Note 1

General-purpose

registers (128 bytes)

Macro service control word

area (52 bytes)

Data area (512 bytes)

Program/data area

(3,840 bytes)

CALLF entry

area (2 Kbytes)

Program/data area

Note 3

CALLT table

area (64 bytes)

Vector table area

(64 bytes)

Internal RAM

(4,352 bytes)

External memory

Note 1

(912,896 bytes)

(256 bytes)

Internal ROM

(128 Kbytes)

On execution of

LOCATION 0H instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM

(65,536 bytes)

Note 2

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit

24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching

function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal

RAM.

Figure 6-3. General-Purpose Register Format

A (R1)

B (R3)

R11

D (R13)

H (R15)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

X (R0)

C (R2)

R10

E (R12)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

Parentheses ( ) indicate an absolute name.

8 banks

Caution

Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling

the program of the 78K/III Series.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are allocated. These registers are mapped to a 256-byte space

of addresses 0FF00H to 0FFFFH

Note

Note On execution of the LOCATION 0H instruction. FFF00H to FFFFFH on execution of the LOCATION 0FH

instruction.

Caution

Do not access an address in this area to which no SFR is allocated. If such an address is accessed

by mistake, the

PD784225 may be in the deadlock status. This deadlock status can be cleared

only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

Symbol ...............................

Symbol indicating an SFR. This symbol is reserved for NEC's assembler

(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the

C compiler (CC78K4).

R/W ....................................

Indicates whether the SFR is read-only, write-only, or read/write.

R/W : Read/write

: Read-only

: Write-only

Bit units for manipulation ..

Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the operand

sfrp of an instruction. To specify the address of this SFR, describe an even

address.

SFRs that can be manipulated in 1-bit units can be described as the operand of

a bit manipulation instruction.

At reset ..............................

Indicates the status of the register when the RESET signal has been input.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 6-1. Special Function Register (SFR) List (1/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 Bit

8 Bits

16 Bits

0FF00H

Port 0

R/W

00H

Note 2

0FF01H

Port 1

0FF02H

Port 2

R/W

0FF03H

Port 3

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

0FF07H

Port 7

0FF0CH

Port 12

P12

0FF0DH

Port 13

P13

0FF10H

16-bit timer counter

TM0

0000H

0FF11H

0FF12H

Capture/compare register 00

CR00

R/W

0FF13H

(16-bit timer/counter)

0FF14H

Capture/compare register 01

CR01

0FF15H

(16-bit timer/counter)

0FF16H

Capture/compare control register 0

CRC0

00H

0FF18H

16-bit timer mode control register

TMC0

0FF1AH

16-bit timer output control register

TOC0

0FF1CH

Prescaler mode register 0

PRM0

0FF20H

Port 0 mode register

PM0

FFH

0FF22H

Port 2 mode register

PM2

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF27H

Port 7 mode register

PM7

0FF2CH

Port 12 mode register

PM12

0FF2DH

Port 13 mode register

PM13

0FF30H

Pull-up resistor option register 0

PU0

00H

0FF32H

Pull-up resistor option register 2

PU2

0FF33H

Pull-up resistor option register 3

PU3

0FF37H

Pull-up resistor option register 7

PU7

0FF3CH

Pull-up resistor option register 12

PU12

0FF40H

Clock output control register

CKS

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2. Because each port is initialized to input mode at reset, "00H" is not actually read. The output latch is

initialized to "0".

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 6-1. Special Function Register (SFR) List (2/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 Bit

8 Bits

16 Bits

0FF42H

Port function control register

PF2

R/W

00H

0FF4EH

Pull-up resistor option register

PUO

0FF50H

8-bit timer counter 1

TM1

TM1W

0000H

0FF51H

8-bit timer counter 2

TM2

0FF52H

Compare register 10 (8-bit timer/counter 1)

CR10 CR1W

R/W

0FF53H

Compare register 20 (8-bit timer/counter 2)

CR20

0FF54H

8-bit timer mode control register 1

TMC1 TMC1W

0FF55H

8-bit timer mode control register 2

TMC2

0FF56H

Prescaler mode register 1

PRM1 PRM1W

0FF57H

Prescaler mode register 2

PRM2

0FF60H

8-bit timer counter 5

TM5 TM5W

0FF61H

8-bit timer counter 6

TM6

0FF64H

Compare register 50 (8-bit timer/counter 5)

CR50 CR5W

R/W

0FF65H

Compare register 60 (8-bit timer/counter 6)

CR60

0FF68H

8-bit timer mode control register 5

TMC5 TMC5W

0FF69H

8-bit timer mode control register 6

TMC6

0FF6CH

Prescaler mode register 5

PRM5 PRM5W

0FF6DH

Prescaler mode register 6

PRM6

0FF70H

Asynchronous serial interface mode register 1

ASIM1

00H

0FF71H

Asynchronous serial interface mode register 2

ASIM2

0FF72H

Asynchronous serial interface status register 1

ASIS1

0FF73H

Asynchronous serial interface status register 2

ASIS2

0FF74H

Transmit shift register 1

TXS1

FFH

Receive buffer register 1

RXB1

0FF75H

Transmit shift register 2

TXS2

Receive buffer register 2

RXB2

0FF76H

Baud rate generator control register 1

BRGC1

R/W

00H

0FF77H

Baud rate generator control register 2

BRGC2

0FF7AH

Oscillation mode select register

0FF80H

A/D converter mode register

ADM

0FF81H

A/D converter input select register

ADIS

0FF83H

A/D conversion result register

ADCR

Undefined

0FF84H

D/A conversion value setting register 0

DACS0

R/W

00H

0FF85H

D/A conversion value setting register 1

DACS1

0FF86H

D/A converter mode register 0

DAM0

0FF87H

D/A converter mode register 1

DAM1

Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 6-1. Special Function Register (SFR) List (3/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 Bit

8 Bits

16 Bits

0FF88H

ROM correction control register

CORC

R/W

00H

0FF89H

ROM correction address pointer H

CORAH

0FF8AH

ROM correction address pointer L

CORAL

0000H

0FF8BH

0FF8DH

External access status enable register

EXAE

00H

0FF90H

Serial operation mode register 0

CSIM0

0FF91H

Serial operation mode register 1

CSIM1

0FF92H

Serial operation mode register 2

CSIM2

0FF94H

Serial I/O shift register 0

SIO0

0FF95H

Serial I/O shift register 1

SIO1

0FF96H

Serial I/O shift register 2

SIO2

0FF98H

Real-time output buffer register L

RTBL

0FF99H

Real-time output buffer register H

RTBH

0FF9AH

Real-time output port mode register

RTPM

0FF9BH

Real-time output port control register

RTPC

0FF9CH

Watch timer mode control register

WTM

0FFA0H

External interrupt rising edge enable register

EGP0

0FFA2H

External interrupt falling edge enable register

EGN0

0FFA8H

In-service priority register

ISPR

0FFA9H

Interrupt select control register

SNMI

R/W

0FFAAH

Interrupt mode control register

IMC

80H

0FFACH

Interrupt mask flag register 0L

MK0L MK0

FFFFH

0FFADH

Interrupt mask flag register 0H

MK0H

0FFAEH

Interrupt mask flag register 1L

MK1L MK1

0FFAFH

Interrupt mask flag register 1H

MK1H

0FFB0H

C bus control register

Note 2

IICCL0

00H

0FFB2H

Prescaler mode register for serial clock

SPRM0

0FFB4H

Slave address register

SVA0

0FFB6H

C bus status register

Note 2

IICS0

0FFB8H

Serial shift register

IIC0

R/W

0FFC0H

Standby control register

STBC

30H

0FFC2H

Watchdog timer mode register

WDM

00H

0FFC4H

Memory expansion mode register

20H

0FFC7H

Programmable wait control register 1

PWC1

AAH

0FFC8H

Programmable wait control register 2

PWC2

AAAAH

00FFCEH

Clock status register

PCS

32H

0FFCFH

Oscillation stabilization time specification register

OSTS

R/W

00H

0FFD0H to

External SFR area

0FFDFH

Notes 1. When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

PD784225Y Subseries only

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 6-1. Special Function Register (SFR) List (4/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 Bit

8 Bits

16 Bits

0FFE0H

Interrupt control register (INTWDTM)

WDTIC

R/W

43H

0FFE1H

Interrupt control register (INTP0)

PIC0

0FFE2H

Interrupt control register (INTP1)

PIC1

0FFE3H

Interrupt control register (INTP2)

PIC2

0FFE4H

Interrupt control register (INTP3)

PIC3

0FFE5H

Interrupt control register (INTP4)

PIC4

0FFE6H

Interrupt control register (INTP5)

PIC5

0FFE8H

Interrupt control register (INTIIC0/INTCSI0)

CSIIC0

0FFE9H

Interrupt control register (INTSER1)

SERIC1

0FFEAH

Interrupt control register (INTSR1/INTCSI1)

SRIC1

0FFEBH

Interrupt control register (INTST1)

STIC1

0FFECH

Interrupt control register (INTSER2)

SERIC2

0FFEDH

Interrupt control register (INTSR2/INTCSI2)

SRIC2

0FFEEH

Interrupt control register (INTST2)

STIC2

0FFEFH

Interrupt control register (INTTM3)

TMIC3

0FFF0H

Interrupt control register (INTTM00)

TMIC00

0FFF1H

Interrupt control register (INTTM01)

TMIC01

0FFF2H

Interrupt control register (INTTM1)

TMIC1

0FFF3H

Interrupt control register (INTTM2)

TMIC2

0FFF4H

Interrupt control register (INTAD)

ADIC

0FFF5H

Interrupt control register (INTTM5)

TMIC5

0FFF6H

Interrupt control register (INTTM6)

TMIC6

0FFF9H

Interrupt control register (INTWT)

WTIC

Note When the LOCATION 0H instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 7-1. Port Functions

Port Name

Pin Name

Function

Specification of Pull-up Resistor

Connection by Software

Port 0

P00 to P05

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 1

P10 to P17

· Input port

Port 2

P20 to P27

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 3

P30 to P37

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 4

P40 to P47

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

· Can directly drive LEDs

Port 5

P50 to P57

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

· Can directly drive LEDs

Port 6

P60 to P67

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

Port 7

P70 to P72

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 12

P120 to P127

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 13

P130, P131

· Can be set in input or output mode bit-wise

7.2 Clock Generator

An on-chip clock generator necessary for operation is provided. This clock generator has a frequency divider.

If high-speed operation is not necessary, the internal operating frequency can be lowered by the frequency divider

to reduce the current consumption.

Figure 7-2. Block Diagram of Clock Generator

XT2

XT1

STOP and bit 2 (MCK) of the
standby control register (STBC)
= 1 when the subsystem clock
is selected as CPU clock

Main system

clock

oscillator

Subsystem

clock

oscillator

Watch timer,
clock output
function

Clock to
peripheral
hardware

CPU
clock
(f

CPU

)

Frequency

divider

Prescaler

STOP,

IDLE

controller

HALT

controller

Selector

IDLE

controller

Internal
system
clock
(f

CLK

)

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Figure 7-3. Example of Using Main System Clock Oscillator

External
clock

PD74HCU04

Crystal resorator
or
ceramic resonator

(1) Crystal/ceramic oscillation

(2) External clock

SS1

Figure 7-4. Example of Using Subsystem Clock Oscillator

32.768

kHz

XT2

XT1

XT2

XT1

External
clock

PD74HCU04

(1) Crystal oscillation

(2) External clock

SS1

Caution

When using the main system clock and subsystem clock oscillator, wire the dotted portions in

Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with other signal lines.

Do not route the wiring in the vicinity of lines through which a high alternating current flows.

Always keep the potential at the ground point of the capacitor in the oscillator the same as

SS1

. Do not ground to a ground pattern through which a high current flows.

Do not extract signals from the oscillator.

Note that the subsystem clock oscillator has a low amplification factor to reduce the current

consumption.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.3 Real-Time Output Port

The real-time output function is to transfer data set in advance to the real-time output buffer register to the output

latch as soon as the timer interrupt or external interrupt has occurred in order to output the data to an external device.

The pins that output the data to the external device constitute a port called a real-time output port.

Because the real-time output port can output signals without jitter, it is ideal for controlling a stepping motor.

Figure 7-5. Block Diagram of Real-Time Output Port

Internal bus

RTPOE

BYTE

EXTR

Output trigger

controller

Real-time output port
control register (RTPC)

Real-time output

port mode register

(RTPM)

Real-time output port output latch

RTP7······································ RTP0

Higher 4 bits of

real-time output

buffer register

(RTBH)

Lower 4 bits of

real-time output

buffer register

(RTBL)

INTP2TRG

INTTM1

INTTM2

Port 12 output latch

P127······································ P120

P12n/RTPn pin output (n = 0 to 7)

P127/ P120/
RTP7 RTP0

······································

RTPOE bit

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.5 A/D Converter

An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with

an A/D converter with a resolution of 8 bits and 8 channels (ANI0 to ANI7).

This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D

conversion result register (ADCR).

The A/D converter can be started in the following two ways:

· Hardware start

Conversion is started by trigger input (P03).

· Software start

Conversion is started by setting the A/D converter mode register.

One analog input channel is selected from ANI0 to ANI7 for A/D conversion. When A/D conversion is started

by means of hardware start, conversion is stopped after it has been completed. When conversion is started by

means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed,

an interrupt request (INTAD) is generated.

Figure 7-7. Block Diagram of A/D Converter

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Sample & hold circuit

Series resistor string

Voltage comparator

Successive approximation
register (SAR)

A/D conversion result register

(ADCR)

Controller

Edge

detector

INTP3/P03

INTAD

INTP3

Internal bus

Selector

Tap selector

Edge

detector

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.7 Serial Interface

Three independent serial interface channels are provided.

· Asynchronous serial interface (UART)/3-wire serial I/O (IOE)

· Clocked serial interface (CSI)

· 3-wire serial I/O (IOE)

· I

C bus interface (I

C) (

PD784225Y Subseries only)

Therefore, communication with an external system and local communication within the system can be simultaneously

executed (see Figure 7-9).

Figure 7-9. Example of Serial Interface

(a) UART + I

PD784225Y (master)

PD4711A

RS-232C

driver/receiver

RS-232C

driver/receiver

[UART]

Port

RxD1

TxD1

RxD2

TxD2

SDA0

SCL0

LCD

PD780078Y (slave)

PD780308Y (slave)

DD0

SDA

SCL

SDA

SCL

DD0

(b) UART + 3-wire serial I/O

PD784225Y (master)

PD4711A

RS-232C

driver/receiver

[UART]

Port

RxD2

TxD2

PD753106 (slave)

SCK

Port

INT

[3-wise serial I/O]

Note

SO1

SI1

SCK1

INTPm

Port

Note Handshake line

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.7.1 Asynchronous serial interface/3-wire serial I/O (UART/IOE)

Two channels of serial interfaces that can select an asynchronous serial interface mode and 3-wire serial I/O

mode are provided.

(1) Asynchronous serial interface mode

In this mode, data of 1 byte following the start bit is transferred or received.

Because an on-chip baud rate generator is provided, a wide range of baud rates can be set.

Moreover, the clock input to the ASCK pin can be divided to define a baud rate.

When the baud rate generator is used, a baud rate conforming to the MIDI standard (31.25 kbps) can be

also obtained.

Figure 7-10. Block Diagram in Asynchronous Serial Interface Mode

Internal bus

Receive buffer register

1, 2 (RXB1, RXB2)

Receive shift register

1, 2 (RX1, RX2)

Transmit shift register

1, 2 (TXS1, TXS2)

Receive control

parity check

Transmit control

parity addition

RxD1, RxD2

TxD1, TxD2

ASCK1, ASCK2

Baud rate generator

INTSR1,
INTSR2

INTST1,
INTST2

Selector

5-bit counter

Transmit/receive clock generation

to f

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.7.2 Clocked serial interface (CSI)

In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data

in synchronization with this clock.

(1) 3-wire serial I/O mode

This mode is to communicate with devices having the conventional clocked serial interface.

Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial

data (SI0 and SO0) lines.

Generally, a handshake line is necessary to check the reception status.

Figure 7-12. Block Diagram in 3-Wise Serial I/O Mode

SI0

SO0

SCK0

INTCSI0

TO2
f

/16

Internal bus

Direction controller

Interrupt
generator

Selector

Serial clock
counter

Serial clock
controller

Serial I/O shift register 0

(SIO0)

(2) I

C (Inter IC) bus mode (supporting multi-master) (

PD784225Y Subseries only)

This mode is to communicate with devices conforming to the I

C bus format.

This mode is to transfer 8-bit data with two or more devices by using two lines: serial clock (SCL0) and serial

data bus (SDA0).

During transfer, a "start condition", "data", and "stop condition" can be output onto the serial data bus. During

reception, these data can be automatically detected by hardware.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

7.9 Buzzer Output Function

Clocks of the following frequencies can be output as buzzer output.

· 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (main system clock: 12.5 MHz)

Figure 7-15. Block Diagram of Buzzer Output Function

Output controller

BUZ

Selector

7.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 to INTP5) are used not only to input interrupt requests

but also to input trigger signals to the internal hardware units. Because these pins operate at an edge of the input

signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to prevent

erroneous detection due to noise.

Pin Name

Detectable Edge

Noise Reduction

NMI

Either or both of rising and falling edges

By analog delay

INTP0 to INTP5

7.11 Watch Timer

The watch timer has the following functions:

· Watch timer

· Interval timer

The watch timer and interval timer functions can be used at the same time.

(1) Watch timer

The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds

by using the 32.768-kHz subsystem clock.

(2) Interval timer

The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

8. INTERRUPT FUNCTION

As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by

program.

Table 8-1. Servicing of Interrupt Request

Servicing Mode

Entity of Servicing

Servicing

Contents of PC and PSW

Vectored interrupt

Software

Branches and executes servicing routine

Saves to and restores

(servicing is arbitrary).

from stack.

Context switching

Automatically switches register bank,

Saves to or restores from

branches and executes servicing routine

fixed area in register bank

(servicing is arbitrary).

Macro service

Firmware

Executes data transfer between memory

Retained

and I/O (servicing is fixed)

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 25 types of sources,

execution of the BRK instruction, BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt

servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the

macro service function is used, however, nesting always proceeds.

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having

the same request, simultaneously generate (see Table 8-2).

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Table 8-2. Interrupt Sources

Type

Default

Source

Internal/

Macro

Priority

Name

Trigger

External

Service

Software

BRK instruction

Instruction execution

BRKCS instruction

Instruction execution

Operand error

If result of exclusive OR between operands
byte and byte is not FFH when MOV STBC,
#byte instruction or MOV WDM, #byte
instruction, LOCATION instruction is executed

Non-maskable

NMI

Pin input edge detection

External

INTWDT

Overflow of watchdog timer

Internal

Maskable

0 (highest)

INTWDTM

Overflow of watchdog timer

Internal

INTP0

Pin input edge detection

External

INTP1

INTP2

INTP3

INTP4

INTP5

INTIIC0

Note

End of I

C bus transfer by CSI0

Internal

INTCSI0

End of 3-wire transfer by CSI0

INTSER1

Occurrence of UART reception error in ASI1

INTSR1

End of UART reception by ASI1

INTCSI1

End of 3-wire transfer by CSI1

INTST1

End of UART transfer by ASI1

INTSER2

Occurrence of UART reception error in ASI2

INTSR2

End of UART reception by ASI2

INTCSI2

End of 3-wire transfer by CSI2

INTST2

End of UART transfer by ASI2

INTTM3

Reference time interval signal from watch timer

INTTM00

Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR00)

INTTM01

Signal indicating coincidence between 16-bit
timer counter and capture/compare register
(CR01)

INTTM1

Occurrence of coincidence signal of 8-bit
timer/counter 1

INTTM2

Occurrence of coincidence signal of 8-bit
timer/counter 2

INTAD

End of conversion by A/D converter

INTTM5

Occurrence of coincidence signal of 8-bit
timer/counter 5

INTTM6

Occurrence of coincidence signal of 8-bit
timer/counter 6

22 (lowest)

INTWT

Overflow of watch timer

Note

PD784255Y Subseries only

Remarks 1. ASI : Asynchronous Serial Interface

CSI : Clocked Serial Interface

2. There are two interrupt sources for the watchdog timer: non-maskable interrupts (INTWDT) and

maskable interrupts (INTWDTM). Either one (but not both) should be selected for actual use.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

8.2 Vectored Interrupt

Execution branches to a servicing routing by using the memory contents of a vector table address corresponding

to the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

· On branching: Saves the status of the CPU (contents of PC and PSW) to stack

· On returning : Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used.

The branch destination address is in a range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt Source

Vector Table Address

Interrupt Source

Vector Table Address

BRK instruction

003EH

INTST1

001CH

Operand error

003CH

INTSER2

001EH

NMI

0002H

INSR2

0020H

INTWDT (non-maskable)

0004H

INTCSI2

INTWDTM (maskable)

0006H

INTST2

0022H

INTP0

0008H

INTTM3

0024H

INTP1

000AH

INTTM00

0026H

INTP2

000CH

INTTM01

0028H

INTP3

000EH

INTTM1

002AH

INTP4

0010H

INTTM2

002CH

INTP5

0012H

INTAD

002EH

INTIIC0

0016H

INTTM5

00030H

INTCSI0

INTTM6

0032H

INTSER1

0018H

INTWT

0038H

INTSR1

001AH

INTCSI1

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

8.3 Context Switching

When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register

bank is selected by hardware. Context switching is a function that branches execution to a vector address stored

in advance in the register bank, and to stack the current contents of the program counter (PC) and program status

word (PSW) to the register bank.

The branch address is in a range of 0 to FFFFH.

Figure 8-1. Context Switching Operation When Interrupt Request Is Generated

0000B
<7> Transfer

PC19 to PC16

PC15 to PC0

<6> Exchange

<5> Save

<2> Save

Temporary register

<1> Save

PSW

<3> Switching of register bank
(RBS0 to RBS2

(0 to 7)

(bits 8 through 11
of temporary register)

<4> RSS

8.4 Macro Service

This function is to transfer data between memory and a special function register (SFR) without intervention by

the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers

data without loading it.

Because this function does not save or restore the status of the CPU, or load data, data can be transferred at

high speeds.

Figure 8-2. Macro Service

CPU

Memory

SFR

Macro service

controller

Read

Write

Read

Internal bus

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

8.5 Application Example of Macro Service

(1) Transmission of serial interface

Transfer data storage buffer (memory)

Data n

Data 1

Data 2

Internal bus

Transmit shift register

TXS1, TXS2 (SFR)

Transfer control

TxD1, TxD2

INTST1, INTST2

Each time macro service request INTST1 and INTST2 are generated, the next transmit data is transferred

from memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when

the transmit data storage buffer has become empty), vectored interrupt request INTST1 and INTST2 are

generated.

(2) Reception of serial interface

Receive data storage buffer (memory)

Data n

Data 1

Data 2

Internal bus

Receive shift register

RXB1, RXB2 (SFR)

Reception control

INTSR1, INTSR2

RxD1, RxD2

Receive buffer register

Each time macro service request INTSR1 and INTSR2 are generated, the receive data is transferred from

RXB1 and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive

data storage buffer has become full), vectored interrupt request INTSR1 and INTSR2 are generated.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

9. LOCAL BUS INTERFACE

The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory

space of 1 Mbyte (refer to Figure 9-1).

Figure 9-1. Example of Local Bus Interface (Multiplexed bus)

PD784225

A8 to A19

ASTB

AD0 to AD7

DD1

Address latch

Q0 to Q7

D0 to D7

SRAM

WE
I/O1 to I/O8

A0 to A19

Data bus

Address bus

9.1 Memory Expansion

External program and data memory can be connected in two stages: 256 Kbytes and 1 Mbytes.

To connect the external memory, ports 4 to 6 are used.

The external memory is connected by using a time-division address/data bus. The number of ports used when

the external memory is connected can be reduced in this mode.

9.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H to FFFFFH) while the RD and WR signals are active.

In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address

decode time.

9.3 External Access Status Function

An active low external access status signal is output from the P37/EXA pin. This signal notifies other devices

connected to the external bus of the external access status, to disable data output to the external bus from other

devices, or enables reception.

The external access status signal is output during external access.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

10. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

· HALT mode

: Stops supply of the operating clock to the CPU. This mode is used in combination

with the normal operation mode for intermittent operation to reduce the average

power consumption.

· IDLE mode

: Stops the entire system with the oscillator continuing operation. The power

consumption in this mode is close to that in the STOP mode. However, the time

required to restore the normal program operation from this mode is almost the

same as that from the HALT mode.

· STOP mode

: Stops the main system clock and thereby to stop all the internal operations of the

chip. Consequently, the power consumption is minimized with only leakage

current flowing.

· Power-saving mode

: The main system clock is stopped with the subsystem clock used as the system

clock. The CPU can operate on the subsystem clock to reduce the current

consumption.

· Power-saving HALT mode : This is a standby function in the power-saving mode and stops the operation clock

of the CPU, to reduce the power consumption of the entire system.

· Power-saving IDLE mode : This is a standby function in the power-saving mode and stops the entire system

except the oscillator, to reduce the power consumption of the entire system.

These modes are programmable.

The macro service can be started from the HALT mode and power-saving HALT mode.

After executing macro service processing, it returns to the HALT mode.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Figure 10-1. Transition of Standby Status

Waits for

oscillation

stabilization

Normal

operation

(operation on

main system

clock)

Macro

service

HALT

(standby)

IDLE

(standby)

Power-

saving mode

(operation on

subsystem

clock)

Power-

saving HALT

mode

(standby)

Power-

saving IDLE

mode

(standby)

STOP

(standby)

End of oscillation stabilization time

Macro service request

End of one processing

End of macro service

Macro service request

End of one processing

Interrupt request

RESET input

Sets HALT mode

Sets IDLE mode

RESET input

NMI, INTP0 to INTP6 input, INTWT,

key return interrupt

Note 2

NMI, INTP0 to INTP6 input,

INTWT, key return interrupt

Note 2

Sets STOP mode

Power-saving IDLE mode is set.

RESET input

Power-saving HALT mode is set.

Normal operation is restored.

NMI, INTP0 to INTP6 input,
INTWT

Note 2

Power-saving HALT mode is set.

RESET input

Interrupt request

Note 1

Interrupt
request of
masked interrupt

Interrupt
request of
masked
interrupt

RESET input

Macro

service

Macro service request

End of one processing

End of macro service

End of one processing

Notes 1. Only unmasked interrupt requests

2. Only unmasked INTP0 to INTP6, INTWT, key return interrupt (P80 to P87)

Remark NMI is valid only for an external input. The watchdog timer cannot be used for the release of standby

(HALT mode/STOP mode/IDLE mode).

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

11. RESET FUNCTION

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset).

During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current

consumption of the entire system can be reduced.

When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 MHz)

elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address

set to the PC, and program execution is started from that branch address. Therefore, the program can be reset

and started from any address.

Figure 11-1. Oscillation of Main System Clock during Reset Period

Oscillation is unconditionally
stopped during rest period

Oscillation stabilization time

Main system clock
oscillator

CLK

RESET input

The RESET input pin has an analog delay noise eliminator to prevent malfunctioning due to noise.

Figure 11-2. Accepting Reset Signal

Analog delay

Analog
delay

Oscillation
stabilization
time

RESET input

Internal reset signal

Internal clock

Time until the clock starts oscillation

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

13. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC,

CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA

Table 13-1. Instruction List by 8-Bit Addressing

Second Operand

#byte

saddr

sfr

!addr16

mem

[WHL+]

None

Note 2

saddr'

!!addr24

[saddrp]

PSWL

[WHL]

First Operand

[%saddrg]

PSWH

(MOV)

MOV

(MOV)

Note 6

MOV

(MOV)

MOV

(MOV)

ADD

Note 1

(XCH)

XCH

(XCH)

Note 6

(XCH)

XCH

(XCH)

(ADD)

Note 1

(ADD)

Note 1

(ADD)

Note 1,6

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

MOV

(MOV)

MOV

ROR

Note 3

MULU

ADD

Note 1

(XCH)

XCH

DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

INC

DEC

saddr

MOV

(MOV)

Note 6

MOV

INC

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

XCH

DEC

ADD

Note 1

DBNZ

sfr

MOV

PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16

MOV

(MOV)

MOV

!!addr24

ADD

Note 1

mem

MOV

[saddrp]

ADD

Note 1

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

(MOV)

MOVBK

Note 5

[TDE]

(ADD)

Note 1

MOVM

Note 4

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of

MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as

rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,

POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 13-2. Instruction List by 16-Bit Addressing

Second Operand

#word

saddrp

sfrp

!addr16

mem

[WHL+]

byte

None

Note 2

rp'

saddrp'

!!addr24

[saddrp]

First Operand

[%saddrg]

(MOVW)

(MOVW) (MOVW)

Note 3

MOVW

(MOVW)

MOVW

(MOVW)

ADDW

Note 1

(XCHW)

(XCHW) (XCHW)

Note 3

(XCHW)

XCHW

(XCHW)

(ADD)

Note 1

(ADDW)

Note 1

(ADDW)

Note 1,3

(ADDW)

Note 1

MOVW

(MOVW)

MOVW

SHRW

MULW

Note 4

ADDW

Note 1

(XCHW)

XCHW

SHLW

INCW

(ADDW)

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

DECW

saddrp

MOVW

(MOVW)

Note 3

MOVW

INCW

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

XCHW

DECW

ADDW

Note 1

sfrp

MOVW

PUSH

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as that of MULW.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

14. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

Parameter

Symbol

Conditions

Ratings

Unit

Supply voltage

DD0

0.3 to +6.5

0.3 to V

DD0

+ 0.3

0.3 to V

SS0

+ 0.3

REF1

D/A converter reference voltage input

0.3 to V

DD0

+ 0.3

Input voltage

0.3 to V

DD0

+ 0.3

Analog input voltage

Analog input pin

0.3 to AV

REF1

+ 0.3

Output voltage

0.3 to V

+ 0.3

Output current, low

Per pin

Total of all pins

100

Output current, high

Per pin

Total of all pins

Operating ambient

40 to +85

temperature

Storage temperature

stg

65 to +150

Caution

Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even

momentarily, the quality of the product may deteriorate. Always use the product within its rated

values.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Main System Clock Oscillator Characteristics (T

C to +85

C, V

= V

DD0

= V

DD1

)

Resonator Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Ceramic

Oscillation frequency (f

)

4.5 V

5.5 V

12.5

MHz

resonator

2.7 V

< 4.5 V

6.25

or crystal

2.0 V

< 2.7 V

3.125

resonator

1.8 V

< 2.0 V

External

X1 input frequency (f

)

4.5 V

5.5 V

12.5

MHz

clock

2.7 V

< 4.5 V

6.25

2.0 V

< 2.7 V

3.125

1.8 V

< 2.0 V

X1 input high-/low-

250

level width (t

WXH

, t

WXL

)

X1 input rising/falling

4.5 V

5.5 V

time (t

, t

)

2.7 V

< 4.5 V

2.0 V

< 2.7 V

1.8 V

< 2.0 V

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

X1 V

PD74HCU04

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Subsystem Clock Oscillator Characteristics (T

C to +85

C, V

= V

DD0

= V

DD1

)

Resonator Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Crystal

Oscillation frequency (f

)

32.768

kHz

resonator

Oscillation stabilization

4.5 V

5.5 V

1.2

time

Note

1.8 V

< 4.5 V

External

XT1 input frequency (f

)

kHz

clock

XT1 input high-/low-level

14.3

15.6

width (t

XTH

, t

XTL

)

Note Time required to stabilize oscillation after applying supply voltage (V

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken

lines in the above figures to avoid an adverse effect from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with the other signal lines.

Do not route the wiring near a signal line through which a high fluctuating current flows.

Always make the ground point of the oscillator capacitor the same potential as V

Do not ground the capacitor to a ground pattern through which a high current flows.

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, customers are required to either evaluate the

oscillation themselves or apply to the resonator manufacturer for evaluation.

XT2

XT1

XT2

XT1

PD74HCU04

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

DC Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V) (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input voltage, low

IL1

Note 1

2.2 V

5.5 V

0.3V

1.8 V

< 2.2 V

0.2V

IL2

P00 to P05, P20, P22, P33,

2.2 V

5.5 V

0.2V

P34, P70, P72, RESET

1.8 V

< 2.2 V

0.15V

IL4

P10 to P17, P130, P131

2.2 V

5.5 V

0.3V

1.8 V

< 2.2 V

0.2V

IL5

X1, X2, XT1, XT2

2.2 V

5.5 V

0.2V

1.8 V

< 2.2 V

0.1V

IL6

P25, P27

2.2 V

5.5 V

0.3V

1.8 V

< 2.2 V

0.2V

Input voltage, high

IH1

Note 1

2.2 V

5.5 V

0.7V

1.8 V

< 2.2 V

0.8V

IH2

P00 to P05, P20, P22, P33,

2.2 V

5.5 V

0.8V

P34, P70, P72, RESET

1.8 V

< 2.2 V

0.85V

IH4

P10 to P17, P130, P131

2.2 V

5.5 V

0.7V

1.8 V

< 2.2 V

0.8V

IH5

X1, X2, XT1, XT2

2.2 V

5.5 V

0.8V

1.8 V

< 2.2 V

0.85V

IH6

P25, P27

2.2 V

5.5 V

0.7V

1.8 V

< 2.2 V

0.8V

Output voltage, low

OL1

For pins other than

4.5 V

5.5 V

0.4

P40 to P47, P50 to P57,

= 1.6 mA

Note 2

P40 to P47, P50 to P57

4.5 V

5.5 V

1.0

= 8 mA

Note 2

OL2

= 400

Note 2

0.5

Output voltage, high

OH1

1 mA

Note 2

4.5 V

5.5 V

1.0

100

Note 2

0.5

Input leakage current,

LIL1

= 0 V

Except X1, X2,

low

XT1, XT2

LIL2

X1, X2, XT1, XT2

Input leakage current,

LIH1

= V

DD0

Except X1, X2,

high

XT1, XT2

LIH2

X1, X2, XT1, XT2

Output leakage current,

LOL1

OUT

= 0 V

low

Output leakage current,

LOH1

OUT

= V

high

Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127

2. Per pin

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

DC Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V) (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Supply voltage

DD1

Operation

= 12.5 MHz, V

= 5.0 V

10%

mode

= 6 MHz, V

= 3.0 V

10%

= 2 MHz, V

= 2.0 V

10%

DD2

HALT mode

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

= 2 MHz, V

= 2.0 V

10%

0.5

3.5

DD3

IDLE mode

= 12.5 MHz, V

= 5.0 V

10%

2.5

= 6 MHz, V

= 3.0 V

10%

0.4

1.3

= 2 MHz, V

= 2.0 V

10%

0.2

0.9

DD4

Operation

= 32 kHz, V

= 5.0 V

10%

200

mode

Note

= 32 kHz, V

= 3.0 V

10%

110

= 32 kHz, V

= 2.0 V

10%

100

DD5

HALT

= 32 kHz, V

= 5.0 V

10%

160

mode

Note

= 32 kHz, V

= 3.0 V

10%

= 32 kHz, V

= 2.0 V

10%

DD6

IDLE

= 32 kHz, V

= 5.0 V

10%

150

mode

Note

= 32 kHz, V

= 3.0 V

10%

= 32 kHz, V

= 2.0 V

10%

Data retention voltage

DDDR

HALT, IDLE modes

1.8

5.5

Data retention current

DDDR

STOP mode

= 2.0 V

10%

= 5.0 V

10%

Pull-up resistor

= 0 V

100

Note When main system clock is stopped.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

AC Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

(1) Read/write operation (1/3)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Cycle time

CYK

4.5 V

5.5 V

2.7 V

< 4.5 V

160

2.0 V

< 2.7 V

320

1.8 V

< 2.0 V

500

Address setup time

SAST

= 5.0 V

10%

(0.5 + a) T

(to ASTB

)

= 3.0 V

10%

(0.5 + a) T

= 2.0 V

10%

(0.5 + a) T

Address hold time

HSTLA

= 5.0 V

10%

0.5T

(from ASTB

)

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

ASTB high-level width

WSTH

= 5.0 V

10%

(0.5 + a) T

= 3.0 V

10%

(0.5 + a) T

= 2.0 V

10%

(0.5 + a) T

110

Address hold time

HRA

= 5.0 V

10%

0.5T

(from RD

)

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Delay time from address to

DAR

= 5.0 V

10%

(1 + a) T

= 3.0 V

10%

(1 + a) T

= 2.0 V

10%

(1 + a) T

Address float time

FAR

= 5.0 V

10%

(from RD

)

= 3.0 V

10%

= 2.0 V

10%

Data input time from

DAID

= 5.0 V

10%

(2.5 + a + n) T

address

= 3.0 V

10%

(2.5 + a + n) T

= 2.0 V

10%

(2.5 + a + n) T

120

Data input time from ASTB

DSTID

= 5.0 V

10%

(2 + n) T

= 3.0 V

10%

(2 + n) T

= 2.0 V

10%

(2 + n) T

Data input time from RD

DRID

= 5.0 V

10%

(1.5 + n) T

= 3.0 V

10%

(1.5 + n) T

= 2.0 V

10%

(1.5 + n) T

Remark T: t

CYK

= 1/f

: Main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

AC Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

(1) Read/write operation (2/3)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Delay time from ASTB

DSTR

= 5.0 V

10%

0.5T

to RD

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Data hold time (from RD

)

HRID

= 5.0 V

10%

= 3.0 V

10%

= 2.0 V

10%

Address active time from

DRA

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Delay time from RD

DRST

= 5.0 V

10%

0.5T

ASTB

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

RD low-level width

WRL

= 5.0 V

10%

(1.5 + n) T

= 3.0 V

10%

(1.5 + n) T

= 2.0 V

10%

(1.5 + n) T

Delay time from address to

DAW

= 5.0 V

10%

(1 + a) T

= 3.0 V

10%

(1 + a) T

= 2.0 V

10%

(1 + a) T

Address hold time

HRD

= 5.0 V

10%

0.5T

(from WR

)

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Delay time from ASTB

DSTOD

= 5.0 V

10%

0.5T + 15

data output

= 3.0 V

10%

0.5T + 30

= 2.0 V

10%

0.5T + 240

Delay time from WR

DWOD

= 5.0 V

10%

0.5T

data output

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Delay time from ASTB

DSTW

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Data setup time (to WR

)

SODWR

= 5.0 V

10%

(1.5 + n) T

= 3.0 V

10%

(1.5 + n) T

= 2.0 V

10%

(1.5 + n) T

Remark T: t

CYK

= 1/f

: Main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

AC Characteristics (T

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

(2) External wait timing (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Input time from address to

DAWT

= 5.0 V

10%

(2 + a) T

WAIT

= 3.0 V

10%

(2 + a) T

= 2.0 V

10%

(2 + a) T

300

Input time from ASTB

DSTWT

= 5.0 V

10%

1.5T

WAIT

= 3.0 V

10%

1.5T

= 2.0 V

10%

1.5T

260

Hold time from ASTB

HSTWT

= 5.0 V

10%

(0.5 + n) T + 5

WAIT

= 3.0 V

10%

(0.5 + n) T + 10

= 2.0 V

10%

(0.5 + n) T + 30

Delay time from ASTB

DSTWTH

= 5.0 V

10%

(1.5 + n) T

WAIT

= 3.0 V

10%

(1.5 + n) T

= 2.0 V

10%

(1.5 + n) T

Input time from RD

DRWTL

= 5.0 V

10%

WAIT

= 3.0 V

10%

= 2.0 V

10%

Hold time from RD

HRWT

= 5.0 V

10%

nT + 5

WAIT

= 3.0 V

10%

nT + 10

= 2.0 V

10%

nT + 30

Delay time from RD

DRWTH

= 5.0 V

10%

(1 + n) T

WAIT

= 3.0 V

10%

(1 + n) T

= 2.0 V

10%

(1 + n) T

Input time from WAIT

DWTID

= 5.0 V

10%

0.5T

data

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T

Delay time from WAIT

DWTR

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T + 5

Delay time from WAIT

DWTW

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

= 2.0 V

10%

0.5T + 5

Delay time from WR

DWWTL

= 5.0 V

10%

WAIT

= 3.0 V

10%

= 2.0 V

10%

Remark T: t

CYK

= 1/f

: Main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Serial Operation (T

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY1

2.7 V

5.5 V

800

3,200

SCK high-/low-level

KH1

2.7 V

5.5 V

350

width

KL1

1,500

SI setup time (to SCK

)

SIK1

2.7 V

5.5 V

SI hold time (from SCK

)

KSI1

SO output delay time

KSO1

(from SCK

)

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

SCK cycle time

KCY2

2.7 V

5.5 V

800

3,200

SCK high-/low-level

KH2

2.7 V

5.5 V

400

width

KL2

1,600

SI setup time (to SCK

)

SIK2

2.7 V

5.5 V

SI hold time (from SCK

)

KSI2

SO output delay time

KSO2

(from SCK

)

(c) UART mode

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

ASCK cycle time

KCY3

4.5 V

5.5 V

417

2.7 V

< 4.5 V

833

1,667

ASCK high-/low-level

KH3

4.5 V

5.5 V

208

width

KL3

2.7 V

< 4.5 V

416

833

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

(d) I

C bus mode (

PD784225Y only)

Parameter

Symbol

Standard Mode

High-Speed Mode

Unit

MIN.

MAX.

MIN.

MAX.

SCL0 clock frequency

CLK

100

400

kHz

Bus free time (between stop

BUF

4.7

1.3

and start conditions)

Hold time

Note1

HD : STA

4.0

0.6

Low-level width of SCL0

LOW

4.7

1.3

clock

High-level width of SCL0

HIGH

4.0

0.6

clock

Setup time of start/restart

SU : STA

4.7

0.6

conditions

Data hold When using

HD : DAT

5.0

time

CBUS-compatible

master

When using I

Note 2

0.9

Note 3

bus

Data setup time

SU : DAT

250

100

Note 4

Rising time of SDA0 and

1,000

20 + 0.1Cb

Note 5

300

SCL0 signals

Falling time of SDA0 and

300

20 + 0.1Cb

Note 5

300

SCL0 signals

Setup time of stop condition

SU : STO

4.0

0.6

Pulse width of spike

restricted by input filter

Load capacitance of each

400

bus line

Notes 1. For the start condition, the first clock pulse is generated after the hold time.

2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

SDA0 signal (on V

IHmin.

) with at least 300 ns of hold time.

3. If the device does not extend the SCL0 signal low-level hold time (t

LOW

), only the maximum data hold

time t

HD : DAT

needs to be satisfied.

4. The high-speed mode I

C bus can be used in a standard mode I

C bus system. In this case, the

conditions described below must be satisfied.

If the device does not extend the SCL0 signal low-level hold time

SU : DAT

250 ns

If the device extends the SCL0 signal low-level hold time

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t

Rmax.

+ t

SU : DAT

1,000 + 250 = 1,250 ns by standard mode I

C bus specification)

5. Cb: Total capacitance per bus line (unit: pF)

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Other Operations (T

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

NMI high-/low-level

WNIL

width

WNIH

INTP input high-/low-

WITL

INTP0 to INTP6

100

level width

WITH

RESET high-/low-level

WRSL

width

WRSH

Clock Output Operation

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

PCL cycle time

CYCL

4.5 V

5.5 V, nT

31,250

PCL high-/low-level

CLL

4.5 V

5.5 V, 0.5T

15,615

width

CLH

PCL rising/falling time

CLR

4.5 V

5.5 V

CLF

2.7 V

< 4.5 V

1.8 V

< 2.7 V

Remark T: t

CYK

= 1/f

: Main system clock frequency)

n: Divided frequency ratio set by software in the CPU

When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

When using the subsystem clock: n = 1

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

A/D Converter Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note

6.25 MHz < f

12.5 MHz,

1.2 %FSR

4.5 V

5.5 V, AV

= V

DD0

3.125 MHz < f

6.25 MHz,

1.2 %FSR

2.7 V

5.5 V, AV

= V

DD0

2 MHz < f

3.125 MHz,

1.6 %FSR

2.0 V

5.5 V, AV

= V

DD0

= 2 MHz, 1.8 V

5.5 V

1.6 %FSR

= V

DD0

Conversion time

CONV

144

Sampling time

SAMP

24/f

Analog input voltage

IAN

Reference voltage

Resistance between

AVREF0

A/D conversion is not performed

and AV

Note Excludes quantization error (

0.2%FSR).

Remark FSR: Full-scale range

D/A Converter Characteristics

C to +85

C, V

= V

DD0

= V

DD1

= AV

= 1.8 to 5.5 V, V

= V

SS0

= V

SS1

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bit

Overall error

Note

2.0 V

5.5 V

0.6 %FSR

R = 10 M

, 2.0 V

REF1

5.5 V

1.8 V

2.0 V

1.2 %FSR

R = 10 M

, 1.8 V

REF1

5.5 V

Settling time

Load conditions:

4.5 V

REF1

5.5 V

C = 30 pF

2.7 V

REF1

< 4.5 V

1.8 V

REF1

< 2.7 V

Output resistance

DACS0, 1 = 55H

Reference voltage

REF1

1.8

DD0

REF1

current

REF1

For only 1 channel

2.5

Note Excludes quantization error (

0.2%FSR).

Remark FSR: Full-scale range

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

16. RECOMMENDED SOLDERING CONDITIONS

The

PD784225 should be soldered and mounted under the following recommended conditions.

For the details of the recommended soldering conditions, refer to the document Semiconductor Device

Mounting Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales representative.

Caution

Soldering conditions for the

PD784224GC-

×××

-8BT,

PD784225YGC-

×××

-8BT, and

PD784225YGK-

×××

-9EU are undetermined because these products are under development.

Table 16-1. Soldering Conditions for Surface Mount Type

(1)

PD784225GC-

×××

-8BT: 80-pin plastic QFP (14

14 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or

IR35-00-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 20 hours)

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or

VP15-00-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 20 hours)

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120

C max. (package surface temperature)

Exposure limit: 7 days

Note

(after that, prebake at 125

C for 20 hours)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Caution

Do not use different soldering methods together (except for partial heating).

(2)

PD784224GK-

×××

-9EU: 80-pin plastic TQFP (fine pitch) (14

20 mm)

PD784225GK-

×××

-9EU: 80-pin plastic TQFP (fine pitch) (14

20 mm)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or

IR35-103-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 20 hours)

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or

VP15-103-2

higher), Count: Two times or less, Exposure limit: 7 days

Note

(after that,

prebake at 125

C for 20 hours)

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120

C max. (package surface temperature)

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Caution

Do not use different soldering methods together (except for partial heating).

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD784225. Also see (5).

(1) Language Processing Software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784225

Device file common to

PD784225, 784225Y Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) Flash Memory Writing Tools

Flashpro II

Dedicated flash programmer for microcontroller incorporating flash memory

(Part No.: FL-PR2),

Flashpro III

(Part No.: FL-PR3, PG-FP3)

FA-80GC

Adapter for writing 80-pin plastic QFP (GC-8BT type) flash memory.

FA-80GK

Adapter for writing 80-pin plastic LQFP (GK-BE9 type) flash memory.

(3) Debugging Tools

When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-CD-IF-A

PC card and cable when notebook PC is used as host machine (PCMCIA socket supported)

IE-70000-PC-IF-C

Interface adapter when using IBM PC/AT

or compatible as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter when using PC that incorporates PCI bus as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784225, 784225Y Subseries

NP-100GF

Emulation probe for 100-pin plastic QFP (GF-3BA type)

NP-100GC

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784225

Device file common to

PD784225, 784225Y Subseries

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

When IE-784000-R in-circuit emulator is used

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-C

Interface adapter used when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-PC-IF-C

Interface adapter when using IBM PC/AT or compatible as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter when using PC that incorporates PCI bus as host machine

IE-78000-R-SV3

Interface adapter and cable used when EWS is used as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784225, 784225Y Subseries

IE-784218-R-EM1

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX3

Emulation probe conversion board necessary when using IE-784225-NS-EM1 on IE-

784000-R. Not necessary when IE-784216-R-EM1 is used.

EP-78064GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EP-78064GC-R

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-

pin plastic LQFP (GC-8EU type) can be mounted

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784225

Device file common to

PD784225, 784225Y Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

(5) Cautions on Using Development Tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784225.

The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito

Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).

The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

For further information, contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (TEL: +81-3-3820-7112)

Osaka Electronic Division (TEL: +81-6-6244-6672)

For third-party development tools, see the 78K/IV Series Selection Guide (U13355E).

The host machine and OS suitable for each software are as follows:

Host Machine

EWS

[OS]

PC-9800 series [Windows]

HP9000 series 700

[HP-UX

]

IBM PC/AT and compatibles

SPARCstation

[SunOS

, Solaris

]

Software

[Japanese/English Windows]

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

Note DOS-based software

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

APPENDIX B. RELATED DOCUMENTS

Documents related to device

Document Name

Document No.

Japanese

English

PD784224, 784225, 784224Y, 784225Y Data Sheet

U12376J

This document

PD78F4225, 78F4225Y Data Sheet

U12377J

Planned

PD784225, 784225Y Subseries User's Manual - Hardware

Planned

PD784225Y Subseries Special Function Register Table

Planned

78K/IV Series User's Manual - Instruction

U10905J

U10905E

78K/IV Series Instruction Table

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note - Software Basics

U10095J

U10095E

Documents related to development tools (User's Manuals)

Document Name

Document No.

Japanese

English

RA78K4 Assembler Package

Operation

U11334J

U11334E

Language

U11162J

U11162E

RA78K Series Structured Assembler Preprocessor

U11743J

U11743E

CC78K4 C Compiler

Operation

U11572J

U11572E

Language

U11571J

U11571E

IE-78K4-NS

U13356J

U13356E

IE-784000-R

U12903J

U12903E

IE-784218-R-EM1

U12155J

U12155E

IE-784225-NS-EM1

U13742J

U13742E

EP-78064

EEU-934

EEU-1469

SM78K4 System Simulator - Windows Base

Reference

U10093J

U10093E

SM78K Series System Simulator

External component

U10092J

U10092E

user open interface

specification

ID78K4-NS Integrated Debugger - PC Base

Reference

U12796J

U12796E

ID78K4 Integrated Debugger - Windows Base

Reference

U10440J

U10440E

ID78K4 Integrated Debugger - HP-UX, SunOS,

Reference

U11960J

U11960E

NEWS-OS Base

Caution

The contents of the above related documents are subject to change without notice. Be sure to

use the latest edition of a document for designing.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

IEBus is a trademark of NEC Corporation.

Windows is a registered trademark or a trademark of Microsoft Corporation in the United States and/or other

countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

Caution This product contains an I

C bus interface circuit.

When using the I

C bus interface, notify its use to NEC when ordering custom code. NEC can

guarantee the following only when the customer informs NEC of the use of the interface:
Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use

these components in an I

C system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

PD784224, 784225, 784224Y, 784225Y

Data Sheet U12376EJ1V0DS00

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829

J99.1

PD784224, 784225, 784224Y, 784225Y

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability

and additional information.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.

Descriptions of circuits, software, and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.

M7D 98. 12

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