Document Outline

COVER
Table of Contents
ORDERING INFORMATION
FUNCTIONS
DIFFERENCES AMONG MODELS IN uPD784225 SUBSERIES
MAJOR DIFFERENCES BETWEEN uPD784225 SUBSERIES, AND uPD784216
- SUBSERIES AND mPD780058 SUBSERIES
PIN CONFIGURATION (Top View)
BLOCK DIAGRAM
PIN FUNCTION
- 5.1 Port Pins
- 5.2 Pins Other Than Port Pins
- 5.3 I/ O Circuit Type of Respective Pins and Recommended Connections of Unused Pins
CPU ARCHITECTURE
- 6.1 Memory Space
- 6.2 CPU Registers
  - 6.2.1 General-purpose registers
  - 6.2.2 Control registers
  - 6.2.3 Special function registers (SFRs)
PERIPHERAL HARDWARE FUNCTIONS
- 7.1 Ports
- 7.2 Clock Generation Circuit
- 7.3 Real-Time Output Port
- 7.4 Timer/ Counter
- 7.5 A/ D Converter
- 7.6 D/ A Converter
- 7.7 Serial Interface
  - 7.7.1 Asynchronous serial interface/ 3-wire serial I/ O (UART/ IOE)
  - 7.7.2 Clocked serial interface (CSI)
- 7.8 Clock Output Function
- 7.9 Buzzer Output Function
- 7.10 Edge Detection Function
- 7.11 Watch Timer
- 7.12 Watchdog Timer
INTERRUPT FUNCTION
- 8.1 Interrupt Sources
- 8.2 Vectored Interrupt
- 8.3 Context Switching
- 8.4 Macro Service
- 8.5 Application Example of Macro Service
LOCAL BUS INTERFACE
- 9.1 Memory Expansion
- 9.2 Programmable Wait
- 9.3 External Access Status Function
STANDBY FUNCTION
RESET FUNCTION
ROM CORRECTION
INSTRUCTION SET
PACKAGE DRAWINGS
APPENDIX A.DEVELOPMENT TOOLS
APPENDIX B.RELATED DOCUMENTS

1997

PRELIMINARY PRODUCT INFORMATION

MOS INTEGRATED CIRCUIT

PD784224, 784225

16/8-BIT SINGLE-CHIP MICROCONTROLLERS

DESCRIPTION

The

PD784225 is a 80-pin general-purpose microcontroller which is function limited version of the

PD784216

with an added ROM correction function.

Flash memory versions, such as

PD78F4225, that can operate in the same voltage range as the mask ROM

version, and various development tools are under development.

The functions are explained in detail in the following user's manuals. Be sure to read this manual when

designing your system.

PD784225, 784225Y Subseries User's Manual - Hardware : Planned

78K/IV Series User's Manual - Instruction

: U10905E

FEATURES

· ROM correction function

· Inherits peripheral functions of

PD780058 subseries

· Pin-compatible with

PD784225Y subseries

· Minimum instruction execution time

160 ns (main system clock f

= 12.5 MHz)

s (subsystem clock f

= 32.768 kHz)

· I/O port: 67 pins

· Timer/counter: 16-bit timer/counter

1 unit

8-bit timer/counter

4 units

· Serial interface: 3 channels

UART/IOE (3-wire serial I/O): 2 channels

CSI (3-wire serial I/O): 1 channel

· Standby function

HALT/STOP/IDLE mode

In power-saving mode: HALT/IDLE mode (with

subsystem clock)

· Clock division function

· Watch timer: 1 channel

· Watchdog timer: 1 channel

· Clock output function

, f

/2, f

, f

selectable

· Buzzer output function

, f

selectable

· A/D converter: 8-bit resolution

8 channels

· D/A converter: 8-bit resolution

2 channels

· Supply voltage: V

= 1.8 to 5.5 V

Document No. U12498EJ1V0PM00 (1st edition)
Date Published June 1997 N
Printed in Japan

APPLICATION FIELD

Car audio, portable audio, telephones, etc.

Unless otherwise specified, the

PD784225 is treated as the representative model in this document.

The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.

PD784224, 784225

ORDERING INFORMATION

Part Number

Package

Internal ROM (Bytes) Internal RAM (Bytes)

PD784224GC-

¥¥¥

-8BT

80-pin plastic QFP (14

14 mm)

96 K

3584

PD784224GK-

¥¥¥

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

96 K

3584

PD784225GC-

¥¥¥

-8BT

80-pin plastic QFP (14

14 mm)

128 K

4352

PD784225GK-

¥¥¥

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

128 K

4352

Remark

¥¥¥

indicates a ROM code suffix.

78K/IV Series Product Development

PD784026

Enhanced A/D, 16-bit timer,
power management

ASSP development

PD784908

PD784915

PD784038Y

C bus compatible model

PD784038

PD784225Y

Multi-master I

C bus

compatible model

Multi-master I

C bus

compatible model

Multi-master I

C bus

compatible model

Enhanced internal memory capacity,
pin-compatible with PD784026

Enhanced internal memory capacity
ROM correction added

100 pins, enhanced I/O and
internal memory capacity

Multi-master I

C bus

compatible model

With IEBus

controller

For CD-ROM,
Flash memory: 56 KB

With software servo control,
analog circuit for VCRs,
enhanced timer

Enhanced functions of
PD784915

With 10-bit A/D

80 pins
ROM correction added

PD784225

PD784216Y

PD784216

PD784928Y

PD784928

PD784218Y

PD784218

PD784054

PD784046

PD78F4943

: Under mass production

: Under development

Standard development

PD784224, 784225

FUNCTIONS

Part Number

PD784224

PD784225

Item

Number of basic instructions

113

(mnemonics)

General-purpose register

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

Minimum instruction execution

· 160 ns/320 ns/640 ns/1280 ns/2560 ns (main system clock: f

= 12.5 MHz)

time

· 61

s (subsystem clock: f

= 32.768 KHz)

Internal

ROM

96 KBytes

128 KBytes

memory

RAM

3584 Bytes

4352 Bytes

Memory space

1 MB with program and data spaces combined

I/O port

Total

CMOS input

CMOS I/O

Pins with pull-up

resistor

LEDs direct

drive output

Real-time output port

4 bits

2, or 8 bits

Timer/counter

16-bit timer/counter : timer register

Pulse output

Capture/compare register

· PWM/PPG output
· Square wave output
· One-shot pulse output

8-bit timer/counter 1 : timer register

Pulse output

Compare register

· PWM output
· Square wave output

8-bit timer/counter 2 : timer register

Pulse output

Compare register

· PWM output
· Square wave output

8-bit timer/counter 5 : timer register

Compare register

8-bit timer/counter 6 : timer register

Compare register

Serial interface

· UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)
· CSI (3-wire serial I/O): 1 channel

A/D converter

8-bit resolution

8 channels

D/A converter

8-bit resolution

2 channels

Clock output

Selectable from f

, f

/2, f

, f

Buzzer output

Selectable from f

, f

Watch timer

1 channel

Watchdog timer

1 channel

Standby

· HALT/STOP/IDLE mode
· In power-saving mode (with subsystem clock): HALT/IDLE mode

Interrupt

Hardware

25 (internal: 18, external: 7)

Software

BRK instruction, BRKCS instruction, operand error

Non-maskable

Internal: 1, external: 1

Maskable

Internal: 17, external: 6

· 4 programmable priority levels
· 3 service modes: vectored interrupt/macro service/context switching

Supply voltage

= 1.8 to 5.5 V

Package

· 80-pin plastic QFP(14

14 mm)

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

Note The pins with ancillary functions are included in the I/O pins.

Pins with

ancillary

functions

Note

PD784224, 784225

CONTENTS

DIFFERENCES AMONG MODELS IN

PD784225 SUBSERIES ............................................... 6

MAJOR DIFFERENCES BETWEEN

PD784225 SUBSERIES, AND

PD784216

SUBSERIES AND

PD780058 SUBSERIES ............................................................................... 7

PIN CONFIGURATION (Top View) .............................................................................................. 8

BLOCK DIAGRAM ............................................................................................................... ........ 10

PIN FUNCTION .............................................................................................................................. 11

5.1

Port Pins ................................................................................................................................................ 11

5.2

Pins Other Than Port Pins .................................................................................................................. 13

5.3

I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins ........... 15

CPU ARCHITECTURE ................................................................................................................... 18

6.1

Memory Space ...................................................................................................................................... 18

6.2

CPU Registers ...................................................................................................................................... 21

6.2.1 General-purpose registers ............................................................................................................ 21

6.2.2 Control registers ............................................................................................................................ 22

6.2.3 Special function registers (SFRs) ................................................................................................. 23

PERIPHERAL HARDWARE FUNCTIONS ................................................................................... 28

7.1 Ports ......................................................................................................................................................... 28

7.2 Clock Generation Circuit ....................................................................................................................... 29

7.3 Real-Time Output Port ........................................................................................................................... 31

7.4 Timer/Counter .......................................................................................................................................... 32

7.5 A/D Converter .......................................................................................................................................... 35

7.6 D/A Converter .......................................................................................................................................... 36

7.7 Serial Interface ........................................................................................................................................ 37

7.7.1

Asynchronous serial interface/3-wire serial I/O (UART/IOE) ...................................................... 38

7.7.2

Clocked serial interface (CSI) ..................................................................................................... 40

7.8

Clock Output Function ........................................................................................................................ 40

7.9

Buzzer Output Function ...................................................................................................................... 41

7.10 Edge Detection Function .................................................................................................................... 41

7.11 Watch Timer .......................................................................................................................................... 41

7.12 Watchdog Timer ................................................................................................................................... 42

INTERRUPT FUNCTION ............................................................................................................... 43

8.1

Interrupt Sources ................................................................................................................................. 43

8.2

Vectored Interrupt ................................................................................................................................ 45

8.3

Context Switching ................................................................................................................................ 46

8.4

Macro Service ....................................................................................................................................... 46

8.5

Application Example of Macro Service ............................................................................................. 47

PD784224, 784225

LOCAL BUS INTERFACE ............................................................................................................. 48

9.1

Memory Expansion .............................................................................................................................. 48

9.2

Programmable Wait ............................................................................................................................. 48

9.3

External Access Status Function ...................................................................................................... 48

10. STANDBY FUNCTION ................................................................................................................... 49

11. RESET FUNCTION ........................................................................................................................ 51

12. ROM CORRECTION ..................................................................................................................... 52

13. INSTRUCTION SET ....................................................................................................................... 53

14. PACKAGE DRAWINGS ............................................................................................................ ..... 58

APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 60

APPENDIX B. RELATED DOCUMENTS ............................................................................................ 62

PD784224, 784225

2. MAJOR DIFFERENCES BETWEEN

PD784225 SUBSERIES, AND

PD784216 SUBSERIES AND

PD780058 SUBSERIES

Series Name

PD784225 Subseries

PD784216 Subseries

PD780058 Subseries

Item

CPU

16-bit CPU

8-bit-CPU

Minimum

With main system

160 ns (at 12.5 MHz)

400 ns (at 5.0 MHz)

instruction

clock selected

execution time

With subsystem

s (at 32.768 kHz)

122

s (at 32.768 kHz)

clock

Memory space

1M bytes

64K bytes

I/O port

Total

67 pins

86 pins

68 pins

CMOS input

8 pins

2 pins

CMOS I/O

59 pins

72 pins

62 pins

N-ch open-drain I/O

6 pins

4 pins

Pins with

Pins with pull-up

57 pins

70 pins

66 pins (flash memory

ancillary

resistor

model: 62 pins)

function

Note

LED direct drive

16 pins

22 pins

12 pins

output

Medium-voltage pin

6 pins

4 pins

Timer/counter

· 16-bit timer/counter

1 unit

· 16-bit timer/counter

1 unit

· 16-bit timer/counter

1 unit

· 8-bit timer/counter

4 units

· 8-bit timer/counter

6 units

· 8-bit timer/counter

2 units

Serial interface

· UART/IOE (3-wire serial I/O)

2 channels

· UART (time-division transfer

· CSI (3-wire serial I/O)

1 channel

function)/IOE (3-wire

serial I/O)

2 channels

· CSI (3-wire serial I/O,

2-wire serial I/O, SBI)

1 channel

· CSI (3-wire serial I/O

with automatic

transmission/reception

function)

1 channel

Interrupt

NMI pin

Provided

None

Macro service

Provided

None

Context switching

Provided

None

Programmable priority 4 levels

2 levels

Standby function

· HALT/STOP/IDLE mode

HALT/STOP mode

· Power-saving mode: HALT/IDLE Mode

ROM correction

Provided

None

Provided

Package

· 80-pin plastic QFP

· 100-pin plastic QFP

· 80-pin plastic QFP

(14

14 mm)

(fine pitch) (14

14 mm)

(14

14 mm)

· 80-pin plastic TQFP

· 100-pin plastic QFP

· 80-pin plastic TQFP

(fine pitch) (12

12 mm)

(14

20 mm)

(fine pitch) (12

12 mm)

Note Pins with ancillary function are included in the I/O pins.

PD784224, 784225

3. PIN CONFIGURATION (Top View)

· 80-pin plastic QFP (14

14 mm)

PD784224GC-

¥¥¥

-8BT

PD784225GC-

¥¥¥

-8BT

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD784224GK-

¥¥¥

-BE9

PD784225GK-

¥¥¥

-BE9

P15/ANI5

P16/ANI6

P17/ANI7

P130/ANO0

P131/ANO1

REF1

P70/SI2/RxD2

P71/SO2/TxD2

P72/SCK2/ASCK2

P20/SI1/RxD1

P21/SO1/TxD1

P22/SCK1/ASCK1

P23/PCL

P24/BUZ

P25/SI0

P26/SO0

P27/SCK0

P40/AD0

P41/AD1

RESET

P127/RTP7

P126/RTP6

P125/RTP5

P124/RTP4

P123/RTP3

P122/RPT2

P121/RTP1

P120/RTP0

P37/EXA

P36/TI01

P35/TI00

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P67/ASTB

P66/WAIT

P65/WR

P42/AD2

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

SS1

P56/A14

P57/A15

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

A14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

DD0

XT1

XT2

TEST

DD1

SS0

P05/INTP5

P04/INTP4

P03/INTP3

P02/INTP2/NMI

P01/INTP1

P00/INTP0

Caution Connect the AV

pin to V

SS0

Remark When using in applications where noise from inside the microcomputer has to be reduced, it is

recommended to take countermeasures against noise such as supplying power to V

DD0

and V

DD1

independently, and connecting V

SS0

and V

SS1

to different ground lines.

PD784224, 784225

A8-A19

: Address Bus

AD0-AD7

: Address/Data Bus

ANI0-ANI7

: Analog Input

ANO0, ANO1

: Analog Output

ASCK1, ASCK2

: Asynchronous Serial Clock

ASTB

: Address Strobe

: Analog Power Supply

REF1

: Analog Reference Voltage

: Analog Ground

BUZ

: Buzzer Clock

EXA

: External Access Status Output

INTP0-INTP5

: Interrupt from Peripherals

NMI

: Non-maskable Interrupt

P00-P05

: Port0

P10-P17

: Port1

P20-P27

: Port2

P30-P37

: Port3

P40-P47

: Port4

P50-P57

: Port5

P60-P67

: Port6

P70-P72

: Port7

P120-P127

: Port12

P130, P131

: Port13

PCL

: Programmable Clock

: Read Strobe

RESET

: Reset

RTP0-RTP7

: Real-time Output Port

RxD1, RxD2

: Receive Data

SCK0-SCK2

: Serial Clock

SI0-SI2

: Serial Input

SO0-SO2

: Serial Output

TEST

: Test

TI00, TI01, TI1, TI2 : Timer Input

TO0-TO2

: Timer Output

TxD1, TxD2

: Transmit Data

DD0

, V

DD1

: Power Supply

SS0

, V

SS1

: Ground

WAIT

: Wait

: Write Strobe

X1, X2

: Crystal (Main System Clock)

XT1, XT2

: Crystal (Subsystem Clock)

1 1

PD784224, 784225

5. PIN FUNCTION

5.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00

I/O

INTP0

P01

INTP1

P02

INTP2/NM1

P03

INTP3

P04

INTP4

P05

INTP5

P10-P17

Input

ANI0-ANI7

P20

I/O

RxD1/SI1

P21

TxD1/SO1

P22

ASCK1/SCK1

P23

PCL

P24

BUZ

P25

SI0

P26

SO0

P27

SCK0

P30

I/O

TO0

P31

TO1

P32

TO2

P33

TI1

P34

TI2

P35

TI00

P36

TI01

P37

EXA

P40-P47

I/O

AD0-AD7

Port 4 (P4):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· All pins set in input mode can be connected to internal pull-up

resistors by software.

· Can drive LEDs.

P50-P57

I/O

A8-A15

Port 5 (P5):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· All pins set in input mode can be connected to internal pull-up

resistors by software.

· Can drive LEDs.

Port 1 (P1):

· 8-bit input port

Port 0 (P0):

· 6-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

Port 2 (P2):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

Port 3 (P3):

· 8-bit I/O port

· Can be set in input or output mode bit-wise.

· Pins set in input mode can be connected to internal pull-up

resistors by software bit-wise.

1 3

PD784224, 784225

5.2 Pins Other Than Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

Input

P35

External count clock input to 16-bit timer register

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer register 1

TI2

P34

External count clock input to 8-bit timer register 2

TO0

Output

P30

16-bit timer output (shared by 14-bit PWM output)

TO1

P31

8-bit timer output (shared by 8-bit PWM output)

TO2

P32

RxD1

Input

P20/SI1

Serial data input (UART1)

RxD2

P70/SI2

Serial data input (UART2)

TxD1

Output

P21/SO1

Serial data output (UART1)

TxD2

P71/SO2

Serial data output (UART2)

ASCK1

Intput

P22/SCK1

Baud rate clock input (UART1)

ASCK2

P72/SCK2

Baud rate clock input (UART2)

SI0

Input

P25

Serial data input (3-wire serial clock I/O0)

SI1

P20/RxD1

Serial data input (3-wire serial clock I/O1)

SI2

P70/RxD2

Serial data input (3-wire serial clock I/O2)

SO0

Output

P26

Serial data output (3-wire serial I/O0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O1)

SO2

P71/TxD2

Serial data output (3-wire serial I/O2)

SCK0

I/O

P27

Serial clock input/output (3-wire serial I/O0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O2)

NMI

Input

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

External interrupt request input

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0-RTP7

Output

P120-P127

Real-time output port that outputs data in synchronization with

trigger

AD0-AD7

I/O

P40-P47

Low-order address/data bus when external memory is connected

A8-A15

Output

P50-P57

Middle-order address bus when external memory is connected

A16-A19

P60-P63

High-order address bus when external memory is connected

1 4

PD784224, 784225

5.2 Pins Other Than Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

Output

P64

Strobe signal output for read operation of external memory

P65

Strobe signal output for write operation of external memory

WAIT

Input

P66

To insert wait state(s) when external memory is accessed

ASTB

Output

P67

Strobe output to externally latch address information output to ports

4 through 6 to access external memory

EXA

Output

P37

External access status output

RESET

Input

System reset input

Input

To connect main system clock oscillation crystal

XT1

Input

To connect subsystem clock oscillation crystal

XT2

ANI0-ANI7

Input

P10-P17

Analog voltage input for A/D converter

ANO0, ANO1

Output

P130, P131

Analog voltage output for D/A converter

REF1

To apply reference voltage for D/A converter

Positive power supply for A/D converter. Connected to V

DD0

GND for A/D converter and D/A converter. Connected to V

SS0

DD0

Positive power supply for port block

SS0

GND potential for port block

DD1

Positive power supply (except port block)

SS1

GND potential (except port block)

TEST

Directly connect this pin to V

SS0

(this pin is for IC test).

1 5

PD784224, 784225

5.3 I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins

Table 5-1 shows symbols indicating the I/O circuit types of the respective pins and the recommended connection

of unused pins.

For the circuit diagram of each type of I/O circuit, refer to Figure 5-1.

Table 5-1. I/O Circuit Type of Respective Pins and Recommended Connections of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connections of Unused Pins

P00/INTP0

8-C

I/O

Input : Individually connected to V

SS0

via resistor

P01/INTP1

Output: Open

P02/INTP2/NMI

P03/INTP3-P05/INTP5

P10/ANI0-P17/ANI7

Input

Connected to V

SS0

or V

DD0

P20/RxD1/SI1

10-B

I/O

Input : Individually connected to V

SS0

via resistor

P21/TxD1/SO1

Output: Open

P22/ASCK1/SCK1

P23/PCL

P24/BUZ

P25/SI0

P26/SO0

P27/SCK0

P30/TO0-P32/TO2

8-C

P33/TI1, P34/TI2

P35/TI00, P36/TI01

P37/EXA

P40/AD0-P47/AD7

5-H

P50/A8-P57/A15

P60/A16-P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P70/RxD2/SI2

8-C

P71/TxD2/SO2

P72/ASCK2/SCK2

P120/RTP0-P127/RTP7

P130/ANO0, P131/ANO1

12-C

RESET

Input

XT1

Connected to V

SS0

XT2

Open

1 8

PD784224, 784225

6. CPU ARCHITECTURE

6.1 Memory Space

A memory space of 1 MByte can be accessed. Mapping of the internal data area (special function registers and

internal RAM) can be specified the LOCATION instruction. The LOCATION instruction must be always executed

after RESET cancellation, and must not be used more than once.

(1) When LOCATION 0 instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784224

0F100H-0FFFFH

00000H-0F0FFH

10000H-17FFFH

PD784225

0EE00H-0FFFFH

00000H-0EDFFH

10000H-1FFFFH

Caution

The following areas that overlap the internal data area of the internal ROM cannot be used when

the LOCATION 0 instruction is executed.

Part Number

Unusable Area

PD784224

0F100H-0FFFFH (3840 Bytes)

PD784225

0EE00H-0FFFFH (4608 Bytes)

· External memory

The external memory is accessed in external memory expansion mode.

(2) When LOCATION 0FH instruction is executed

· Internal memory

The internal data area and internal ROM area are mapped as follows:

Part Number

Internal Data Area

Internal ROM Area

PD784224

FF100H-FFFFFH

00000H-17FFFH

PD784225

FEE00H-FFFFFH

00000H-1FFFFH

· External memory

The external memory is accessed in external memory expansion mode.

PD784224, 784225

Notes 1. Accessed in external memory expansion mode.

2. This 3840-Byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0 instruction: 94464 Bytes, on execution of LOCATION 0FH instruction: 98304 Bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Figure 6-1. Memory Map of

PD784224

Internal ROM
(61696 Bytes)

(256 Bytes)

Special function registers (SFR)

Internal RAM
(3584 Bytes)

External memory

Note 1

(928 KBytes)

Note 1

General-purpose
registers (128 Bytes)

Macro service control word
area (52 Bytes)

Data area (512 Bytes)

Program/data area
(3072 Bytes)

CALLF entry
area (2 KBytes)

Program/data area

Note 3

CALLT table
area (64 Bytes)

Vector table area
(64 Bytes)

Internal RAM
(3584 Bytes)

External memory

Note 1

(980736 Bytes)

(256 Bytes)

Internal ROM
(96 KBytes)

On execution of

LOCATION 0 instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Note 2

Internal ROM

(32768 Bytes)

PD784224, 784225

Figure 6-2. Memory Map of

PD784225

Notes 1. Accessed in external memory expansion mode.

2. This 4608-Byte area can be used as an internal ROM only when the LOCATION 0FH instruction is executed.

3. On execution of LOCATION 0 instruction: 126464 Bytes, on execution of LOCATION 0FH instruction: 131072 Bytes

4. Base area and entry area for reset or interrupt. However, the internal RAM area is not used as a reset entry area.

Internal ROM
(60928 Bytes)

(256 Bytes)

Special function registers (SFR)

Internal RAM
(4352 Bytes)

External memory

Note 1

(896KBytes)

Note 1

General-purpose
registers (128 Bytes)

Macro service control word
area (52 Bytes)

Data area (512 Bytes)

Program/data area
(3840 Bytes)

CALLF entry
area (2 KBytes)

Program/data area

Note 3

CALLT table
area (64 Bytes)

Vector table area
(64 Bytes)

Internal RAM
(4352 Bytes)

External memory

Note 1

(912896 Bytes)

(256 Bytes)

Internal ROM
(128 KBytes)

On execution of

LOCATION 0 instruction

Special function registers (SFR)

Note 1

On execution of

LOCATION 0FH instruction

Note 4

Internal ROM
(65536 Bytes)

Note 2

2 1

PD784224, 784225

6.2 CPU Registers

6.2.1 General-purpose registers

Sixteen 8-bit general-purpose registers are available. Two 8-bit registers can be also used in pairs as a 16-bit

24-bit address specification registers.

Eight banks of these registers are available which can be selected by using software or the context switching

function.

The general-purpose registers except V, U, T, and W registers for address expansion are mapped to the internal

RAM.

Figure 6-3. General-Purpose Register Format

A (R1)

B (R3)

R11

D (R13)

H (R15)

VVP (RG4)

UUP (RG5)

TDE (RG6)

WHL (RG7)

X (R0)

C (R2)

R10

E (R12)

L (R14)

AX (RP0)

BC (RP1)

RP2

RP3

VP (RP4)

UP (RP5)

DE (RP6)

HL (RP7)

Parentheses ( ) indicate an absolute name.

8 banks

Caution

Registers R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers,

respectively, by setting the RSS bit of the PSW to 1. However, use this function only for recycling

the program of the 78K/III Series.

2 3

PD784224, 784225

6.2.3 Special function registers (SFRs)

The special function registers, such as the mode registers and control registers of the internal peripheral

hardware, are registers to which special functions are allocated. These registers are mapped to a 256-Byte space

of addresses 0FF00H through 0FFFFH

Note

Note On execution of the LOCATION 0 instruction. FFF00H through FFFFFH on execution of the LOCATION

0FH instruction.

Caution

Do not access an address in this area to which no SFR is allocated. If such an address is accessed

by mistake, the

PD784225 may be in the deadlock status. This deadlock status can be cleared

only by inputting the RESET signal.

Table 6-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows:

Symbol ...............................

Symbol indicating an SFR. This symbol is reserved for NEC's assembler

(RA78K4). It can be used an sfr variable by the #pragma sfr directive with the

C compiler (CC78K4).

R/W ....................................

Indicates whether the SFR is read-only, write-only, or read/write.

R/W : Read/write

: Read-only

: Write-only

Bit units for manipulation ..

Bit units in which the value of the SFR can be manipulated.

SFRs that can be manipulated in 16-bit units can be described as the

operand sfrp of an instruction. To specify the address of this SFR, describe

an even address.

SFRs that can be manipulated in 1-bit units can be described as the operand

of a bit manipulation instruction.

At reset ..............................

Indicates the status of the register when the RESET signal has been input.

2 4

PD784224, 784225

Table 6-1. Special Function Register (SFR) List (1/4)

Address

Note 1

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 bit

8 bits

16 bits

0FF00H

Port 0

R/W

00H

Note 2

0FF01H

Port 1

0FF02H

Port 2

R/W

0FF03H

Port 3

0FF04H

Port 4

0FF05H

Port 5

0FF06H

Port 6

0FF07H

Port 7

0FF0CH

Port 12

P12

0FF0DH

Port 13

P13

0FF10H

16-bit timer register

TM0

0000H

0FF11H

0FF12H

Capture/compare register 00

CR00

R/W

0FF13H

(16-bit timer/counter)

0FF14H

Capture/compare register 01

CR01

0FF15H

(16-bit timer/counter)

0FF16H

Capture/compare control register 0

CRC0

00H

0FF18H

16-bit timer mode control register

TMC0

0FF1AH

16-bit timer output control register

TOC0

0FF1CH

Prescaler mode register 0

PRM0

0FF20H

Port 0 mode register

PM0

FFH

0FF22H

Port 2 mode register

PM2

0FF23H

Port 3 mode register

PM3

0FF24H

Port 4 mode register

PM4

0FF25H

Port 5 mode register

PM5

0FF26H

Port 6 mode register

PM6

0FF27H

Port 7 mode register

PM7

0FF2CH

Port 12 mode register

PM12

0FF2DH

Port 13 mode register

PM13

0FF30H

Pull-up resistor option register 0

PU0

00H

0FF32H

Pull-up resistor option register 2

PU2

0FF33H

Pull-up resistor option register 3

PU3

0FF37H

Pull-up resistor option register 7

PU7

0FF3CH

Pull-up resistor option register 12

PU12

0FF40H

Clock output control register

CKS

Notes 1. When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION

0FH instruction is executed.

2. Because each port is initialized to input mode at reset, "00H" is not actually read. The output latch

is initialized to "0".

2 5

PD784224, 784225

Table 6-1. Special Function Register (SFR) List (2/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 bit

8 bits

16 bits

0FF42H

Port function control register

PF2

R/W

00H

0FF4EH

Pull-up resistor option register

PUO

0FF50H

8-bit timer register 1

TM1

TM1W

0000H

0FF51H

8-bit timer register 2

TM2

0FF52H

Compare register 10 (8-bit timer/counter 1)

CR10 CR1W

R/W

0FF53H

Compare register 20 (8-bit timer/counter 2)

CR20

0FF54H

8-bit timer mode control register 1

TMC1 TMC1W

0FF55H

8-bit timer mode control register 2

TMC2

0FF56H

Prescaler mode register 1

PRM1 PRM1W

0FF57H

Prescaler mode register 2

PRM2

0FF60H

8-bit timer register 5

TM5 TM5W

0FF61H

8-bit timer register 6

TM6

0FF64H

Compare register 50 (8-bit timer/counter 5)

CR50 CR5W

R/W

0FF65H

Compare register 60 (8-bit timer/counter 6)

CR60

0FF68H

8-bit timer mode control register 5

TMC5 TMC5W

0FF69H

8-bit timer mode control register 6

TMC6

0FF6CH

Prescaler mode register 5

PRM5 PRM5W

0FF6DH

Prescaler mode register 6

PRM6

0FF70H

Asynchronous serial interface mode register 1

ASIM1

00H

0FF71H

Asynchronous serial interface mode register 2

ASIM2

0FF72H

Asynchronous serial interface status register 1

ASIS1

0FF73H

Asynchronous serial interface status register 2

ASIS2

0FF74H

Transmit shift register 1

TXS1

FFH

Receive buffer register 1

RXB1

0FF75H

Transmit shift register 2

TXS2

Receive buffer register 2

RXB2

0FF76H

Baud rate generator control register 1

BRGC1

R/W

00H

0FF77H

Baud rate generator control register 2

BRGC2

0FF7AH

Oscillation mode select register

0FF80H

A/D converter mode register

ADM

0FF81H

A/D converter input select register

ADIS

0FF83H

A/D conversion result register

ADCR

Undefined

0FF84H

D/A conversion value setting register 0

DACS0

R/W

00H

0FF85H

D/A conversion value setting register 1

DACS1

0FF86H

D/A converter mode register 0

DAM0

0FF87H

D/A converter mode register 1

DAM1

Note When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2 6

PD784224, 784225

Table 6-1. Special Function Register (SFR) List (3/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 bit

8 bits

16 bits

0FF88H

ROM correction control register

CORC

R/W

00H

0FF89H

ROM correction address pointer H

CORAH

0FF8AH

ROM correction address pointer L

CORAL

0000H

0FF8BH

0FF8DH

External access status enable register

EXAE

00H

0FF90H

Serial operation mode register 0

CSIM0

0FF91H

Serial operation mode register 1

CSIM1

0FF92H

Serial operation mode register 2

CSIM2

0FF94H

Serial I/O shift register 0

SIO0

0FF95H

Serial I/O shift register 1

SIO1

0FF96H

Serial I/O shift register 2

SIO2

0FF98H

Real-time output buffer register L

RTBL

0FF99H

Real-time output buffer register H

RTBH

0FF9AH

Real-time output port mode register

RTPM

0FF9BH

Real-time output port control register

RTPC

0FF9CH

Watch timer mode control register

WTM

0FFA0H

External interrupt rising edge enable register

EGP0

0FFA2H

External interrupt falling edge enable register

EGN0

0FFA8H

In-service priority register

ISPR

0FFA9H

Interrupt select control register

SNMI

R/W

0FFAAH

Interrupt mode control register

IMC

80H

0FFACH

Interrupt mask flag register 0L

MK0L MK0

FFFFH

0FFADH

Interrupt mask flag register 0H

MK0H

0FFAEH

Interrupt mask flag register 1L

MK1L MK1

0FFAFH

Interrupt mask flag register 1H

MK1H

0FFC0H

Standby control register

STBC

30H

0FFC2H

Watchdog timer mode register

WDM

00H

0FFC4H

Memory expansion mode register

20H

0FFC7H

Programmable wait control register 1

PWC1

AAH

00FFCEH

Clock status register

PCS

32H

0FFCFH

Oscillation stabilization time specification register

OSTS

R/W

00H

0FFD0H-

External SFR area

0FFDFH

Note When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2 7

PD784224, 784225

Table 6-1. Special Function Register (SFR) List (4/4)

Address

Note

Special Function Register (SFR) Name

Symbol

R/W

Bit Units for Manipulation

At Reset

1 bit

8 bits

16 bits

0FFE0H

Interrupt control register (INTWDTM)

WDTIC

R/W

43H

0FFE1H

Interrupt control register (INTP0)

PIC0

0FFE2H

Interrupt control register (INTP1)

PIC1

0FFE3H

Interrupt control register (INTP2)

PIC2

0FFE4H

Interrupt control register (INTP3)

PIC3

0FFE5H

Interrupt control register (INTP4)

PIC4

0FFE6H

Interrupt control register (INTP5)

PIC5

0FFE8H

Interrupt control register (INTCSI0)

CSIIC0

0FFE9H

Interrupt control register (INTSER1)

SERIC1

0FFEAH

Interrupt control register (INTSR1/INTCSI1)

SRIC1

0FFEBH

Interrupt control register (INTST1)

STIC1

0FFECH

Interrupt control register (INTSER2)

SERIC2

0FFEDH

Interrupt control register (INTSR2/INTCSI2)

SRIC2

0FFEEH

Interrupt control register (INTST2)

STIC2

0FFEFH

Interrupt control register (INTTM3)

TMIC3

0FFF0H

Interrupt control register (INTTM00)

TMIC00

0FFF1H

Interrupt control register (INTTM01)

TMIC01

0FFF2H

Interrupt control register (INTTM1)

TMIC1

0FFF3H

Interrupt control register (INTTM2)

TMIC2

0FFF4H

Interrupt control register (INTAD)

ADIC

0FFF5H

Interrupt control register (INTTM5)

TMIC5

0FFF6H

Interrupt control register (INTTM6)

TMIC6

0FFF9H

Interrupt control register (INTWT)

WTIC

Note When the LOCATION 0 instruction is executed. Add "F0000H" to this value when the LOCATION 0FH

instruction is executed.

2 9

PD784224, 784225

Table 7-1. Port Functions

Port Name

Pin Name

Function

Specification of Pull-up Resistor

Connection by Software

Port 0

P00-P05

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 1

P10-P17

· Input port

Port 2

P20-P27

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 3

P30-P37

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 4

P40-P47

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

· Can directly drive LEDs

Port 5

P50-P57

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

· Can directly drive LEDs

Port 6

P60-P67

· Can be set in input or output mode bit-wise

Can be specified in 1-port units

Port 7

P70-P72

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 12

P120-P127

· Can be set in input or output mode bit-wise

Can be specified bit-wise

Port 13

P130, P131

· Can be set in input or output mode bit-wise

7.2 Clock Generation Circuit

An on-chip clock generation circuit necessary for operation is provided. This clock generation circuit has a divider

circuit. If high-speed operation is not necessary, the internal operating frequency can be lowered by the divider

circuit to reduce the current consumption.

Figure 7-2. Block Diagram of Clock Generation Circuit

XT2

XT1

STOP

Main system
clock
oscillation
circuit

Subsystem
clock
oscillation
circuit

Watch timer,
clock output function

Clock to
peripheral hardware

CPU
clock
(f

CPU

)

Divider
circuit

Prescaler

Standby
control
circuit

Wait
control
circuit

Selector

3 0

PD784224, 784225

Figure 7-3. Example of Using Main System Clock Oscillation Circuit

External
clock

PD74HCU04

Crystal resorator
or
ceramic resonator

(1) Crystal/ceramic oscillation

(2) External clock

SS1

Figure 7-4. Example of Using Subsystem Clock Oscillation Circuit

32.768

kHz

XT2

XT1

XT2

XT1

External
clock

PD74HCU04

(1) Crystal oscillation

(2) External clock

SS1

Caution

When using the main system clock and subsystem clock oscillation circuit, wire the dotted

portions in Figures 7-3 and 7-4 as follows to avoid adverse influence from wiring capacitance.

Keep the wiring length as short as possible.

Do not cross the wiring with other signal lines.

Do not route the wiring in the vicinity of lines through which a high alternating current flows.

Always keep the potential at the ground point of the capacitor in the oscillation circuit the same

as V

SS1

. Do not ground to a ground pattern through which a high current flows.

Do not extract signals from the oscillation circuit.

Note that the subsystem clock oscillation circuit has a low amplification factor to reduce the

current consumption.

3 5

PD784224, 784225

7.5 A/D Converter

An A/D converter converts an analog input variable into a digital signal. This microcontroller is provided with

an A/D converter with a resolution of 8 bits and 8 channels (ANI0 through ANI7).

This A/D converter is of successive approximation type and the result of conversion is stored to an 8-bit A/D

conversion result register (ADCR).

The A/D converter can be started in the following two ways:

· Hardware start

Conversion is started by trigger input (P03).

· Software start

Conversion is started by setting the A/D converter mode register.

One analog input channel is selected from ANI0 through ANI7 for A/D conversion. When A/D conversion is started

by means of hardware start, conversion is stopped after it has been completed. When conversion is started by

means of software start, A/D conversion is repeatedly executed, and each time conversion has been completed,

an interrupt request (INTAD) is generated.

Figure 7-7. Block Diagram of A/D Converter

ANI0

ANI1

ANI2

ANI3

ANI4

ANI5

ANI6

ANI7

Sample & hold circuit

Series resistor string

Voltage comparator

Successive approximation
register (SAR)

A/D conversion result register

(ADCR)

Control
Circuit

Edge
detection
circuit

INTP3/P03

INTAD

INTP3

Internal bus

Selector

Tap selector

Edge
detection
circuit

4 0

PD784224, 784225

7.7.2 Clocked serial interface (CSI)

In this mode, the master device starts transfer by making the serial clock active and communicates 1-byte data

in synchronization with this clock.

· 3-wire serial I/O mode

This mode is to communicate with devices having the conventional clocked serial interface.

Basically, communication is established in this mode with three lines: one serial clock (SCK0) and two serial

data (SI0 and SO0) lines.

Generally, a handshake line is necessary to check the reception status.

Figure 7-12. Block Diagram in 3-Wise Serial I/O Mode

SI0

SO0

SCK0

INTCSI0

INTTM2
f

/16

Internal bus

Direction control circuit

Interrupt
generation circuit

Selector

Serial clock
counter

Serial clock
control circuit

Serial I/O shift register 0

(SIO0)

7.8 Clock Output Function

Clocks of the following frequencies can be output.

· 97.7 kHz/195 kHz/391 kHz/781 kHz/1.56 MHz/3.13 MHz/6.25 MHz/12.5 MHz

(main system clock: 12.5 MHz)

· 32.768 kHz (subsystem clock: 32.768 kHz)

Figure 7-13. Block Diagram of Clock Output Function

Synchronization
circuit

Output control circuit

PCL

Selector

4 1

PD784224, 784225

7.9 Buzzer Output Function

Clocks of the following frequencies can be output as buzzer output.

· 1.5 kHz/3.1 kHz/6.1 kHz/12.2 kHz (main system clock: 12.5 MHz)

Figure 7-14. Block Diagram of Buzzer Output Function

Output control circuit

BUZ

Selector

7.10 Edge Detection Function

The interrupt input pins (INTP0, INTP1, NMI/INTP2, INTP3 through INTP5) are used not only to input interrupt

requests but also to input trigger signals to the internal hardware units. Because these pins operate at an edge

of the input signal, they have a function to detect an edge. Moreover, a noise reduction circuit is also provided to

prevent erroneous detection due to noise.

Pin Name

Detectable Edge

Noise Reduction

NMI

Either or both of rising and falling edges

By analog delay

INTP0 through INTP5

7.11 Watch Timer

The watch timer has the following functions:

· Watch timer

· Interval timer

The watch timer and interval timer functions can be used at the same time.

(1) Watch timer

The watch timer sets the WTIF flag of the interrupt control register (WTIC) at time intervals of 0.5 seconds

by using the 32.768-kHz subsystem clock.

(2) Interval timer

The interval timer generates an interrupt request (INTTM3) at predetermined time intervals.

4 3

PD784224, 784225

8. INTERRUPT FUNCTION

As the servicing in response to an interrupt request, the three types shown in Table 8-1 can be selected by

program.

Table 8-1. Servicing of Interrupt Request

Servicing Mode

Entity of Servicing

Servicing

Contents of PC and PSW

Vectored interrupt

Software

Branches and executes servicing routine

Saves to and restores

(servicing is arbitrary).

from stack.

Context switching

Automatically switches register bank,

Saves to or restores from

branches and executes servicing routine

fixed area in register bank

(servicing is arbitrary).

Macro service

Firmware

Executes data transfer between memory

Retained

and I/O (servicing is fixed)

8.1 Interrupt Sources

Table 8-2 shows the interrupt sources available. As shown, interrupts are generated by 25 types of sources,

execution of the BRK instruction, BRKCS instruction, or an operand error.

The priority of interrupt servicing can be set to four levels, so that nesting can be controlled during interrupt

servicing and that which of the two or more interrupts that simultaneously occur should be serviced first. When the

macro service function is used, however, nesting always proceeds.

The default priority is the priority (fixed) of the service that is performed if two or more interrupt requests, having

the same request, simultaneously generate (refer to Table 8-2).

4 4

PD784224, 784225

Table 8-2. Interrupt Sources

Type

Default

Source

Internal/

Macro

Priority

Name

Trigger

External

Service

Software

BRK instruction

Instruction execution

BRKCS instruction

Instruction execution

Operand error

If result of exclusive OR between operands
byte and byte is not FFH when MOV STBC,
#byte instruction or MOV WDM, #byte instruc-
tion, LOCATION instruction is executed

Non-maskable

NMI

Pin input edge detection

External

INTWDT

Overflow of watchdog timer

Internal

Maskable

0 (highest)

INTWDTM

Overflow of watchdog timer

Internal

INTP0

Pin input edge detection

External

INTP1

INTP2

INTP3

INTP4

INTP5

INTCSI0

End of 3-wire transfer by CSI0

Internal

INTSER1

Occurrence of UART reception error in ASI1

INTSR1

End of UART reception by ASI1

INTCSI1

End of 3-wire transfer by CSI1

INTST1

End of UART transfer by ASI1

INTSER2

Occurrence of UART reception error in ASI2

INTSR2

End of UART reception by ASI2

INTCSI2

End of 3-wire transfer by CSI2

INTST2

End of UART transfer by ASI2

INTTM3

Reference time interval signal from watch timer

INTTM00

Signal indicating coincidence between 16-bit
timer register and capture/compare register
(CR00)

INTTM01

Signal indicating coincidence between 16-bit
timer register and capture/compare register
(CR01)

INTTM1

Occurrence of coincidence signal of 8-bit
timer/counter 1

INTTM2

Occurrence of coincidence signal of 8-bit
timer/counter 2

INTAD

End of conversion by A/D converter

INTTM5

Occurrence of coincidence signal of 8-bit
timer/counter 5

INTTM6

Occurrence of coincidence signal of 8-bit
timer/counter 6

22 (lowest)

INTWT

Overflow of watch timer

Remark ASI : Asynchronous Serial Interface

CSI : Clocked Serial Interface

4 5

PD784224, 784225

8.2 Vectored Interrupt

Execution branches to a servicing routing by using the memory contents of a vector table address corresponding

to the interrupt source as the address of the branch destination.

So that the CPU performs interrupt servicing, the following operations are performed:

· On branching: Saves the status of the CPU (contents of PC and PSW) to stack

· On returning : Restores the status of the CPU (contents of PC and PSW) from stack

To return to the main routine from an interrupt service routine, the RETI instruction is used.

The branch destination address is in a range of 0 to FFFFH.

Table 8-3. Vector Table Address

Interrupt Source

Vector Table Address

Interrupt Source

Vector Table Address

BRK instruction

003EH

INTST1

001CH

Operand error

003CH

INTSER2

001EH

NMI

0002H

INSR2

0020H

INTWDT (non-maskable)

0004H

INTCSI2

INTWDTM (maskable)

0006H

INTST2

0022H

INTP0

0008H

INTTM3

0024H

INTP1

000AH

INTTM00

0026H

INTP2

000CH

INTTM01

0028H

INTP3

000EH

INTTM1

002AH

INTP4

0010H

INTTM2

002CH

INTP5

0012H

INTAD

002EH

INTCSI0

0016H

INTTM5

0030H

INTSER1

0018H

INTTM6

0032H

INTSR1

001AH

INTWT

0038H

INTCSI1

4 6

PD784224, 784225

8.3 Context Switching

When an interrupt request is generated or when the BRKCS instruction is executed, a predetermined register

bank is selected by hardware. Context switching is a function that branches execution to a vector address stored

in advance in the register bank, and to stack the current contents of the program counter (PC) and program status

word (PSW) to the register bank.

The branch address is in a range of 0 to FFFFH.

Figure 8-1. Context Switching Operation When Interrupt Request Is Generated

0000B
<7> Transfer

PC19-16

PC15-0

<6> Exchange

<5> Save

<2> Save

Temporary register

<1> Save

PSW

<3> Switching of register bank
(RBS0 to RBS2

(0 to 7)

(bits 8 through 11
of temporary register)

<4> RSS

8.4 Macro Service

This function is to transfer data between memory and a special function register (SFR) without intervention by

the CPU. A macro service controller accesses the memory and SFR in the same transfer cycle and directly transfers

data without loading it.

Because this function does not save or restore the status of the CPU, or load data, data can be transferred at

high speeds.

Figure 8-2. Macro Service

CPU

Memory

SFR

Macro service

controller

Read

Write

Read

Internal bus

4 7

PD784224, 784225

8.5 Application Example of Macro Service

(1) Transmission of serial interface

Transfer data storage buffer (memory)

Data n

Data n1

Data 1

Data 2

Internal bus

Transmit shift register

TXS1, TXS2(SFR)

Transfer control

TxD1, TxD2

INTST1, INTST2

Each time macro service request INTST1 and INTST2 are generated, the next transmit data is transferred from

memory to TXS1 and TXS2. When data n (last byte) has been transferred to TXS1 and TXS2 (when the transmit

data storage buffer has become empty), vectored interrupt request INTST1 and INTST2 are generated.

(2) Reception of serial interface

Receive data storage buffer (memory)

Data n

Data n1

Data 1

Data 2

Internal bus

Receive shift register

RXB1, RXB2(SFR)

Reception control

INTSR1, INTSR2

RxD1, RxD2

Receive buffer register

Each time macro service request INTSR1 and INTSR2 are generated, the receive data is transferred from RXB1

and RXB2 to memory. When data n (last byte) has been transferred to memory (when the receive data storage

buffer has become full), vectored interrupt request INTSR1 and INTSR2 are generated.

4 8

PD784224, 784225

9. LOCAL BUS INTERFACE

The local bus interface can connect an external memory or I/O (memory mapped I/O) and support a memory

space of 1 MByte (refer to Figure 9-1).

Figure 9-1. Example of Local Bus Interface (Multiplexed bus)

PD784225

A8-A19

ASTB

AD0-AD7

DD1

Address latch

Q0-Q7

D0-D7

SRAM

I/O1-I/O8

A0-A19

Data bus

Address bus

9.1 Memory Expansion

External program and data memory can be connected in two stages: 256K bytes and 1 Mbytes.

To connect the external memory, ports 4 through 6 are used.

The external memory is connected by using a time-division address/data bus. The number of ports used when

the external memory is connected can be reduced in this mode.

9.2 Programmable Wait

Wait state(s) can be inserted to the memory space (00000H through FFFFFH) while the RD and WR signals are

active.

In addition, there is an address wait function that extends the active period of the ASTB signal to gain the address

decode time.

9.3 External Access Status Function

An active low external access status signal is output from the P37/EXA pin. This signal notifies other devices

connected to the external bus of the external access status, to disable data output to the external bus from other

devices, or enables reception.

The external access status signal is output during external access.

4 9

PD784224, 784225

10. STANDBY FUNCTION

This function is to reduce the power consumption of the chip, and can be used in the following modes:

· HALT mode

: Stops supply of the operating clock to the CPU. This mode is used in combination

with the normal operation mode for intermittent operation to reduce the average

power consumption.

· IDLE mode

: Stops the entire system with the oscillation circuit continuing operation. The

power consumption in this mode is close to that in the STOP mode. However, the

time required to restore the normal program operation from this mode is almost

the same as that from the HALT mode.

· STOP mode

: Stops the main system clock and thereby to stop all the internal operations of the

chip. Consequently, the power consumption is minimized with only leakage

current flowing.

· Power-saving mode

: The main system clock is stopped with the subsystem clock used as the system

clock. The CPU can operate on the subsystem clock to reduce the current

consumption.

· Power-saving HALT mode : This is a standby function in the power-saving mode and stops the operation clock

of the CPU, to reduce the power consumption of the entire system.

· Power-saving IDLE mode : This is a standby function in the power-saving mode and stops the entire system

except the oscillation circuit, to reduce the power consumption of the entire

system.

These modes are programmable.

The macro service can be started from the HALT mode and power-saving HALT mode.

After executing macro service processing, it returns to the HALT mode.

5 0

PD784224, 784225

Figure 10-1. Transition of Standby Status

Power-

saving mode

(operation on

subsystem

clock)

Power-

saving HALT

mode

(standby)

Power-

saving IDLE

mode

(standby)

Power-saving IDLE mode is set.

RESET input

Power-saving HALT mode is set.

Normal operation is restored.

Power-saving HALT mode is set.

RESET input

Interrupt request

Note1

Interrupt request of
masked interrupt

Interrupt
request of
masked
interrupt

Waits for

oscillation

stabilization

Normal

operation

(operation on

main system

clock)

Macro

service

HALT

(standby)

IDLE

(standby)

STOP

(standby)

Oscillation stabilization

time expires

Macro service request

End of one processing

End of macro service

Macro service request

End of one processing

Interrupt request

Note 1

RESET input

Sets HALT mode

Sets IDLE mode

RESET input

Sets STOP mode

RESET input

End of one processing

Macro service request

End of macro service

End of one processing

Macro service request

Macro

service

NMI, INTP0-INTP5
input, INTWT

Note 2

NMI, INTP0-INTP5

input, INTWT

Note 2

NMI, INTP0-INTP5 input, INTWT

Note 2

Notes 1. Only interrupt requests that are not masked

2. INTP0-INTP5 and INTWT are not masked.

5 1

PD784224, 784225

11. RESET FUNCTION

When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset).

During the reset period, oscillation of the main system clock is unconditionally stopped. Consequently, the current

consumption of the entire system can be reduced.

When the RESET signal goes high, the reset status is cleared, oscillation stabilization time (41.9 ms at 12.5 MHz)

elapses, the contents of the reset vector table are set to the program counter (PC), execution branches to an address

set to the PC, and program execution is started from that branch address. Therefore, the program can be reset

and started from any address.

Figure 11-1. Oscillation of Main System Clock during Reset Period

Oscillation is unconditionally
stopped during reset period.

Oscillation stabilization time

Main system clock
oscillation circuit

CLK

RESET input

The RESET input pin has an analog delay noise rejection circuit to prevent malfunctioning due to noise.

Figure 11-2. Accepting Reset Signal

Analog delay

Analog
delay

Oscillation
stabilization
time

RESET input

Internal reset signal

Internal clock

5 3

PD784224, 784225

13. INSTRUCTION SET

(1) 8-bit instructions (The instructions in parentheses are combinations realized by describing A as r)

MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,

ROLC, SHR, SHL, ROR4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC,

MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHIKL, CHKLA

Table 13-1. Instruction List by 8-Bit Addressing

Second Operand

#byte

saddr

sfr

!addr16

mem

[WHL+]

None

Note 2

saddr'

!!addr24

[saddrp]

PSWL

[WHL]

First Operand

[%saddrg]

PSWH

(MOV)

MOV

(MOV)

Note 6

MOV

(MOV)

MOV

(MOV)

ADD

Note 1

(XCH)

XCH

(XCH)

Note 6

(XCH)

XCH

(XCH)

(ADD)

Note 1

(ADD)

Note 1

(ADD)

Note 1,6

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

(ADD)

Note 1

MOV

(MOV)

MOV

ROR

Note 3

MULU

ADD

Note 1

(XCH)

XCH

DIVUW

(ADD)

Note 1

ADD

Note 1

ADD

Note 1

ADD

Note 1

INC

DEC

saddr

MOV

(MOV)

Note 6

MOV

INC

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

XCH

DEC

ADD

Note 1

DBNZ

sfr

MOV

PUSH

ADD

Note 1

(ADD)

Note 1

ADD

Note 1

POP

CHKL

CHKLA

!addr16

MOV

(MOV)

MOV

!!addr24

ADD

Note 1

mem

MOV

[saddrp]

ADD

Note 1

[%saddrg]

mem3

ROR4

ROL4

MOV

PSWL

PSWH

B, C

DBNZ

STBC, WDM

MOV

[TDE+]

(MOV)

MOVBK

Note 5

[TDE]

(ADD)

Note 1

MOVM

Note 4

Notes 1. The operands of ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as that of ADD.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The operands of ROL, RORC, ROLC, SHR, and SHL are the same as that of ROR.

4. The operands of XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as that of

MOVM.

5. The operands of XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as that of

MOVBK.

6. The code length of some instructions having saddr2 as saddr in this combination is short.

5 4

PD784224, 784225

(2) 16-bit instructions (The instructions in parentheses are combinations realized by describing AX as

rp)

MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH,

POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW

Table 13-2. Instruction List by 16-Bit Addressing

Second Operand

#word

saddrp

sfrp

!addr16

mem

[WHL+]

byte

None

Note 2

rp'

saddrp'

!!addr24

[saddrp]

First Operand

[%saddrg]

(MOVW)

(MOVW) (MOVW)

Note 3

MOVW

(MOVW)

MOVW

(MOVW)

ADDW

Note 1

(XCHW)

Note 3

(XCHW)

XCHW

(XCHW)

(ADD)

Note 1

(ADDW)

Note 1

(ADDW)

Note 1,3

(ADDW)

Note 1

MOVW

(MOVW)

MOVW

SHRW

MULW

Note 4

ADDW

Note 1

(XCHW)

XCHW

SHLW

INCW

(ADDW)

Note 1

ADDW

Note 1

ADDW

Note 1

ADDW

Note 1

DECW

saddrp

MOVW

(MOVW)

Note 3

MOVW

INCW

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

XCHW

DECW

ADDW

Note 1

sfrp

MOVW

PUSH

ADDW

Note 1

(ADDW)

Note 1

ADDW

Note 1

POP

!addr16

MOVW

(MOVW)

MOVW

MOVTBLW

!!addr24

mem

MOVW

[saddrp]

[%saddrg]

PSW

PUSH

POP

ADDWG

SUBWG

post

PUSH

POP

PUSHU

POPU

[TDE+]

(MOVW)

SACW

byte

MACW

MACSW

Notes 1. The operands of SUBW and CMPW are the same as that of ADDW.

2. Either the second operand is not used, or the second operand is not an operand address.

3. The code length of some instructions having saddrp2 as saddrp in this combination is short.

4. The operands of MULUW and DIVUX are the same as that of MULW.

6 0

PD784224, 784225

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for supporting development of a system using the

PD784225.

Language processor software

RA78K4

Note 1

Assembler package common to 78K/IV series

CC78K4

Note 1

C compiler package common to 78K/IV series

CC78K4-L

Note 1

C compiler library source file common to 78K/IV series

Flash memory writing tool

Flashpro II

Dedicated flash writer. Manufactured by Naito Densei Machida Mfg. Co., Ltd.

Pending

Flash memory writing adapter

Debugging tool

IE-784000-R

In-circuit emulator common to 78K/IV series

IE-784000-R-BK

Break board common to 78K/IV series

IE-784218-R-EM1

Emulation board for evaluation of

PD784225 subseries

IE-784000-R-EM

IE-70000-98-IF-B

Interface adapter when PC-9800 series (except notebook type) is used as host machine

IE-70000-98N-IF

Interface adapter and cable when notebook type PC-9800 series is used as host machine

IE-70000-PC-IF-B

Interface adapter when IBM PC/AT

is used as host machine

IE-78000-R-SV3

Interface adapter and cable when EWS is used as host machine

Pending

Emulation probe common to

PD784225 subseries

SM78K4

Note 2

System simulator common to 78K/IV series

ID78K4

Note 2

Integrated debugger for IE-784000-R

DF784225 (Pending)

Note 3

Device file for

PD784225 subseries

Real-time OS

RX78K/IV

Note 3

Real-time OS for 78K/IV series

MX78K4

Note 4

OS for 78K/IV series

Remark RA78K4, CC78K4, SM78K4, and ID78K4 are used in combination with DF784225.

6 2

PD784224, 784225

APPENDIX B. RELATED DOCUMENTS

Documents related to device

Document Name

Document No.

Japanese

English

PD784224, 784225 Preliminary Product Information

U11725J

This document

PD78F4225 Preliminary Product Information

U12499J

Planned

PD784225, 784225Y Subseries User's Manual - Hardware

Planned

PD784225 Subseries Special Function Register Table

Planned

78K/IV Series User's Manual - Instruction

U10905J

U10905E

78K/IV Series Instruction Table

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note - Software Basics

U10095J

U10095E

Documents related to development tools (User's Manuals)

Document Name

Document No.

Japanese

English

RA78K4 Assembler Package

Operation

U11334J

U11334E

Language

U11162J

RA78K Series Structured Assembler Preprocessor

EEU-817

EEU-1402

CC78K4 Series

Operation

EEU-960

Language

EEU-961

CC78K Series Library Source File

U12322J

IE-784000-R

EEU-5004

EEU-1534

IE-784218-R-EM1

U12155J

U12155E

SM78K4 System Simulator - Windows Based

Reference

U10093J

U10093E

SM78K Series System Simulator

External parts

U10092J

U10092E

user open interface

specification

ID78K4 Integrated Debugger - Windows Based

Reference

U10440J

U10440E

ID78K4 Integrated Debugger HP9000 Series 700

Reference

U11960J

On preparation

(HP-UX Based)

Caution

The contents of the above related documents are subject to change without notice. Be sure to

use the latest edition of a document for designing.

6 5

PD784224, 784225

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

6 6

PD784224, 784225

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

6 8

PD784224, 784225

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific:

Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

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