Document Outline

COVER
FEATURES
ORDERING INFORMATION
PIN CONFIGURATION (TOP VIEW)
BLOCK DIAGRAM
1. PIN FUNCTIONS
- 1.1 LIST OF PIN FUNCTION
- 1.2 PIN INPUT/OUTPUT CIRCUITS
- 1.3 PIN MASK OPTIONS
- 1.4 UNUSED PIN CONNECTIONS
2. INTERNAL BLOCK FUNCTIONS
- 2.1 REGISTERS
- 2.2 ARITHMETIC LOGIC UNIT (ALU) ...16 BITS
- 2.3 PROGRAM STATUS WORD (PSW)
- 2.4 MEMORY
- 2.5 PORT FUNCTIONS
- 2.6 TIMER
- 2.7 TIMER/EVENT COUNTER
- 2.8 SERIAL INTERFACE
- 2.9 ANALOG/DIGITAL CONVERTER
- 2.10 ZERO-CROSS DETECTOR
3. INTERRUPT FUNCTIONS
- 3.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION
- 3.2 NON-MASKABLE INTERRUPT OPERATION
- 3.3 MASKABLE INTERRUPT OPERATION
- 3.4 INTERRUPT OPERATION BY SOFTI INSTRUCTION
4. STANDBY FUNCTIONS
- 4.1 HALT MODE
- 4.2 HALT MODE RELEASE
- 4.3 SOFTWARE STOP MODE
- 4.4 SOFTWARE STOP MODE RELEASE
- 4.5 HARDWARE STOP MODE
- 4.6 HARDWARE STOP MODE RELEASE
- 4.7 LOW SUPPLY VOLTAGE DATA RETENTION MODE
5. RESET OPERATIONS
6. INSTRUCTION SET
- 6.1 IDENTIFIER/DESCRIPTION OF OPERAND
- 6.2 SYMBOL DESCRIPTION OF INSTRUCTION CODE
- 6.3 INSTRUCTION EXECUTION TIME
7. LIST OF MODE REGISTERS
8. ELECTRICAL SPECIFICATIONS
9. CHARACTERISTIC CURVES
10. PACKAGE DRAWINGS
11. RECOMMENDED SOLDERING CONDITIONS
12. DIFFERENCES AMONG uPD78C18, uPD78C14, AND uPD78C12A
APPENDIX DEVELOPMENT TOOLS

1995

DATA SHEET

PD78C17, 78C18

The information in this document is subject to change without notice.

The mark 5 shows revised points.

Document No.

IC-2789B

(O.D.No.

IC-8048B)

Date Published

June 1995 P

Printed in Japan

8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER)

The

PD78C18 is an 8-bit CMOS microcontroller which integrates 16-bit ALU, ROM, RAM, an A/D converter, a

multi-function timer/event counter, and a general-purpose serial interface onto a single chip, and whose memory

(ROM/RAM) is externally expandable up to 31 Kbytes. The

PD78C18 can operate at low power consumption

because of its CMOS architecure and is provided with a standby function that enables data retention with an even

lower power consumption.

The

PD78C17 is the ROM-less version of the

PD78C18. Its memory (ROM/RAM) is expandable externally up

to 63 Kbytes.

A detailed explanation of the functions is provided in the user's manual listed below. It should be read before

starting design work.

87AD Series

PD78C18 User's Manual: IEU-1314

FEATURES

· 159 types of instructions: 87AD series instruction set plus multiply/divide and 16-bit operation instructions

· Instruction cycle: 0.8

s (at 15-MHz operation)

· Internal ROM: 32768 x 8 bits (

PD78C18 only)

· Internal RAM: 1024 x 8 bits

· Up to 64 Kbytes of memory (ROM/RAM) can be directly addressed.

· High-resolution 8-bit A/D converter: 8 analog inputs

· General-purpose serial interface: Asynchronous, synchronous, I/O interface modes

· Multi-function 16-bit timer/event counter

· Two 8-bit timers

· I/O lines

Input/output ports

: 28 (

PD78C17), 40 (

PD78C18)

Edge detection inputs : 4

· 11 interrupt functions External : 3, Internal: 8 (Non-maskable: 1, Maskable: 10)

· Zero-cross detection function: (2 inputs)

· Standby function: HALT mode, hardware/software STOP mode

· Mask option pull-up resistors can be incorporated into Ports A, B, and C. (

PD78C18 only)

ORDERING INFORMATION

Part Number

Package

PD78C17CW

64-pin plastic shrink DIP (750 mils)

PD78C17GF-3BE

64-pin plastic QFP (14 x 20 mm)

PD78C17GQ-36

64-pin plastic QUIP

PD78C18CW-xxx

64-pin plastic shrink DIP (750 mils)

PD78C18GF-xxx-3BE

64-pin plastic QFP (14 x 20 mm)

PD78C18GQ-xxx-36

64-pin plastic QUIP

1990

MOS INTEGRATED CIRCUIT

PD78C17,78C18

CONTENTS

PIN FUNCTIONS ..........................................................................................................................................

1.1

LIST OF PIN FUNCTION ......................................................................................................................................7

1.2

PIN INPUT/OUTPUT CIRCUITS ..........................................................................................................................9

1.3

PIN MASK OPTIONS .........................................................................................................................................15

1.4

UNUSED PIN CONNECTIONS ..........................................................................................................................15

INTERNAL BLOCK FUNCTIONS ..............................................................................................................16

2.1

REGISTERS .........................................................................................................................................................16

2.2

ARITHMETIC LOGIC UNIT (ALU) .....................................................................................................................17

2.3

PROGRAM STATUS WORD (PSW) .................................................................................................................. 17

2.4

MEMORY ............................................................................................................................................................19

2.5

PORT FUNCTIONS .............................................................................................................................................22

2.6

TIMER ..................................................................................................................................................................31

2.7

TIMER/EVENT COUNTER .................................................................................................................................34

2.8

SERIAL INTERFACE ...........................................................................................................................................41

2.9

ANALOG/DIGITAL CONVERTER ......................................................................................................................52

2.10 ZERO-CROSS DETECTOR .................................................................................................................................55

INTERRUPT FUNCTIONS .........................................................................................................................57

3.1

INTERRUPT CONTROL CIRCUIT CONFIGURATION ...................................................................................... 58

3.2

NON-MASKABLE INTERRUPT OPERATION ...................................................................................................61

3.3

MASKABLE INTERRUPT OPERATION ............................................................................................................63

3.4

INTERRUPT OPERATION BY SOFTI INSTRUCTION ...................................................................................... 64

STANDBY FUNCTIONS ............................................................................................................................65

4.1

HALT MODE .......................................................................................................................................................65

4.2

HALT MODE RELEASE ......................................................................................................................................66

4.3

SOFTWARE STOP MODE .................................................................................................................................68

4.4

SOFTWARE STOP MODE RELEASE ................................................................................................................ 68

4.5

HARDWARE STOP MODE .................................................................................................................................69

4.6

HARDWARE STOP MODE RELEASE ...............................................................................................................70

4.7

LOW SUPPLY VOLTAGE DATA RETENTION MODE ..................................................................................... 71

RESET OPERATIONS ................................................................................................................................72

INSTRUCTION SET ...................................................................................................................................73

6.1

IDENTIFIER/DESCRIPTION OF OPERAND ...................................................................................................... 73

6.2

SYMBOL DESCRIPTION OF INSTRUCTION CODE ........................................................................................ 74

6.3

INSTRUCTION EXECUTION TIME ...................................................................................................................75

LIST OF MODE REGISTERS .....................................................................................................................87

ELECTRICAL SPECIFICATIONS ................................................................................................................88

CHARACTERISTIC CURVES .....................................................................................................................99

10. PACKAGE DRAWINGS ...........................................................................................................................102

PD78C17,78C18

PIN FUNCTIONS

1.1

LIST OF PIN FUNCTION (1/2)

Function

Pin Name

I/O

PA7 to PA0

(Port A)

Input-output

8-bit input-output port, which can specify input/output (Port A) bit-wise.

8-bit input-output port, which can specify input/output (Port B) bit-wise.

PB7 to PB0

(Port B)

Input-output

Port C
8-bit input-output port,
which can specify input/output bit-wise.

PC1/RxD

Receive Data
Input pin for serial data.

Input-output/
Input

PC0/T

Input-output/
Output

Transmit Data
Output pin for serial data.

Serial Clock
Input-output pin for serial clock.
It becomes output pin for the internal clock

use, and input pin for the external.

PC2/SCK

Interrupt Request/Timer Input
Maskable interrupt input pin of the
edge trigger (falling edge), or an
external clock input pin for a timer.
Also, it can be used as a zero-cross

detection pin for AC input.

Input-output/
Input/Input

PC3/INT2/TI

PC4/TO

Timer Output
Square wave defining one cycle of
internal clock or timer counter time as
half cycle is output.

Input-output/
Output

Input-output/
Input

PC5/CI

Counter Input
External pulse input pin to timer/event
counter.

PC6/CO0
PC7/CO1

Counter Output 0, 1
Programmable square wave output by
timer/event counter.

Input-output/
Output

PD7 to PD0/
AD7 to AD0

Input-output/
Input-output

Address/Data Bus
When external memory is used, it
becomes multiplexed address/data bus.

Port D
8-bit input-output port, which can specify
input/output in byte units (

PD78C18).

PF7 to PF0/
AB15 to AB8

Input-output/
Output

Port F
8-bit input-output port, which can specify
input/output bit-wise.

Address Bus
When external memory is used, it
becomes address bus.

Output

Strobe signal which is output for write operation of external memory. It becomes high
in any cycle other than the data write machine cycle of external memory. When RESET
signal is either low or in the hardware STOP mode, this signal becomes output high-
impedance.

WR
(Write Strobe)

Output

RD
(Read Strobe)

Output

ALE
(Address Latch
Enable)

Strobe signal which is output for read operation of external memory. It becomes high in
any cycle other than the read machine cycle of external memory. When RESET signal is
either low or in the hardware STOP mode, this signal becomes output high-impedance.

Strobe signal to latch externally the lower address information which is output to PD7 to
PD0 pins to access external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes output high-impedance.

Input-output/
Input-output

PD78C17,78C18

X1, X2
(Crystal)

RESET
(Reset)

STOP
(Stop)

1.1

LIST OF PIN FUNCTION (2/2)

Function

Pin Name

I/O

Input-output

The

PD78C18 sets MODE0 pin to "0" (low level), and MODE1 pin to "1" (high level).

Note

The

PD78C17 allows you to set MODE0, MODE1 pins to select 4 K, 16 K, or 63 Kbytes for

the size of the memory which is installed externally.

MODE0

MODE1

External Memory

4 Kbytes

16 Kbytes

63 Kbytes

Also, when each of MODE0 and MODE1 pins is set to "1"

Note

, it is synchronized to ALE to

output a control signal.

Non-maskable interrupt input pin of the edge trigger (falling edge)

A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a
zero-cross detection pin for AC input.

8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection
(falling edge) input.

A common pin serving both as a reference voltage input pin for A/D converter and as a
control pin for A/D converter operation.

Power supply pin for A/D converter.

GND pin for A/D converter.

Crystal connection pins for system clock oscillation. X1 should be input when a clock is
supplied from outside. Inverted clock of X1 should be input to X2.

Low-level active system reset input.

Control signal input pin in hardware STOP mode. The oscillation stops when the low-
level is input.

Positive power supply pin.

GND pin.

MODE0
MODE1
(Mode)

NMI
(Non-Maskable
Interrupt)

Input

INT1
(Interrupt
Request)

AN7 to AN0
(Analog Input)

Input

AREF

(Reference
Voltage)

(Analog V

)

(Analog V

)

Input

Note

Connect a pull-up resistor. Resistance R should be 4 [k

]

0.4t

CYC

] (t

CYC

is in nanoseconds).

Remark

The

PD78C18 can incorporate (mask option) pull-up resistors on to ports A, B, and C.

PD78C17,78C18

INTERNAL BLOCK FUNCTIONS

2.1

REGISTERS

The central registers are the sixteen 8-bit registers and four 16-bit registers shown in Fig. 2-1.

Fig. 2-1 Register Configuration

(a)

General registers (B, C, D, E, H, L)

There are two sets of general registers (MAIN: B, C, D, E, H, L; ALT: B', C', D', E', H', L'). They function

as auxiliary registers for the accumulator, and have a data pointer function as register pairs (BC, DE, HL;

B'C', D'E', H'L'). In particular, four register pairs DE, D'E', HL, and H'L', have a base register function.

When the two sets are used, if an interrupt occurs in one set, the register contents are saved into the

other register set without saving them into the memory so that interrupt servicing can be carried out. The

other set of registers can also be used as data pointer expansion registers. Two addressing modes, single-

step automatic increment/decrement modes and a two-step automatic increment mode, are available for

the register pairs, DE, HL, D'E', and H'L', so that the processing time can be reduced. BC, DE, and HL can

be simultaneously replaced with the ALT register by means of the EXX instruction. The HL register can be

independently replaced with the ALT register by means of the EXH instruction.

(b) Working register vector register (V)

When a working area is set in the memory space, the high-order 8 bits of the memory address are

selected using the V register and the low-order 8 bits are addressed by the immediate data in the instruc-
tion. Thus, the memory area specified with the V register can be used as working registers with a 256 x 8-
bit configuration.

Because a working register can be specified with a 1-byte address field, program reduction is possible

by using the working area for software flags, parameters, and counters. The V register can be replaced
with the ALT register paired with an accumulator by means of the EXA instruction.

EA'

MAIN

ALT

PD78C17,78C18

(c)

Accumulator (A)

In the

PD78C17 and 78C18, because an accumulator type architecture is used, 8-bit data processing

such as 8-bit arithmetic and logical operation instructions is mainly performed by this accumulator.

This accumulator can be replaced with the ALT register paired with the vector register (V) by means of

the EXA instruction.

(d) Expansion accumulator (EA)

16-bit data processing such as 16-bit arithmetic and logical operation instructions is mainly performed

by EA.

This accumulator can be replaced with the ALT register EA' by means of the EXA instruction.

(e)

Program counter (PC)

This is a 16-bit register which holds information on the next program address to be executed. This

fetched. When an instruction associated with a branch is executed, immediate data or register contents are

loaded. RESET input clears this counter to 0000H.

(f)

Stack pointer (SP)

This is a 16-bit register which holds the start address of the memory stack area (LIFO format).

SP contents are decremented when a CALL or PUSH instruction is executed or an interrupt is generated,

and incremented when a RETURN or POP instruction is executed.

2.2

ARITHMETIC LOGIC UNIT (ALU) ...16 BITS

The ALU executes data processing such as 8-bit arithmetic and logical operations, shift and rotation, data

processing such as 16-bit arithmetic and logical operations and shift operations, 8-bit multiplication and 16-bit

by 8-bit division.

2.3

PROGRAM STATUS WORD (PSW)

This word consists of 6 types of flags which are set/reset according to instruction execution results. Three of

these flags (Z, HC, and CY) can be tested by an instruction. PSW contents are automatically saved to the stack

when an interrupt (external, internal, or SOFTI instruction) is generated, and restored by the RETI instruction.

RESET input resets all bits to (0).

Fig. 2-2 PSW Configuration

(a)

Z (Zero)

When the operation result is zero, this flag is set (1). In all other cases, it is reset (0).

(b) SK (Skip)

When the skip condition is satisfied, this flag is set (1). If the condition is not satisfied, it is reset (0).

(c)

HC (Half Carry)

If an 8-bit operation generates a carry out of bit 3 or a borrow into bit 3, this flag is set (1). In all other

cases, it is reset (0).

(d) L1

When the "MVI A, byte" instruction is stacked, this flag is set (1). In all other cases, it is reset (0).

PD78C17,78C18

(e)

When the "MVI L, byte;LXI H, word" instruction is stacked, this flag is set (1). In all other cases, it is

reset (0).

(f)

CY (Carry)

When a 16-bit operation generates a carry out of or a borrow into bit 7 or 15, this flag is set (1). In all

other cases, it is reset (0).

When one of 35 types of ALU instructions, rotation instructions, or carry manipulation instructions is

executed, various flags are affected as shown in Table 2-1.

Table 2-1 Flag Operations

ADDX
ADCX
SUBX
SBBX

ANAX
ORAX
XRAX

ADDNCX
SUBNBX

GTAX
LTAX

ONAX
OFFAX

NEAX
EQAX

ADI
ACI
SUI

SBI

ANI
ORI

XRI

ADINC

SUINB

GTI

LTI

ONI
OFFI

NEI
EQI

immediate

reg, memory

Operation

skip

RLR

RLL

SLR

SLL

DRLR

DRLL

DSLR

DSLL

SLRC

SLLC

STC
CLC

MVI

A, byte

MVI

L, byte

LXI

H, word

BIT
SK
SKN
SKIT
SKN IT
RETS

Other All instructions

........

Affected

(Set or Reset)

1 ........

Set

0 ........

Reset

........

No affected

ANIW
ORIW

GTIW
LTIW

ONIW
OFFIW

NEIW
EQIW

ADDW
ADCW
SUBW
SBBW

ANAW
ORAW
XRAW

ADDNCW
SUBNBW

GTAW
LTAW

ONAW
OFFAW

NEAW
EQAW

INRW
DCRW

ADD
ADC
SUB
SBB
DADD
DADC
DSUB
DSBB
EADD
ESUB
ANA
ORA
XRA
DAN
DOR
DXR

ADDNC
SUBNB

GTA
LTA

DADDNC
DSUBNB

DGT
DLT
ONA
OFFA
DON
DOFF
NEA
EQA
DNE
DEQ
INR
DCR
DAA

0
0
0

PD78C17,78C18

2.4

MEMORY

The

PD78C17 and 78C18 can address a maximum of 64 Kbytes of memory. The memory maps are shown in

Figs. 2-3 and 2-4. The external memory area and the internal RAM area can be freely used as program memory

and data memory. Because the access timing for internal memory and external memory are the same, pro-

cessing can be executed at high speeds.

(a)

Interrupt start addresses

The interrupt start addresses are all fixed as follows:

NMI ....................... 0004H
INTT0/INTT1 ......... 0008H
INT1/INT2 ............. 0010H
INTE0/INTE1 ......... 0018H
INTEIN/INTAD ...... 0020H
INTSR/INTST ........ 0028H
SOFTI .................... 0060H

(b) Call address table

The call address of a 1-byte call instruction (CALT) can be stored in the 64-byte area (for 32 call ad-

dresses) from address 0080H to address 00BFH.

(c)

Specific memory area

The reset start address, interrupt start addresses, and the call table are allocated to addresses 0000H to

00BFH, and this area takes account of these in use. Addresses 0800H to 0FFFH are directly addressable by

a 2-byte call instruction (CALF).

The

PD78C18 has on-chip mask programmable ROM in addresses 0000H to 7FFFH.

(d) Internal data memory area

1-Kbyte RAM is incorporated in addresses FC00H to FFFFH. The RAM contents are retained for 1-Kbyte

internal data memory area in standby operation.

(e)

External memory area

With the

PD78C17, the external memory can be expanded in steps in 63-Kbyte area (0000H to FBFFH)

by setting the MODE0 and MODE1 pins (see Table 2-3).

With the

PD78C18, the external memory can be expanded in steps in 31-Kbyte area (8000H to FBFFH)

by setting the MEMORY MAPPING register (see Fig. 2-13).

The external memory is accessed using AD7 to AD0 (multiplexed address/data bus), AB7 to AB0 (ad-

dress bus), and the RD, WR, and ALE signals. Both programs and data can be stored in the external

memory.

(f) Working register area

A 256-byte working register area can be set in any memory location (specified by the V register) and

working register addressing is possible.

PD78C17,78C18

2.5

PORT FUNCTIONS

(1)

PA7 to PA0 (PORT A)

This is an 8-bit input/output port which has input/output buffer and output latch functions. Port A can

be set as to input or output bit-wise using the MODE A register. And

PD78C18 port A pull-up resistor

specification is performed bit-wise by mask option.

Port A is set as follows when setting the input port or after reset.

High-impedance : Without pull-up resistor
High level

: With pull-up resistor

Fig. 2-5 Port A

(a)

When specified as output port (MAn = 0)

The output latch is effective, enabling data exchange by a transfer instruction between the output latch

and the accumulator. Direct bit setting/resetting of output latch contents is possible by an arithmetic or

logical operation instruction without the use of an accumulator. Once data is written to the output latch,

the data is held until a port A manipulation instruction is executed or the data is reset.

Fig. 2-6 Port A Specified as Output Port

Note Only

PD78C18

Internal Bus

Latch

Output

Latch

Output

Buffer

Mask OptionNote

Internal Bus

Output

Latch

Mask OptionNote

Note Only

PD78C18

PD78C17,78C18

(b) When specified as input port (MAn = 1)

PA line contents can be loaded into an accumulator by a transfer instruction. They can also be directly

tested bit-wise by an arithmetic or logical operation instruction without the use of an accumulator.

Fig. 2-7 Port A Specified as Input Port

Actual execution of an instruction which manipulates port A is performed in 8-bit units. If a port A read

instruction (MOV A, PA) is executed, the input line contents of the port specified for input and the output

latch contents of the port specified for output are loaded into an accumulator. When a port A write instruc-

tion (MOV PA, A) is executed, data is written to the output latch of both ports specified for input and

output. However, the output latch contents of a bit specified as an input port cannot be loaded to the

accumulator and are not output to an external pin (which functions as input pin), because the output buffer

is off.

MODE A register (MA)

8-bit register which specifies port A input/output.

Port A input/output can be specified bit-wise. If the MODE A register corresponding bit is set (1),

this register is input, and if the bit is reset (0), this register is output.

After RESET input or in the hardware STOP mode, all the bits are set, and port A is in the input

mode resulting in the below status.

High-impedance : Without pull-up resistor
High level

: With pull-up resistor

Fig. 2-8 MODE A Register Format

MA 7

MA 6

MA 5

MA 4

MA 3

MA 2

MA 1

MA 0

(n = 0 to 7)

Note Only

PD78C18

= Output

= Input

Internal Bus

Output

Latch

Mask OptionNote

PD78C17,78C18

(2)

PB7 to PB0 (PORT B)

Like port A, port B is an 8-bit input/output port with input/output buffer and output latch functions. Port B

can be set as an input or output port bit-wise using the MODE B register (MB).

PD78C18 port B pull-up

resistor specification is performed bit-wise by mask option.

Port B is set as follows when setting the input port or after reset.

High-impedance : Without pull-up resistor

High level

: With pull-up resistor

As with port A, direct bit setting/resetting of port B output latch contents is possible by an arithmetic or

logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is

also possible.

MODE B Register (MB)

Like the MODE A register, the MODE B register is an 8-bit register which specifies port B input/

output bit-wise.

After RESET input or in the hardware STOP mode, all the bits are set (1), and port B is in the input

mode resulting in the status below.

High-impedance : Without pull-up resistor

High level

: With pull-up resistor

Fig. 2-9 Mode B Register Format

MB 7

MB 6

MB 5

MB 4

MB 3

MB 2

MB 1

(n = 0 to 7)

= Output

= Input

MB 0

PD78C17,78C18

MCC

= 1

= x

MCC

= 0

MCC

= 0

Output

= 1

Input

D output

D inpit

SCK input/output

INT2/TI input

TO output

CI input

CO0 output

CO1 output

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

(3)

PC7 to PC0 (PORT C)

Port C (PC7 to PC0) is an 8-bit special input/output port which functions as various control signals as

well as general-purpose input/output ports in which input/output is set bit-wise like port A. These are

switched over bit-wise according to the setting of the MODE C register and MODE CONTROL C register as

shown below.

Table 2-2 Operation of PC7 to PC0

(n = 0 to 7)

PD78C18 port C pull-up resistor specification is performed bit-wise by mask option.

In the operation when data is set in the general-purpose input/output ports, as with port A, direct bit

setting/resetting/testing of port C output latch contents is possible by an arithmetic or logical operation

instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible.

MODE CONTROL C Register (MCC)

8-bit register which specifies the port C port/ control signal input/output mode bit-wise.

If the MODE CONTROL C register corresponding bits are set (1), PC7 to PC0 are in the control signal

input/output mode, and if these are reset (0), in the port mode.

After RESET input or in the hardware STOP mode, all the bits of the MODE CONTROL C register are

reset (0), and the port mode is set.

PD78C17,78C18

MODE C register (MC)

The MODE C register is an 8-bit register by which, like the MODE A register of port A, port C input/

output specification is performed bit-wise.

Contents of the MODE C register corresponding to the bits set to the control mode by the MODE

CONTROL C register are ignored.

After RESET input or in the hardware STOP mode, all bits of the MODE C register are set (1). And

this time, because all bits of the MODE CONTROL C register are reset (0), port C becomes an input

port and the below state is set.

High-impedance : Without pull-up resistor

High level

: With pull-up resistor

Fig. 2-11 MODE C register Format

MC 7

MC 6

MC 5

MC 4

MC 3

MC 2

MC 1

MC 0

(n = 0 to 7)

(4)

PD7 to PD0 (PORT D)

PD78C17

Can be used for address/data bus. These have no functions as a port.

PD78C18

8-bit general-purpose input/output ports also used as multiplexed address/data bus. These ports can be

specified for input/output in byte units (8-bit units) as general-purpose input/output ports, and function as

multiplexed address/data bus when external expansion memory is connected. This switchover is per-

formed by the MEMORY MAPPING register.

In the operation when data is set in the general-purpose input/output ports, unless input/output is

specified in byte units, as with port A, direct bit setting/resetting/testing of port F output latch contents is

possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer

to/from an accumulator is also possible.

= Output

= Input

PD78C17,78C18

When this is set as general-purpose input/output ports, as with port A, direct bit setting/resetting/ testing

of port C output latch contents is possible by an arithmetic or logical operation instruction without the use

of an accumulator. Data transfer to/from an accumulator is also possible.

PD78C17 MEMORY MAPPING register (MM)

A register which controls internal RAM access permission.

Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not internal RAM is permitted.

When internal RAM is used in external extension and external memory is used in the area, RAE bit

is set to "0" and internal RAM access is prohibited.

Contents of RAE bit is retained, even if RESET signal is input in the normal operation. However, at

power-on reset, RAE bit is undefined and RAE bit should be initialized by an instruction.

Fig. 2-12

PD78C17 MEMORY MAPPING Register Format

(5)

PF7 to PF0 (PORT F)

PD78C17

General-purpose input/output ports also used as address bus.

These pins function as address outputs corresponding to the size of externally installed memory accord-

ing to the MODE0 and MODE1 pin settings.

Pins which are not used for address output can be used for general-purpose input/output ports which

have the same port function as for port A. Input/output setting is performed by the MODE F register.

Table 2-3 Operation of

PD78C17's PF7 to PF0

MODE1

MODE0

PF 7

PF 6

PF 5

PF 4

PF 3

PF 2

PF 1

PF 0

External Address

Space

Port

AB11

AB10

AB9

AB8

4 Kbytes

Port

AB13

AB12

AB11

AB10

AB9

AB8

16 Kbytes

Setting prohibited

AB15 AB14 AB13

AB12 AB11

AB10

AB9

AB8

63 Kbytes

RAE

Internal RAM Access

Disable

Enable

PD78C17,78C18

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

External Memory

Port

Maximum 256 bytes

Port

AB11

AB10

AB9

AB8

Maximum 4 Kbytes

Port

AB13

AB12

AB11

AB10

AB9

AB8

Maximum 16 Kbytes

AB15

AB14

AB13

AB12

AB11

AB10

AB9

AB8

Maximum 31 Kbytes

PD78C18

8-bit general-purpose input/output ports also used as address bus.

Can specify input/output bit-wise as general-purpose input/output ports, and address signal is output

according to external extension memory size when the external expansion memory of 256 bytes or greater

is accessed.

This switchover is performed by the MEMORY MAPPING and MODE F registers.

When this is set as general-purpose input/ourput ports, as with port A, direct bit setting/resetting/testing

of port C output latch contents is possible by an arithmetic or logical operation instruction without the use

of an accumulator. Data transfer to/from an accumulator is also possible.

PD78C18 MEMORY MAPPING register (MM)

4-bit register which specifies PD7 to PD0 and PF7 to PF0 port/extension mode and controls internal

RAM access permission.

Bits 0, 1, and 2 (MM0, MM1, MM2) in the MEMORY MAPPING register control specification of PD7

to PD0 port/extension mode, input/output, and PF7 to PF0 address line.

When bits MM1 and MM2 in the MEMORY MAPPING register are "0", PD7 to PD0 and PF7 to PF0

are set as general-purpose input/output port, input/output of PD7 to PD0 is specified by MM0, and

input/output of PF7 to PF0 is specified by the MODE F register.

4 types of external extension memory (256 bytes, 4 Kbytes, 16 Kbytes, and 31 Kbytes) can be

selected, and ports which are not used for address line are used as general-purpose input/output

ports.

Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not the access to internal RAM is

permitted.

When internal RAM is not used in external extension and external memory uses the area, RAE bit is

set to "0" and internal RAM access is prohibited.

After RESET input or in the hardware STOP mode, bits MM0, MM1, and MM2 of the MEMORY

MAPPING register are reset (0), and PD7 to PD0 become input ports (high-impedance).

Even if the RESET signal is input in the normal operation, contents of the RAE bit are retained.

However, the RAE bit is undefined after power-on reset, the RAE bit should be initialized by an

instruction.

PD78C17,78C18

Fig. 2-13

PD78C18 MEMORY MAPPING Register Format

RAE

MM2

MM1

MM0

0 0 1

Port
mode

Single
chip

PD7 to PD0 = Extension

mode

PF7 to PF0 = Port mode

PD7 to PD0 = Input port
PF7 to PF0 = Port mode

PD7 to PD0 = Output port
PF7 to PF0 = Port mode

Disable

Enable

Internal RAM Access

MODE F register (MF)

The MODE F register specifies port F input/output in the same way as for the MODE A register in

port A. However, contents of the MODE F register corresponding to port F bits specified as address

line by the MEMORY MAPPING register are in the output mode.

After RESET input or in the hardware STOP mode, all the bits of the MODE F register are set (1) and

port F is an input port (high-impedance).

Fig. 2-14 MODE F Register Format

MF 7

MF 6

MF 5

MF 4

MF 3

MF 2

MF 1

MF 0

(n = 0 to 7)

Extension
mode

Exten-
sion
mode

PD7 to PD0 =
PF3 to PF0 =
PF7 to PF4 = Port mode

PD7 to PD0 =
PF5 to PF0 =
PF7 and PF6 = Port mode

16 Kbytes

4 Kbytes

PD7 to PD0 =
PF7 to PF0 =

256 bytes

31 Kbytes

= Output

= Input

PD78C17,78C18

2.6

TIMER

This is an interval timer which has two 8-bit timers (TIMER0, TIMER1). These are programmable indepen-

dently. By cascading these can also be used as 16-bit interval timer, and can be used for counting TI input.

The timer is composed of TIMER0 and TIMER1, as shown in 2-15, including 8-bit TIMER REG (TM0, TM1), 8-

bit COMPARATOR, 8-bit UPCOUNTER, and TIMER F/F. Input selection, timer operation and TO output are

controlled by the timer mode register (TMM).

In TIMER0,

s: 12-MHz operation) and

384

(32

s: 12-MHz operation) internal clock and TI input are

input. In TIMER1, not only these inputs but also TIMER0 match signal are input.

Because TIMER0 operates in the same way as TIMER1, TIMER0 operation is described below.

At first, a count value is set in TIMER REG0, and TIMER0 input and TIMER0 start data (bit 4 in the timer

mode register = "0") are set in the timer mode register to start TIMER0. The UPCOUNTER is incremented one

input at a time. The COMPARATOR always compares contents of the incremented UPCOUNTER with those of

TIMER REG0, and if these match, the match signal (internal interrupt: INTT0) is generated. This match clears

contents of UPCOUNTER and increment starts again from 00H. Therefore, the interval is set by count time,

which is a count value set by TIMER REG0. This allows the timer to operate as an interval timer which gener-

ates interrupts repeatedly.

By setting (1) bit 1 (MKT0) of the interrupt mask register (MKL), internal interrupt (INTT0) is disabled.

The TO output has timers COMPARATOR match signal and TIMER F/F complemented by

(250 ns: 12-MHz

operation) internal clocks, and can obtain a square wave which has a half period of the count time or

. By

setting the timer/event counter mode register (ETMM), this output can be used for the timer event counter

reference time.

By setting the serial mode register (SMH), the timer can be used as the serial clock (SCK) in serial interface.

PD78C17,78C18

(1)

Timer mode register (TMM)

This is an 8-bit register which controls TIMER0, TIMER1, and TIMER F/F operation (see Fig. 2-16).

The timer mode register bits 0 and 1 (TF0, TF1) control the TIMER F/F operating mode, bits 2 and 3

(CK00, CK01) control TIMER0 input clock, bit 4 (TS0) controls TIMER0 operation. Bits 5 and 6 (CK10, CK11)

control TIMER1 input clock, and bit 7 (TS1) controls TIMER1 operation.

TS0 and TS1 bits clear these UPCOUNTERs to 00H by "1", and stop increment. By changing "1" to "0",

the UPCOUNTER starts increment from 00H.

The internal clock (

) divides the oscillator frequency by 3, the internal clock (

) divides it by 12, and

the internal clock (

384

) divides it by 384.

After RESET input, the timer mode register is set to FFH, the UPCOUNTERs in TIMER0 and TIMER1 are

cleared in the suspended state, and TIMER F/F is reset.

Fig. 2-16 Timer Mode Register (TMM) Format

TS1

CK11

CK10

TS0

CK01

CK00

TF1

TF0

TIMER0 COMPARATOR match signal

TIMER1 COMPARATOR match signal

Internal clock (

)

TIMER F/F reset

TIMER F/F Input, Operating Mode

TMM

Disable

TIMER0 Input Clock

Internal clock (

)

Internal clock (

384

)

TI input

TIMER0 Operation

Reset

Increment

TIMER0 COMPARATOR match signal

TIMER0 Input Clock

Internal clock (

)

Internal clock (

384

)

TI input

TIMER1 Operation

Reset

Increment

PD78C17,78C18

2.7

TIMER/EVENT COUNTER

The

PD78C17 and 78C18 have a 16-bit multi-function timer/event counter having the following functions.

o Interval timer
o External event counter
o Frequency measurement
o Pulse width measurement
o Programmable square wave output
o One pulse output

The timer/event counters are composed of 16-bit timer/event counter upcounter (ECNT), timer/event counter

capture register (ECPT), comparator, timer/event counter REG0 and REG1 (ETM0, ETM1), control circuits for

I/O, interrupt, and clear.

ECNT is a 16-bit upcounter which counts an input pulse, and cleared by the clear control circuit.

The ECPT register is a 16-bit buffer register which retains the contents of ECNT. The timing to latch contents

of ECNT by the ECPT register is the falling edge of CI input when input to ECNT is an internal clock, and is the

falling edge of TO output when input to ECNT is CI input.

The ETM0 and ETM1 registers are two 16-bit registers which set a number of counts and data is exchanged

by 16-bit data transfer instructions via an extended accumulator.

The comparator compares contents of ECNT with contents of the ETM0 and ETM1 registers, and if these

match, a match signal is generated.

The interrupt control circuit controls interrupts from the timer/event counter. The following interrupt sources

are generated. These are generated by three signals: the ECNT and ETM0 register match signal (INTE0), the

ECNT and ETM1 register match signal (INTE1), and the CI input or timer output (TO) falling edge (INTEIN).

PD78C17,78C18

Next, the operation which outputs a square wave to the CO0 pin is described.

At first, after ECNT is cleared, a count value (ETM0 < ETM1) is set in the ETM0 and ETM1 registers, and data

for LV0 initial status specification and to enable LV0 level inversion is set in the timer/event counter output

mode register.

In the timer/event counter mode register, by setting an input to ECNT to

s: 12-MHz operation) internal

clock, the ECNT clear mode to the ECNT and ETM1 register match signal, and CO0 pin output timing to the

ECNT and ETM0 register match signal or ECNT and ETM1 register match signal, the timer/event counter starts

operation.

ECNT is incremented one

internal clock at a time, the comparator compares incremented ECNT with the

ETM0 and ETM1 registers, and if these match, the match signal (CP0, CP1) is generated. By this match signal,

LV0 level is output to the CO0 pin, and LV0 level is inverted.

ECNT is cleared by the ECNT and ETM1 register match signal (CP1), ECNT increments again from 0000H,

and the above-mentioned steps are repeated (see Fig. 2-20).

Therefore, a programmable square wave which has the ETM0 and ETM1 register count as a pulse width is

output.

Fig. 2-20 Square Wave Output

Remarks

ETM0 register = m

ETM1 register = n

(m < n: m and n are count values.)

Reference
Clock (

)

CP0

CP1

CO0

Start

PD78C17,78C18

(1)

Timer/event counter mode register (ETMM)

This is an 8-bit register which controls the timer/event counter (see Fig. 2-21).

The timer/event counter mode register bits 0 and 1 (ET0, ET1) control the timer event counter upcounter

(ECNT) input clock, bits 2 and 3 (EM0, EM1) control the ECNT clear mode, bits 4 and 5 (CO00, CO01)

control output timing when the output latch contents are output to the counter output0 (CO0). Bits 6 and 7

(CO10, CO11) control CO1 output timing.

The internal clock (

) divides the oscillation frequency by 12.

After RESET input or in the hardware STOP mode, the timer/event counter mode register is reset to 00H.

Fig. 2-21 Timer/Event Counter Mode Register Format

CO11

CO10

CO01

CO00

EM 1

EM 0

ET 1

ET 0

Internal clock (

)

while CI input is in the high level

CI input

CI input while TO is in the high level

ECNT Input Clock

ETMM

ECNT Clear Mode

Stop after clear

Free running

Clear a full count at a time

Clear by matching ECNT and ETM1

Clear at the fall of CI input (ET1 = 0)

Clear the fall of TO

(ET1 = 1)

CO0 Output Timing

ECNT and ETM0 match

Setting prohibited

ECNT and ETM0 match, or

CI input fall

ECNT and ETM0 match, or

ECNT and ETM1 match

CO1 Output Timing

ECNT and ETM1 match

Setting prohibited

ECNT and ETM1 match, or

CI input fall

ECNT and ETM0 match, or

ECNT and ETM1 match

PD78C17,78C18

(2)

Timer/event counter output mode register (EOM)

This is an 8-bit register which controls the timer/event counters CO0 and CO1 (Counter Output 0, 1)

operating mode.

The timer/event counter output mode register bits 0 and 4 (LO0, LO1) control whether or not LV0 and

LV1 level are output to the CO0 and CO1 pins, bits 1 and 5 (LD0, LD1) control whether or not LV0 and LV1

level are inverted at an output timing specified by the timer/event counter mode register, bits 2, 3, 6, and 7

(LRE0, LRE1, LRE2, LRE3) control LV0 and LV1 setting/resetting.

Bits LO0, LO1, LRE0, LRE1, LRE2, and LRE3 are automatically reset (0) after individual operations.

After RESET input or in the hardware STOP mode, the timer/event counter output mode register is reset

to 00H.

Fig. 2-22 Timer/Event Counter Output Mode Register (EOM) Format

LRE3

LRE2

LD 1

LO 1

LRE1

LRE0

LD 0

LO 0

LV0 Data Output

Output contents of LV0

No operation

LV0 Level Inversion

Enable

Disable

Setting prohibited

LV0 Set/Reset

No operation

Resets LV0

Sets LV0

LV1Data Output

Output contents of LV1

No operation

LV1 Level Inversion

Enable

Disable

Setting prohibited

LV1 Set/Reset

No operation

Resets LV1

Sets LV1

PD78C17,78C18

2.8

SERIAL INTERFACE

The

PD78C17 and 78C18 have the serial interface using the transmit/receive method by start/stop bit. The

three types of operating modes are shown below.

· Asynchronous (start-stop) mode : Establishes data bit synchronization and character synchronization

by start bit.

· Synchronous mode

: Data transfer is performed in synchronization with the serial clock.

· I/O interface mode

: As for serial data transfer in the

PD7801/78C06A etc., data transfer

is performed in synchronization with the serial clock.

The serial interface block is composed of the serial data input (RxD), serial data output (TxD), 3 serial clock

input/output (SCK) pins, transfer control block, two 8-bit serial registers for transmission and reception, and 8-

bit transmission buffer and reception buffer (see Fig. 2-23).

As the serial registers and buffers for transmission and reception are provided, transmission or reception is

individually performed (full-duplex double buffer transmitter/receiver).

However, the serial clock (SCK) is shared in transmission and reception, and half-duplex transmission/

reception is performed in the synchronous mode and I/O mode.

Fig. 2-23 Serial Interface Block Diagram

Remarks

= f

x 1/24

Where, f

= oscillation frequency (MHz)

384

= f

x 1/384

Internal Bus

INTSR

Receive Buffer (RXB)

Serial Mode Register
(SML, SMH)

Transmit Buffer (TXB)

Serial Register (S¡P)

Serial Register (P¡S)

PC1/R

PC2/SCK

SK1, SK2

384

TO Output

PC0/T

Control

Reception

Transmission

Control

INTST

PD78C17,78C18

Start Bit

Parity Bit

Stop Bit

N = 6, 7

(1) Asynchronous mode

In case of the asynchronous mode, clock rate, character length, number of stop bits, parity enable, and

odd or even parity specifications can be controlled by the serial mode register (SML).

Transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH).

If data is written to the transmission buffer by the "MOV TXB, A" instruction and preceding data transfer

is terminated, contents of the transmission buffer are transferred to the serial register automatically. The

start bit (1 bit), parity bit (odd/even number, no parity), and stop bit (1 or 2 bits) are automatically added to

data which is transferred to the serial register. And this data is transmitted from the TxD pin starting from

the least significant bit (LSB).

If the transmit buffer is empty, the internal interrupt (INTST) is generated.

Transmission data is transmitted from the TxD pin at the fall of SCK in the transfer speed of x1, x1/16, or

x1/64 serial clock (SCK).

The maximum data transfer speed in transmission is set by SCK and clock rate in 12-MHz operation as

shown below.

When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1).

By setting bit 2 (MKST) of the interrupt mask register (MKH), the internal interrupt (INTST) is disabled.

Fig. 2-24 Asynchronous Data Format

Internal Clock

Data Transfer

Speed

External Clock

Data Transfer

Speed

SCK

Clock Rate

SCK

x16

x64

500 kbps

125 kbps

31.25 kbps

660 kbps

125 kbps

31.25 kbps

500 kHz

660 kHz

2 MHz

PD78C17,78C18

Receive operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH).

The start bit is confirmed by detecting the low level of RxD input and the low level after 1 or 2 bits.

Reception is performed by sampling character bit, parity bit, and stop bit following the low level. When

data specified in the serial register from RxD is input, data is transferred to the receive buffer. If the receive

buffer is full, the internal interrupt (INTSR) is generated.

By setting (1) bit 1 (MKSR) of the interrupt mask register (MKH), the internal interrupt (INTSR) is

disabled.

In reception, odd or even parity is checked (when PEN bit = 1). If data do not match (parity error), if

stop bit is low (framing error), or if the next data is transferred to the receive buffer when the receive

buffer is full (overrun error), the error flag is set (1).

However, because error interrupt mechanism is not provided, test is executed by the skip instruction

(SKIT, SKNIT).

The serial clock (SCK) can be selected as an external or internal clock by the serial mode register (SMH).

Three types of

384

, or TO outputs can be selected as internal clock. This clock can be output to off-

chip. Or the external serial clock can be input.

By using the internal clock (TO output) as SCK, the data transfer speed can be flexibly changed by

program.

The maximum data transfer speed in reception is set by SCK and the clock rate in 12-MHz operation as

shown below.

Internal Clock

Data Transfer

Speed

External Clock

Data Transfer

Speed

SCK

Clock Rate

SCK

500 kbps

125 kbps

31.25 kbps

125 kbps

31.25 kbps

500 kHz

2 MHz

660 kHz

1 MHz

660 kbps

1 Mbps

Note1

Notes

1. If data of transfer speed 660 kbps to 1 Mbps is received, 2 stop bits are required.

2. In x1 clock rate, RxD and SCK synchronization needs to be externally established.

For an example, when data is transferred in the data transfer speed of 110 to 9600 bps, when the timer

input clock is set as internal clock (

), the timer count value (C) is shown below.

Data Transfer
Speed (bps)

Oscillation Frequency

(MHz)

7.3728

14.7456

11.0592

9600

4800

2400

1200

600

300

150

110

128

175

C =

192

262

C =

128

256

370

C =

Note2

x16

x64

PD78C17,78C18

(2)

Synchronous mode

In the synchronous mode, data transfer is performed with 8-bit character length fixed, and with no parity

bit. Therefore, the serial mode register (SML) is set to 0CH (see Fig. 2-26).

Transmission operation is enabled by setting (1) bit 3 (TxE) of the serial mode register (SMH).

If data is written to the transmit buffer by the "MOV TXB, A" instruction and preceding data transfer is

terminated, the contents of the transmit buffer are automatically transferred to the serial register and

converted to serial data, and data starting from LSB are transmitted from TxD at the falling edge of SCK.

The serial data is transferred in the same rate as for SCK.

Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and

maximum 1 Mbps when an external clock is used (12-MHz operation).

When data is transferred from the transmit buffer to the serial register and the transmit buffer is

empty, the internal interrupt (INTST) is generated.

When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1).

Fig. 2-26 Serial Mode Register Format in Synchronous Mode

SML

Synchronous Operation

Character Length 8-Bit Fixed

Parity Disable

RxE

TxE

SK 1

SMH

SCK Selection

External clock

Internal clock (TO output)

Internal clock (

384

)

Internal clock (

)

Transmission Enable

Reception Enable

Disable

Enable

SK 2

Search Mode

Disable

Enable

Disable

Enable

PD78C17,78C18

In the synchronous mode, 2 types of receive operation can be selected. This mode can be controlled by

SE bit of the serial mode register (SMH).

By setting SE bit (1), the search mode is set. On each 1-bit reception from the RxD pin, the contents of

the serial register are transferred to the receive buffer and the internal interrupt (INTSR) is generated.

Because the

PD78C17(A)/78C18(A) don't have a synchronous character detection circuit by hardware, a

synchronous character detection is required by software.

If receive synchronization is established after a synchronous character is detected, SE bit is reset (0).

By resetting the SE bit, the character mode is set. On each 8-bit data reception, the contents of the serial

By setting (1) MKSR bit of the interrupt mask register, the internal interrupt (INTSR) is disabled.

In the synchronous mode, data is output from TxD at the falling edge of SCK, and data is input from

RxD at the rising edge of SCK.

SCK can be selected as an internal clock or external clock by setting the serial mode register (SMH).

Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and

maximum 660 kbps when an external clock is used (12-MHz operation).

PD78C17,78C18

(3)

I/O interface mode

When input/output is extended to off-chip or I/O controllers (A/D converter, liquid crystal display

controller, etc.) are connected to this chip, this mode is effective.

In the I/O interface mode, data transfer is performed starting from the most significant bit (MSB) with

8-bit character length fixed, and with no parity bits. Therefore, the serial mode register (SML) should be

set to 0CH and bit 5 (IOE) of the serial mode register (SMH) is set to "1".

This mode establishes synchronization by controlled SCK (8 cycles of the serial clock) and SCK should

be high except during data transfer.

The transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH).

If data is written by the "MOV TXB, A" instruction, data is transferred to the serial register automati-

cally, and is output from TxD at the falling edge of controlled SCK. The transmit buffer is empty, the

internal interrupt (INTST) is generated.

Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and

maximum 1 Mbps when an external clock is used (12-MHz operation).

The reception operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH), and

receive data is input to the serial register at the rising edge of controlled SCK. When the serial register

receives 8-bit data, data is transferred from the serial register to the receive buffer and the internal inter-

rupt (INTSR) is generated.

SCK can be selected as an internal clock or external clock by the serial mode register (SMH).

Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and

maximum 660 kbps when an external clock is used for SCK (12-MHz operation). 6 states or more is re-

quired in 8th SCK high-level width.

PD78C17,78C18

(4)

Serial mode register (SML, SMH)

These are two 8-bit registers which control the serial interface operation (see Figs. 2-28 and 2-29).

The serial mode low register (SML) bits 0 and 1 (B1, B2) control switchover of the asynchronous mode

and synchronous operation and clock rate in the asynchronous mode, bits 2 and 3 (L1, L2) control charac-

ter length, bit 4 (PEN) controls parity enable, bit 5 (EP) controls odd or even parity, and bits 6 and 7 (S1,

S2) control a number of stop bits.

After RESET input or in the hardware STOP mode, the serial mode low register (SML) is set to 48H.

The serial mode high register (SMH) bits 0 and 1 (SK1, SK2) control whether an internal clock or

external clock is used as the serial clock (SCK), bit 2 (TxE) controls the transmission operation, bit 3 (RxE)

controls the reception operation, bit 4 (SE) controls whether or not the search mode is set in the synchro-

nous mode. Bit 5 (IOE) controls whether the synchronous mode or I/O interface mode is set, and bit 6

(TSK) starts the serial clock when data is received using the internal clock in the I/O interface mode. The

TSK bit is automatically reset (0) after the serial clock starts.

When the serial clock is specified as an internal clock, the SCK value is determined by the following

expressions.

Internal clock (

SCK = f

/24

Internal clock (

384

SCK = f

/384

Internal clock (TO output):

Timer input clock is

SCK = f

/(24 x C)

Timer input clock is

384

SCK = f

/(768 x C)

TIMER F/F input is

SCK = f

However, f

is set in the oscillation frequency, SCK is set in the serial clock, and C is set in the timer

count value.

When TIMER F/F input is

in case of the internal clock (TO output), the asynchronous mode can only be

used when the clock rate is 16 or 64.

After RESET input or in the hardware STOP mode, the serial mode high register (SMH) is reset to 00H.

PD78C17,78C18

2.9

ANALOG/DIGITAL CONVERTER

The

PD78C17 and 78C18 have on-chip 8-bit high-speed and high-resolution analog/digital (A/D) converter

with 8-multiplexed analog input (AN7 to AN0), and 4 "Conversion Result" registers (CR0 to CR3) to retain a

conversion result. This A/D converter uses the successive approximation method.

In the A/D converter operation, either the scan mode or select mode can be selected by software.

In the select mode, one of analog inputs is selected by the A/D channel mode register before starting A/D

conversion. Conversion values are stored to CR0 through CR3 sequentially. In the scan mode, Analog conver-

sion values AN0 to AN3 or AN4 to AN7 are stored to CR0 through CR3 sequentially. This mode switchover is

specified by the A/D channel mode register.

In case of the select mode, one of the analog inputs is selected by the A/D channel mode register and the A/

D conversion starts. Conversion values are stored to CR0 through CR3 sequentially. When four CR registers are

set to conversion values, the internal interrupt (INTAD) is generated. The A/D converter continues A/D conver-

sion and sequential storage of conversion values beginning with CR0 until the A/D channel mode register is

changed.

In case of the scan mode, the analog input AN0 to AN3 (ANI2 = 0) or AN4 to AN7 (ANI2 = 1) can be selected.

If bit 3 (ANI2) of the A/D channel mode register is set to "0", analog inputs AN0, AN1, AN2, AN3 and AN0

are selected in that order. These input A/D conversion values CR0, CR1, CR2, CR3, and CR0 are stored in that

order. If ANI2 of the A/D channel mode register is set to "1", analog inputs AN4, AN5, AN6, AN7, and AN4 are

selected in that order, and these input A/D conversion values CR0, CR1, CR2, CR3, and CR0 in that order. In the

scan mode, like in the select mode, when four CR registers are set to conversion values, the internal interrupt

(INTAD) is generated.

In the scan mode, too, the above-mentioned operation is repeated until the A/D channel mode register is

changed.

By setting (1) bit 0 (MKAD) of the interrupt mask register (MKH), the internal interrupt (INTAD) is disabled.

PD78C17,78C18

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

(1)

A/D channel mode register (ANM)

This is an 8-bit register which controls A/D converter operation. Bit 0 (MS) of the A/D channel mode

bit 4 (FR) controls A/D operation according to change of the oscillator frequency.

In the A/D channel mode register, the operating mode specification is written, and the contents of this

After RESET input or in the hardware STOP mode, the A/D channel mode register is set to 00H.

Fig. 2-31 A/D Channel Mode Register Format

ANI2

ANI1

ANI0

Operating Mode Specification

Select mode

Scan mode

Analog Input Specification

Oscillator frequency

9 MHz

(144 states)

Oscillator frequency > 9 MHz

(192 states)

(2)

A/D converter operation control method

The A/D converter can stop conversion operation by controlling the V

AREF

input voltage. If a voltage

greater than V

IH1

is input to the V

AREF

pin, the A/D converter starts conversion operation and the conversion

results are guaranteed in V

AREF

= 3.4 V to AV

. If the V

AREF

pin input voltage is set to less than V

IL1

during

the conversion operation, the A/D converter conversion operation stops. At this time, contents of CR0 to

CR3 are undefined.

Even if the V

AREF

input voltage is changed for A/D converter stop control, the A/D channel mode

AREF

input voltage is greater than 3.4 V, the A/D converter

restarts operation beginning with storage of conversion values to CR0 in the mode directly before the stop

state is set.

Even if the V

AREF

input voltage level is changed, the detection function of AN4 to AN7 input edge is not

affected.

Caution

When V

AREF

is low, inputs AN0 to AN7 in the range of AV

to AV

are necessary.

PD78C17,78C18

A digital pulse generated in the zero-cross detector of the INT1 pin is sent to the interrupt control circuit. The

INTF1 interrupt request flag is set at the zero-cross point from the negative to the positive state of the AC

signal (rising edge), and if INT1 interrupt is enabled, interrupt servicing is started. A digital pulse generated in

the INT2/TI pin zero-cross detector is sent to the interrupt control circuit and interrupt servicing can be started

at the zero-cross point from the positive to the negative state of the AC signal (falling edge) as with the INT1

pin, and can also be used as a timer input clock.

The format of the zero-cross mode register (ZCM), which controls self-bias for zero-cross detection of the

INT1 and INT2/TI pins, is shown in Fig. 2-34.

Fig. 2-34 Zero-Cross Mode Register Format

ZC2

ZC1

INT1 Pin

Generates self-bias

Does not generate self-bias

ZCM

INT2/T1 Pin

Generates self-bias

Does not generate self bias

When the ZC1 and ZC2 bits of the zero-cross mode register are set to "0", a self-bias for zero-cross detection

of each pin is not generated and each pin responds as a normal digital input.

When the ZC1 and ZC2 bits are set to "1", a self-bias is generated and an AC input signal zero-cross can be

detected by connecting a capacitor to each pin. Each pin with ZC1 and ZC2 bits set to "1" can be directly driven

without the use of an external capacitor. In this case, each pin responds as a digital input. However, an input

load current is necessary and an external circuit output driver must be considered. Thus, when no zero-cross

detection is executed and each pin is used simply as an interrupt input or timer input, the ZC1 and ZC2 bits of

the zero-cross mode register should be set to "0".

RESET input sets both the ZC1 and ZC2 bits to "1" and a self-bias is generated.

The zero-cross function of the INT2/TI (shared as PC3) pin can operate only when the control mode is

specified by the MODE CONTROL C register (MCC). In the port mode, the zero-cross detection function does

not operate.

Caution

Unlike other CMOS circuits, a supply current is always present in the zero-cross detector because

of its operation points. This also applies in the standby modes (HALT and software/hardware STOP

modes). Thus, when the zero-cross detector is operated (with self-bias generation: ZCX = 1),

slightly more current flows than without zero-cross detector operation, and its effect is greater in

the software/hardware STOP mode.

PD78C17,78C18

(a) REQUEST REGISTER

This register consists of 11 interrupt request flags which are set by the different interrupt requests. A flag is

reset when an interrupt request is acknowledged or a skip instruction (SKIT or SKNIT) is executed. RESET

input resets all flags.

There are 11 types of interrupt request flags.

· INTFNMI

Set (1) by a falling edge input to the NMI pin. Unlike other interrupt request flags, this flag cannot be

tested by a skip instruction.

· INTFT0

Set (1) by TIMER0 COMPARATOR match signal.

· INTFT1

Set (1) by TIMER1 COMPARATOR match signal.

· INTF1

Set (1) by a rising edge input to the INT1 pin.

· INTF2

Set (1) by a falling edge input to the INT2 pin.

· INTFE0

Set (1) by a match signal when timer/event counter ECNT and ETM0 register contents match.

· INTFE1

Set (1) by a match signal when timer/event counter ECNT and ETM1 register contents match.

· INTFEIN

Set (1) by a falling edge of the timer/event counter CI input or timer output (TO).

· INTFAD

Set (1) when A/D converter conversion values are transferred to the four registers CR0 to CR3.

· INTFSR

Set (1) when the serial interface receive buffer becomes full.

· INTFST

Set (1) when the serial interface transmit buffer becomes empty.

(b) MASK REGISTER

This is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (NMI). It

can be set (1) or reset (0) bit-wise by an instruction. An interrupt request is masked (disabled) or enabled when

the corresponding bit of the mask register is "1" or "0", respectively.

All bits of the mask register are set by RESET input and all interrupt requests except non-maskable inter-

rupts are masked. All bits of the mask register are set in the hardware STOP mode.

PD78C17,78C18

(c) PRIORITY CONTROL circuit

This circuit controls the 6 priority levels described earlier. If two or more interrupt request flags are set

simultaneously, the interrupt with the highest priority according to the priority is acknowledged.

(d) TEST CONTROL circuit

This circuit comes into operation when a skip instruction (SKIT or SKNIT) is executed to test interrupt

request flags (except INTFNMI) for each interrupt source, NMI pin states, and test flags.

(e) INTERRUPT ENABLE F/F (IE F/F)

This is a flip-flop which is set by the EI instruction and reset by the DI instruction. This flip-flop is reset

when an interrupt is acknowledged, and by RESET input, too. Interrupts are enabled when this flip-flop is set,

and disabled when it is reset.

(f) TEST FLAG REGISTER

This register consists of 7 test flags which do not generate interrupt requests. These flags are tested or

reset by the skip instructions (SKIT, SKNIT).

· OV

Set (1) when the timer/event counter ECNT overflows.

· ER

Set (1) in the event of a parity error, framing error or overrun error in serial interface.

· SB

Set (1) if V

pin increases from a level lower than specified to a level higher than specified.

· AN7 to AN4

Set (1) by a falling edge input to pins AN7 to AN4.

3.2

NON-MASKABLE INTERRUPT OPERATION

When the interrupt request flag (INTFNMI) is set by a falling edge input to the NMI pin, a non-maskable

interrupt is acknowledged by means of the following procedure irrespective of the EI/DI state (see Fig. 3-3).

(i)

A check is made to see if INTFNMI is set at the end of each instruction. If INTFNMI is set, a non-

maskable interrupt is acknowledged and INTFNMI is reset.

(ii) When the non-maskable interrupt is acknowledged, the IE F/F is reset and all interrupts except for non-

maskable interrupts and the SOFTI instruction are placed in the disabled state (DI state).

(iii) PSW, PC high byte, and PC low byte are saved into the stack memory in that order.

(iv) The program jumps to the interrupt address (0004H).

These interrupt operations are automatically carried out in 16 states.

The interrupt request flag (INTFNMI) cannot be tested by the skip instruction. However, the NMI pin status

can be tested by the skip instruction (SKIT NMI, SKNIT NMI). Therefore, by testing the NMI pin status with the

skip instructions in several times in the non-maskable interrupt service routine, noise of comparatively long

period or periodical noise can be removed. The NMI pin status is not changed even if the status is tested by

the skip instruction.

PD78C17,78C18

3.3

MASKABLE INTERRUPT OPERATION

Interrupt requests except non-maskable interrupts and the SOFTI instruction are maskable interrupts which

can be enabled/disabled (IE F/F set/reset) by the EI/DI instructions and can be masked individually by means of

the mask register.

When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for

more than the specified time, an interrupt request flag is set. If an internal interrupt request is generated, an

interrupt request flag is immediately set. Once the interrupt request flag is set, both the external and internal

interrupts are serviced using the following procedure (see Fig. 3-3).

(i) In the EI state (IE F/F = 1), a check is made to see if the interrupt request flag has been set at the end

checked at end of each instruction. If the flag has been set, the interrupt cycle starts. However, interrupt

requests masked by the mask register are not checked.

(ii) If two or more interrupt request flags have been set simultaneously, their priorities are checked. The

interrupt with the highest priority is acknowledged and the others are held pending.

(iii) When an interrupt request is acknowledged, the interrupt request flag is automatically reset. If two types

of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt

request flag is not reset. This is because the two types are identified by software at a later stage.

(iv) When an interrupt request is acknowledged, the IE F/F is reset, and all interrupts except non-maskable

interrupts and the SOFTI instruction are placed in the disabled state (DI state).

(v) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order.

(vi) The program jumps to the interrupt address.

These interrupt operations are automatically carried out in 16 states.

The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority

when interrupts are enabled by execution of the EI instruction.

With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt

address. Unmasking both types, unmasking one type, or masking both kinds can be selected by setting the

mask register.

(1) When both types are unmasked

The corresponding bits of the mask register for two types of interrupt requests are both set to "0". In this

case, the interrupt request is the logical sum of the two interrupt request flags.

If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one

or both interrupt request flags having the same priority and the program jumps to the interrupt address, the

interrupt request flag is not reset. Therefore, the interrupt request is identified by executing a skip instruction

which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request

flag is reset.

(2) When one type is unmasked

For two types of interrupt requests having the same priority, the corresponding bit of the mask register for

the interrupt request to be unmasked is set to "0" and the other bit is set to "1". In this case, if an interrupt

request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged

in accordance with the interrupt operation, the interrupt request flag is automatically reset.

When the masked interrupt request flag is set, that interrupt request is held pending. When the pending

interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in

the interrupt enable state.

(3) When both types are masked

The corresponding bits of the mask register for two types of interrupt request are both set to "1". In this

case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set.

When the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt

requests of higher priority in the interrupt enabled state.

PD78C17,78C18

STANDBY FUNCTIONS

Three standby modes are available for the

PD78C17 and 78C18 to save power consumption in the program

standby mode (the HALT mode, software STOP mode, and hardware STOP mode).

4.1

HALT MODE

When the HLT instruction is executed, the HALT mode is set unless the interrupt request flag of the un-

masked interrupt is set. In the HALT mode the CPU clock stops and program execution also stops. However,

the contents of all registers and internal RAM just before the stoppage are retained. In the HALT mode, the

timer, timer/event counter, serial interface, A/D converter, and interrupt control circuit are operational.

Table 4-1 shows the status of the

PD78C17 and 78C18 output pins in the HALT mode.

Table 4-1 Output Pin Statuses

Output Pin

Single Chip

Note1

External Expansion

PA7 to PA0

Data retained

PB7 to PB0

Data retained

PC7 to PC0

Data retained

PD7 to PD0

Data retained

High-impedance

PF7 to PF0

Data retained

Next address retained

Note2

Data retained

Note3

WR, RD

High-level

ALE

High-level

Notes 1.

PD78C18 only

2. Address output pin

3. Port data output pin

Caution

Because an interrupt request flag is used to release the HALT mode, HLT instruction execution does

not set the HALT mode if even a single interrupt request flag for an unmasked interrupt is set.

Thus, when setting the HALT mode when there is a possibility that an interrupt request flag may

have been set (when there is a pending interrupt), one of the following procedures should be

followed: First process the pending interrupt; or, reset the interrupt request flag by executing a

skip instruction; or, mask all interrupts except those used to release the HALT mode.

PD78C17,78C18

(2) Release by interrupt request flag

The HALT mode is released if at least one interrupt request flag is set by the generation of a non-maskable

interrupt (NMI) or one of ten unmasked maskable interrupts (INTT0, INTT1, INT1, INT2, INTE0, INTE1, INTEIN,

INTAD, INTST, and INTSR).

When the HALT mode is released by a non-maskable interrupt, the instruction following the HLT instruction

is not executed and the program jumps to the interrupt address (0004H) irrespective of the interrupt enabled/

disabled (EI/DI) state.

When the HALT mode is released by a maskable interrupt, operation after release differs depending on

whether the EI or DI state is set.

(i)

EI state

The instruction following the HLT instruction is not executed and the program jumps to the corresponding

interrupt address.

Fig. 4-2 HALT Mode Release Timing (in EI State)

CPU
Operation

OSC

INTF

HLT

Interrupt Execution Interrupt Routine

(ii) DI state

Execution restarts with the instruction following the HLT instruction (without jumping to the interrupt

address). Because the interrupt request flag used for release remains set, it should be reset by a skip

instruction when required.

Fig. 4-3 HALT Mode Release Timing (in DI State)

CPU
Operation

OSC

INTF

HLT

Following Instruction
Execution

PD78C17,78C18

4.3

SOFTWARE STOP MODE

When the STOP instruction is executed, the software STOP mode is set unless the interrupt request flag for

an unmasked external interrupt is set. In the software STOP mode, all clocks stop. When this mode is set,

program execution stops and the contents of all registers and internal RAM are retained (the timer upcounter is

cleared to 00H). Only the NMI and RESET signals used to release the software STOP mode are valid, and all

other functions stop.

The statuses of the

PD78C17 and 78C18 output pins in the software STOP mode are the same as for the

HALT mode, as shown in Table 4-1.

Cautions

Internal interrupts should be masked before executing the STOP instruction to prevent errors

due to an internal interrupt during the oscillation stabilization time at release of the software

STOP mode.

The TIMER1 match signal is used as the signal to start CPU operation to secure an oscillation

stabilization period after the software STOP mode has been released by setting the non-

maskable interrupt request flag. Thus, it is necessary to set a count value in TIMER REG which

takes account of the oscillation stabilization time, and to set the timer mode register to the

timer operating state, before executing the STOP instruction.

4.4

SOFTWARE STOP MODE RELEASE

(1) Release by RESET signal

When the RESET signal changes from the high to low level in the software STOP mode, the software STOP

mode is released and clock oscillation starts as soon as the reset state is set. When the RESET signal is driven

high after oscillation has stabilized, the CPU starts program execution at address 0.

When the RESET signal changes from the high to low level, clock oscillation starts but it takes time for

oscillation to stabilize. The RESET signal low-level width must therefore be longer than the oscillation stabiliza-

tion time.

When the RESET signal is input, the RAM contents are retained but the contents of other registers are

undefined.

Fig. 4-4 Software STOP Mode Release Timing (RESET Input)

CPU
Operation

OSC

RESET

STOP

Address 0 Instruction Execution

If the software STOP mode is released by the RESET signal, program execution starts at address 0 as in the

case of a normal power-on reset. The SB (Standby) flag can be used to identify the program execution mode.

The SB flag is set (1) when the V

pin rises from the specified low level or below to the specified high level or

above, and is reset (0) by executing a skip instruction. Thus, by testing the SB flag using a skip instruction in

the program executed after RESET input, a set SB flag indicates a power-on start, and a reset SB flag indicates

a start due to release of the software STOP mode.

PD78C17,78C18

CPU
Operation

OSC

INTFNMI

STOP

Interrupt Execution

Wait (Programmable)

Interrupt Routine

TIMER1
Match Signal

(2) Release by interrupt request flag

When the non-maskable interrupt request flag is set in the software STOP mode, the software STOP mode is

released and simultaneously clock oscillation starts. When clock oscillation starts, the timer upcounter starts

counting up from 00H in accordance with the setting before execution of the STOP instruction. CPU operation

is started by a match signal (wait time taking account of the oscillation stabilization time) from the TIMER1

UPCOUNTER. In this case, the UPCOUNTER match signal does not set the interrupt request flag. The timer

mode register of the timer after generation of the match signal is set to FFH and timer operation is stopped.

After the elapse of the oscillation stabilization time, the program jumps to the interrupt address (0004H)

irrespective of the interrupt enabled/disabled (EI/DI) state and without executing the instruction following the

STOP instruction.

FIg. 4-5 Software STOP Mode Release Timing

4.5

HARDWARE STOP MODE

When the STOP signal changes from the high to low level, the hardware STOP mode is set. In this mode all

clocks stop. When the hardware STOP mode is set, program execution stops and the internal RAM contents

just before stoppage are retained, and the STOP signal used to release the hardware STOP mode is valid. All

other functions stop and the reset state is set.

In the hardware STOP mode, the

PD78C17 and 78C18 output pins become high-impedance.

PD78C17,78C18

4.6

HARDWARE STOP MODE RELEASE

When the STOP signal changes from the low to high level in the hardware STOP mode, the hardware STOP

mode is released and simultaneously clock oscillation starts. After the elapse of the wait time (approximately

65 ms at 12 MHz) which takes account of the oscillation stabilization time, the CPU starts program execution at

address 0 (see Fig. 4-6).

Fig. 4-6 Hardware STOP Mode Release Timing

CPU
Operation

Instruction
Execution

Address 0 Instruction
Execution

STOP

OSC

Wait
approx. 65 ms/12 MHz

The hardware STOP mode is not released by a high-to-low transition of the RESET signal. When the STOP

signal changes from low to high while the RESET signal is low, the hardware STOP mode is released and clock

oscillation starts. If the RESET signal returns from the low to high level, the CPU starts program execution at

address 0 without waiting for the elapse of the oscillation stabilization time (see Fig. 4-7). For also the case

where the RESET signal changes from high to low immediately after the hardware STOP mode is released (the

STOP signal changes from low to high), the program is executed when the RESET signal returns from low to

high (see Fig. 4-8).

The oscillation stabilization time should therefore be taken into account when returning the RESET signal to

the high level.

After RESET signal input RAM contents are retained, but the contents of other registers are undefined.

PD78C17,78C18

RESET OPERATIONS

When RESET input becomes low, then system reset is activated to create the following status.

o INTERRUPT ENABLE F/F is reset and interrupt is disabled.

o All the interrupt mask registers are set (1) and interrupt is masked.

o An interrupt request flag is reset (0) and pended interrupt is eliminated.

o All PSWs are reset (0).

o 0000H is loaded into the program counter (PC).

o The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the

MODE CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the

ports (A, B, C, D, and F) become input port (high-impedance).

o All the test flags but SB flag are reset (0).

o A timer mode register is set to FFH, and TIMER F/F is reset.

o The mode register (ETMM, EOM) of a timer/event counter is reset (0).

o The serial mode high register (SMH) of serial interface is reset (0), while the serial mode low register

(SML) is set to 48H.

o The A/D channel mode register of the A/D converter is reset (0).

o WR, RD, ALE signals become high-impedance.

o The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1).

o Data memory and the following register contents are undefined.

o The internal timing generator is initialized.

Stack pointer (SP)

Expansion accumulator (EA, EA'), accumulator (A, A')

General register (B, C, D, E, H, L, B', C', D', E', H', L')

Output latch of each port

TIMER REG0, 1 (TM0, TM1)

TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1)

RAE bit of MEMORY MAPPING register

SB flag of test flag

When RESET input becomes high, the reset status is released. Then, execution of the program is started

from 0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if

necessary.

PD78C17,78C18

Note NMI can also be described as FNMI.

Identifier

Description

V, A, B, C, D, E, H, L

EAH, EAL, B, C, D, E, H, L

A, B, C

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF,

TXB, TM0, TM1, ZCM

sr1

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3

sr2

PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM

sr3

ETM0, ETM1

sr4

ECMT, ECPT

SP, B, D, H

rp1

V, B, D, H, EA

rp2

SP, B, D, H, EA

rp3

B, D, H

rpa

B, D, H, D+, H+, D, H

rpa1

B, D, H

rpa2

B, D, H, D+, H+, D, H, D+byte, H+A, H+B, H+EA, H+byte

rpa3

D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte

8-bit immediate data

word

16-bit immediate data

byte

8-bit immediate data

bit

3-bit immediate data

CY, HC, Z

irf

NMI

Note

, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB

Remarks

1. sr to sr4 (special register)

2. rp to rp3 (register pair)

4. f (flag)

PORT A

ETMM :

TIMER/EVENT

PORT B

COUNTER MODE

PORT C

EOM

TIMER/EVENT

PORT D

COUNTER OUTPUT

PORT F

MODE

MODE A

ANM

A/D CHANNEL MODE

MODE B

CR0

A/D CONVERSION

MODE C

RESULT 0 to 3

MCC

MODE CONTROL C

CR3

MODE F

TXB

BUFFER

MEMORY MAPPING

RXB

BUFFER

TM0

TIMER REG0

SMH

SERIAL MODE High

TM1

TIMER REG1

SML

SERIAL MODE Low

TMM

TIMER MODE

MKH

MASK High

ETM0 :

TIMER/EVENT

MKL

MASK Low

COUNTER REG0

ZCM

ZERO CROSS MODE

ETM1 :

TIMER/EVENT

COUNTER REG1

ECNT

TIMER/EVENT

COUNTER UPCOUNTER

ECPT

TIMER/EVENT

COUNTER CAPTURE

STACK POINTER

EXTENDED

ACCUMULATOR

(BC)

(DE)

(HL)

D+

(DE)+

H+

(HL)+

(DE)

(HL)

D++

(DE)++

H++

(HL)++

D + byte :

(DE + byte)

H + A

(HL + A)

H + B

(HL + B)

H + EA

(HL + EA)

H + byte :

(HL + byte)

NMI

NMI INPUT

FT0

INTFT0

FT1

INTFT1

INTF1

INTF2

FE0

INTFE0

FE1

INTFE1

FEIN

INTFEIN

FAD

INTFAD

FSR

INTFSR

FST

INTFST

ERROR

OVERFLOW

AN4

ANALOG INPUT 4 to 7

AN7

STANDBY

CARRY

HALF CARRY

ZERO

5. irf (interrupt flag)

INSTRUCTION SET

6.1

IDENTIFIER/DESCRIPTION OF OPERAND

3. rpa to rpa3 (rp addressing)

PD78C17,78C18

6.2

SYMBOL DESCRIPTION OF INSTRUCTION CODE

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

reg

V
A
B
C

0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0

0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1

0
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0

0
0
1
1
0
1
1
0
0
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
1
0

0
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0

Special-reg

PA
PB
PC
PD
PF
MKH
MKL
ANM
SMH
SML
EOM
ETMM
TMM
MM
MCC
MA
MB
MC
MF
TXB
RXB
TM0
TM1
CR0
CR1
CR2
CR3
ZCM

0
1

special-reg

ETM0

ETM1

0
1

special-reg

ECNT

ECPT

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

reg-pair

BC
DE
HL
EA

0
0
0
0
1

0
0
1
1
0

0
1
0
1
0

reg-pair

VA
BC
DE
HL
EA

0
0
0
1

0
1
1
0

0
0
1
0

flag

sr3

sr4

rp1

irf

0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0

0
0
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0

0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0

INTF

NMI
FT0
FT1
F1
F2
FE0
FE1
FEIN
FAD
FSR
FST
ER
OV
AN4
AN5
AN6
AN7
SB

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

reg

EAH

EAL

B
C
D
E
H

rpa

0
0
0
0
1
1
1
1
0
1
1
1
1

0
0
1
1
0
0
1
1
1
0
0
1
1

0
1
0
1
0
1
0
1
1
0
1
0
1

addressing

(BC)
(DE)
(HL)
(DE)+
(HL)+
(DE)-
(HL)-
(DE + byte)
(HL + A)
(HL + B)
(HL + EA)
(HL + byte)

0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
1
1
0
1
1
1
1

1
1
0
0
1
0
0
1
1

0
1
0
1
1
0
1
0
1

addressing

(DE)
(HL)
(DE)++
(HL)++
(DE + byte)
(HL + A)
(HL + B)
(HL + EA)
(HL + byte)

0
0
0
0
1
1
1
1
1

rpa3

rpa

rpa1

rpa2

sr1

sr2

rp2

rp3

PD78C17,78C18

Note 1

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

8-bit data transfer instructions

MOV

MVI

r1, A

A, r1

sr, A

A, sr1

r, word

word, r

r, byte

sr2, byte

MVIW

wa, byte

MVIX

rpa1, byte

STAW

LDAW

STAX

rpa2

LDAX

rpa2

EXX

EXA

EXH

BLOCK

DMOV

rp3, EA

EA, rp3

0 0 0 1 1 T

0 0 0 0 1 T

0 1 0 0 1 1 0 1

0 1 0 0 1 1 0 0

0 1 1 1 0 0 0 0

0 1 1 0 1 R

0 1 1 0 0 1 0 0

0 1 1 1 0 0 0 1

0 1 0 0 1 0 A

0 1 1 0 0 0 1 1

0 0 0 0 0 0 0 1

0 1 1 1 A

0 1 0 1 A

0 0 0 1 0 0 0 1

0 0 0 1 0 0 0 0

0 1 0 1 0 0 0 0

0 0 1 1 0 0 0 1

1 0 1 1 0 1 P

1 0 1 0 0 1 P

1 1 S

0 1 1 0 1 R

0 1 1 1 1 R

Data

0 0 0 0 S

Offset

Data

Offset

Data*

Low Adrs

Data

High Adrs

sr1

(word)

byte

sr2

byte

(V. wa)

byte

(rpa1)

byte

(V. wa)

(rpa2)

B', C

C', D

E', H

H', L

V, A

V', A', EA

EA'

(DE)

(HL) , C

C 1

End if borrow

rp3

EAL, rp3

EAH

EAL

rp3

, EAH

rp3

H, L

H', L'

7/13*

(C + 1)

Note 2

Notes

Instruction Group

16-bit data transfer instructions

PD78C17,78C18

Notes

Instruction Group

8-bit operation instructions (register)

Note 1

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

16-bit data transfer instructions

DMOV

STEAX

sr3, EA

EA, sr4

word

rpa3

word

LDED

word

LHLD

word

LSPD

word

LDEAX

rpa3

PUSH

rp1

POP

rp1

LXI

TABLE

ADD

ADC

0 1 0 0 1 0 0 0

0 1 1 1 0 0 0 0

0 1 0 0 1 0 0 0

1 0 1 1 0 Q

1 0 1 0 0 Q

0 P

0 1 0 0

0 1 0 0 1 0 0 0

0 1 1 0 0 0 0 0

0 0 0 1 1 1 1 0

0 0 1 0 1 1 1 0

0 0 1 1 1 1 1 0

0 0 0 0 1 1 1 0

Data*

Low Adrs

High Adrs

sr3

(word)

C, (word + 1)

(word)

E, (word + 1)

(word)

L, (word + 1)

(word)

, (word + 1)

(rpa3)

EAL, (rpa3 + 1)

EAH

(word), B

(word + 1)

(word), D

(word + 1)

(word), H

(word + 1)

(word), SP

(word + 1)

EAL

(rpa3), EAH

(rpa3 + 1)

(SP 1)

rp1

, (SP 2)

rp1

rp2

word

(PC + 3 + A)

SBCD

SDED

SHLD

SSPD

LBCD

rp2, word

A, r

r, A

A, r

r, A

Note 2

0 1 1 1 0 0 0 0

0 1 0 0 1 0 0 0

1 1 0 1 0 0 1 U

1 1 0 0 0 0 0 V

1 0 0 1 C

0 0 0 1 1 1 1 1

0 0 1 0 1 1 1 1

0 0 1 1 1 1 1 1

0 0 0 0 1 1 1 1

1 0 0 0 C

Low Byte

1 0 1 0 1 0 0 0

1 1 0 0 0 R

0 1 0 0

1 1 0 1

0 1 0 1

Data*

High Byte

14/20

SP 2

(PC + 3 + A + 1)

A + r

r + A

A + r + CY

r + A + CY

rp1

(SP), rp1

(SP + 1)

SP + 2

sr4

PD78C17,78C18

Note

Instruction Group

Note

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

Immediate data operation instructions

ACI

ADINC

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

SUI

A, byte

r, byte

sr2, byte

SBI

SUINB

ANI

A, byte

r, byte

0 1 0 0 0 1 1 0

0 1 1 1 0 1 0 0

0 1 1 0

0 1 0 1 0 1 1 0

0 1 1 1 0 1 0 0

0 0 1 0 0 1 1 0

0 1 1 1 0 1 0 0

0 1 1 0 0 1 1 0

0 1 1 1 0 1 0 0

0 1 1 1 0 1 1 0

0 1 1 1 0 1 0 0

0 0 1 1 0 1 1 0

0 1 1 1 0 1 0 0

0 0 0 0 0 1 1 1

0 1 1 1 0 1 0 0

1 0 0 0 S

0 1 0 1 0 R

Data

A + byte

r + byte

sr2

sr2 + byte

A + byte + CY

r + byte + CY

sr2

sr2 + byte + CY

A + byte

r + byte

sr2

sr2 + byte

A byte

r byte

sr2

sr2 byte

A byte CY

r byte CY

A byte

sr2

sr2 byte

byte

r byte

ADI

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

0 1 1 0

Data

0 1 0 0 0 R

Data

1 0 1 0 S

0 0 1 0 0 R

0 1 0 0 S

0 1 1 0 0 R

1 1 0 0 S

Data

0 1 1 1 0 R

1 1 1 0 S

Data

0 0 1 1 0 R

0 1 1 0 S

Data

sr2

sr2 byte CY

No
Borrow

No Carry

Data

0 0 0 0 1 R

PD78C17,78C18

Note

Instruction Group

Note

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

Immediate data operation instructions

GTI

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

LTI

A, byte

r, byte

sr2, byte

NEI

EQI

0 1 1 0 0 1 0 0

0 0 0 1 0 1 1 1

0 1 1 0

0 0 0 1 0 1 1 0

0 1 1 1 0 1 0 0

0 0 1 0 0 1 1 1

0 1 1 1 0 1 0 0

0 0 1 1 0 1 1 1

0 1 1 1 0 1 0 0

0 1 1 0 0 1 1 1

0 1 1 1 0 1 0 0

0 1 1 1 0 1 1 1

0 1 1 1 0 1 0 0

0 0 0 1 0 R

Data

byte

sr2

byte

sr2

byte

A byte 1

r byte 1

sr2 byte 1

A byte

r byte

sr2 byte

A byte

sr2 byte

r byte

sr2 byte

A byte

ORI

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

0 1 1 0

Data

0 0 1 0 S

0 0 1 0 1 R

0 1 0 1 S

0 0 1 1 1 R

0 1 1 1 S

Data

0 1 1 0 1 R

1 1 0 1 S

Data

0 1 1 1 1 R

1 1 1 1 S

Data

r byte

No Zero

Data

ANI

sr2, byte

XRI

Zero

0 1 1 1 0 1 0 0

0 0 0 1 S

0 0 0 1 1 R

0 0 1 1 S

Data

sr2

byte

Zero

No
Borrow

No Zero

Borrow

No
Borrow

PD78C17,78C18

Note

Instruction Group

Note

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

Working register operation instructions

OFFI

ADDW

A, byte

r, byte

sr2, byte

A, byte

r, byte

sr2, byte

SBBW

ORAW

LTAW

EQAW

0 1 0 0 0 1 1 1

0 1 1 1 0 1 0 0

0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 1 0 1 0 0

1 0 0 1 S

0 1 0 1 1 R

Data

offset

byte

sr2

byte

sr2

byte

A + (V. wa)

A + (V. wa) + CY

A + (V. wa)

A (V. wa)

(V. wa)

A (V. wa)

(V. wa)

A (V. wa)

ONI

0 1 1 0

Data

0 1 0 0 1 R

Data

1 0 1 1 S

1 1 0 1

Data

Borrow

No
Borrow

No Carry

Immediate data

operation instructions

ADCW

ADDNCW

SUBW

SUBNBW

ANAW

XRAW

GTAW

NEAW

ONAW

1 1 0 0 0 0 0 0

1 0 1 0

1 1 1 0

1 1 1 1

1 0 1 1

1 0 0 0 1 0 0 0

1 0 0 1

1 0 0 1 0 0 0 0

1 0 1 0 1 0 0 0

1 0 1 1

1 1 1 0

1 1 1 1

1 1 0 0

(V. wa)

A (V. wa) 1

A (V. wa) CY

No Zero

Zero

No Zero

Zero

No Zero

PD78C17,78C18

Note

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

Working register operation instructions

LTIW

EQIW

wa, byte

DADD

EA, r2

EA, rp3

ESUB

DSUBNB

DOR

EA, rp3

0 1 1 1 0 1 0 0

0 0 0 0 0 1 0 1

0 0 0 1

Data

(V. wa)

byte

(V. wa)

byte

(V. wa) byte 1

(V. wa) byte

(V. wa)

byte

(V. wa)

byte

EA + r2

EA + rp3 +CY

EA + rp3

EA r2

rp3

EA rp3

OFFAW

EA, rp3

EA, r2

EA, rp3

0 1 1 1

1 1 0 1 1 0 0 0

Offset

Borrow

No
Borrow

No Carry

ONIW

OFFIW

EADD

DADC

DADDNC

DSUB

DSBB

DAN

DXR

1 1 0 1

1 0 1 0

1 1 1 1

1 0 1 1

1 0 0 1

EA rp3

EA rp3 CY

EA + rp3

Zero

No Zero

ANIW

ORIW

GTIW

NEIW

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 1 0 0 0 0

0 1 0 0

0 0 0 0

0 1 0 0

0 1 0 0 0 0 R

1 1 0 0 0 1 P

0 1 1 0 0 0 R

1 1 1 0 0 1 P

1 0 0 1 0 1 P

1 0 0 0 1 1 P

0 1 1 0

Offset

No Zero

16-bit operation instructions

Note

Instruction Group

PD78C17,78C18

Note 1

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

DON

MUL

EA, rp3

INX

DCRW

DAA

CLC

0 1 1 1 0 1 0 0

EA rp3 1

EA rp3

rp3

r2, r2

Remainder

r2 + 1

(V. wa)

(V. wa) + 1

EA + 1

r2 1

(V. wa)

(V. wa) 1

A + 1

Decimal Adjust Accumulator

DGT

Offset

Borrow

No
Borrow

Carry

DIV

INR

INRW

DCR

DCX

STC

NEGA

rp 1

EA 1

rp + 1

Zero

No Zero

DLT

DNE

DEQ

DOFF

0 0 1 0 0 0 0 0

0 0 1 0 1 1 R

0 0 1 1 1 0 1 0

16-bit operation instructions

EA, rp3

0 1 0 0 1 0 0 0

0 1 0 0 0 0 R

0 0 P

0 0 1 0

1 0 1 0 1 0 0 0

0 1 0 1 0 0 R

0 0 1 1 0 0 0 0

0 0 P

0 0 1 1

1 0 1 0 1 0 0 1

0 1 1 0 0 0 0 1

0 1 0 0 1 0 0 0

1 0 1 0 1 1 P

1 0 1 1

1 1 1 0

1 1 1 1

1 1 0 0

1 1 0 1

0 0 1 1

Offset

0 0 1 0 1 0 1 0

0 0 1 0 1 0 1 1

No Zero

Carry

Borrow

Note 2

Addition/subtraction instructions

Note 3

Note

Instruction Group

Multiply/divide instructions

Other operation instructions

PD78C17,78C18

Note

Instruction Group

Note

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

SLL

SLLC

DSLL

JEA

CALB

0 1 0 0 1 0 0 0

Rotate Left Digit

Rotate Right Digit

m + 1

, r2

CY, CY

m 1

, r2

CY, CY

m + 1

, r2

0, CY

m 1

, r2

0, CY

m + 1

, r2

0, CY

m 1

, r2

0, CY

n + 1

, EA

CY, CY

n 1

, EA

CY, CY

n 1

, EA

0, CY

word

B, PC

RLD

word

Carry

SLRC

DRLL

DRLR

JMP

CALL

CALF

PC + 1 + jdisp 1

PC + 2 + jdisp

n + 1

, EA

0, CY

RRD

RLL

RLR

SLR

0 0 0 0 0 1 R

Rotation/shift instructions

0 1 0 1 0 1 0 0

0 0 1 0 0 0 0 1

1 1

0 1 0 0 1 1 1

0 1 0 0 1 0 0 0

0 1 0 0 0 0 0 0

0 0 1 1 1 0 0 0

Low Adrs

0 0 1 0 1 0 0 1

Carry

Jump instructions

Call Instructions

DSLR

word

JRE

word

0 1 0 0 1 0 0 0

0 1 1 1 1

jdisp 1

jdisp

0 0 1 0 1 0 0 0

Low Adrs

0 1 R

1 0 0 1

0 0 R

0 0 1 0 0 1 R

0 0 R

1 0 1 1 0 1 0 0

0 0 0 0

1 0 1 0 0 1 0 0

0 0 0 0

High Adrs

(SP 1)

(PC + 3)

, (SP 2)

(PC + 3)

(SP 1)

(PC + 2)

, (SP 2)

(PC + 2)

word, SP

SP 2

B, PC

C, SP

SP 2

(SP 1)

(PC + 2)

, (SP 2)

(PC + 2)

15 11

00001, PC

10 0

fa, SP

SP 2

PD78C17,78C18

* 1. Data is B2 if rpa2 = D + byte, H + byte.

2. Data is B3 if rpa3 = D + byte, H + byte.

3. In the State item, a figure is in the right side of slash if rpa2 and rpa3 are D + byte, H + A, H + B, H + EA, H + byte.

Remarks

The idle state when each instruction is skipped is different from the execution state as shown below.

1-byte instruction

4 states

3-byte instruction (with *)

10 states

2-byte instruction (with *)

7 states

3-byte instruction

11 states

2-byte instruction

8 states

4-byte instruction

14 states

Notes

Instruction Group

Call instructions

Note 1

Mnemonic

Operand

Instruction Code

State

Operation

Skip

Condition

RETI

word

NOP

irf

HLT

1 0 0

(SP 1)

(PC + 1)

, (SP 2)

(PC + 1)

(SP), PC

(SP + 1)

(SP), PC

(SP + 1), SP

SP + 2

(SP), PC

(SP + 1)

Skip if (V. wa) bit = 1

Skip if f = 1

Skip if f = 0

Skip if irf = 1, then reset irf

Skip if irf = 0

Enable Interrupt

Disable Interrupt

Set Halt Mode

CALT

Offset

Uncondi-
tional skip

f = 1

SKN

SKIT

SKNIT

STOP

Set Stop Mode

No Operation

(V. wa)bit

= 1

SOFTI

RET

RETS

BIT

0 0 0 0 1 F

bit, wa

irf

0 1 0 0 1 0 0 0

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0

1 0 1 1 1 0 1 0

0 1 0 0 1 0 0 0

0 0 0 1

1 0 1 1 1 0 1 1

0 0 1 1 1 0 1 1

Note 2

CPU control instructions

0 1 1 1 0 0 1 0

1 0 1 1 1 0 0 0

1 0 0 1

0 1 1 0 0 0 1 0

0 1 0 1 1 B

0 1 0 I

0 1 1 I

(128 + 2ta), PC

(129 + 2ta), SP

SP 2

(SP 1)

PSW, (SP 2)

(PC + 1)

, (SP 3)

(PC + 1)

, PC

0060H, SP

SP 3

Reset irf, if irf = 1

SP + 2

PC + n

PSW

(SP + 2), SP

SP + 3

f = 0

irf = 1

irf = 0

Return

instructions

Skip instructions

PD78C17,78C18

LIST OF MODE REGISTERS

Read/

Name of Mode Registers

Function

Write

MODE A register

Specifies bit-wise the input/output of the port A.

MODE B register

Specifies bit-wise the input/output of the port B.

MCC

MODE CONTROL

Specifies bit-wise the port/control mode of the port C.

C register

MODE C register

Specifies bit-wise the input/output of the port C which is in port mode.

MEMORY MAPPING

Specifies the port/expansion mode of port D and port F.

MODE F register

Specifies bit-wise the input/output of the port F which is in port mode.

TMM

Timer mode register

R/W

Specifies operating mode of timer.

ETMM

Timer/event counter

Specifies the operating mode of timer/event counter.

mode register

EOM

Timer/event counter

R/W

Control the output level of CO0 and CO1.

output mode register

SML

Serial mode register

Specifies the operating mode of serial interface.

SMH

R/W

MKL

Interrupt mask register

R/W

Specifies the enable/disable of the interrupt request.

MKH

ANM

A/D channel mode

R/W

Specifies the operating mode of A/D converter.

ZCM

Zero-cross mode

Specifies the operation of zero-cross detector circuit.

PD78C17,78C18

DC CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +5.0 V

10 %, V

= AV

= 0 V)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Input voltage, low

IL1

All except RESET, STOP, NMI,

0.8

SCK, INT1, TI, AN7 to AN4

IL2

RESET, STOP, NMI, SCK, INT1,

0.2V

TI, AN7 to AN4

Input voltage,

IH1

All except RESET, STOP, NMI,

2.2

high

SCK, INT1, TI, AN7 to AN4, X1, X2

IH2

RESET, STOP, NMI, SCK, INT1,

0.8V

TI, AN7 to AN4, X1, X2

Output voltage, low

= 2.0 mA

0.45

Output voltage,

= 1.0 mA

high

1.0

= 100

0.5

Input current

INT1

Note1

, TI (PC3)

Note2

; 0 V

200

Input leakage

All except INT1, TI (PC3); 0 V

current

Output leakage

0 V

current

power

DD1

Operating mode f

= 15 MHz

0.5

1.3

supply current

DD2

STOP mode

power

DD1

Operating mode f

= 15 MHz

supply current

DD2

HALT mode f

= 15 MHz

Data retention

DDDR

Hardware/software STOP mode

2.5

voltage

Data retention

DDDR

Hardware/software

Note3

DDDR

= 2.5 V

current

STOP mode

DDDR

= 5 V

10 %

Pull-up resistor

Ports A, B, and C

3.5 V

5.5 V,

= 0 V

Notes 1. If self-bias should be generated by ZCM register.

2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register.

3. If self-bias is not generated.

PD78C17,78C18

AC CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +5.0 V

10 %, V

= AV

= 0 V)

Read/write Operation:

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

X1 input cycle time

CYC

250

Address setup time (to ALE

)

= 15 MHz, CL = 100 pF

Address hold time (from ALE

)

delay time from address

100

Address float time from RD

AFR

= 100 pF

Data input time from address

= 15 MHz, C

= 100 pF

250

Data input time from ALE

LDR

135

Data input time from RD

120

delay time from ALE

Data hold time (from RD

)

RDH

= 100 pF

ALE

delay time from RD

= 15 MHz, C

= 100 pF

RD low-level width

In Data Read

215

= 15 MHz, C

= 100 pF

In OP Code Fetch

415

= 15 MHz, C

= 100 pF

ALE high-level width

= 15 MHz, C

= 100 pF

M1 setup time (to ALE

)

= 15 MHz

M1 hold time (from ALE

)

IO/M setup time (to ALE

)

IO/M hold time (from ALE

)

delay time from address

= 15 MHz, C

= 100 pF

100

Data output time from ALE

LDW

180

Data output time from WR

= 100 pF

100

delay time from ALE

= 15 MHz, C

= 100 pF

Data setup time (to WR

)

165

Data hold time (from WR

)

WDH

ALE

delay time from WR

WR low-level width

215

PD78C17,78C18

Serial Operation :

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

SCK cycle time

CYK

SCK input

Note1

800

Note2

400

SCK output

1.6

SCK low-level width

KKL

SCK input

Note1

335

Note2

160

SCK output

700

SCK high-level width

KKH

SCK input

Note1

335

Note2

160

SCK output

700

D setup time (to SCK

)

RXK

Note1

D hold time (from SCK

)

KRX

Note1

D delay time from SCK

KTX

Note1

210

Notes 1. If clock rate is

1 in asynchronous mode, synchronous mode, or I/O interface mode.

2. If clock rate is

16 or

64 in asynchronous mode.

Remark

The numeric values in the table are those when f

= 15 MHz, C

= 100 pF.

Zero-Cross Characteristics :

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

Zero-cross detection input

AC combination

1.8

VAC

P-P

60-Hz sine wave

Zero-cross accuracy

135

Zero-cross detection input

0.05

kHz

frequency

Other Operation :

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

MAX.

UNIT

TI high, low-level width

TIH

, t

TIL

CYC

CI high, low-level width

CI1H

, t

CI1L

Event count mode

CYC

CI2H

CI2L

Pulse width test mode

CYC

NMI high, low-level width

NIH

, t

NIL

INT1 high, low-level width

I1H

, t

I1L

CYC

INT2 high, low-level width

I2H

, t

I2L

CYC

AN7 to AN4, low-level width

ANH

, t

ANL

CYC

RESET high, low-level width

RSH

, t

RSL

PD78C17,78C18

A/D CONVERTER CHARACTERISTICS (T

= 40 to +85

C, V

= +5.0 V

10 %, V

= AV

= 0 V,

 0.5 V

, 3.4 V

AREF

)

PARAMETER

SYMBOL

TEST CONDITIONS

MIN.

TYP.

MAX.

UNIT

Resolution

Bits

Absolute accuracy

Note

3.4 V

AREF

, 66 ns

CYC

170 ns

0.8 %

FSR

4.0 V

AREF

, 66 ns

CYC

170 ns

0.6 %

FSR

= 10 to +70

0.4 %

FSR

4.0 V

AREF

, 66 ns

CYC

170 ns

Conversion time

CONV

66 ns

CYC

110 ns

576

CYC

110 ns

CYC

170 ns

432

CYC

Sampling time

SAMP

66 ns

CYC

110 ns

CYC

110 ns

CYC

170 ns

CYC

Analog input voltage

IAN

AN7 to AN0 (including unused pins)

0.3

AREF

+ 0.3

Analog input

impedance

Reference voltage

AREF

3.4

AREF

current

AREF1

Operating mode

1.5

3.0

AREF2

STOP mode

0.7

1.5

power supply

DD1

Operating mode f

= 15 MHz

0.5

1.3

current

DD2

STOP mode

Note Quantization error (

1/2 LSB) is not included.

AC Timing Test Point

2.2 V

0.8 V

2.2 V

0.8 V

Test Points

1.0 V

0.45 V

PD78C17,78C18

PARAMETER

EXPRESSION

MIN./MAX.

UNIT

2T 100

MIN.

T 30

MIN.

3T 100

MIN.

7T 220

MAX.

LDR

5T 200

MAX.

4T 150

MAX.

T 50

MIN.

2T 50

MIN.

4T 50 (In data read)

MIN.

7T 50 (In OP code fetch)

2T 40

MIN.

2T 100

MIN.

T 30

MIN.

2T 100

MIN.

T 30

MIN.

3T 100

MIN.

LDW

T + 110

MAX.

T 50

MIN.

4T 100

MIN.

WDH

2T 70

MIN.

2T 50

MIN.

4T 50

MIN.

CYK

6T (SCK input)

Note1

/12T (SCK input)

Note2

MIN.

24T (SCK output)

KKL

2.5T + 5 (SCK input)

Note1

/5T + 5 (SCK input)

Note2

MIN.

12T 100 (SCK output)

KKH

2.5T + 5 (SCK input)

Note1

/5T + 5 (SCK input)

Note2

MIN.

12T 100 (SCK output)

Notes 1. If clock rate is

16,

64 in asynchronous mode.

2. If clock rate is

1, in asynchronous mode, synchronous mode, or I/O interface mode.

Remarks

T = t

CYC

= 1/f

Other items which are not listed in this table are not dependent on oscillator frequency (f

CYC

-Dependent AC Characteristics Expression

105

PD78C17,78C18

Package peak temperature: 215

Time: Within 40 s (at 200

C or higher), Count:

Twice or less
<Attention>
(1) Perform the second reflow when the

device temperature has come down to
the room temperature from the heating
by the first reflow.

(2) Do not wash the soldered portion with

flux following the first reflow.

Package peak temperature: 235

Time: Within 30 s (at 210

C or higher), Count:

Twice or less
<Attention>
(1) Perform the second reflow when the

device temperature has come down to
the room temperature from the heating
by the first reflow.

(2) Do not wash the soldered portion with

flux following the first reflow.

11. RECOMMENDED SOLDERING CONDITIONS

This

PD78C17 and 78C18 should be soldered and mounted under the following recommended conditions.

For details of the conditions, refer to the document "Surface Device Mounting Technology Manual" (IEI-

1207).

For soldering methods and conditions other than those recommended below, contact an NEC sales repre-

sentative.

Table 11-1 Surface Mounting Type Soldering Conditions

PD78C17GF-3BE:

64-pin plastic QFP (14

20 mm)

PD78C18GF-

×××

-3BE: 64-pin plastic QFP (14

20 mm)

Recommended

Soldering Method

Soldering Conditions

Condition Symbol

Infrared ray reflow

IR35-00-2

VSP

VP15-00-2

Wave soldering

WS60-00-1

Partial heating

Caution

Do not use several soldering methods in combination (except partial heating).

Table 11-2 Through-Hole Type Soldering Condition

PD78C17CW:

64-pin plastic shrink DIP (750 mils)

PD78C18CW-

×××

64-pin plastic shrink DIP (750 mils)

PD78C17GQ-36:

64-pin plastic QUIP

PD78C18GQ-

×××

-36: 64-pin plastic QUIP

Soldering Method

Soldering Conditions

Wave soldering (pin only)

Solder bath temperature: 260

C or lower, Time: Within 10 s

Partial heating

Pin temperature: 300

C or lower, Time: Within 3 s (per pin)

Caution

Wave soldering must be applied to pins only, and care must be taken to prevent solder from

coming into direct with the package body.

Solder bath temperature: 260

C or lower,

Time: Within 10 s, Count: Once, Preheating
temperature: 120

C MAX.

(package surface temperature)

Pin temperature: 300

C or lower,

Time: Within 3 s (per pin row)

107

PD78C17,78C18

APPENDIX DEVELOPMENT TOOLS

The following development tools are available to develop a system which uses the

PD78C17 or 78C18.

Language Processor

Ordering Code (Product Name)

S5A13RA87

S5A10RA87

S7B13RA87

S7B10RA87

Host Machine

PC-9800

series

IBM PC/AT

This is a program which converts a program written in mnemonic to an object code for which

microcontroller execution is possible.

Besides, it contains a function to automatically create a symbol table, and optimize a branch

instruction.

87AD series

relocatable assembler

(RA87)

PG-1500

PA-78CP14CW/

GF/GQ

PA-78CP14CW

PA-78CP14GF

PA-78CP14GQ

PG-1500

controller

With a provided board and an optional programmer adapter connected, this PROM programmer

can manipulate from a stand-alone or host machine to perform programming on single-chip

microcontroller which incorporates PROM.

It is also capable of programming a typical PROM ranging from 256 K to 4 Mbits.

PROM programmer adapter for the

PD78CP18. Used by connecting to PG-1500.

For the

PD78CP18CW

For the

PD78CP18GF-3BE

For the

PD78CP18GQ-36

Connected PG-1500 to a host machine by using serial and parallel interfaces, to control the PG-

1500 on a host machine.

Hardware

Note

Ver. 5.00/5.00A are provided with the task swap function, but it cannot be used with this software.

Remark

Operation of assemblers and the PG-1500 controller are guaranteed only on the host machines and

operating systems shown above.

Ordering Code (Product Name)

S5A13PG1500

S5A10PG1500

S7B10PG1500

Host Machine

PC-9800

series

IBM PC/AT

MS-DOS

Ver. 2.11

Ver. 5.00A

Note

PC DOS

(Ver. 3.1)

Soft

ware

PROM Write Tools

MS-DOS

Ver. 2.11

Ver. 5.00A

Note

PC DOS

(Ver. 3.1)

Supply Medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Supply Medium

3.5-inch 2HD

5-inch 2HD

5-inch 2HC

109

PD78C17,78C18

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be

taken to stop generation of static electricity as much as possible, and quickly

dissipate it once, when it has occurred. Environmental control must be

adequate. When it is dry, humidifier should be used. It is recommended to

avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools including

work bench and floor should be grounded. The operator should be grounded

using wrist strap. Semiconductor devices must not be touched with bare

hands. Similar precautions need to be taken for PW boards with semiconductor

devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

device behave differently than Bipolar or NMOS devices. Input levels of CMOS

devices must be fixed high or low by using a pull-up or pull-down circuitry. Each

unused pin should be connected to V

or GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused

pins must be judged device by device and related specifications governing the

devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed immedi-

ately after power-on for devices having reset function.

MS-DOS is a trademark of Microsoft Corporation.

PC/AT and PC DOS are trademarks of IBM Corporation.

PD78C17,78C18

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11

License not needed:

PD78C17CW, 78C17GF-3BE, and 78C17GQ-36

The customer must judge

the need for license:

PD78C18CW-

×××

, 78C18GF-

×××

-3BE, and 78C18GQ-

×××

-36

The export of these products from Japan is regulated by the Japanese government. The export of some or all of

these products may be prohibited without governmental license. To export or re-export some or all of these

products from a country other than Japan may also be prohibited without a license from that country. Please call

an NEC sales representative.

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