Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- QUALITY GRADE
- PIN CONFIGURATION (TOP VIEW)
- BLOCK DIAGRAM
- DIFFERENCES BETWEEN THE uPD78CP18(A) AND uPD78CP18
- 1. LIST OF PORT FUNCTIONS
- 1.1 PORT FUNCTIONS
- 1.2 NON-PORT FUNCTIONS (IN NORMAL OPERATION)
- 1.3 NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)
- 1.4 HANDLING OF UNUSED PINS
- 2. MEMORY CONFIGURATION
- 3. MEMORY EXTENSION
- 3.1 MODE PINS
- 3.2 MEMORY MAPPING REGISTER (MM)
- 4. PROM PROGRAMMING
- 4.1 PROM PROGRAMMING OPERATING MODES
- 4.2 PROM WRITING PROCEDURE
- 4.3 PROM READING PROCEDURE
- 5. SCREENING OF ONE-TIME PROM VERSIONS
- 6. ELECTRICAL SPECIFICATIONS
- 7. CHARACTERISTIC CURVES (REFERENCE VALUE)
- 8. PACKAGE DRAWINGS
- 9. RECOMMENDED SOLDERING CONDITIONS
- 10. DIFFERENCES BETWEEN THE uPD78CP18(A) AND uPD78C18(A)
- APPENDIX DEVELOPMENT TOOLS
1994
8-BIT SINGLE-CHIP MICROCOMPUTER
Document No.
IC-3233A
(O. D. No.
IC-8702A)
Date Published March 1995 P
Printed in Japan
PD78CP18(A)
MOS INTEGRATED CIRCUIT
DATA SHEET
The information in this document is subject to change without notice.
The mark
5
shows major revised points.
DESCRIPTION
The
PD78CP18(A) is a version of the
PD78C18(A) in which the internal mask ROM is replaced by one-time PROM.
The one-time PROM version can be programmed once only by users, and is ideally suited for small-scall of many
differnt products, and rapid development and time-to-market of a new product.
The detailed functions are descrived in the following user's manual. Read this manual before starting design
work.
87AD series
PD78C18 user's manual: IEU-1314
FEATURES
High reliability compared to the
PD78CP18
Compatible with the
PD78C11A(A), 78C12A(A), 78C14(A), 78C18(A)
Internal PROM: 32768 W
8
Internal PROM capacity can be changed by software to conform to the
PD78C11A(A), 78C12A(A), 78C14(A),
78C18(A).
PROM programming characteristics:
PD27C256A compatible
Power supply voltage range: 5 V
10 %
Supports QTOP
TM
microcomputer
Remark
QTOP microcomputer is the generic name of NEC's single-chip microcomputers for which NEC
provides total service including writing, marking, screening, and inspection.
ORDERING INFORMATION
Part Number
Package
Internal ROM
PD78CP18GF(A)-3BE
64-pin plastic QFP (14
20 mm)
One-time PROM
PD78CP18GQ(A)-36
64-pin plastic QUIP
One-time PROM
QUALITY GRADE
Part Number
Quality Grade
PD78CP18GF(A)-3BE
Special
PD78CP18GQ(A)-36
Special
Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.
5
1993
2
PD78CP18(A)
PIN CONFIGURATION (TOP VIEW)
PD78CP18GQ(A)-36
1
A0/PA0
2
A1/PA1
3
A2/PA2
4
A3/PA3
5
A4/PA4
6
A5/PA5
7
A6/PA6
8
A7/PA7
9
PB0
10
PB1
11
PB2
12
PB3
13
PB4
14
PB5
15
CE/PB6
16
OE/PB7
17
PC0/T
X
D
18
PC1/R
X
D
19
PC2/SCK
20
PC3/INT2
21
PC4/TO
22
PC5/CI
23
PC6/CO0
24
PC7/CO1
25
A9/NMI
26
INT1
27
MODE1
28
RESET
29
MODE0
30
X2
31
X1
32
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
DD
STOP/V
PP
PD7/O7
PD6/O6
PD5/O5
PD4/O4
PD3/O3
PD2/O2
PD1/O1
PD0/O0
PF7
PF6/A14
PF5/A13
PF4/A12
PF3/A11
PF2/A10
PF1
PF0/A8
ALE
WR
RD
AV
DD
V
AREF
AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
AV
SS
3
PD78CP18(A)
PD78CP18GF(A)-3BE
AN4
AN3
AN2
AN1
AN0
AV
SS
V
SS
X1
X2
MODE0
RESET
MODE1
INT1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
52
53
54
55
56
57
58
59
60
61
62
63
64
A0/PA0
A1/PA1
O3/PD3
O4/PD4
O5/PD5
O6/PD6
O7/PD7
V
PP/
STOP
V
DD
A2/PA2
A3/PA3
A4/PA4
A5/PA5
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
PF3/A11
PF2/A10
PF1
PF0/A8
ALE
WR
RD
AV
DD
V
AREF
AN7
AN6
AN5
PF7
PF6/A14
PF5/A13
PF4/A12
51
50
49
1
2
3
PB1
PB2
PB3
PB4
PB5
CE/PB6
OE/PB7
PC0/T
X
D
PC1/R
X
D
PC2/SCK
PC3/INT2
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
A9/NM1
A6/PA6
A7/PA7
PB0
PD2/O2
PD1/O1
PD0/O0
4
PD78CP18(A)
SERIAL I/O
X1
ALU
(8/16)
PC0/T
X
D
X2
PC1/R
X
D
PC2/SCK
OSC
INT.
CONTROL
A9/NMI
INT1
8
8
4
8
TIMER
TIMER/EVENT
COUNTER
8
8
8
PC3/INT2/TI
PC4/TO
PC5/CI
PC6/CO0
PC7/CO1
A/D
CONVERTER
V
AREF
AV
DD
AV
SS
8
LATCH
INC/DEC
PC
SP
EA
EA'
V
A
B
C
D
E
H
L
V'
A'
B'
C'
D'
E'
H'
L'
BUFFER
10
16
15
PROM
(32-KBYTE)
DATA
MEMORY
(1-KBYTE)
8/16
INST. REG
LATCH
LATCH
16
16
INTERNAL DATA BUS
16
16
16
6
INST.
DECODER
8
8
STANDBY
CONTROL
SYSTEM
CONTROL
READ/WRITE
CONTROL
RESET
V
SS
V
DD
V
PP/
STOP
MODE0
MODE1
ALE
WR
RD
POR
T F
8
8
5
POR
T D
8
8
8
POR
T C
8
PC7 to PC0
8
POR
T B
6
PB5 to PB0
8
POR
T A
8
PA7/A7 to PA0/A0
8
16
AN7 to AN0
PSW
PD7/O7/AD7
to PD0/O0/AD0
PF7/AB15
MAIN
G.R
ALT
G.R
8
8
PF6/A14/AB14
to PF2/A10/AB10
PF1/AB9
PF0/A8/AB8
OE/PB7
CE/PB6
Note
BLOCK DIAGRAM
Note Can be used only when RAE bit of MM register is 1.
External memory is needed in case of 0.
5
PD78CP18(A)
DIFFERENCES BETWEEN THE
PD78CP18(A) AND
PD78CP18
PD78CP18
PD78CP18(A)
Standard
Special
Input leakage current
AN7 to AN0;
10
A (MAX.)
64-pin plastic shrink DIP (750 mil)
64-pin plastic QUIP
64-pin plastic QFP (14
20 mm)
64-pin ceramic shrink DIP with
window (750 mil)
64-pin ceramic WQFN
Input leakage current
AN7 to AN0:
1
A (MAX.)
64-pin plastic QFP (14
20 mm)
64-pin plastic QUIP
Quality grade
Electrical
specifications
Package
Product
Name
Item
6
PD78CP18(A)
CONTENTS
1.
LIST OF PORT FUNCTIONS .......................................................................................................................7
1.1
PORT FUNCTIONS ...............................................................................................................................................7
1.2
NON-PORT FUNCTIONS (IN NORMAL OPERATION) ..................................................................................... 8
1.3
NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ) ..................................................... 10
1.4
HANDLING OF UNUSED PINS ......................................................................................................................... 10
2.
MEMORY CONFIGURATION ....................................................................................................................11
3.
MEMORY EXTENSION .............................................................................................................................16
3.1
MODE PINS ........................................................................................................................................................ 16
3.2
MEMORY MAPPING REGISTER (MM) ............................................................................................................17
4.
PROM PROGRAMMING ...........................................................................................................................20
4.1
PROM PROGRAMMING OPERATING MODES ............................................................................................... 21
4.2
PROM WRITING PROCEDURE ......................................................................................................................... 22
4.3
PROM READING PROCEDURE ......................................................................................................................... 23
5.
SCREENING OF ONE-TIME PROM VERSIONS ...................................................................................... 24
6.
ELECTRICAL SPECIFICATIONS ................................................................................................................25
7.
CHARACTERISTIC CURVES (REFERENCE VALUE) ..............................................................................39
8.
PACKAGE DRAWINGS .............................................................................................................................42
9.
RECOMMENDED SOLDERING CONDITIONS ........................................................................................44
10. DIFFERENCES BETWEEN THE
PD78CP18(A) AND
PD78C18(A) ..................................................... 45
APPENDIX. DEVELOPMENT TOOLS ..........................................................................................................46
7
PD78CP18(A)
1.
LIST OF PORT FUNCTIONS
1.1
PORT FUNCTIONS
PA7 to PA0
(Port A)
Input/Output
PB7 to PB0
(Port B)
8-bit input-output port, which can specify input/output bit-wise.
Function
Pin Name
I/O
PC7 to PC0
(Port C)
PD7 to PD0
(Port D)
PF7 to PF0
(Port F)
8-bit input-output port, which can specify input/output in byte units.
8-bit input-output port, which can specify input/output bit-wise.
Remark
These port pins have alternate function pins as shown in 1.2 "NON-PORT FUNCTIONS (IN NORMAL
OPERATION)" and 1.3 "NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)".
8
PD78CP18(A)
1.2
NON-PORT FUNCTIONS (IN NORMAL OPERATION)
Pin Name
I/O
Output
T
X
D
(Transmit Data)
R
X
D
(Receive Data)
SCK
(Serial Clock)
INT2
(Interrupt Request)
Input/output
Serial data output pin
Serial data input pin
Function
PC1
PC0
PC2
Input
PC3
Edge trigger (falling edge) maskable interrupt input pin
Timer external clock input pin
TI
(Timer Input)
Zero-cross
TO
(Timer Output)
CI
(Counter Input)
AC input zero-cross detection pin
During timer count time, square wave with one internal clock cycle as
one half cycle is output.
Timer/event counter external pulse input pin
Input
Input
Input
Output
PC5
PC4
CO0 and CO1
(Counter
Output 0, 1)
AD7 to AD0
(Address/Data
Bus 7 to 0)
AB15 to AB8
(Address Bus
15 to 8)
Serial clock input/output pin. Output when internal clock is used, input
when external clock is used.
Output
PC6 and PC7
Square wave output programmable by timer/event counter.
Input/output
PD7 to PD0
Multiplexed address/data bus when external memory is used
Output
PF7 to PF0
Address bus when external memory is used
Output
Strobe signal which is output for write operation of external memory. It
becomes high in any cycle other than the data write machine cycle of
external memory. When RESET signal is either low or in the hardware
STOP mode, this signal becomes high-impedance.
Output
Strobe signal which is output for read operation of external memory. It
becomes high in any cycle other than the data read machine cycle of
external memory. When RESET signal is either low or in the hardware STOP
mode, this signal becomes output high-impedance.
RD
(Read Strobe)
WR
(Write Strobe)
Output
ALE
(Address
Latch Enable)
Strobe signal to latch externally the lower address information which is
output to PD7 to PD0 pins to access external memory. When RESET signal
is either low or in the hardware STOP mode, this signal becomes high-
impedance.
MODE0
MODE1
(Mode)
Set MODE0 pin to "0" (low level), and MODE1 pin to "1" (high level)
Note
Non-maskable interrupt input pin of the edge trigger (falling edge)
NMI
(Non-Maskable
Interrupt)
Input
Note Pull-up. Pull-up resister R is 4 [k
]
R
0.4 t
CYC
[k
] (t
CYC
is ns unit).
Alternate
Function Pin
Input
Input
Input/output
9
PD78CP18(A)
X1, X2
(Crystal)
RESET
(Reset)
STOP
(Stop)
V
DD
V
SS
A maskable interrupt input pin of the edge trigger (rising edge). Also, it can
be used as a zero-cross detection pin for AC input.
8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge
detection (falling edge) input.
A common pin serving both as a reference voltage input pin for A/D
converter and as a control pin for A/D converter operation.
Power supply pin for A/D converter.
GND pin for A/D converter.
Crystal connection pins for system clock oscillation. X1 should be input
when a clock is supplied from outside. Inverted clock of X1 should be input
in X2.
Low-level active system reset input.
Hardware STOP mode control signal input pin. When the low level is input
to this pin, the oscillation stops.
Positive power supply pin.
GND pin.
Pin Name
I/O
Function
Alternate
Function Pin
INT1
(Interrupt
Request)
AN7 to AN0
(Analog Input)
Input
Input
Input
V
AREF
(Reference
Voltage)
AV
DD
(Analog V
DD
)
AV
SS
(Analog V
SS
)
Input
Input
10
PD78CP18(A)
1.3
NON-PORT FUNCTIONS (DURING PROM WRITE/VERIFY AND READ)
Pin Name
I/O
Function
Alternate
Function Pin
A7 to A0
Input
Address lower 8 bit input pins
Chip enable signal input pin
Output enable signal input pin
Data input/output pins
Address higher 7 bit input pins
Set MODE0 pin to "1" (high level), and MODE1 pin to "0" (low level).
Set to "0" (low level).
High-voltage application pin
"1" (high level) is input when EPROM is read.
Input
CE
Input
OE
PB6
PB7
Input/output
O7 to O0
PD7 to PD0
Input
PF6 to PF2
A14 to A10
PA7 to PA0
PF0
A8
NMI
A9
MODE0
MODE1
RESET
V
PP
Input
Input
Input
STOP
1.4
HANDLING OF UNUSED PINS
PA7 to PA0
PB7 to PB0
PC7 to PC0
PD7 to PD0
PF7 to PF0
RD
WR
ALE
STOP
INT1, NMI
AV
DD
V
AREF
AV
SS
AN7 to AN0
Recommended Connection
Pin
Connect to V
DD
.
Connect to V
SS
or V
DD
.
Connect to V
DD
.
Connect to V
SS
.
Connect to AV
SS
or AV
DD
.
Leave open.
Connect to V
SS
or V
DD
via resistor.
11
PD78CP18(A)
2.
MEMORY CONFIGURATION
The
PD78CP18(A) memory can operate in the following 4 modes according to the mode specification.
q
q
PD78C11A mode (see Figure 2-1)
q
q
PD78C12A mode (see Figure 2-2)
q
q
PD78C14 mode (see Figure 2-3)
q
q
PD78C18 mode (see Figure 2-4)
In addition, the internal PROM and internal RAM address ranges can be specified for efficient mapping of external
memory (excluding PROM) (see 3.2 "MEMORY MAPPING REGISTER (MM)").
The vector area and call table area are common to all modes.
Setting the hardware/software STOP mode or HALT mode enables internal RAM data to be retained at a low
consumption current.
12
PD78CP18(A)
FEFFH
FF00H
FFFFH
0080H
00BFH
External Memory
61184W
8
Internal RAM
256W
8
0000H
0000H
0004H
RESET
NMI
0008H INTT0/INTT1
0010H INT1/INT2
0018H INTE0/INTE1
0020H INTEIN/INTAD
0028H INTSR/INTST
0060H SOFTI
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0081H
0082H
0083H
00BEH
t = 0
t = 1
t = 31
Call
Table
Area
Internal PROM
4096W
8
0FFFH
1000H
00C0H
USER'S AREA
0FFFH
Vector
Area
Figure 2-1. Memory Map (
PD78C11A Mode)
13
PD78CP18(A)
FEFFH
FF00H
FFFFH
0080H
00BFH
External Memory
57088W
8
Internal RAM
256W
8
0000H
0000H
0004H
RESET
NMI
0008H INTT0/INTT1
0010H INT1/INT2
0018H INTE0/INTE1
0020H INTEIN/INTAD
0028H INTSR/INTST
0060H SOFTI
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0081H
0082H
0083H
00BEH
t = 0
t = 1
t = 31
Call
Table
Area
Internal PROM
8192W
8
1FFFH
2000H
00C0H
USER'S AREA
1FFFH
Vector
Area
Figure 2-2. Memory Map (
PD78C12A Mode)
14
PD78CP18(A)
FEFFH
FF00H
FFFFH
0080H
00BFH
External Memory
48896W
8
Internal RAM
256W
8
0000H
0000H
0004H
RESET
NMI
0008H INTT0/INTT1
0010H INT1/INT2
0018H INTE0/INTE1
0020H INTEIN/INTAD
0028H INTSR/INTST
0060H SOFTI
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0081H
0082H
0083H
00BEH
t = 0
t = 1
t = 31
Call
Table
Area
Internal PROM
16384W
8
3FFFH
4000H
00C0H
USER'S AREA
3FFFH
Vector
Area
Figure 2-3. Memory Map (
PD78C14 Mode)
15
PD78CP18(A)
FBFFH
FC00H
FFFFH
0080H
00BFH
External Memory
31744W
8
Internal RAM
1024W
8
0000H
0000H
0004H
RESET
NMI
0008H INTT0/INTT1
0010H INT1/INT2
0018H INTE0/INTE1
0020H INTEIN/INTAD
0028H INTSR/INTST
0060H SOFTI
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
LOW ADRS
HIGH ADRS
0081H
0082H
0083H
00BEH
t = 0
t = 1
t = 31
Call
Table
Area
Internal PROM
32768W
8
7FFFH
8000H
00C0H
USER'S AREA
7FFFH
Vector
Area
Figure 2-4. Memory Map (
PD78C18 Mode)
16
PD78CP18(A)
3.
MEMORY EXTENSION
The
PD78CP18(A) allows external memory extension by means of the MEMORY MAPPING register (MM) or the
MODE0 and MODE1 pins. Also, the internal PROM and internal RAM access areas can be specified by means of bits
MM7, MM6 and MM5 of the MEMORY MAPPING register.
3.1
MODE PINS
The
PD78CP18(A) can be switched between programming mode and normal operation mode according to the
specification of the MODE0 and MODE1 pins.
Table 3-1 shows the modes set by the MODE pins.
Table 3-1. Modes Set By MODE Pins
MODE1
MODE2
Operating Mode
L
L
Setting prohibited
L
H
Programming mode
Note
H
L
Normal operation mode
H
H
Setting prohibited
Note See 4. "PROM PROGRAMMING".
When MODE0 and MODE1 are driven high, a 4 [k
]
R
0.4 t
CYC
[k
] pull-up resistor should be used (t
CYC
: ns units).
17
PD78CP18(A)
3.2
MEMORY MAPPING REGISTER (MM)
The MEMORY MAPPING register is an 8-bit register which performs the following controls:
Port/extension mode specification for PD7 to PD0 and PF7 to PF0
Enabling/disabling of internal RAM accesses
Specification of internal PROM and RAM access areas
The configuration of the MEMORY MAPPING register is shown in Figure 3-1.
(1)
Bits MM2 to MM0
These bits control the PD7 to PD0 port/extension mode specification, input/output specification, and the PF7 to
PF0 address output specification.
As shown in Figure 3-1, there is a choice of four capacities for the connectable external memory:
256 bytes
4 Kbytes
16 Kbytes
32 K/48 K/56 K/60 Kbytes (set by bits MM7 to MM5)
Ports of PF7 to PF0 not used as address outputs can be used as general-purpose ports.
When RESET signal is input or in the hardware STOP mode, these bits are reset to (0) and PD7 to PD0 are set
to input port mode (high-impedance).
(2)
MM3 bit (RAE)
This bit enables (RAE = 1) and disables (RAE = 0) internal RAM access. This bit should be set to "0" during standby
operation and when externally connected RAM, not internal RAM, is used.
In normal operation this bit retains its value when RESET signal is input. However, the RAE bit is undefined after
a power-on reset, and must therefore be initialized by an instruction.
(3)
Bits MM7 to MM5
These bits specify the access area of the internal PROM.
When STOP or RESET signal is input, these bits are reset, selecting the 32-Kbyte mode (
PD78C18 mode).
These bits are only valid in the
PD78CG14, 78CP14, 78CP18, 78CP14(A), and 78CP18(A); if data is written to these
bits in the
PD78C11A(A), 78C12A(A), 78C14(A), or 78C18(A), it will be ignored. Therefore, a program developed
on the
PD78CP18(A) can be directly ported to mask ROM.
18
PD78CP18(A)
Figure 3-1. MEMORY MAPPING Register Format
7
6
5
4
3
2
1
0
RAE
MM2
MM1
MM0
MM7
MM6
MM5
Extension
mode
Extension
mode
Extension
mode
PD7 to PD0 = Extension
mode
PF7 to PF0 = Port mode
PD7 to PD0 = Input port
PF7 to PF0 = Port mode
PD7 to PD0 = Output port
PF7 to PF0 = Port mode
PD7 to PD0 =
PF3 to PF0 =
PF7 to PF4 = Port mode
PD7 to PD0 =
PF7 to PF0 =
32 K/48 K/
56K/60K
Note
bytes
Single chip
Port
mode
256 bytes
4 Kbytes
Exten-
sion
mode
16 Kbytes
1
0
0
0
1
0
1
1
0
1
1
1
PD7 to PD0 =
PF5 to PF0 =
PF7 & PF6 = Port mode
0 0 1
0
0
0
Internal PROM
Internal RAM
Access Area
Access Area
0
0
0
0000H to 7FFFH
FC00H to FFFFH
(32 Kbytes:
(1 Kbyte)
PD78C18 mode)
0
0
1
0000H to 3FFFH
FF00H to FFFFH
(16 Kbytes:
(256 bytes)
PD78C14 mode)
0
1
1
0000H to 1FFFH
FF00H to FFFFH
(8 Kbytes:
(256 bytes)
PD78C12A mode)
1
0
1
0000H to 0FFFH
FF00H to FFFFH
(4 Kbytes:
(256 bytes)
PD78C11A mode)
Other than above
Setting Prohibited
MM7
MM6
MM5
Internal PROM/RAM Access Areas
Note
Depends on MM7 to MM5 bit-setting
Disable
Enable
0
1
Internal RAM Access
19
PD78CP18(A)
Figure 3-2. External Extension Modes Set by MEMORY MAPPING Register
Caution
The internal PROM and internal RAM access areas are determined by MM7 to MM5.
External Memory
(32/48/56/
60 KBytes)
External Memory
(32/48/56/
60 KBytes)
Internal PROM
(4/8/16/32
KBytes)
Not Used
4-KByte Extension Mode
Not Used
256-Byte Extension Mode
Not Used
Port Mode
Not Used
Not Used
Not Used
64K
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal RAM
Internal RAM
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
Internal PROM
(4/8/16/32
KBytes)
External Memory(256 Bytes)
External Memory(256 Bytes)
External Memory(256 Bytes)
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
Internal RAM
External Memory
(16 KBytes)
External Memory
(16 KBytes)
External Memory(4 KBytes)
External Memory(4 KBytes)
Internal RAM
Internal RAM
16-KByte Extension Mode
32-/48-/56-/60-KByte
Extension Mode
0
0
64K
64K
0
64K
64K
0
0
20
PD78CP18(A)
Pin Name
Function
RESET
Low-level input (at write/verify and read)
MODE0
High-level input (at write/verify and read)
MODE1
Low-level input (at write/verify and read)
V
PP
Note
High-voltage input (at write/verify), high-level input (at read)
CE
Note
Chip enable input
OE
Note
Output enable input
A14 to A0
Note
Address input
O7 to O0
Note
Data input (at write), data output (at verify, read)
V
DD
Note
Supply voltage input
4.
PROM PROGRAMMING
The
PD78CP18(A) incorporates 32768
8-bit PROM as a program memory. The pins shown in Table 4-1 are used
for write/verify operations on this PROM.
PD78CP18(A) program timing is compatible with the
PD27C256A.
Please read the following in conjunction with documentation of the
PD27C256A.
Table 4-1. Pins Used in PROM Programming
Note These pins correspond to the
PD27C256A.
Caution
The
PD78CP18(A) one-time PROM version is not equipped with an erasure window, and therefore
ultraviolet erasure cannot be performed on it.
21
PD78CP18(A)
Caution When +12.5 V is applied to V
PP
and +6 V is applied to V
DD
, setting both CE and OE to "L" is prohibited.
Table 4-3. Recommended Connection of Unused Pins (in PROM Programming Mode)
Operating Mode
CE
Note
OE
Note
V
PP
Note
V
DD
Note
RESET
MODE0
MODE1
Program
L
H
+12.5 V
+6 V
L
H
L
Program verify
H
L
Program inhibit
H
H
Read
L
L
+5 V
+5 V
Output disable
L
H
Standby
H
L/H
Note
These pins correspond to the
PD27C256A.
4.1
PROM PROGRAMMING OPERATING MODES
The PROM programming operating mode is set as shown in Table 4-2. Pins not used for programming should
be handled as shown in Table 4-3.
Table 4-2. PROM Programming Modes
Pin
Recommended Connection
INT1
Connect to V
SS
.
X1
AN0 to AN7
V
AREF
AV
DD
AV
SS
Pins other than the
Connect to V
SS
via individual resistor.
above
X2
Leave open.
22
PD78CP18(A)
A14/PF6-A10/PF2
A9/NMI
A8/PF0
A7/PA7-A0/PA0
O7/PD7-O0/PD0
V
PP
V
IH
V
DD
+ 1
V
DD
V
IH
V
IL
V
IH
V
IL
V
PP
V
DD
CE/PB6
OE/PB7
Data Input
Data Output
Data Input
Address (Lower 8 Bits)
Address (Higher 7 Bits)
Write
Verify
Additional Write
Repeated X Times
4.2
PROM WRITING PROCEDURE
The PROM writing procedure is as shown below, allowing high-speed writing.
(1)
Connect unused pins to V
SS
via a pull-down resistor, and supply +6 V to V
DD
and +12.5 V to V
PP
.
(2)
Provide the initial address.
(3)
Provide the write data.
(4)
Provide a 1-ms program pulse (active low) to the CE pin.
(5)
Verify mode. If written, go to (7); if not written, repeat (3) to (5). If the write operation has failed 25 times, go
to (6).
(6)
Halt write operation due to defective device.
(7)
Provide write data and program pulse of X times x 3 ms (X; repeated times from (3) to (5)) (additional write).
(8)
Increment the address.
(9)
Repeat (3) to (8) until the final address.
Figure 4-1. PROM Write/Verify Timing
23
PD78CP18(A)
Address Input
Data Output
A14/PF6-A10/PF2
A9/NMI
A8/PF0
CE/PB6
OE/PB7
O7/PD7-O0/PD0
4.3
PROM READING PROCEDURE
PROM contents can be read onto the external data bus (O7 to O0) using the following procedure.
(1)
Connect unused pins to V
SS
via a pull-down resistor.
(2)
Supply +5 V to the V
DD
and V
PP
pins.
(3)
Input address of data to be read to pins A14 to A0.
(4)
Read mode
(5)
Output data to pins O7 to O0.
Timing for steps (2) to (5) above is shown in Figure 4-2.
Figure 4-2. PROM Read Timing
24
PD78CP18(A)
5.
SCREENING OF ONE-TIME PROM VERSIONS
Because of their construction, one-time PROM versions cannot be fully tested by NEC before shipment. After the
necessary data has been written, it is recommended that screening be implemented in which PROM verification is
performed after high-temperature storage under the following conditions.
Storage Temperature
Storage Time
125
C
24 hours
NEC provides writing, marking, screening, and inspection services for single-chip microcomputers labeld QTOP
microcomputers. For details, consult NEC.
5
25
PD78CP18(A)
6.
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C)
PARAMETER
SYMBOL
TEST CONDITIONS
RATINGS
UNIT
V
DD
0.5 to +7.0
V
AV
DD
AV
SS
to V
DD
+ 0.5
V
Power supply voltage
AV
SS
0.5 to +0.5
V
V
PP
0.5 to +13.5
V
Other than NMI/A9 pin
0.5 to V
DD
+ 0.5
V
Input voltage
V
I
NMI/A9 pin
0.5 to +13.5
V
Output voltage
V
O
0.5 to V
DD
+ 0.5
V
All output pins
4.0
mA
Output current low
I
OL
Total of all output pins
100
mA
All output pins
2.0
mA
Output current high
I
OH
Total of all output pins
50
mA
A/D converter reference
input voltage
Ambient operating temperature
T
A
40 to +85
C
Storage temperature
T
stg
65 to +150
C
Caution
If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,
the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the
values exceeding which the product may be physically damaged. Be sure to use the product with these
rated values never exceeded.
V
AREF
0.5 to AV
DD
+ 0.3
V
5
5
26
PD78CP18(A)
RESONATOR
RECOMMENDED CIRCUIT
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
4
15
Ceramic or
crystal
Oscillator frequency (f
XX
)
MHz
resonator
A/D converter used
5.8
15
A/D converter not
used
X1 input frequency (f
X
)
MHz
External clock
X1 rise time,
fall time (t
r
, t
f
)
X1 input high-, low-
level width (t
H
, t
L
)
Cautions
1. Place the oscillator as close as possible to the X1 and X2 pins.
2. Ensure that no other signal lines pass through the shaded area.
OSCILLATOR CHARACTERISTICS
(T
A
= 40 to +85
C, V
DD
= AV
DD
= +5.0 V
10 %, V
SS
= AV
SS
= 0 V,
V
DD
0.8 V
AV
DD
V
DD
, 3.4 V
V
AREF
AV
DD
)
X1
X2
C2
C1
X1
X2
HCMOS
Inverter
A/D converter used
5.8
15
A/D converter not
used
0
20
ns
20
250
ns
4
15
27
PD78CP18(A)
V
IL1
0
0.8
V
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7
Input voltage low
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7
All except RESET, STOP, NMI,
SCK, INT1, TI, AN4 to AN7, X1, X2
Input voltage high
RESET, STOP, NMI, SCK, INT1,
TI, AN4 to AN7, X1, X2
Output voltage low
V
OL
I
OL
= 2.0 mA
0.45
V
V
DD
1.0
Output voltage high
V
OH
V
DD
0.5
Input current
I
I
INT1
Note1
, TI(PC3)
Note2
; 0 V
V
I
V
DD
200
A
All except INT1, TI (PC3),
Input leakage
AN7 to AN0; 0 V
V
I
V
DD
current
AN7 to AN0; 0 V
V
I
V
DD
1
A
Output leakage
current
AI
DD1
Operating mode f
XX
= 15 MHz
0.5
1.3
mA
AI
DD2
STOP mode
10
20
A
I
DD1
Operating mode f
XX
= 15 MHz
16
35
mA
I
DD2
HALT mode f
XX
= 15 MHz
7
13
mA
Data retention
voltage
Hardware/software
Note3
V
DDDR
= 2.5 V
1
15
A
I
DDDR
STOP mode
V
DDDR
= 5 V
10 %
10
50
A
DC CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= AV
DD
= +5.0 V
10 %, V
SS
= AV
SS
= 0 V)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
C
I
10
pF
f
C
= 1 MHz
Output capacitance
C
O
Unmeasured pins
20
pF
returned to 0 V
Input-output capacitance
C
IO
20
pF
CAPACITANCE (T
A
= 25
C, V
DD
= V
SS
= 0 V)
Notes 1. If self-bias should be generated by ZCM register.
2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register.
3. If self-bias is not generated.
V
IL2
0
0.2V
DD
V
V
IH1
2.2
V
DD
V
V
IH2
0.8 V
DD
V
DD
V
10
A
I
LO
0 V
V
O
V
DD
10
A
I
LI
AV
DD
power supply
current
V
DD
power supply
current
Data retention
current
V
DDDR
Hardware/software STOP mode
2.5
V
I
OH
= 1.0 mA
V
I
OH
= 100
A
V
5
28
PD78CP18(A)
AC CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= AV
DD
= +5.0 V
10 %, V
SS
= AV
SS
= 0 V)
READ/WRITE OPERATION:
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
X1 input cycle time
t
CYC
66
167
ns
Address setup time (to ALE
)
t
AL
30
ns
Address hold time (from ALE
)
t
LA
f
XX
= 15 MHz, CL = 150 pF
35
ns
RD
delay time from address
t
AR
100
ns
Address float time from RD
t
AFR
C
L
= 150 pF
20
ns
Data input time from address
t
AD
250
ns
Data input time from ALE
t
LDR
135
ns
f
XX
= 15 MHz, C
L
= 150 pF
Data input time from RD
t
RD
120
ns
RD
delay time from ALE
t
LR
15
ns
Data hold time (from RD
)
t
RDH
C
L
= 150 pF
0
ns
ALE
delay time from RD
t
RL
f
XX
= 15 MHz, C
L
= 150 pF
80
ns
In data read
f
XX
= 15 MHz, C
L
= 150 pF
RD low-level width
t
RR
In OP code fetch
f
XX
= 15 MHz, C
L
= 150 pF
ALE high-level width
t
LL
f
XX
= 15 MHz, C
L
= 150 pF
90
ns
WR
delay time from address
t
AW
100
ns
f
XX
= 15 MHz, C
L
= 150 pF
Data output time from ALE
t
LDW
197
ns
Data output time from WR
t
WD
C
L
= 150 pF
140
ns
WR
delay time from ALE
t
LW
15
ns
Data setup time (to WR
)
t
DW
127
ns
Data hold time (from WR
)
t
WDH
f
XX
= 15 MHz, C
L
= 150 pF
60
ns
ALE
delay time from WR
t
WL
80
ns
WR low-level width
t
WW
215
ns
215
ns
415
ns
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
Zero-cross detection input
V
ZX
1
1.8
VAC
P-P
Zero-cross accuracy
A
ZX
AC coupling
135
mV
60-Hz sine wave
Zero-cross detection input
frequency
ZERO-CROSS CHARACTERISTICS :
f
ZX
0.05
1
kHz
29
PD78CP18(A)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
Note1
800
ns
SCK input
SCK cycle time
t
CYK
Note2
400
ns
SCK output
1.6
s
Note1
335
ns
SCK input
SCK low-level width
t
KKL
Note2
160
ns
SCK output
700
ns
Note1
335
ns
SCK input
SCK high-level width
t
KKH
Note2
160
ns
SCK output
700
ns
R
X
D setup time (to SCK
)
t
RXK
Note1
80
ns
R
X
D hold time (from SCK
)
t
KRX
Note1
80
ns
T
X
D delay time from SCK
t
KTX
Note1
210
ns
Notes 1. If clock rate is
1 in asynchronous mode, synchronous mode, or I/O interface mode.
2. If clock rate is
16 or
64 in asynchronous mode.
Remark
The numeric values in the table are those when f
XX
= 15 MHz, CL = 100 pF.
SERIAL OPERATION :
OTHER OPERATION :
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
MAX.
UNIT
TI high-, low-level width
t
TIH
, t
TIL
6
t
CYC
Event counter mode
t
CI1H
, t
CI1L
6
t
CYC
Frequency test mode
CI high-, low-level width
Pulse width test mode
t
CI2H
, t
CI2L
ECNT latch and clear input
48
t
CYC
INTEIN set input
NMI high-, low-level width
t
NIH
, t
NIL
10
s
INT1 high-, low-level width
t
I1H
, t
I1L
36
t
CYC
INT2 high-, low-level width
t
I2H
, t
I2L
36
t
CYC
AN4 to AN7, low-level width
t
ANH
, t
ANL
36
t
CYC
RESET high-, low-level width
t
RSH
, t
RSL
10
s
30
PD78CP18(A)
2.2 V
0.8 V
2.2 V
0.8 V
Test Points
V
DD
1.0 V
0.45 V
A/D CONVERTER CHARACTERISTICS (T
A
= 40 to +85
C, V
DD
= +5.0 V
10 %, V
SS
= AV
SS
= 0 V,
V
DD
0.5 V
AV
DD
V
DD
, 3.4 V
V
AREF
AV
DD
)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Resolution
8
Bits
3.4 V
V
AREF
AV
DD
, 66 ns
t
CYC
167 ns
0.8 %
FSR
Absolute accuracy
Note
4.0 V
V
AREF
AV
DD
, 66 ns
t
CYC
167 ns
0.6 %
FSR
T
A
= 10 to +70
C,
4.0 V
V
AREF
AV
DD
, 66 ns
t
CYC
167 ns
66 ns
t
CYC
110 ns
576
t
CYC
Conversion time
t
CONV
110 ns
t
CYC
167 ns
432
t
CYC
66 ns
t
CYC
110 ns
96
t
CYC
Sampling time
t
SAMP
110 ns
t
CYC
167 ns
72
t
CYC
Analog input voltage
V
IAN
0.3
V
AREF
+ 0.3
V
Analog input
impedance
Reference voltage
V
AREF
3.4
AV
DD
V
I
AREF1
Operating mode
1.5
3.0
mA
V
AREF
current
I
AREF2
STOP mode
0.7
1.5
mA
AV
DD
power supply
AI
DD1
Operating mode f
XX
= 15 MHz
0.5
1.3
mA
current
AI
DD2
STOP mode
10
20
A
Note Quantization error (
1/2 LSB) is not included.
AC Timing Test Point
R
AN
50
M
0.4 %
FSR
5
31
PD78CP18(A)
PARAMETER
EXPRESSION
MIN./MAX.
UNIT
t
AL
2T 100
MIN.
ns
t
LA
T 30
MIN.
ns
t
AR
3T 100
MIN.
ns
t
AD
7T 220
MAX.
ns
t
LDR
5T 200
MAX.
ns
t
RD
4T 150
MAX.
ns
t
LR
T 50
MIN.
ns
t
RL
2T 50
MIN.
ns
4T 50 (In data read)
t
RR
MIN.
ns
7T 50 (In OP code fetch)
t
LL
2T 40
MIN.
ns
t
AW
3T 100
MIN.
ns
t
LDW
T + 130
MAX.
ns
t
LW
T 50
MIN.
ns
t
DW
4T 140
MIN.
ns
t
WDH
2T 70
MIN.
ns
t
WL
2T 50
MIN.
ns
t
WW
4T 50
MIN.
ns
12T
(SCK input)
Note1
t
CYK
6T
(SCK input)
Note2
MIN.
ns
24T
(SCK output)
5T + 5
(SCK input)
Note1
t
KKL
2.5T + 5
(SCK input)
Note2
MIN.
ns
12T 100 (SCK output)
5T + 5
(SCK input)
Note1
t
KKH
2.5T + 5
(SCK input)
Note2
MIN.
ns
12T 100 (SCK output)
Notes 1. If clock rate is
1, in asynchronous mode, synchronous mode, or I/O interface mode.
2. If clock rate is
16,
64 in asynchronous mode.
Remarks
1.
T = t
CYC
= 1/f
XX
2.
Other items which are not listed in this table are not dependent on oscillator frequency (f
XX
).
t
CYC
-Dependent AC Characteristics Expression
32
PD78CP18(A)
X1
PF7 to PF0
PD7 to PD0
ALE
t
CYC
Address (Higher)
Address (Lower)
t
RDH
Read Data
t
LDR
t
AD
t
RL
t
RD
t
RR
t
AFR
t
LA
t
LL
t
AR
t
AL
t
LR
RD
Address (Higher)
Address (Lower)
t
LDW
t
LL
t
AL
t
WD
t
DW
t
WDH
t
WL
t
WW
t
LW
t
AW
Write Data
X1
PF7 to PF0
PD7 to PD0
ALE
WR
t
LA
Timing Waveforms
Read Operation
Write Operation
33
PD78CP18(A)
Serial Operation
Timer/Event Counter Input Timing
Timer Input Timing
t
CYK
t
KKL
t
KKH
t
RXK
t
KRX
t
KTX
SCK
T
X
D
R
X
D
TI
t
TIL
t
TIH
CI
t
CI1L
t
CI1H
Event Counter Mode
CI
t
CI2L
t
CI2H
Pulse Width Test Mode
34
PD78CP18(A)
X1
t
CYC
t
H
0.8V
DD
0.8 V
t
f
t
r
t
L
RESET
t
RSL
t
RSH
0.8V
DD
0.2V
DD
Interrupt Input Timing
External Clock Timing
Reset Input Timing
NMI
t
NIL
t
NIH
INT1
INT2
t
I1H
t
I1L
t
I2L
t
I2H
35
PD78CP18(A)
90 %
STOP
V
DD
V
DDDR
t
RVD
10 %
t
FVD
t
SSTVD
t
HVDST
V
IH2
V
IL2
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Data retention power
supply voltage
V
DDDR
= 2.5 V
1
15
A
I
DDDR
V
DDDR
= 5 V
10 %
10
50
A
V
DD
rise/fall time
t
RVD
, t
FVD
200
s
STOP setup time
t
SSTVD
12T + 0.5
s
(to V
DD
)
Note
STOP hold time
t
HVDST
12T + 0.5
s
(from V
DD
)
Note
DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (T
A
= 40
to +85
C)
Note T= t
CYC
= 1/f
XX
Data Retention Timing
V
DDDR
2.5
5.5
V
5
supply current
Data retention power
36
PD78CP18(A)
5
50
mA
5
30
mA
Input voltage high
V
IH
V
IH
2.4
V
PARAMETER
SYMBOL
SYMBOL
Note
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
DDP
+ 0.3
Input voltage low
V
IL
V
IL
0.3
0.8
V
Input leakage current
I
LIP
I
LI
0
V
I
V
DDP
; except INT1, TI (PC3)
10
A
V
DD
1.0
Output voltage low
V
OL
V
OL
I
OL
= 2.0 mA
0.45
V
Output leakage
current
EPROM programming mode
5.75
6.0
6.25
V
EPROM read mode
4.5
5.0
5.5
V
EPROM programming mode
12.2
12.5
12.8
V
EPROM read mode
V
PP
= V
DDP
V
EPROM programming mode
5
50
mA
EPROM read mode
CE = V
IL
, V
I
= V
IH
EPROM programming mode
CE = V
IL
, OE = V
IH
EPROM read mode
1
100
A
DC PROGRAMMING CHARACTERISTICS (T
A
= 25
5
C, MODE1 = V
IL
, MODE0 = V
IH
, V
SS
= 0 V)
Note Corresponding
PD27C256A symbol
Output voltage high
V
OH
V
OH
I
OH
= 1.0 mA
V
V
DDP
supply voltage
V
DDP
V
DD
V
PP
supply voltage
V
PP
V
PP
V
DDP
supply current
I
DD
I
DD
V
PP
supply current
I
PP
I
PP
I
LO
0
V
O
V
DDP
, OE = V
IH
10
A
37
PD78CP18(A)
t
SMC
2
s
AC PROGRAMMING CHARACTERISTICS (T
A
= 25
5
C, MODE1 = V
IL
, MODE0 = V
IH
, V
SS
= 0 V)
PARAMETER
SYMBOL SYMBOL
Note1
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
Address setup time (to CE
)
t
SAC
t
AS
2
s
OE
delay time from data
t
DDOO
t
OES
2
s
Input data setup time (to CE
)
t
SIDC
t
DS
2
s
Address hold time (from CE
)
t
HCA
t
AH
2
s
Input data hold time (from CE
)
t
HCID
t
DH
2
s
Output data hold time (from OE
)
t
HOOD
t
DF
0
130
ns
V
PP
setup time (to CE
)
t
SVPC
t
VPS
2
s
V
DDP
setup time (to CE
)
t
SVDC
t
VDS
2
s
Initial program pulse width
t
WL1
t
PW
0.95
1.0
1.05
ms
Additional program pulse width
t
WL2
t
OPW
2.85
78.75
ms
EPROM programming/read mode
setup time (to CE
)
Note2
Data output time from address
t
DAOD
t
ACC
OE = V
IL
1
s
Data output time from CE
t
DCOD
t
CE
1
s
Data output time from OE
t
DOOD
t
OE
1
s
Data hold time (from OE
)
t
HCOD
t
DF
0
130
ns
Data hold time (from address)
t
HAOD
t
OH
OE = V
IL
0
ns
Notes 1. Corresponding
PD27C256A symbol
2. Indicates state in which MODE1 = V
IL
and MODE0 = V
IH
.
38
PD78CP18(A)
A12 to A0
Effective Address
Data Output
Hi-Z
CE
OE
D7 to D0
t
DCOD
t
DAOD
t
DOOD
Hi-Z
t
HCOD
t
HAOD
A12 to A0
Effective Address
D7 to D0
Data Input
Data Output
Data Input
V
PP
V
DDP
V
DDP
+ 1
V
DDP
V
IH
V
IL
V
IH
V
IL
V
PP
V
DDP
CE
OE
V
IH
V
IL
MODE1
MODE0
MODE1 = V
IL
MODE0 = V
IH
t
SAC
t
SIDC
t
SMC
t
SVPC
t
SVDC
t
HCID
t
HOOD
t
HCA
t
SIDC
t
HCID
t
WL2
t
WL1
t
DDOO
t
DOOD
PROM Programming Mode Timing
Cautions
1. Ensure that V
DDP
is applied before V
PP
, and cut after V
PP
.
2. Ensure that V
PP
does not exceed +13 V including overshoot.
PROM Read Mode Timing
Cautions
1. If you wish to read within the t
DAOD
range, the OE input delay time from the fall of CE should be a
maximum of t
DAOD
- t
DOOD
.
2. t
HCOD
is the time from the point at which OE or CE (whichever is first) reaches V
IH
.
39
PD78CP18(A)
30
25
20
15
10
5
0
0
4.5
5.0
5.5
(T
A
= 25 C, f
XX
= 15 MHz)
I
DD1
(TYP.)
Power Supply Voltage V
DD
[V]
V
DD
Power Supply Current I
DD1
, I
DD2
[mA]
(T
A
= 25 C, V
DD
= 5 V)
Oscillator Frequency f
XX
[MHz]
V
DD
Power Supply Current I
DD1
, I
DD2
[mA]
30
20
10
0
0
5
10
15
I
DD1
(TYP.)
I
DD2
(TYP.)
I
DD2
(TYP.)
6.0
7.
CHARACTERISTIC CURVES (REFERENCE VALUE)
I
DD1
, I
DD2
vs. V
DD
I
DD1
, I
DD2
vs. f
XX
40
PD78CP18(A)
I
OL
vs. V
OL
I
OH
vs. V
OH
2.5
2.0
1.5
1.0
0.5
0
0
0.1
0.2
0.3
0.4
0.5
(T
A
= 25 C, V
DD
= 5 V)
TYP.
Output Voltage Low V
OL
[V]
Output Current Low I
OL
[mA]
1.5
1.0
0.5
0
0
0.1
0.2
0.3
0.4
0.5
(T
A
= 25 C, V
DD
= 5 V)
Power Supply Voltage Output Voltage High V
DD
V
OH
[V]
Output Current High I
OH
[mA]
TYP.
41
PD78CP18(A)
I
DDDR
vs. V
DDDR
10
8
6
4
2
0
0
2
3
4
5
6
(T
A
= 25 C)
TYP.
Data Retention Power Supply Voltage V
DDDR
[V]
Data Retention Power Supply Current I
DDDR
[
A]
42
PD78CP18(A)
8.
PACKAGE DRAWINGS
H
I
M
C
P
A
64
1
32
33
M
N
J
K
S
W
X
P64GQ-100-36
ITEM
MILLIMETERS
INCHES
A
C
H
I
J
K
M
N
P
S
W
1.27 (T.P.)
0.25
16.5
0.100 (T.P.)
0.050 (T.P.)
0.010
0.157
1.634
NOTE
X
4.0
0.750
Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maxi-
mum material condition.
0.142
0.043
0.020
24.13
0.950
0.010
0.25
2.54 (T.P.)
+0.004
0.005
+0.011
0.006
+0.012
0.008
+0.004
0.005
41.5
+0.3
0.2
0.50
+0.10
1.1
+0.25
0.15
+0.10
0.05
+0.3
3.6
+0.1
+1.05
19.05
+1.05
0.650
+0.004
0.003
+0.013
0.012
+0.042
+0.042
64 PIN PLASTIC QUIP
43
PD78CP18(A)
N
A
M
F
B
51
52
32
K
L
64 PIN PLASTIC QFP (14
20)
64
1
20
19
33
P
D
C
detail of lead end
S
Q
55
G
M
I
H
J
P64GF-100-3B8,3BE,3BR-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
23.60.4
14.00.2
1.0
0.400.10
0.20
20.00.2
0.9290.016
0.039
0.039
0.008
0.039 (T.P.)
0.795
NOTE
M
N
0.12
0.15
1.80.2
1.0 (T.P.)
0.005
0.006
+0.004
0.003
Each lead centerline is located within 0.20
mm (0.008 inch) of its true position (T.P.) at
maximum material condition.
0.071
0.016
0.551
0.80.2
0.031
P
2.7
0.106
0.6930.016
17.60.4
1.0
+0.009
0.008
Q
0.10.1
0.0040.004
S
3.0 MAX.
0.119 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
+0.008
0.009
44
PD78CP18(A)
Infrared reflow
Package peak temperature: 235
C, Duration: 30 sec. max. (at 210
C or higher),
IR35-00-2
Count: Twice or less
<Attention>
(1)
Perform the second reflow at the time the device temperature is lowered to
the room temperature from the heating by the first reflow.
(2)
Do not wash the soldered portion with the flux following the first reflow.
VPS
Package peak temperature: 215
C, Duration: 40 sec. max. (at 200
C or higher),
VP15-00-2
Count: Twice or less
<Attention>
(1)
Perform the second reflow at the time the device temperature is lowered to
the room temperature from the heating by the first reflow.
(2)
Do not wash the soldered portion with the flux following the first reflow.
Wave soldering
Solder bath temperature: 260
C max., Duration: 10 sec. max., Count: Once
WS60-00-1
Preheating temperature: 120
C max. (package surface temperature)
Partial heating
Pin temperature: 300
C max., Duration: 3 sec. max. (per device side row of pins)
----
9.
RECOMMENDED SOLDERING CONDITIONS
The
PD78CP18(A) should be soldered and mounted under the following recommended conditions.
For details of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual (IEI-1207)".
For soldering methods and conditions other than those recommended below, contact an NEC representative.
Table 9-1. Surface Mount Type Soldering Conditions
PD78CP18GF(A)-3BE: 64-Pin Plastic QFP (14
20 mm)
Recommended
Condition Symbol
Soldering Method
Soldering Conditions
Caution
Use of more than one soldering method should be avoided (except in the case of pin part heating).
Table 9-2. Through-Hole Type Soldering Conditions
PD78CP18GQ(A)-36: 64-Pin Plastic QUIP
Soldering Method
Soldering Conditions
Wave soldering
Solder bath temperature: 260
C
max., Duration: 10 sec. max.
(pin part only)
Partial heating
Pin temperature: 300
C max., Duration: 3 sec. max. (per pin)
Caution
Wave soldering is used on the pin only, and care must be taken to prevent solder from coming into
direct contact with the body.
5
45
PD78CP18(A)
Internal ROM
32 K
8 bits
32 K
8 bits
(PROM)
(mask ROM)
Internal RAM
1 K
8 bits
1 K
8 bits
Pin connection
PB7/OE
PB7
PB6/CE
PB6
STOP/V
PP
STOP
NMI/A9
NMI
PA7/A7 to PA0/A0
PA7 to PA0
PF6/A14 to PF2/A10
PF6 to PF2
PF0/A8
PF0
PD7/O7 to PD0/O0
PD7 to PD0
Mode set by MODE pins (when
PROM programming mode
Operates as the
PD78C17(A)
MODE0 is set to 1, and MODE1
(ROM-less mode)
to 0)
External memory 16 K extension
mode
MODE0 pin input/output function
Input only
Note
Input/output
Internal memory access area
Yes
No
setting by MM register
Port A to Port C
Pull-up resistors not incorporated
Pull-up resistor incorporation
selectable bit-wise by mask
option
Note An emulation control signal is not output even if the MODE0 pin is pulled high.
10. DIFFERENCES BETWEEN THE
PD78CP18(A) AND
PD78C18(A)
PD78CP18(A)
PD78C18(A)
Part Number
Item
46
PD78CP18(A)
Ordering Code (Product Name)
S5A13RA87
S5A10RA87
S7B13RA87
S7B10RA87
APPENDIX DEVELOPMENT TOOLS
The following development tools are available to develop a system which uses the
PD78CP18(A).
Language Processor
This is a program which converts a program written in mnemonic to an object code for which
microcomputer execution is possible.
Moreover, it contains a function to automatically create a symbol/table, and optimize branch
instructions.
87AD series
relocatable assembler
(RA87)
Supply Medium
3.5-inch 2HD
5-inch 2HD
3.5-inch 2HC
5-inch 2HC
5
PG-1500
PA-78CP14GF/
GQ
PA-78CP14GF
PA-78CP14GQ
PG-1500
controller
PROM Write Tools
With a provided board and an optional programmer adapter connected, this PROM programmer
can manipulate from a stand-alone or host machine to perform programming on a single-chip
microcomputer which incorporates PROM.
It is also capable of programming a typical PROM ranging from 256 K to 4 M bits.
PROM programmer adapter for the
PD78CP18(A). Used by connecting to the PG-1500.
For the
PD78CP18GF(A)-3BE
For the
PD78CP18GQ(A)-36
Connects the PG-1500 to a host machine by using serial and parallel interface, to control the PG-
1500 on a host machine.
Hardware
Ordering Code (Product Name)
S5A13PG1500
S5A10PG1500
S7B10PG1500
Supply Medium
3.5-inch 2HD
5-inch 2HD
5-inch 2HC
Host Machine
PC-9800
series
IBM PC/AT
Soft
ware
Note Versions 5.00 and 5.00A have a task swap function, but this function cannot be used with this software.
Remark
The operations of the assembler and the PG-1500 controller are guaranteed only on the above host
machines and operating systems.
OS
MS-DOS
Ver. 2.11
to
Ver. 5.00A
Note
PC DOS
(Ver. 3.1)
OS
MS-DOS
TM
Ver. 2.11
to
Ver. 5.00A
Note
PC DOS
TM
(Ver. 3.1)
Host Machine
PC-9800
series
IBM PC/AT
TM
47
PD78CP18(A)
Debugging Tools
An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for the
PD78CP18(A). The following
table shows its system configuration.
Remark
The operations of the IE controller are guaranteed only on the above host machines and operating
systems.
IE-78C11-M
IE-78C11-M
control program
(IE controller)
The IE-78C11-M is an in-circuit emulator which works with the 87AD series.
It can be connected to a host machine to perform efficient debugging.
Connects the IE-78C11-M to host machine by using the RS-233C, to control the IE-78C11-M on
host machine.
Hardware
Ordering Code (Product Name)
S5A13IE78C11
S5A10IE78C11
S7B10IE78C11
Supply Medium
3.5-inch 2HD
5-inch 2HD
5-inch 2HC
Host Machine
PC-9800
series
IBM PC/AT
OS
MS-DOS
Ver. 2.11
to
Ver. 3.30D
PC DOS
(Ver. 3.1)
Soft
ware
48
PD78CP18(A)
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static
electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental
control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid
using insulators that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive material. All test and
measurement tools including work bench and floor should be grounded. The operator should be
grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar
precautions need to be taken for PW boards wiht semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does
not define the initial operation status of the device. Immediately after the power source is turned
ON, the devices with reset function have not yet been initialized. Hence, power-on does not
guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD78CP18(A)
QTOP is a trademark of NEC Corporation.
MS-DOS is a trademark of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special:
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.
M4 94.11
[MEMO]
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