Document Outline

• COVER
• INTRODUCTION
• CHAPTER 1 OUTLINE
  • 1.1 Features
  • 1.2 Applications
  • 1.3 Ordering Information
  • 1.4 Pin Configuration (Top View)
  • 1.5 K1 Family Lineup
    • 1.5.1 78K0/Kx1 product lineup
    • 1.5.2 V850ES/Kx1 product lineup
  • 1.6 Block Diagram
  • 1.7 Outline of Functions
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 Pin Function List
  • 2.2 Description of Pin Functions
    • 2.2.1 P00 to P06 (port 0)
    • 2.2.2 P10 to P17 (port 1)
    • 2.2.3 P20 to P27 (port 2)
    • 2.2.4 P30 to P33 (port 3)
    • 2.2.5 P40 to P43 (port 4)
    • 2.2.6 P50 to P53 (port 5)
    • 2.2.7 P60 to P63 (port 6)
    • 2.2.8 P70 to P77 (port 7)
    • 2.2.9 P120 (port 12)
    • 2.2.10 P130 (port 13)
    • 2.2.11 P140 and P141 (port 14)
    • 2.2.12 AVREF
    • 2.2.13 AVSS
    • 2.2.14 RESET#
    • 2.2.15 REGC
    • 2.2.16 X1 and X2
    • 2.2.17 XT1 and XT2
    • 2.2.18 VDD and EVDD
    • 2.2.19 VSS and EVSS
    • 2.2.20 VPP (flash memory versions only)
    • 2.2.21 IC (mask ROM versions only)
  • 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Space
    • 3.1.1 Internal program memory space
    • 3.1.2 Internal data memory space
    • 3.1.3 Special function register (SFR) area
    • 3.1.4 Data memory addressing
  • 3.2 Processor Registers
    • 3.2.1 Control registers
    • 3.2.2 General-purpose registers
    • 3.2.3 Special Function Registers (SFRs)
  • 3.3 Instruction Address Addressing
    • 3.3.1 Relative addressing
    • 3.3.2 Immediate addressing
    • 3.3.3 Table indirect addressing
    • 3.3.4 Register addressing
  • 3.4 Operand Address Addressing
    • 3.4.1 Implied addressing
    • 3.4.2 Register addressing
    • 3.4.3 Direct addressing
    • 3.4.4 Short direct addressing
    • 3.4.5 Special function register (SFR) addressing
    • 3.4.6 Register indirect addressing
    • 3.4.7 Based addressing
    • 3.4.8 Based indexed addressing
    • 3.4.9 Stack addressing
• CHAPTER 4 PORT FUNCTIONS
  • 4.1 Port Functions
  • 4.2 Port Configuration
    • 4.2.1 Port 0
    • 4.2.2 Port 1
    • 4.2.3 Port 2
    • 4.2.4 Port 3
    • 4.2.5 Port 4
    • 4.2.6 Port 5
    • 4.2.7 Port 6
    • 4.2.8 Port 7
    • 4.2.9 Port 12
    • 4.2.10 Port 13
    • 4.2.11 Port 14
  • 4.3 Registers Controlling Port Function
  • 4.4 Port Function Operations
    • 4.4.1 Writing to I/O port
    • 4.4.2 Reading from I/O port
    • 4.4.3 Operations on I/O port
• CHAPTER 5 CLOCK GENERATOR
  • 5.1 Functions of Clock Generator
  • 5.2 Configuration of Clock Generator
  • 5.3 Registers Controlling Clock Generator
  • 5.4 System Clock Oscillator
    • 5.4.1 X1 oscillator
    • 5.4.2 Subsystem clock oscillator
    • 5.4.3 When subsystem clock is not used
    • 5.4.4 Ring-OSC oscillator
    • 5.4.5 Prescaler
  • 5.5 Clock Generator Operation
  • 5.6 Time Required to Switch Between Ring-OSC Clock and X1 Input Clock
  • 5.7 Time Required for CPU Clock Switchover
  • 5.8 Clock Switching Flowchart and Register Setting
    • 5.8.1 Switching from Ring-OSC clock to X1 input clock
    • 5.8.2 Switching from X1 input clock to Ring-OSC clock
    • 5.8.3 Switching from X1 input clock to subsystem clock
    • 5.8.4 Switching from subsystem clock to X1 input clock
    • 5.8.5 Register settings
• CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 AND 01
  • 6.1 Functions of 16-Bit Timer/Event Counters 00 and 01
  • 6.2 Configuration of 16-Bit Timer/Event Counters 00 and 01
  • 6.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01
  • 6.4 Operation of 16-Bit Timer/Event Counters 00 and 01
    • 6.4.1 Interval timer operation
    • 6.4.2 PPG output operations
    • 6.4.3 Pulse width measurement operations
    • 6.4.4 External event counter operation
    • 6.4.5 Square-wave output operation
    • 6.4.6 One-shot pulse output operation
  • 6.5 Cautions for 16-Bit Timer/Event Counters 00 and 01
• CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51
  • 7.1 Functions of 8-Bit Timer/Event Counters 50 and 51
  • 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51
  • 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51
  • 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51
    • 7.4.1 Operation as interval timer
    • 7.4.2 Operation as external event counter
    • 7.4.3 Square-wave output operation
    • 7.4.4 PWM output operation
  • 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51
• CHAPTER 8 8-BIT TIMERS H0 AND H1
  • 8.1 Functions of 8-Bit Timers H0 and H1
  • 8.2 Configuration of 8-Bit Timers H0 and H1
  • 8.3 Registers Controlling 8-Bit Timers H0 and H1
  • 8.4 Operation of 8-Bit Timers H0 and H1
    • 8.4.1 Operation as interval timer/square-wave output
    • 8.4.2 Operation as PWM output mode
    • 8.4.3 Carrier generator mode operation (8-bit timer H1 only)
• CHAPTER 9 WATCH TIMER
  • 9.1 Functions of Watch Timer
  • 9.2 Configuration of Watch Timer
  • 9.3 Register Controlling Watch Timer
  • 9.4 Watch Timer Operations
    • 9.4.1 Watch timer operation
    • 9.4.2 Interval timer operation
  • 9.5 Cautions for Watch Timer
• CHAPTER 10 WATCHDOG TIMER
  • 10.1 Functions of Watchdog Timer
  • 10.2 Configuration of Watchdog Timer
  • 10.3 Registers Controlling Watchdog Timer
  • 10.4 Operation of Watchdog Timer
    • 10.4.1 Watchdog timer operation when �Ring-OSC cannot be stopped� is selected by a mask option
    • 10.4.2 Watchdog timer operation when �Ring-OSC can be stopped by software� is selected by mask option
    • 10.4.3 Watchdog timer operation in STOP mode (when �Ring-OSC can be stopped by software� is selected by mask option)
    • 10.4.4 Watchdog timer operation in HALT mode (when �Ring-OSC can be stopped by software� is selected by mask option)
• CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
  • 11.1 Functions of Clock Output/Buzzer Output Controller
  • 11.2 Configuration of Clock Output/Buzzer Output Controller
  • 11.3 Register Controlling Clock Output/Buzzer Output Controller
  • 11.4 Clock Output/Buzzer Output Controller Operations
    • 11.4.1 Clock output operation
    • 11.4.2 Operation as buzzer output
• CHAPTER 12 A/D CONVERTER
  • 12.1 Functions of A/D Converter
  • 12.2 Configuration of A/D Converter
  • 12.3 Registers Used in A/D Converter
  • 12.4 A/D Converter Operations
    • 12.4.1 Basic operations of A/D converter
    • 12.4.2 Input voltage and conversion results
    • 12.4.3 A/D converter operation mode
  • 12.5 How to Read A/D Converter Characteristics Table
  • 12.6 Cautions for A/D Converter
• CHAPTER 13 SERIAL INTERFACE UART0
  • 13.1 Functions of Serial Interface UART0
  • 13.2 Configuration of Serial Interface UART0
  • 13.3 Registers Controlling Serial Interface UART0
  • 13.4 Operation of Serial Interface UART0
    • 13.4.1 Operation stop mode
    • 13.4.2 Asynchronous serial interface (UART) mode
    • 13.4.3 Dedicated baud rate generator
• CHAPTER 14 SERIAL INTERFACE UART6
  • 14.1 Functions of Serial Interface UART6
  • 14.2 Configuration of Serial Interface UART6
  • 14.3 Registers Controlling Serial Interface UART6
  • 14.4 Operation of Serial Interface UART6
    • 14.4.1 Operation stop mode
    • 14.4.2 Asynchronous serial interface (UART) mode
    • 14.4.3 Dedicated baud rate generator
• CHAPTER 15 SERIAL INTERFACES CSI10 AND CSI11
  • 15.1 Functions of Serial Interfaces CSI10 and CSI11
  • 15.2 Configuration of Serial Interfaces CSI10 and CSI11
  • 15.3 Registers Controlling Serial Interfaces CSI10 and CSI11
  • 15.4 Operation of Serial Interfaces CSI10 and CSI11
    • 15.4.1 Operation stop mode
    • 15.4.2 3-wire serial I/O mode
• CHAPTER 16 MULTIPLIER/DIVIDER
  • 16.1 Functions of Multiplier/Divider
  • 16.2 Configuration of Multiplier/Divider
  • 16.3 Register Controlling Multiplier/Divider
  • 16.4 Operations of Multiplier/Divider
    • 16.4.1 Multiplication operation
    • 16.4.2 Division operation
• CHAPTER 17 INTERRUPT FUNCTIONS
  • 17.1 Interrupt Function Types
  • 17.2 Interrupt Sources and Configuration
  • 17.3 Registers Controlling Interrupt Functions
  • 17.4 Interrupt Servicing Operations
    • 17.4.1 Maskable interrupt acknowledgement
    • 17.4.2 Software interrupt request acknowledgement
    • 17.4.3 Multiple interrupt servicing
    • 17.4.4 Interrupt request hold
• CHAPTER 18 KEY INTERRUPT FUNCTION
  • 18.1 Functions of Key Interrupt
  • 18.2 Configuration of Key Interrupt
  • 18.3 Register Controlling Key Interrupt
• CHAPTER 19 STANDBY FUNCTION
  • 19.1 Standby Function and Configuration
    • 19.1.1 Standby function
    • 19.1.2 Registers controlling standby function
  • 19.2 Standby Function Operation
    • 19.2.1 HALT mode
    • 19.2.2 STOP mode
• CHAPTER 20 RESET FUNCTION
  • 20.1 Register for Confirming Reset Source
• CHAPTER 21 CLOCK MONITOR
  • 21.1 Functions of Clock Monitor
  • 21.2 Configuration of Clock Monitor
  • 21.3 Registers Controlling Clock Monitor
  • 21.4 Operation of Clock Monitor
• CHAPTER 22 POWER-ON-CLEAR CIRCUIT
  • 22.1 Functions of Power-on-Clear Circuit
  • 22.2 Configuration of Power-on-Clear Circuit
  • 22.3 Operation of Power-on-Clear Circuit
  • 22.4 Cautions for Power-on-Clear Circuit
• CHAPTER 23 LOW-VOLTAGE DETECTOR
  • 23.1 Functions of Low-Voltage Detector
  • 23.2 Configuration of Low-Voltage Detector
  • 23.3 Registers Controlling Low-Voltage Detector
  • 23.4 Operation of Low-Voltage Detector
  • 23.5 Cautions for Low-Voltage Detector
• CHAPTER 24 REGULATOR
  • 24.1 Outline of Regulator
• CHAPTER 25 MASK OPTIONS
• CHAPTER 26 ROM CORRECTION
  • 26.1 Functions of ROM Correction
  • 26.2 Configuration of ROM Correction
  • 26.3 Register Controlling ROM Correction
  • 26.4 ROM Correction Usage Example
  • 26.5 ROM Correction Application
  • 26.6 Program Execution Flow
  • 26.7 Cautions for ROM Correction
• CHAPTER 27 uPD78F0134, 78F0138
  • 27.1 Internal Memory Size Switching Register
  • 27.2 Internal Expansion RAM Size Switching Register
  • 27.3 Writing with Flash Programmer
  • 27.4 Programming Environment
  • 27.5 Communication Mode
  • 27.6 Handling of Pins on Board
    • 27.6.1 VPP pin
    • 27.6.2 Serial interface pins
    • 27.6.3 RESET# pin
    • 27.6.4 Port pins
    • 27.6.5 REGC pin
    • 27.6.6 Other signal pins
    • 27.6.7 Power supply
  • 27.7 Programming Method
    • 27.7.1 Controlling flash memory
    • 27.7.2 Flash memory programming mode
    • 27.7.3 Selecting communication mode
    • 27.7.4 Communication commands
• CHAPTER 28 INSTRUCTION SET
  • 28.1 Conventions Used in Operation List
    • 28.1.1 Operand identifiers and specification methods
    • 28.1.2 Description of operation column
    • 28.1.3 Description of flag operation column
  • 28.2 Operation List
  • 28.3 Instructions Listed by Addressing Type
• CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS, (A) GRADE PRODUCTS)
• CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A1) GRADE PRODUCTS)
• CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS)
• CHAPTER 32 PACKAGE DRAWINGS
• CHAPTER 33 RECOMMENDED SOLDERING CONDITIONS
• CHAPTER 34 CAUTIONS FOR WAIT
  • 34.1 Cautions for Wait
  • 34.2 Peripheral Hardware That Generates Wait
  • 34.3 Example of Wait Occurrence
• APPENDIX A DEVELOPMENT TOOLS
  • A.1 Software Package
  • A.2 Language Processing Software
  • A.3 Control Software
  • A.4 Flash Memory Writing Tools
  • A.5 Debugging Tools (Hardware)
    • A.5.1 When using in-circuit emulators IE-78K0-NS and IE-78K0-NS-A
    • A.5.2 When using in-circuit emulator IE-78K0K1-ET
  • A.6 Debugging Tools (Software)
  • A.7 Embedded Software
• APPENDIX B NOTES ON TARGET SYSTEM DESIGN
• APPENDIX C REGISTER INDEX
  • C.1 Register Index (In Alphabetical Order with Respect to Register Names)
  • C.2 Register Index (In Alphabetical Order with Respect to Register Symbol)
• APPENDIX D REVISION HISTORY
  • D.1 Major Revisions in This Edition