Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- 78K/0 SERIES LINEUP
- FUNCTION OVERVIEW
- PIN CONFIGURATION (TOP VIEW)
- BLOCK DIAGRAM
- 1. DIFFERENCES BETWEEN uPD78F0233 AND MASK ROM VERSION
- 2. PIN FUNCTION LIST
- 2.1 Port Pins
- 2.2 Non-port Pins
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
- 3. MEMORY SIZE SWITCHING REGISTER (IMS)
- 4. FLASH MEMORY PROGRAMMING
- 4.1 Selection of Transmission Method
- 4.2 Flash Memory Programming Functions
- 4.3 Connection to Flashpro II
- 5. ELECTRICAL SPECIFICATIONS
- 6. PACKAGE DRAWING
- APPENDIX A DEVELOPMENT TOOLS
- APPENDIX B RELATED DOCUMENTS
1998
PRELIMINARY DATA SHEET
Document No. U13322EJ1V0DS00 (1st edition)
Date Published June 1998 N CP(K)
Printed in Japan
The
PD78F0233 is a member of the
PD780232 Subseries that belongs to the 78K/0 Series. It replaces the
internal ROM
Note
of the
PD780232 with a flash memory.
Since the
PD78F0233 enables write/erase electrically while mounted on a board, it is suitable for applications
involving system evaluation during system development, small-scale production, and for systems that are expected
to be frequently upgraded.
Note Internal ROM capacity varies (refer to 1. DIFFERENCES BETWEEN
PD78F0233 AND MASK ROM
VERSION for details).
The details of functions are described in the following user's manuals. Be sure to read them before
designing.
PD780232 Subseries User's Manual
: Under preparation
78K/0 Series User's Manual -- Instructions : U12326E
FEATURES
Pin-compatible with mask ROM versions (except V
PP
pin)
Flash memory
: 24 Kbytes
Note
Internal high-speed RAM : 768 bytes
Internal buffer RAM
: 32 bytes
FIPTM display RAM
: 112 bytes
Operable in the same supply voltage as mask ROM version (V
DD
= 4.5 to 5.5 V)
Note The flash memory capacity can be changed with the memory size switching register (IMS).
Remark
Refer to 1. DIFFERENCES BETWEEN
PD78F0233 AND MASK ROM VERSION for the differences
between the flash memory version and mask ROM versions.
ORDERING INFORMATION
Part Number
Package
Internal ROM
PD78F0233GC-8BT
80-pin plastic QFP (14
14 mm)
Flash memory
MOS INTEGRATED CIRCUIT
PD78F0233
8-BIT SINGLE-CHIP MICROCONTROLLER
The information in this document is subject to change without notice.
2
PD78F0233
Preliminary Data Sheet
78K/0 SERIES LINEUP
The following shows the 78K/0 Series lineup. The designations appearing inside the boxes are subseries names.
Note Under planning
80-pin
PD78098
Control
TM
FIP
TM
driving
100-pin
LCD driving
IEBus supported
42/44-pin
64-pin
64-pin
64-pin
80-pin
100-pin
80-pin
80-pin
100-pin
100-pin
80-pin
78K/0
Series
Basic subseries for driving FIP, Display output total: 34
Basic subseries for driving LCDs, on-chip UART
Y subseries support I
2
C bus specification
Products under development
Products in mass production
80-pin
100-pin
PD78054
PD78014
PD780001
PD78002
PD78002Y
PD78083
PD78044H
PD78044F
PD78064B
PD78064
PD78098B
PD78064Y
EMI-noise reduced version of the PD78098
EMI-noise reduced version of the PD78078
Timer was added to the PD78054 and external interface function was enhanced
I/O and FIP C/D of the PD78044F were enhanced, Display output total: 53
EMI-noise reduced version of the PD78064
PD78058F
PD780058
PD78070A
PD78078
80-pin
PD780308
SIO of the PD78064 was enhanced, and ROM and RAM capacities were expanded
100-pin
PD78075B
100-pin
100-pin
PD780024
64-pin
PD780034
64-pin
64-pin
PD78014H
64-pin
PD78018F
ROM-less versions of the PD78078
EMI-noise reduced version of the PD78054
UART and D/A converter were added to the PD78014, and I/O was enhanced
A/D converter of the PD780024 was enhanced
Serial I/O of the PD78018F was enhanced
Serial I/O of the PD78054 was enhanced and EMI-noise reduced version
EMI-noise reduced version of the PD78018F
Serial I/O of the PD78078Y was enhanced and only selected functions are provided
A/D converter and 16-bit timer were added to the PD78002
A/D converter was added to the PD78002
Basic subseries for control
On-chip UART, capable of operating at low voltage (1.8 V)
PD780924
64-pin
PD780964
64-pin
PD780988
64-pin
Inverter control
100-pin
On-chip inverter control circuit and UART. EMI-noise reduced version
A/D converter of the PD780924 was enhanced
Inverter control, timer, and SIO of the PD780964 were enhanced. ROM and RAM capacities were expanded
I/O and FIP C/D of the PD78044H were enhanced, Display output total: 48
PD780232
80-pin
Panel control, on-chip FIP C/D, Display output total: 53
N-ch open-drain input/output was added to the PD78044F, Display output total: 34
IEBus controller was added to the PD78054
80-pin
PD780973
On-chip controller/driver for operating automobile meters
Meter control
Low-voltage (1.8 V) operation versions of the PD78014, with several ROM and RAM capacities are available
PD78054Y
PD78058FY
PD780024Y
PD780034Y
PD780058Y
Note
PD780018AY
PD78070AY
PD78078Y
PD78014Y
PD78018FY
PD780308Y
PD780208
PD780228
3
PD78F0233
Preliminary Data Sheet
The major functional differences among the subseries are shown below.
Function
ROM
Timer
8-bit 10-bit 8-bit
V
DD
External
Serial Interface
I/O
MIN.
Subseries Name
Capacity
8-bit 16-bit Watch WDT
A/D
A/D
D/A
Value
Expansion
Control
PD78075B 32 K to 40 K 4 ch 1 ch 1 ch 1 ch 8 ch
--
2 ch 3 ch (UART: 1 ch)
88
1.8 V
PD78078
48 K to 60 K
PD78070A
--
61
2.7 V
PD780058 24 K to 60 K 2 ch
3 ch (time division
68
1.8 V
UART: 1 ch)
PD78058F 48 K to 60 K
3 ch (UART: 1 ch)
69
2.7 V
PD78054
16 K to 60 K
2.0 V
PD780034 8 K to 32 K
--
8 ch
--
3 ch (UART: 1 ch,
51
1.8 V
PD780024
8 ch
--
time division 3-wire: 1 ch)
PD78014H
2 ch
53
PD78018F 8 K to 60 K
PD78014
8 K to 32 K
2.7 V
PD780001 8 K
--
--
1 ch
39
--
PD78002
8 K to 16 K
1 ch
--
53
PD78083
--
8 ch
1 ch (UART: 1 ch)
33
1.8 V
--
Inverter
PD780988 32 K to 60 K 3 ch Note 1
--
1 ch
--
8 ch
--
3 ch (UART: 2 ch)
47
4.0 V
control
PD780964 8 K to 32 K
Note 2
2 ch (UART: 2 ch)
2.7 V
PD780924
8 ch
--
FIP drive
PD780208 32 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
--
--
2 ch
74
2.7 V
--
PD780228 48 K to 60 K 3 ch
--
--
1 ch
72
4.5 V
PD780232 16 K to 24 K
4 ch
2 ch
40
PD78044H 32 K to 48 K 2 ch 1 ch 1 ch
8 ch
1 ch
68
2.7 V
PD78044F 16 K to 40 K
2 ch
LCD drive
PD780308 48 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
--
--
3 ch (time division
57
2.0 V
--
UART: 1 ch)
PD78064B 32 K
2 ch (UART: 1 ch)
PD78064
16 K to 32 K
IEBus
PD78098B 40 K to 60 K 2 ch 1 ch 1 ch 1 ch 8 ch
--
2 ch 3 ch (UART: 1 ch)
69
2.7 V
supported
PD78098
32 K to 60 K
Meter
PD780973 24 K to 32 K 3 ch 1 ch 1 ch 1 ch 5 ch
--
--
2 ch (UART: 1 ch)
56
4.5 V
--
control
Notes 1. 16-bit timer: 2 channels
10-bit timer: 1 channel
2. 10-bit timer: 1 channel
4
PD78F0233
Preliminary Data Sheet
FUNCTION OVERVIEW
Item
Function
Internal memory
Flash memory
24 Kbytes
Note
High-speed RAM
768 bytes
Buffer RAM
32 bytes
FIP display RAM
112 bytes
General-purpose register
8 bits
32 registers (8 bits
8 registers
4 banks)
Minimum instruction execution time
On-chip minimum instruction execution time variable function
0.4
s/0.8
s/1.6
s/3.2
s/6.4
s (@ 5.0-MHz operation with main system clock)
Instruction set
Multiply/divide (8 bits
8 bits, 16 bits
8 bits)
Bit manipulate (set, reset, test, Boolean operation)
I/O ports
Total
: 40
(including alternate function pins for FIP)
CMOS I/Os
: 24
CMOS outputs
: 16
FIP controller/driver
Total of display outputs
: 53
15-mA display current
: 20
5-mA display current
: 33
A/D converter
8-bit resolution
4 channels
Power supply voltage: AV
DD
= 4.5 to 5.5 V
Serial interface
2-wire serial mode (transmit only)
: 1 channel
3-wire serial mode (with automatic transmit/receive function) : 1 channel
Timer
8-bit remote control timer
: 1 channel
8-bit timer
: 2 channels
Watchdog timer
: 1 channel
Vectored
Maskable
Internal: 10, external: 2
interrupt
Non-maskable
Internal: 1
source
Software
1
Power supply voltage
V
DD
= 4.5 to 5.5 V
Package
80-pin plastic QFP (14
14 mm)
Note The flash memory capacity can be changed with the memory size switching register (IMS).
5
PD78F0233
Preliminary Data Sheet
PIN CONFIGURATION (TOP VIEW)
80-pin plastic QFP (14
14 mm)
PD78F0233GC-8BT
Cautions 1. Connect directly V
PP
pin to V
SS1
in normal operation mode.
2. Connect AV
DD
pin to V
DD1
.
3. Connect AV
SS
pin to V
SS1
.
Remark
When the
PD78F0233 is used in applications that require reduction of the noise from inside the
microcontroller, the implementation of noise reduction measures, such as supplying voltage to V
DD0
and
V
DD1
individually and connecting V
SS0
and V
SS1
to different ground lines, is recommended.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
V
LOAD
V
DD2
FIP20
FIP21
FIP22
FIP23
FIP24/P30
FIP25/P31
FIP26/P32
FIP27/P33
FIP28/P34
FIP29/P35
FIP30/P36
FIP31/P37
FIP32/P40
FIP33/P41
FIP34/P42
FIP35/P43
FIP36/P44
FIP37/P45
ANI1
ANI0
V
SS0
AV
DD
V
DD0
P64/FIP52
P63/FIP51
P62/FIP50
P61/FIP49
P60/FIP48
P57/FIP47
P56/FIP46
P55/FIP45
P54/FIP44
P53/FIP43
P52/FIP42
P51/FIP41
P50/FIP40
P47/FIP39
P46/FIP38
FIP0
FIP1
FIP2
FIP3
FIP4
FIP5
FIP6
FIP7
FIP8
FIP9
FIP10
FIP11
FIP12
FIP13
FIP14
FIP15
FIP16
FIP17
FIP18
FIP19
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
V
DD1
V
SS1
X1
X2
V
PP
RESET
P27/SCK1
P26/SI1
P25/SO1
P24/BUSY
P23
P22
P21/SO3
P20/SCK3
P00/INTP0
P01/INTP1
P02/TI
AV
SS
ANI3
ANI2
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
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