Document Outline

• COVER
•  Preface
• Table of Contents
  • Chapter 1 Outline (�PD780828A Subseries)
    • 1.1  Features
    • 1.2  Application
    • 1.3  Ordering Information
    • 1.4  Quality Grade
    • 1.5  Pin Configuration (Top View)
      • Figure 1-1: Pin Configuration
    • 1.6  78K/0 Series Expansion
      • Figure 1-2: 78K/0 Series Expansion
      • Table 1-1: The major functional differences between the subseries
    • 1.7  Block Diagram
      • Figure 1-3: Block Diagram
    • 1.8  Overview of Functions
      • Table 1-2: Overview of Functions
    • 1.9  Differences between Flash and Mask ROM version
      • Table 1-3: Differences between Flash and Mask ROM version
  • Chapter 2 Pin Function (�PD780828A Subseries)
    • 2.1  Pin Function List
      • Table 2-1:  Pin Input/Output Types (1/2)
    • 2.2  Non-Port Pins
      • Table 2-2: Non-Port Pins (1/2)
    • 2.3  Description of Pin Functions
      • 2.3.1  P00 to P03 (Port 0)
      • 2.3.2  P10 to P14 (Port 1)
      • 2.3.3  P20 to P27 (Port 2)
      • 2.3.4  P34 to P37 (Port 3)
      • 2.3.5  P40 to P47 (Port 4)
      • 2.3.6  P50 to P57 (Port 5)
      • 2.3.7  P60 to P65 (Port 6)
      • 2.3.8  P80 to P87 (Port 8)
      • 2.3.9  P90 to P97 (Port 9)
      • 2.3.10  CTXD
      • 2.3.11  CRXD
      • 2.3.12  CCLK
      • 2.3.13  COM0 to COM3
      • 2.3.14  VLCD
      • 2.3.15  AVDD / AVREF
      • 2.3.16  AVSS
      • 2.3.17  RESET
      • 2.3.18  X1 and X2
      • 2.3.19  SMVDD
      • 2.3.20  SMVSS
      • 2.3.21  VDD0, VDD1
      • 2.3.22  VSS0, VSS1
      • 2.3.23  VPP (�PD78F0828A only)
      • 2.3.24  IC (Mask ROM version only)
        • Figure 2-1: Connection of IC Pins
    • 2.4  Pin I/O Circuits and Recommended Connection of Unused Pins
      • Table 2-3: Types of Pin Input/Output Circuits (1/2)
      • Figure 2-2: Pin Input/Output Circuits (1/3)
  • Chapter 3 CPU Architecture
    • 3.1  Memory Space
      • Figure 3-1: Memory Map of the �PD780824A
      • Figure 3-2: Memory Map of the �PD780826A
      • Figure 3-3: Memory Map of the �PD780828A
      • Figure 3-4: Memory Map of the �PD78F0828A
      • 3.1.1  Internal program memory space
        • Table 3-1: Internal ROM Capacities
        • Table 3-2: Vectored Interrupts
      • 3.1.2  Internal data memory space
        • Table 3-3: Internal high-speed RAM
        • Table 3-4: Internal expansion RAM (including sharing with DCAN)
      • 3.1.3  Special function register (SFR) area
      • 3.1.4  Data memory addressing
        • Figure 3-5: Data Memory Addressing of �PD780824A
        • Figure 3-6: Data Memory Addressing of �PD780826A
        • Figure 3-7: Data Memory Addressing of �PD780828A
        • Figure 3-8: Data Memory Addressing of �PD78F0828A
    • 3.2  Processor Registers
      • 3.2.1  Control registers
        • Figure 3-9: Program Counter Configuration
        • Figure 3-10: Program Status Word Configuration
        • Figure 3-11: Stack Pointer Configuration
        • Figure 3-12: Data to be Saved to Stack Memory
        • Figure 3-13: Data to be Reset to Stack Memory
      • 3.2.2  General registers
        • Figure 3-14: General Register Configuration
      • 3.2.3  Special function register (SFR)
        • Table 3-5: Special Function Register List (1/3)
    • 3.3  Instruction Address Addressing
      • 3.3.1  Relative addressing
        • Figure 3-15: Relative Addressing
      • 3.3.2  Immediate addressing
        • Figure 3-16: Immediate Addressing
      • 3.3.3  Table indirect addressing
        • Figure 3-17: Table Indirect Addressing
      • 3.3.4  Register addressing
        • Figure 3-18: Register Addressing
    • 3.4  Operand Address Addressing
      • 3.4.1  Implied addressing
        • Table 3-6: Implied Addressing
      • 3.4.2  Register addressing
        • Table 3-7: Register Addressing
        • Figure 3-19: Register Addressing
      • 3.4.3  Direct addressing
        • Table 3-8: Direct addressing
        • Figure 3-20: Direct addressing
      • 3.4.4  Short direct addressing
        • Table 3-9: Short direct addressing
        • Figure 3-21: Short direct addressing
      • 3.4.5  Special function register (SFR) addressing
        • Table 3-10: Special-Function Register (SFR) Addressing
        • Figure 3-22: Special-Function Register (SFR) Addressing
      • 3.4.6  Register indirect addressing
        • Table 3-11: Register indirect addressing
        • Figure 3-23: Register indirect addressing
      • 3.4.7  Based addressing
        • Table 3-12: Based addressing
        • Figure 3-24: Based addressing description example
      • 3.4.8  Based indexed addressing
        • Table 3-13: Based indexed addressing
        • Figure 3-25: Based indexed addressing description example
      • 3.4.9  Stack addressing
        • Figure 3-26: Stack addressing description example
  • Chapter 4 Port Functions
    • 4.1  Port Functions
      • Figure 4-1: Port Types
      • Table 4-1: Pin Input/Output Types (1/2)
    • 4.2  Port Configuration
      • Table 4-2: Port Configuration
      • 4.2.1  Port 0
        • Figure 4-2: P00 to P03 Configurations
      • 4.2.2  Port 1
        • Figure 4-3: P10 to P14 Configurations
      • 4.2.3  Port 2
        • Figure 4-4: P20 to P27 Configurations
      • 4.2.4  Port 3
        • Figure 4-5: P34 to P37 Configurations
      • 4.2.5  Port 4
        • Figure 4-6: P40 to P47 Configurations
      • 4.2.6  Port 5
        • Figure 4-7: P50 to P57 Configurations
      • 4.2.7  Port 6
        • Figure 4-8: P60 to P65 Configurations
      • 4.2.8  Port 8
        • Figure 4-9: P80 to P87 Configurations
      • 4.2.9  Port 9
        • Figure 4-10: P90 to P97 Configurations
    • 4.3  Port Function Control Registers
      • Figure 4-11: Port Mode Register Format
      • Figure 4-12: Pull-Up Resistor Option Register (PUm) Format
      • Figure 4-13: Port Function Register (PF3, PF4, PF8 and PF9) Format
    • 4.4  Port Function Operations
      • 4.4.1  Writing to input/output port
      • 4.4.2  Reading from input/output port
      • 4.4.3  Operations on input/output port
  • Chapter 5 Clock Generator
    • 5.1  Clock Generator Functions
    • 5.2  Clock Generator Configuration
      • Table 5-1: Clock Generator Configuration
      • Figure 5-1: Block Diagram of Clock Generator
    • 5.3  Clock Generator Control Register
      • Figure 5-2: Processor Clock Control Register Format
    • 5.4  System Clock Oscillator
      • 5.4.1  Main system clock oscillator
        • Figure 5-3: External Circuit of Main System Clock Oscillator
        • Figure 5-4: Examples of Oscillator with Bad Connection (1/3)
    • 5.5  Clock Generator Operations
    • 5.6  Changing System Clock and CPU Clock Settings
      • 5.6.1  Time required for switchover between system clock and CPU clock
        • Table 5-2: Maximum Time Required for CPU Clock Switchover
      • 5.6.2  System clock and CPU clock switching procedure
        • Figure 5-5: System Clock and CPU Clock Switching
  • Chapter 6 16-Bit Timer 2
    • 6.1  16-Bit Timer 2 Functions
      • Figure 6-1: Timer 2 (TM2) Block Diagram
    • 6.2  16-Bit Timer 2 Configuration
      • Table 6-1: Timer 2 Configuration
    • 6.3  16-Bit Timer 2 Control Registers
      • Figure 6-2: 16-Bit Timer Mode Control Register (TMC2) Format
      • Figure 6-3: Capture Pulse Control Register (CRC2) Format
      • Figure 6-4: Prescaler Mode Register (PRM2) Format
    • 6.4  16-Bit Timer 2 Operations
      • 6.4.1  Pulse width measurement operations
        • Figure 6-5: Configuration Diagram for Pulse Width Measurement by Using the Free Running Counter
        • Figure 6-6: Timing of Pulse Width Measurement Operation by Using the Free Running Counter and On...
        • Figure 6-7: CR2m Capture Operation with Rising Edge Specified
        • Figure 6-8: Timing of Pulse Width Measurement Operation by Free Running Counter (with Both Edges...
    • 6.5  16-Bit Timer 2 Precautions
      • Figure 6-9: 16-Bit Timer Register Start Timing
      • Figure 6-10: Capture Register Data Retention Timing
  • Chapter 7 8-Bit Timer/Event Counters 50 and 51
    • 7.1  8-Bit Timer/Event Counters 50 and 51 Functions
      • 7.1.1  8-bit operation modes
        • Table 7-1: 8-Bit Timer/Event Counter 50 Interval Times
        • Table 7-2: 8-Bit Timer/Event Counter 51 Interval Times
        • Table 7-3: 8-Bit Timer/Event Counter 50 Square-Wave Output Ranges
        • Table 7-4: 8-Bit Timer/Event Counter 51 Square-Wave Output Ranges
      • 7.1.2  16-bit operation modes
        • Table 7-5: 16-Bit Timer/Event Counter TM50/TM51 Interval Times
        • Table 7-6: 16-Bit Timer/Event Counter TM50/TM51 Square-Wave Output Ranges
    • 7.2  8-Bit Timer/Event Counters 50 and 51 Configurations
      • Table 7-7: 8-Bit Timer/Event Counters 50 and 51 Configurations
      • Figure 7-1: 8-Bit Timer/Event Counter 50 Block Diagram
      • Figure 7-2: 8-Bit Timer/Event Counter 51 Block Diagram
      • Figure 7-3: Block Diagram of 8-Bit Timer/Event Counters 50 and 51 Output Control Circuit
    • 7.3  8-Bit Timer/Event Counters 50 and 51 Control Registers
      • Figure 7-4: Timer Clock Select Register 50 Format
      • Figure 7-5: Timer Clock Select Register 51 Format
      • Figure 7-6: 8-Bit Timer Mode Control Register 50 Format
      • Figure 7-7: 8-Bit Timer Mode Control Register 51 Format (1/2)
      • Figure 7-8: Port Mode Register 3 Format
      • Figure 7-9: Port Mode Register 9 Format
    • 7.4  8-Bit Timer/Event Counters 50 and 51 Operations
      • 7.4.1  Interval timer operations
        • Figure 7-10: 8-Bit Timer Mode Control Register Settings for Interval Timer Operation
        • Figure 7-11: Interval Timer Operation Timings (1/3)
        • Table 7-8: 8-Bit Timer/Event Counters 50 Interval Times
        • Table 7-9: 8-Bit Timer/Event Counters 51 Interval Times
      • 7.4.2  External event counter operation
        • Figure 7-12: 8-Bit Timer Mode Control Register Setting for External Event Counter Operation
        • Figure 7-13: External Event Counter Operation Timings (with Rising Edge Specified)
      • 7.4.3  Square-wave output
        • Figure 7-14: 8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation
        • Figure 7-15: Square-wave Output Operation Timing
        • Table 7-10: 8-Bit Timer/Event Counters 50 Square-Wave Output Ranges
        • Table 7-11: 8-Bit Timer/Event Counters 51 Square-Wave Output Ranges
      • 7.4.4  PWM output operations
        • Figure 7-16: 8-Bit Timer Control Register Settings for PWM Output Operation
        • Figure 7-17: PWM Output Operation Timing (Active high setting)
        • Figure 7-18: PWM Output Operation Timings (CRn0 = 00H, active high setting)
        • Figure 7-19: PWM Output Operation Timings (CRn = FFH, active high setting)
        • Figure 7-20: PWM Output Operation Timings (CRn changing, active high setting)
    • 7.5  Operation as interval timer (16-bit operation)
      • Figure 7-21: 8-Bit Timer Mode Control Register Settings for 16-Bit Interval Timer Operation
      • Figure 7-22: 16-Bit Resolution Cascade Mode (with TM50 and TM51)
      • Table 7-12: 8-Bit Timer/Event Counters Interval Times (16-Bit Timer/Event Counter Mode)
      • Table 7-13: 8-Bit Timer/Event Counter Square-Wave Output Ranges (16-Bit Timer/Event Counter Mode)
    • 7.6  Cautions on 8-Bit Timer/Event Counters 50 and 51
      • Figure 7-23: 8-bit Timer Registers 50 and 51 Start Timings
      • Figure 7-24: External Event Counter Operation Timings
      • Figure 7-25: Timings after Compare Register Change during Timer Count Operation
  • Chapter 8 8-Bit Timer 52
    • 8.1  8-Bit Timer 52 Functions
      • Table 8-1: 8-Bit Timer 52 Interval Times
    • 8.2  8-Bit Timer 52 Configurations
      • Table 8-2: 8-Bit Timer 52 Configurations
      • Figure 8-1: 8-Bit Timer/Event Counter 52 Block Diagram
    • 8.3  8-Bit Timer 52 Control Registers
      • Figure 8-2: Timer Clock Select Register 52 Format
      • Figure 8-3: 8-Bit Timer Output Control Register Format
    • 8.4  8-Bit Timer 52 Operations
      • 8.4.1  Interval timer operations
        • Figure 8-4: 8-Bit Timer Mode Control Register Settings for Interval Timer Operation
        • Figure 8-5: Interval Timer Operation Timings (1/3)
  • Chapter 9 Watch Timer
    • 9.1  Watch Timer Functions
      • Figure 9-1: Block Diagram of Watch Timer
      • Table 9-1: Interval Timer Interval Time
    • 9.2  Watch Timer Configuration
      • Table 9-2: Watch Timer Configuration
    • 9.3  Watch Timer Mode Register (WTM)
      • Figure 9-2: Watch Timer Mode Control Register (WTM) Format (1/2)
    • 9.4  Watch Timer Operations
      • 9.4.1  Watch timer operation
      • 9.4.2  Interval timer operation
        • Table 9-3: Interval Timer Operation
        • Figure 9-3: Operation Timing of Watch Timer/Interval Timer
  • Chapter 10 Watchdog Timer
    • 10.1  Watchdog Timer Functions
      • Table 10-1: Watchdog Timer Inadvertent Program Overrun Detection Times
      • Table 10-2: Interval Times
    • 10.2  Watchdog Timer Configuration
      • Table 10-3: Watchdog Timer Configuration
      • Figure 10-1: Watchdog Timer Block Diagram
    • 10.3  Watchdog Timer Control Registers
      • Figure 10-2: Timer Clock Select Register 2 Format
      • Figure 10-3: Watchdog Timer Mode Register Format
    • 10.4  Watchdog Timer Operations
      • 10.4.1  Watchdog timer operation
        • Table 10-4: Watchdog Timer Overrun Detection Time
      • 10.4.2  Interval timer operation
        • Table 10-5: Interval Timer Interval Time
  • Chapter 11 Clock Output Control Circuit
    • 11.1  Clock Output Control Circuit Functions
      • Figure 11-1: Remote Controlled Output Application Example
    • 11.2  Clock Output Control Circuit Configuration
      • Table 11-1: Clock Output Control Circuit Configuration
      • Figure 11-2: Clock Output Control Circuit Block Diagram
    • 11.3  Clock Output Function Control Registers
      • Figure 11-3: Timer Clock Select Register 0 Format
      • Figure 11-4: Port Mode Register 6 Format
  • Chapter 12 A/D Converter
    • 12.1  A/D Converter Functions
      • Figure 12-1: A/D Converter Block Diagram
      • Figure 12-2: Power-Fail Detection Function Block Diagram
    • 12.2  A/D Converter Configuration
      • Table 12-1: A/D Converter Configuration
    • 12.3  A/D Converter Control Registers
      • Figure 12-3: A/D Converter Mode Register (ADM1) Format
      • Figure 12-4: Analog Input Channel Specification Register (ADS1) Format
      • Figure 12-5: Power-Fail Compare Mode Register (PFM) Format
      • Figure 12-6: Power-fail compare threshold value register (PFT)
    • 12.4  A/D Converter Operations
      • 12.4.1  Basic Operations of A/D Converter
        • Figure 12-7: Basic Operation of 8-Bit A/D Converter
      • 12.4.2  Input voltage and conversion results
        • Figure 12-8: Relation between Analog Input Voltage and A/D Conversion Result
      • 12.4.3  A/D converter operation mode
        • Figure 12-9: A/D Conversion
    • 12.5  A/D Converter Precautions
      • Figure 12-10: Example Method of Reducing Current Consumption in Standby Mode
      • Figure 12-11: Analog Input Pin Handling
      • Figure 12-12: A/D Conversion End Interrupt Request Generation Timing
    • 12.6  Cautions on Emulation
      • 12.6.1  D/A converter mode register (DAM0)
        • Figure 12-13: D/A Converter Mode Register (DAM0) Format
  • Chapter 13 Serial Interface SIO30
    • 13.1  SIO30 Functions
      • Figure 13-1: Block Diagram of SIO30
    • 13.2  SIO30 Configuration
      • Table 13-1: Composition of SIO30
    • 13.3  List of SFRs (Special Function Registers)
      • Table 13-2: List of SFRs (Special Function Registers)
    • 13.4  Serial Interface Control Register
      • Figure 13-2: Format of Serial Operation Mode Register (CSIM30)
    • 13.5  Serial Interface Operations
      • 13.5.1  Operation stop mode
        • Figure 13-3: Format of Serial Operation Mode Register (CSIM30)
      • 13.5.2  Three-wire serial I/O mode
        • Figure 13-4: Format of Serial Operation Mode Register (CSIM30)
        • Figure 13-5: Timing of Three-wire Serial I/O Mode
  • Chapter 14 Serial Interface SIO31
    • 14.1  SIO31 Functions
      • Figure 14-1: Block Diagram of SIO31
    • 14.2  SIO31 Configuration
      • Table 14-1: Composition of SIO31
    • 14.3  List of SFRs (Special Function Registers)
      • Table 14-2: List of SFRs (Special Function Registers)
    • 14.4  Serial Interface Control Register
      • Figure 14-2: Format of Serial Operation Mode Register (CSIM31)
      • Figure 14-3: Format of Serial Mode Switch Register (SIOSWI)
      • Table 14-3: Operating Modes and Start Trigger
    • 14.5  Serial Interface Operations
      • 14.5.1  Operation stop mode
        • Figure 14-4: Format of Serial Operation Mode Register (CSIM31)
      • 14.5.2  Three-wire serial I/O mode
        • Figure 14-5: Format of Serial Operation Mode Register (CSIM31)
        • Figure 14-6: Format of Serial Mode Switch Register (SIOSWI)
        • Table 14-4: Operating Modes and Start Trigger
      • 14.5.3  Two-wire serial I/O mode
        • Figure 14-7: Format of Serial Operation Mode Register (CSIM31)
        • Figure 14-8: Format of Serial Mode Switch Register (SIOSWI)
        • Table 14-5: Operating Modes and Start Trigger
        • Figure 14-9: Timing of Three-wire Serial I/O Mode
        • Figure 14-10: Timing of Two-wire Serial I/O Mode
  • Chapter 15 Serial Interface Channel UART
    • 15.1  UART Functions
      • Figure 15-1: Block Diagram of UART
    • 15.2  UART Configuration
      • Table 15-1: Configuration of UART
    • 15.3  List of SFRS (Special Function Registers)
      • Table 15-2: List of SFRs (Special Function Registers)
    • 15.4  Serial Interface Control Registers
      • Figure 15-2: Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2)
      • Figure 15-3: Format of Asynchronous Serial Interface Status Register (ASIS0)
      • Figure 15-4: Format of Baud Rate Generator Control Register (BRGC0) (1/2)
    • 15.5  Serial Interface Operations
      • 15.5.1  Operation stop mode
        • Figure 15-5: Register Settings
      • 15.5.2  Asynchronous serial interface (UART) mode
        • Figure 15-6: Format of Asynchronous Serial Interface Mode Register (ASIM0) (1/2)
        • Figure 15-7: Format of Asynchronous Serial Interface Status Register (ASIS0)
        • Figure 15-8: Format of Baud Rate Generator Control Register (BRGC0) (1/2)
        • Table 15-3: Relation between 5-bit Counter�s Source Clock and �n� Value
        • Table 15-4: Relation between Main System Clock and Baud Rate
        • Figure 15-9: Error Tolerance (when k = 0), including Sampling Errors
        • Figure 15-10: Format of Transmit/Receive Data in Asynchronous Serial Interface
        • Figure 15-11: Timing of Asynchronous Serial Interface Transmit Completion Interrupt
        • Figure 15-12: Timing of Asynchronous Serial Interface Receive Completion Interrupt
        • Table 15-5: Causes of Receive Errors
        • Figure 15-13: Receive Error Timing
    • 15.6  Behavior of UART during Standby of the Controller
  • Chapter 16 CAN Controller
    • Table 16-1: Outline of the Function
    • 16.1  CAN Protocol
      • 16.1.1  Protocol Mode Function
      • 16.1.2  Message Format
      • 16.1.3  Data Frame / Remote Frame
        • Figure 16-1: Data Frame
        • Figure 16-2: Remote Frame
      • 16.1.4  Description of each field
        • Figure 16-3: Data Frame
        • Figure 16-4: Arbitration Field/Standard Format Mode
        • Figure 16-5: Arbitration Field/Extended Format Mode
        • Table 16-2: Bit Number of the Identifier
        • Table 16-3: RTR Setting
        • Table 16-4: Mode Setting
        • Figure 16-6: Control Field (Standard Format Mode)
        • Figure 16-7: Control Field (Extended Format Mode)
        • Table 16-5: Data Length Code Setting
        • Figure 16-8: Data Field
        • Figure 16-9: CRC Field
        • Figure 16-10: ACK Field
        • Figure 16-11: End of Frame
        • Figure 16-12: Interframe Space/Error Active
        • Figure 16-13: Interframe Space/Error Passive
        • Table 16-6: Operation in the Error State
      • 16.1.5  Error Frame
        • Figure 16-14: Error Frame
        • Table 16-7: Definition of each Field
      • 16.1.6  Overload Frame
        • Figure 16-15: Overload Frame
        • Table 16-8: Definition of each Frame
    • 16.2  Function
      • 16.2.1  Arbitration
        • Table 16-9: Arbitration
      • 16.2.2  Bit Stuffing
        • Table 16-10: Bit Stuffing
      • 16.2.3  Multi Master
      • 16.2.4  Multi Cast
      • 16.2.5  Sleep Mode/Stop Function
      • 16.2.6  Error Control Function
        • Table 16-11: Error Types
        • Table 16-12: Output Timing of the Error Frame
        • Table 16-13: Types of Error
        • Table 16-14: Error Counter
      • 16.2.7  Baud Rate Control Function
        • Figure 16-16: Nominal Bit Time (8 to 25 Time Quanta)
        • Table 16-15: Segment Name and Segment Length
        • Figure 16-17: Adjusting Synchronization of the Data Bit
        • Figure 16-18: Bit Synchronization
      • 16.2.8  State Shift Chart
        • Figure 16-19: Transmission State Shift Chart
        • Figure 16-20: Reception State Shift Chart
        • Figure 16-21: Error State Shift Chart
    • 16.3  Outline Description
      • Figure 16-22: Structural Block Diagram
    • 16.4  Connection with Target System
      • Figure 16-23: Connection to the CAN Bus
    • 16.5  CAN Controller Configuration
      • Table 16-16:  CAN Configuration
    • 16.6  Special Function Register for CAN-module
      • Table 16-17: SFR Definitions
      • Table 16-18:  SFR Bit Definitions
    • 16.7  Message and Buffer Configuration
      • Table 16-19: Message and Buffer Configuration
    • 16.8  Transmit Buffer Structure
    • 16.9  Transmit Message Format
      • Table 16-20: Transmit Message Format
      • Figure 16-24: Transmit Message Definition Bits
      • Figure 16-25: Transmit Identifier
      • Figure 16-26: Transmit Data
    • 16.10  Receive Buffer Structure
    • 16.11  Receive Message Format
      • Table 16-21: Receive Message Format
      • Figure 16-27: Control bits for Receive Identifier
      • Figure 16-28: Receive Status Bits (1/2)
      • Figure 16-29: Receive Identifier
      • Figure 16-30: Receive Data
    • 16.12  Mask Function
      • Table 16-22:  Mask Function
      • Figure 16-31: Identifier Compare with Mask
      • Figure 16-32: Control Bits for Mask Identifier
      • Figure 16-33: Mask Identifier
    • 16.13  Operation of the CAN Controller
      • 16.13.1  CAN control register (CANC)
        • Figure 16-34: CAN Control Register (1/2)
        • Figure 16-35: DCAN Support
        • Table 16-23: Possible Setup of the SOFOUT Function
        • Table 16-24: Transmission / Reception Flag
        • Figure 16-36: Time Stamp Function
        • Figure 16-37: SOFOUT Toggle Function
        • Figure 16-38: Global Time System Function
      • 16.13.2  DCAN Error Status Register
        • Figure 16-39: CAN Error Status Register (1/3)
        • Table 16-25: Possible Reactions of the DCAN
      • 16.13.3  CAN Transmit Error Counter
        • Figure 16-40: Transmit Error Counter
      • 16.13.4  CAN Receive Error Counter
        • Figure 16-41: Receive Error Counter
      • 16.13.5  Message Count Register
        • Figure 16-42: Message Count Register (MCNT) (1/2)
    • 16.14  Baudrate Generation
      • Figure 16-43: Bit Rate Prescaler (1/2)
      • Figure 16-44: Synchronization Control Registers 0 and 1 (1/2)
    • 16.15  Function Control
      • 16.15.1  Transmit Control
        • Figure 16-45: Transmit Control Register (1/2)
      • 16.15.2  Receive Control
        • Figure 16-46: Receive Message Register
      • 16.15.3  Mask Control
        • Figure 16-47: Mask Control Register (1/2)
        • Table 16-26: Mask Operation Buffers
      • 16.15.4  Special Functions
        • Figure 16-48: Redefinition Control Register (1/2)
    • 16.16  Interrupt Information
      • 16.16.1  Interrupt Vectors
        • Table 16-27: Interrupt Sources
      • 16.16.2  Transmit Interrupt
      • 16.16.3  Receive Interrupt
      • 16.16.4  Error Interrupt
    • 16.17  Influence of the standby Function of the CAN Controller
      • 16.17.1  CPU Halt Mode
      • 16.17.2  CPU Stop Mode
      • 16.17.3  DCAN Sleep Mode
      • 16.17.4  DCAN Stop Mode
    • 16.18  Functional Description by Flowcharts
      • 16.18.1  Initialization
        • Figure 16-49: Initialization Flow Chart
      • 16.18.2  Transmit Preparation
        • Figure 16-50: Transmit Preparation
      • 16.18.3  Abort Transmit
        • Figure 16-51: Transmit Abort
      • 16.18.4  Handling by the DCAN
        • Figure 16-52: Handling of Semaphore Bits by DCAN-Module
      • 16.18.5  Receive Event Oriented
        • Figure 16-53: Receive with Interrupt, Software Flow
      • 16.18.6  Receive Task Oriented
        • Figure 16-54: Receive, Software Polling
  • Chapter 17 LCD Controller / Driver
    • 17.1  LCD Controller/Driver Functions
      • Table 17-1: Maximum Number of Display Pixels
    • 17.2  LCD Controller/Driver Configuration
      • Table 17-2: LCD Controller/Driver Configuration
      • Figure 17-1: LCD Controller/Driver Block Diagram
      • Figure 17-2: LCD Clock Select Circuit Block Diagram
    • 17.3  LCD Controller/Driver Control Registers
      • Figure 17-3: LCD Display Mode Register (LCDM) Format
      • Figure 17-4: LCD Display Control Register (LCDC) Format
    • 17.4  LCD Controller/Driver Settings
    • 17.5  LCD Display Data Memory
      • Figure 17-5: Relationship between LCD Display Data Memory Contents and Segment/Common Outputs
    • 17.6  Common Signals and Segment Signals
      • Table 17-3: COM Signals
      • Table 17-4: LCD Drive Voltage
      • Figure 17-6: Common Signal Waveform
      • Figure 17-7: Common Signal and Segment Signal Voltages and Phases
    • 17.7  Supplying LCD Drive Voltage VLC0, VLC1, and VLC2
      • Table 17-5: LCD Drive Voltage Supply
      • Figure 17-8: Example of Connection of LCD Drive Power Supply (1/2)
    • 17.8  Display Mode
      • 17.8.1  4-time-division display example
        • Table 17-6: Selection and Non-Selection Voltages (COM0 to COM3)
        • Figure 17-9: 4-Time-Division LCD Display Pattern and Electrode Connections
        • Figure 17-10: 4-Time-Division LCD Panel Connection Example
        • Figure 17-11: 4-Time-Division LCD Drive Waveform Examples (1/3 Bias Method)
    • 17.9  Cautions on Emulation
      • 17.9.1  LCD timer control register (LCDTM)
        • Figure 17-12: LCD Timer Control Register (LCDTM) Format
  • Chapter 18 Sound Generator
    • 18.1  Sound Generator Function
      • Figure 18-1: Sound Generator Block Diagram
      • Figure 18-2: Concept of Each Signal
    • 18.2  Sound Generator Configuration
      • Table 18-1: Sound Generator Configuration
    • 18.3  Sound Generator Control Registers
      • Figure 18-3: Sound Generator Control Register (SGCR) Format (1/2)
      • Table 18-2: Maximum and Minimum Values of the Buzzer Output Frequency
      • Figure 18-4: Sound Generator Buzzer Control Register (SGBR) Format
      • Figure 18-5: Sound Generator Amplitude Register (SGAM) Format
    • 18.4  Sound Generator Operations
      • 18.4.1  To output basic cycle signal SGOF (without amplitude)
        • Figure 18-6: Sound Generator Output Operation Timing
      • 18.4.2  To output basic cycle signal SGO (with amplitude)
        • Figure 18-7: Sound Generator Output Operation Timing
  • Chapter 19 Meter Controller / Driver
    • 19.1  Meter Controller/Driver Functions
      • Figure 19-1: Meter Controller/Driver Block Diagram
      • Figure 19-2: 1-bit Addition Circuit Block Diagram
    • 19.2  Meter Controller/Driver Configuration
      • Table 19-1:  Meter Controller/Driver Configuration
    • 19.3  Meter Controller/Driver Control Registers
      • Figure 19-3: Timer Mode Control Register (MCNTC) Format
      • Figure 19-4: Compare Control Register n (MCMPCn) Format
      • Figure 19-5: Port Mode Control Register (PMC) Format (1/2)
      • Figure 19-6: Meter Controller/Driver Clock Register (SMSWI) Format
    • 19.4  Meter Controller/Driver Operations
      • 19.4.1  Basic operation of free-running up counter (SMCNT)
        • Figure 19-7: Restart Timing after Count Stop (Count Start � Count Stop � Count Start)
      • 19.4.2  Update of PWM data
        • Figure 19-8: Update of PWM data
      • 19.4.3  Operation of 1-bit addition circuit
        • Figure 19-9: Timing in 1-bit Addition Circuit Operation
      • 19.4.4  PWM output operation (output with 1 clock shifted)
        • Figure 19-10: Timing of Output with 1 Clock Shifted
  • Chapter 20 Interrupt Functions
    • 20.1  Interrupt Function Types
    • 20.2  Interrupt Sources and Configuration
      • Table 20-1: Interrupt Source List
      • Figure 20-1: Basic Configuration of Interrupt Function (1/2)
    • 20.3  Interrupt Function Control Registers
      • Table 20-2: Various Flags Corresponding to Interrupt Request Sources
      • Figure 20-2: Interrupt Request Flag Register Format
      • Figure 20-3: Interrupt Mask Flag Register Format
      • Figure 20-4: Priority Specify Flag Register Format
      • Figure 20-5: Formats of External Interrupt Rising Edge Enable Register and External Interrupt Fa...
      • Figure 20-6: Program Status Word Format
    • 20.4  Interrupt Servicing Operations
      • 20.4.1  Non-maskable interrupt request acknowledge operation
        • Figure 20-7: Flowchart from Non-Maskable Interrupt Generation to Acknowledge
        • Figure 20-8: Non-Maskable Interrupt Request Acknowledge Timing
        • Figure 20-9: Non-Maskable Interrupt Request Acknowledge Operation
      • 20.4.2  Maskable interrupt request acknowledge operation
        • Table 20-3: Times from Maskable Interrupt Request Generation to Interrupt Service
        • Figure 20-10: Interrupt Request Acknowledge Processing Algorithm
        • Figure 20-11: Interrupt Request Acknowledge Timing (Minimum Time)
        • Figure 20-12: Interrupt Request Acknowledge Timing (Maximum Time)
      • 20.4.3  Software interrupt request acknowledge operation
      • 20.4.4  Multiple interrupt servicing
        • Table 20-4: Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing
        • Figure 20-13: Multiple Interrupt Example (1/2)
      • 20.4.5  Interrupt request reserve
        • Figure 20-14: Interrupt Request Hold
  • Chapter 21 Standby Function
    • 21.1  Standby Function and Configuration
      • 21.1.1  Standby function
      • 21.1.2  Standby function control register
        • Figure 21-1: Oscillation Stabilization Time Select Register Format
        • Figure 21-2: Standby Timing
    • 21.2  Standby Function Operations
      • 21.2.1  HALT mode
        • Table 21-1: HALT Mode Operating Status
        • Figure 21-3: HALT Mode Clear upon Interrupt Generation
        • Figure 21-4: HALT Mode Release by RESET Input
        • Table 21-2: Operation after HALT Mode Release
      • 21.2.2  STOP mode
        • Table 21-3: STOP Mode Operating Status
        • Figure 21-5: STOP Mode Release by Interrupt Generation
        • Figure 21-6: Release by STOP Mode RESET Input
        • Table 21-4: Operation after STOP Mode Release
  • Chapter 22 Reset Function
    • 22.1  Reset Function
      • Figure 22-1: Block Diagram of Reset Function
      • Figure 22-2: Timing of Reset Input by RESET Input
      • Figure 22-3: Timing of Reset due to Watchdog Timer Overflow
      • Figure 22-4: Timing of Reset Input in STOP Mode by RESET Input
      • Table 22-1: Hardware Status after Reset (1/3)
  • Chapter 23 �PD78F0828A and Memory Definition
    • Table 23-1: Differences among �PD78F0828A and Mask ROM Versions
    • 23.1  Memory Size Switching Register (IMS)
      • Figure 23-1: Memory Size Switching Register Format
      • Table 23-2: Values to be set after Reset for the Memory Size Switching Register
    • 23.2  Internal Expansion RAM Size Switching Register
      • Figure 23-2: Internal Expansion RAM Size Switching Register Format
      • Table 23-3: Examples of internal Expansion RAM Size Switching Register Settings
      • Table 23-4: Values when the Internal Expansion RAM Size Switching Register is Reset
    • 23.3  Self-Programming and Oscillation Control Register
      • Figure 23-3: Self-Programming and Oscillation Control Register Format
    • 23.4  Flash memory programming with flash programmer
      • 23.4.1  Selection of transmission method
        • Table 23-5: Transmission Method List
        • Figure 23-4: Transmission Method Selection Format
      • 23.4.2  Initialization of the programming mode
      • 23.4.3  Flash memory programming function
        • Table 23-6: Main Functions of Flash Memory Programming
      • 23.4.4  Flash programmer connection
        • Figure 23-5: Connection of using the 3-Wire SIO30 Method
        • Figure 23-6: Connection of using the 3-Wire SIO30 Method with Handshake
        • Figure 23-7: Connection of using the UART Method
      • 23.4.5  Flash programming precautions
    • 23.5  Flash Self-Programming Control
      • 23.5.1  Flash Self-Programming Mode Control Register
        • Figure 23-8: Flash Self-Programming Mode Control Register Format
  • Chapter 24 Instruction Set
    • 24.1  Legends Used in Operation List
      • 24.1.1  Operand identifiers and description methods
        • Table 24-1: Operand Identifiers and Description Methods
      • 24.1.2  Description of �operation� column
    • 24.2  Operation List
      • Table 24-2: Operation List (1/8)
    • 24.3  Instructions Listed by Addressing Type
      • Table 24-3: 8-bit instructions
      • Table 24-4: 16-bit instructions
      • Table 24-5: Bit manipulation instructions
      • Table 24-6: Call/instructions/branch instructions
  • Chapter 25 Electrical Specifications
    • 25.1  Absolute Maximum Ratings
    • 25.2  Capacitance
    • 25.3  Main System Clock Oscillation Circuit Characteristics
    • 25.4  DC Characteristics
    • 25.5  AC Characteristics
      • 25.5.1  Basic Operation
      • 25.5.2  Serial Interface
      • 25.5.3  Sound Generator Characteristics
      • 25.5.4  Meter Controller / Driver Characteristics
      • 25.5.5  A/D Converter Characteristics
      • 25.5.6  Data Memory Stop Mode Low Supply Voltage Data Retention Characteristics
      • 25.5.7  Flash Memory Programming Characteristics: �PD78F0828A(A)
  • Chapter 26 Package Drawing
  • Chapter 27 Recommended Soldering Conditions
  • Appendix A  Development Tools
    • Figure A-1: Development Tool Configuration
    • A.1  Language Processing Software
    • A.2  Flash Memory Writing Tools
    • A.3  Debugging Tools
  • Appendix B  Embedded Software
    • B.1  Real-Time OS
    • B.2  Fuzzy Inference Development Support System
  • Appendix C  Index
  • Appendix D  Revision History