Document Outline
- COVER
- FEATURES
- ORDERING INFORMATION
- 78K/0 SERIES LINEUP
- OVERVIEW OF FUNCTIONS
- PIN CONFIGURATION (Top View)
- BLOCK DIAGRAM
- 1. DIFFERENCES BETWEEN uPD78F0988 AND MASK ROM VERSIONS
- 2. PIN FUNCTIONS
- 2.1 Port Pins
- 2.2 Non-Port Pins
- 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
- 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
- 4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
- 5. FLASH MEMORY PROGRAMMING
- 5.1 Selection of Communication Mode
- 5.2 Flash Memory Programming Functions
- 5.3 Connection of Flashpro II and Flashpro III
- 6. ELECTRICAL SPECIFICATIONS
- 7. PACKAGE DRAWINGS
- APPENDIX A. DEVELOPMENT TOOLS
- APPENDIX B. RELATED DOCUMENTS
PRELIMINARY DATA SHEET
1997, 1999
The
PD78F0988 is a member of the
PD780988 Subseries of the 78K/0 Series that substitute flash memory for
the internal ROM of the
PD780988. Flash memory can be written or erased electrically without having to remove
it from board. Therefore, the
PD78F0988 is best suited for evaluation in system development, small-scale
production, or systems likely to be upgraded frequently.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
PD780988 Subseries User's Manual:
U13029E
78K/0 Series Instructions User's Manual: U12326E
FEATURES
Pin-compatible with mask ROM version (except V
PP
pin)
Flash memory: 60 Kbytes
Note 1
Internal high-speed RAM: 1024 bytes
Internal expansion RAM: 1024 bytes
Note 2
Operable in the same supply voltage range as the mask ROM version (V
DD
= 4.0 to 5.5 V)
Notes 1.
The capacity of the flash memory can be changed with the internal memory size switching register (IMS).
2.
The capacity of the internal expansion RAM can be changed with the internal expansion RAM size
switching register (IXS).
Remark
For the differences between the flash memory versions and the mask ROM versions, refer to
1. DIFFERENCES BETWEEN
PD78F0988 AND MASK ROM VERSIONS.
ORDERING INFORMATION
Part Number
Package
PD78F0988CW
64-pin plastic shrink DIP (750 mil)
PD78F0988GC-AB8
64-pin plastic QFP (14
14 mm)
MOS INTEGRATED CIRCUIT
8-BIT SINGLE-CHIP MICROCONTROLLER
PD78F0988
Document No. U12805EJ1V0DS00 (1st edition)
Date Published June 1999 N CP(K)
Printed in Japan
The mark shows major revised points.
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
2
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
78K/0 SERIES LINEUP
The products in the 78K/0 Series are listed below. The names enclosed in boxes are subseries names.
PD780955
PD78083
PD78044F
80-pin
Basic subseries for FIP driving, Total display output: 34
PD78044H
80-pin
PD78044F with N-ch open-drain I/O, Total display output: 34
PD780232
80-pin
For panel control and on-chip FIP C/D, Total display output: 53
PD780034A
PD780024A
PD780024AY
PD78014H
PD78018F
64-pin
64-pin
64-pin
64-pin
PD780024A with enhanced A/D converter
PD78018F with enhanced serial I/O
PD78018F with reduced EMI noise
Basic subseries for control
PD78018FY
PD780034AY
PD780078
64-pin
PD780034A with timer and enhanced serial I/O
PD780078Y
PD780208
PD780228
PD780308
PD78064B
PD78064
PD780308Y
PD78064Y
42/44-pin
100-pin
100-pin
100-pin
100-pin
100-pin
For LCD driving
For FIP
TM
driving
78K/0
Series
On-chip UART and capable of low-voltage (1.8 V) operation
PD78044F with enhanced I/O and FIP C/D, Total display output: 53
PD78044H with enhanced I/O and FIP C/D, Total display output: 48
PD780988
64-pin
For inverter control
PD780841
80-pin
Call ID supporting
On-chip inverter control circuit and UART, EMI noise reduced product
On-chip Call ID function and simple DTMF, EMI noise reduced product
PD78064 with enhanced SIO and expanded ROM and RAM
PD78064 with reduced EMI noise
Basic subseries for LCD driving and on-chip UART
80-pin
On-chip J1850 (CLASS2) controller
Specialized in DCAN controller
PD78098B
PD780973
PD780824
80-pin
80-pin
80-pin
80-pin
For meter control
Bus interface supporting
PD78054 with IEBus
TM
controller, EMI noise reduced product
On-chip DCAN/IEBus controller
On-chip controller/driver for automobile meter driving
For automobile meter driving and on-chip DCAN controller
80-pin
Ultra low power consumption and on-chip UART
In mass-production
Under development
Y subseries products are compatible with I
2
C bus.
PD780065
80-pin
PD780024A with expanded RAM
PD780058
PD78058F
PD78054
80-pin
80-pin
80-pin
PD78054 with enhanced serial I/O
PD78054 with reduced EMI noise
PD78018F with UART and D/A converter, and enhanced I/O
100-pin
PD78078
PD78070A
PD78075B
100-pin
100-pin
100-pin
For control
PD78054 with timer and enhanced external interface function
PD78078 with reduced EMI noise
ROM-less version of the PD78078
PD78078Y with enhanced serial I/O and restricted function
PD78054Y
PD78058FY
PD780058Y
PD780018AY
PD78070AY
PD78078Y
PD780948
100-pin
On-chip DCAN controller
PD780958
100-pin
For industrial meter control
PD780814
64-pin
PD780833Y
PD780701Y
3
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
For
PD78075B 32 K to 40 K
4 ch
1 ch
1 ch
1 ch
8 ch
2 ch
3 ch (UART: 1 ch) 88
1.8 V
control
PD78078
48 K to 60 K
PD78070A
61
2.7 V
PD780058
24 K to 60 K
2 ch
3 ch (time-division UART: 1 ch) 68
1.8 V
PD78058F 48 K to 60 K
3 ch (UART: 1 ch) 69
2.7 V
PD78054
16 K to 60 K
2.0 V
PD780065
40 K to 48 K
4 ch (UART: 1 ch) 60
2.7 V
PD780078
48 K to 60 K
2 ch
8 ch
3 ch (UART: 2 ch) 52
1.8 V
PD780034A 8 K to 32 K
1 ch
3 ch (UART: 1 ch) 51
PD780024A
8 ch
PD78014H
2 ch
53
PD78018F 8 K to 60 K
PD78083
8 K to 16 K
1 ch (UART: 1 ch) 33
For
PD780988
16 K to 60 K
3 ch
Note
1 ch
8 ch
3 ch (UART: 2 ch) 47
4.0 V
inverter
control
For FIP
PD780208
32 K to 60 K
2 ch
1 ch
1 ch
1 ch
8 ch
2 ch
74
2.7 V
driving
PD780228
48 K to 60 K
3 ch
1 ch
72
4.5 V
PD780232
16 K to 24 K
4 ch
2 ch
40
PD78044H 32 K to 48 K
2 ch
1 ch
1 ch
8 ch
1 ch
68
2.7 V
PD78044F 16 K to 40 K
2 ch
For LCD
PD780308
48 K to 60 K
2 ch
1 ch
1 ch
1 ch
8 ch
3 ch (time-division UART: 1 ch) 57
2.0 V
driving
PD78064B 32 K
2 ch (UART: 1 ch)
PD78064
16 K to 32 K
Call ID
PD780841
24 K to 32 K
2 ch
1 ch
1 ch
2 ch
2 ch (UART: 1 ch) 61
2.7 V
supporting
Bus
PD780948
60 K
2 ch
2 ch
1 ch
1 ch
8 ch
3 ch (UART: 1 ch) 79
4.0 V
interface
PD78098B 40 K to 60 K
1 ch
2 ch
69
2.7 V
supporting
PD780814
32 K to 60 K
2 ch
12 ch
2 ch (UART: 1 ch) 46
4.0 V
For meter
PD780958
48 K to 60 K
4 ch
2 ch
1 ch
2 ch (UART: 1 ch) 69
2.2 V
control
PD780973
24 K to 32 K
3 ch
1 ch
1 ch
5 ch
56
4.5 V
PD780824
32 K to 60 K
59
4.0 V
PD780955
40 K
6 ch
1 ch
2 ch (UART: 2 ch) 50
2.2 V
Timer
8-bit 16-bit Watch WDT
Serial
Interface
I/O
8-bit
A/D
ROM
Capacity
External
Expansion
V
DD
MIN.
Value
Subseries Name
Function
10-bit
A/D
8-bit
D/A
The major functional differences among the subseries are listed below.
Note 16-bit timer: 2 channels
10-bit timer: 1 channel
4
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
OVERVIEW OF FUNCTIONS
Item
Function
Internal
Flash memory
60 Kbytes
Note 1
memory
High-speed RAM
1024 bytes
Expansion RAM
1024 bytes
Note 2
Memory space
64 Kbytes
General-purpose register
8 bits
32 registers (8 bits
8 registers
4 banks)
Instruction cycle
On-chip instruction execution time variable function
0.24
s/0.48
s/0.96
s/1.9
s/3.8
s (@ 8.38-MHz operation with system clock)
Instruction set
16-bit operation
Multiply/divide (8 bits
8 bits, 16 bits
8 bits)
Bit manipulation (set, reset, test, Boolean operation)
BCD adjust, etc.
I/O ports
Total:
47
CMOS inputs:
8
CMOS I/Os:
39
Real-time output ports
8 bits
1 or 4 bits
2
6 bits
1 or 4 bits
1
A/D converter
10-bit resolution
8 channels
Power supply voltage: AV
DD
= 4.0 to 5.5 V
Serial interface
UART mode: 2 channels
3-wire serial I/O mode: 1 channel
Timer
16 bit timer/event counter:
2 channels
8-bit timer/event counter:
3 channels
10-bit inverter control timer: 1 channel
Watchdog timer:
1 channel
Timer output
11 (general-purpose outputs: 5 and inverter control outputs: 6)
Vectored
Maskable
Internal: 16, external: 8
interrupt
Non-maskable
Internal: 1
sources
Software
1
Power supply voltage
V
DD
= 4.0 to 5.5 V
Operating ambient temperature T
A
= 40 to +85
C
Package
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14
14 mm)
Notes 1.
The capacity of the flash memory can be changed with the internal memory size switching register
(IMS).
2.
The capacity of the internal expansion RAM can be changed with the internal expansion RAM size
switching register (IXS).
5
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
PIN CONFIGURATION (Top View)
64-Pin Plastic Shrink DIP (750 mil)
PD78F0988CW
Caution
In the normal operation mode, connect the V
PP
pin directly to V
SS0
.
Remark
When the
PD78F0988 is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to
V
DD0
and V
DD1
individually and connecting V
SS0
and V
SS1
to different ground lines, is recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P50
P51/SCK
P52/SI
P53/SO
P54/TI000/TO00/INTP4
P55/TI010/INTP5
P56/TI001/TO01/INTP6
P57/TI011/INTP7
V
SS0
V
DD0
TO70
TO71
TO72
TO73
TO74
TO75
P20/RxD00
P21/TxD00
P22/RxD01
P23/TxD01
P24/TI50/TO50
P25/TI51/TO51
P26/TI52/TO52
V
DD1
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P37/RTP7
P36/RTP6
P35/RTP5
P34/RTP4
P33/RTP3
P32/RTP2
P31/RTP1
P30/RTP0
P01/INTP1
P00/INTP0/TOFF7
V
SS1
X1
X2
TEST
P03/INTP3/ADTRG
P02/INTP2
RESET
AV
DD
AV
REF
P10/ANI0
P11/ANI1
P12/ANI2
P13/ANI3
P14/ANI4
P15/ANI5
P16/ANI6
P17/ANI7
AV
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
6
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
64-Pin Plastic QFP (14
14 mm)
PD78F0988GC-AB8
Caution
In the normal operation mode, connect the V
PP
pin directly to V
SS0
.
Remark
When the
PD78F0988 is used in applications where the noise generated inside the microcontroller
needs to be reduced, the implementation of noise reduction measures, such as supplying voltage to
V
DD0
and V
DD1
individually and connecting V
SS0
and V
SS1
to different ground lines, is recommended.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P50
P51/SCK
P52/SI
P53/SO
P54/TI000/TO00/INTP4
P55/TI010/INTP5
P56/TI001/TO01/INTP6
P57/TI011/INTP7
V
SS0
V
DD0
TO70
TO71
TO72
TO73
TO74
TO75
P33/RTP3
P32/RTP2
P31/RTP1
P30/RTP0
P01/INTP1
P00/INTP0/TOFF7
V
SS1
X1
X2
TEST
P03/INTP3/ADTRG
P02/INTP2
RESET
AV
DD
AV
REF
P10/ANI0
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P20/RxD00
P21/TxD00
P22/RxD01
P23/TxD01
P24/TI50/TO50
P25/TI51/TO51
P26/TI52/TO52
V
DD1
AV
SS
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P37/RTP7
P36/RTP6
P35/RTP5
P34/RTP4
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
7
PD78F0988
Preliminary Data Sheet U12805EJ1V0DS00
AD0 to AD7:
Address/Data Bus
ADTRG:
AD Trigger Input
ANI0 to ANI7:
Analog Input
ASTB:
Address Strobe
AV
DD
:
Analog Power Supply
AV
REF
:
Analog Reference Voltage
AV
SS
:
Analog Ground
INTP0 to INTP7:
External Interrupt Input
P00 to P03:
Port 0
P10 to P17:
Port 1
P20 to P26:
Port 2
P30 to P37:
Port 3
P40 to P47:
Port 4
P50 to P57:
Port 5
P64 to P67:
Port 6
RD:
Read Strobe
RESET:
Reset
RTP0 to RTP7:
Real-time Port
RxD00, RxD01:
Receive Data
SCK:
Serial Clock
SI:
Serial Input
SO:
Serial Output
TI000, TI001,
TI010, TI011,
TI50 to TI52:
Timer Input
TO00, TO01,
TO50 to TO52,
TO70 to TO75:
Timer Output
TOFF7:
Timer Output Off
TxD00, TxD01:
Transmit Data
V
DD0
, V
DD1
:
Power Supply
V
PP
:
Programming Power Supply
V
SS0
, V
SS1
:
Ground
WAIT:
Wait
WR:
Write Strobe
X1, X2:
Crystal
PD78F0988
8
Preliminary Data Sheet U12805EJ1V0DS00
BLOCK DIAGRAM
8-bit timer/
event counter 50
8-bit timer/
event counter 51
8-bit timer/
event counter 52
Watchdog timer
A/D converter
Interrrupt
control
Real-time
output port
TO50/TI50/P24
ANI0/P10 to
ANI7/P17
AV
DD
AV
SS
AV
REF
INTP1/P01 and
INTP2/P02
78K/0
CPU core
Flash
memory
(60 Kbytes)
RAM
(1024 bytes)
V
DD0
,
V
DD1
V
SS0
,
V
SS1
V
PP
Port 0
Port 1
Port 3
Port 4
Port 5
Port 6
External
access
System
control
P00 to P03
P10 to P17
P30 to P37
Port 2
P20 to P26
P40 to P47
P50 to P57
P64 to P67
AD0/P40 to
AD7/P47
RD/P64
WR/P65
WAIT/P66
ASTB/P67
RESET
X1
X2
TO51/TI51/P25
16-bit timer/
event counter 00
16-bit timer/
event counter 01
TI000/TO00/INTP4/P54
TI010/INTP5/P55
TI011/INTP7/P57
TI001/TO01/INTP6/P56
TO52/TI52/P26
UART00
UART01
RTP0/P30 to
RTP7/P37
TxD00/P21
RxD00/P20
TxD01/P23
RxD01/P22
SIO3
SCK/P51
SI/P52
SO/P53
INTP0/TOFF7/P00
INTP3/ADTRG/P03
INTP5/TI010/P55
INTP6/TI001/TO01/P56
INTP4/TI000/TO00/P54
INTP7/TI011/P57
Real-time
pulse unit
TO70 to TO75
PD78F0988
9
Preliminary Data Sheet U12805EJ1V0DS00
CONTENTS
1. DIFFERENCES BETWEEN
PD78F0988 AND MASK ROM VERSIONS ...................................... 10
2. PIN FUNCTIONS ................................................................................................................................ 11
2.1
Port Pins .................................................................................................................................................... 11
2.2
Non-Port Pins ........................................................................................................................................... 12
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 14
3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................... 16
4. INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS) ............................................. 17
5. FLASH MEMORY PROGRAMMING ................................................................................................. 18
5.1
Selection of Communication Mode ....................................................................................................... 18
5.2
Flash Memory Programming Functions ............................................................................................... 19
5.3
Connection of Flashpro II and Flashpro III .......................................................................................... 19
6. ELECTRICAL SPECIFICATIONS ...................................................................................................... 21
7. PACKAGE DRAWINGS ..................................................................................................................... 36
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................. 38
APPENDIX B. RELATED DOCUMENTS ................................................................................................ 40
PD78F0988
10
Preliminary Data Sheet U12805EJ1V0DS00
1.
DIFFERENCES BETWEEN
PD78F0988 AND MASK ROM VERSIONS
The
PD78F0988 is a product with a flash memory which enables on-board writing, erasing and rewriting of
programs.
Except for flash memory specifications, the same functions as those of mask ROM versions can be obtained by
setting the internal memory size switching register (IMS) and internal expansion RAM size switching register (IXS).
Table 1-1 shows the differences between the flash memory version (
PD78F0988) and mask ROM versions
(
PD780982, 780983, 780984, 780986, 780988).
Table 1-1. Differences between
PD78F0988 and Mask ROM Versions
Item
PD78F0988
Mask ROM Versions
Internal ROM structure
Flash memory
Mask ROM
Internal ROM capacities
60 Kbytes
PD780982: 16 Kbytes
PD780983: 24 Kbytes
PD780984: 32 Kbytes
PD780986: 48 Kbytes
PD780988: 60 Kbytes
Internal expansion RAM capacities
1024 bytes
PD780982: None
PD780983: None
PD780984: None
PD780986: 1024 bytes
PD780988: 1024 bytes
Change of internal ROM capacity with internal
Available
Note 1
Not available
memory size switching register (IMS)
Change of internal expansion RAM capacity with
Available
Note 2
Not available
internal expansion RAM size switching register (IXS)
TEST pin
Not provided
Provided
V
PP
pin
Provided
Not provided
Notes 1. Flash memory capacity becomes 60 Kbytes by RESET input.
2. Internal expansion RAM capacity becomes 0 byte by RESET input.
Caution
There are differences in noise immunity and noise radiation between the flash memory and mask
ROM versions. When pre-producing an application set with the flash memory version and then
mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations for the
commercial samples (not engineering samples) of the mask ROM versions.
PD78F0988
11
Preliminary Data Sheet U12805EJ1V0DS00
2.
PIN FUNCTIONS
2.1
Port Pins
Pin Name
I/O
Function
After Reset
Alternate
Function
P00
I/O
Port 0
Input
INTP0/TOFF7
P01
4-bit I/O port
INTP1
P02
Input/output can be specified in 1-bit units.
INTP2
P03
An on-chip pull-up resistor can be specified by means of
INTP3/ADTRG
software.
P10 to P17
Input
Port 1
Input
ANI0 to ANI7
8-bit input only port
P20
I/O
Port 2
Input
RxD00
P21
7-bit I/O port
TxD00
P22
Input/output can be specified in 1-bit units.
RxD01
P23
An on-chip pull-up resistor can be specified by means of
TxD01
P24
software.
TI50/TO50
P25
TI51/TO51
P26
TI52/TO52
P30 to P37
I/O
Port 3
Input
RTP0 to RTP7
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
P40 to P47
I/O
Port 4
Input
AD0 to AD7
8-bit I/O port
Input/output can be specified in 1-bit units.
An on-chip pull-up resistor can be specified by means of
software.
P50
I/O
Port 5
Input
--
P51
8-bit I/O port
SCK
P52
Input/output can be specified in 1-bit units.
SI
P53
LEDs can be driven directly.
SO
P54
An on-chip pull-up resistor can be specified by means of
INTP4/TI000/TO00
P55
software.
INTP5/TI010
P56
INTP6/TI001/TO01
P57
INTP7/TI011
P64
I/O
Port 6
Input
RD
P65
4-bit I/O port
WR
P66
Input/output can be specified in 1-bit units.
WAIT
P67
An on-chip pull-up resistor can be specified by means of
ASTB
software.
PD78F0988
12
Preliminary Data Sheet U12805EJ1V0DS00
2.2
Non-Port Pins (1/2)
Pin Name
I/O
Function
After Reset
Alternate
Function
INTP0
Input
External interrupt request input for which the valid edge
Input
P00/TOFF7
INTP1
(rising edge, falling edge, or both rising and falling
Input
P01
INTP2
edges) can be specified
Input
P02
INTP3
Input
P03/ADTRG
INTP4
Input
P54/TI000/TO00
INTP5
Input
P55/TI010
INTP6
Input
P56/TI001/TO01
INTP7
Input
P57/TI011
TI50
Input
External count clock input to 8-bit timer (TM50)
Input
P24/TO50
TI51
External count clock input to 8-bit timer (TM51)
Input
P25/TO51
TI52
External count clock input to 8-bit timer (TM52)
Input
P26/TO52
TI000
External count clock input to 16-bit timer (TM00)
Input
P54/INTP4/TO00
Capture trigger input to capture register (CR000, CR010) of
16-bit timer (TM00)
TI010
Capture trigger input to capture register (CR000) of 16-bit
Input
P55/INTP5
timer (TM00)
TI001
External count clock input to 16-bit timer (TM01)
Input
P56/INTP6/TO01
Capture trigger input to capture register (CR001, CR011) of
16-bit timer (TM01)
TI011
Capture trigger input to capture register (CR001) of 16-bit
Input
P57/INTP7
timer (TM01)
TO50
Output
8-bit timer (TM50) output
Input
P24/TI50
TO51
8-bit timer (TM51) output
Input
P25/TI51
TO52
8-bit timer (TM52) output
Input
P26/TI52
TO00
16-bit timer (TM00) output
Input
P54/INTP4/TI000
TO01
16-bit timer (TM01) output
Input
P56/INTP6/TI001
RTP0 to RTP7 Output
Real-time output port that outputs pulses in synchronization
Input
P30 to P37
with trigger signals outputs from the real-time pulse unit
TxD00
Output
Asynchronous serial interface serial data output
Input
P21
TxD01
Input
P23
RxD00
Input
Asynchronous serial interface serial data input
Input
P20
RxD01
Input
P22
SCK
I/O
Serial interface serial clock input/output
Input
P51
SI
Input
Serial interface serial data input
Input
P52
SO
Output
Serial interface serial data output
Input
P53
ANI0 to ANI7 Input
A/D converter analog input
Input
P10 to P17
ADTRG
Input
External trigger signal input to the A/D converter
Input
P03/INTP3
TO70 to TO75 Output
Timer output for the 3-phase PWM inverter control
Hi-Z
TOFF7
Input
Timer output (TO70 to TO75) stop external input
Input
P00/INTP0
AD0 to AD7
I/O
Address/data bus for expanding memory externally
Input
P40 to P47
RD
Output
Strobe signal output for reading from external memory
Input
P64
WR
Strobe signal output for writing to external memory
Input
P65
WAIT
Input
Wait insertion at external memory access
Input
P66
ASTB
Output
Strobe output that externally latches address information
Input
P67
output to ports 4 and 5 to access external memory
AV
REF
Input
A/D converter reference voltage input
AV
DD
A/D converter analog power supply
PD78F0988
13
Preliminary Data Sheet U12805EJ1V0DS00
2.2
Non-Port Pins (2/2)
Pin Name
I/O
Function
After Reset
Alternate
Function
AV
SS
A/D converter ground potential
RESET
Input
System reset input
X1
Input
Connecting crystal resonator for system clock oscillation
X2
V
DD0
Positive power supply for ports
V
SS0
Ground potential for ports
V
DD1
Positive power supply except for ports
V
SS1
Ground potential except for ports
V
PP
High-voltage application during program write/verify.
In the normal operation mode, connect directly to V
SS0
.
PD78F0988
14
Preliminary Data Sheet U12805EJ1V0DS00
2.3
Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
For the input/output circuit configuration of each type, refer to Figure 2-1.
Table 2-1. Types of Pin Input/Output Circuits
Pin Name
Input/Output
I/O
Recommended Connection of Unused Pins
Circuit Type
P00/INTP0/TOFF7
8-C
Input/output
Independently connect to V
SS0
via a resistor.
P01/INTP1
P02/INTP2
P03/INTP3/ADTRG
P10/ANI0 to P17/ANI7
25
Input
Independently connect to V
DD0
or V
SS0
via a resistor.
P20/RxD00
8-C
Input/output
P21/TxD00
5-H
P22/RxD01
8-C
P23/TxD01
5-H
P24/TI50/TO50
8-C
P25/TI51/TO51
P26/TI52/TO52
P30/RTP0 to P37/RTP7
5-H
P40/AD0 to P47/AD7
P50
P51/SCK
8-C
P52/SI
5-H
P53/SO
P54/INTP4/TI000/TO00
P55/INTP5/TI010
P56/INTP6/TI001/TO01
P57/INTP7/TI011
P64/RD
P65/WR
P66/WAIT
P67/ASTB
TO70 to TO75
4
Output
Leave open.
RESET
2
Input
AV
DD
Connect to V
DD0
.
AV
REF
Connect to V
SS0
.
AV
SS
V
PP
Connect directly to V
SS0
.
PD78F0988
15
Preliminary Data Sheet U12805EJ1V0DS00
Figure 2-1. Pin Input/Output Circuits
Type 2
Schmitt-triggered input with hysteresis characteristics
Push-pull output that enables high-impedance output
(both P-ch and N-ch are off)
IN
Type 4
data
output
disable
P-ch
IN/OUT
V
DD0
N-ch
input
enable
P-ch
V
DD0
pullup
enable
Type 5-H
V
SS0
data
output
disable
P-ch
OUT
V
DD0
N-ch
V
SS0
data
output
disable
P-ch
IN/OUT
V
DD0
N-ch
P-ch
V
DD0
pullup
enable
V
SS0
Type 8-C
Type 25
input
enable
Comparator
+
P-ch
N-ch
V
REF
(threshold voltage)
V
SS0
IN
PD78F0988
16
Preliminary Data Sheet U12805EJ1V0DS00
7
6
5
4
3
2
1
0
Address
After reset
R/W
IMS
RAM2 RAM1 RAM0
0
ROM3 ROM2 ROM1 ROM0
FFF0H
CFH
R/W
ROM3 ROM2 ROM1 ROM0
Selection of Internal
ROM Capacity
0
1
0
0
16 Kbytes
0
1
1
0
24 Kbytes
1
0
0
0
32 Kbytes
1
1
0
0
48 Kbytes
1
1
1
1
60 Kbytes
Other than above
Setting prohibited
RAM2 RAM1 RAM0
Selection of Internal
High-Speed RAM Capacity
1
1
0
1024 bytes
Other than above
Setting prohibited
3.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is set by software not to use a part of internal memory. The memory mapping can be made the same
as that of mask ROM versions with different types of internal memory capacity by setting IMS.
IMS is set with an 8-bit memory manipulation instruction.
IMS is set to CFH by RESET input.
Figure 3-1. Format of Internal Memory Size Switching Register
Table 3-1 shows the IMS setting values to make the memory mapping the same as those of mask ROM versions.
Table 3-1. Setting Value of Internal Memory Size Switching Register
Target Mask ROM Versions
IMS Setting Value
PD780982
C4H
PD780983
C6H
PD780984
C8H
PD780986
CCH
PD780988
CFH
PD78F0988
17
Preliminary Data Sheet U12805EJ1V0DS00
7
6
5
4
3
2
1
0
Address
After reset
R/W
0
0
0
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0
FFF4H
0CH
R/W
IXS
IXRAM4 IXRAM3 IXRAM2 IXRAM1 IXRAM0 Selection of Internal
Expansion RAM Capacity
0
1
0
1
0
1024 bytes
0
1
1
0
0
No internal expansion RAM
Other than above
Setting prohibited
4.
INTERNAL EXPANSION RAM SIZE SWITCHING REGISTER (IXS)
This register is used to set internal expansion RAM capacity by software. The memory mapping can be made
the same as that of mask ROM versions with different types of internal expansion RAM capacity by setting IXS.
IXS is set with an 8-bit memory manipulation instruction.
IXS is set to 0CH by RESET input.
Figure 4-1. Format of Internal Expansion RAM Size Switching Register
Table 4-1 shows the IXS setting values to make the memory mapping the same as those of mask ROM versions.
Table 4-1. Setting Value of Internal Expansion RAM Size Switching Register
Target Mask ROM Versions
IXS Setting Value
PD780982
0CH
PD780983
PD780984
PD780986
0AH
PD780988
PD78F0988
18
Preliminary Data Sheet U12805EJ1V0DS00
V
PP
RESET
10 V
V
DD
V
SS
V
DD
V
SS
1 2 n
V
PP
pulses
Flash memory write mode
5.
FLASH MEMORY PROGRAMMING
On-board writing of flash memory (with device mounted on target system) is supported. On-board writing is done
after connecting a dedicated flash programmer (Flashpro II (part number FL-PR2), Flashpro III (part numbers FL-PR3
and PG-FP3)) to the host machine and target system. Moreover, writing to flash memory can also be performed using
a flash memory writing adapter connected to Flashpro II or Flashpro III.
Remark
FL-PR2 and FL-PR3 are products of NAITO DENSEI MACHIDA MFG. CO., LTD.
5.1
Selection of Communication Mode
Writing to flash memory is performed using Flashpro II and III with a serial communication mode. Select the
communication mode for writing from Table 5-1. For the selection of the communication mode, a format like the one
shown in Figure 5-1 is used. The communication modes are selected using the V
PP
pulse numbers shown in Table
5-1.
Table 5-1. Communication Mode List
Communication Mode
Number of
Pin Used
Number of
Channels
V
PP
Pulses
3-wire serial I/O
1
SCK/P51
0
SI/P52
SO/P53
UART
1
RxD00/P20
8
TxD00/P21
Pseudo 3-wire serial I/O
1
P24/TI50/TO50 (Serial data input)
12
mode
Note
P25/TI51/TO51 (Serial data output)
P26/TI52/TO52 (Serial clock input)
Note
Serial transfer is performed by controlling ports with software.
Caution
Always select the communication mode according to the number of V
PP
pulses shown in Table 5-
1.
Figure 5-1. Communication Mode Selection Format
PD78F0988
19
Preliminary Data Sheet U12805EJ1V0DS00
Note
For input to X1, not CLK but a normal oscillator can also be used.
5.2
Flash Memory Programming Functions
Flash memory writing is performed through command and data transmit/receive operations using the selected
communication mode. The main functions are listed in Table 5-2.
Table 5-2. Main Functions of Flash Memory Programming
Function
Description
Batch erase
Erases the contents of the entire memory.
Batch blank check
Checks that the entire memory has been deleted.
Data write
Performs writing to flash memory according to the write start address and the
number of the data to be written (the number of bytes).
Batch verify
Compares the contents of the entire memory and the input data.
5.3
Connection of Flashpro II and Flashpro III
The connection of the Flashpro II, Flashpro III and the
PD78F0988 differs depending on the communication mode.
Each type of connection is shown in Figures 5-2, 5-3, and 5-4, respectively.
Figure 5-2. Connection of Flashpro II and Flashpro III Using 3-Wire Serial I/O Mode
V
PP
V
CLK
DD
RESET
Flashpro II, III
SCK
SCK
SO
SI
GND
V
PP
V
V
SS0
X1
V
V
DD0
Note
DD1
RESET
SI
SO
SS1
PD78F0988
PD78F0988
20
Preliminary Data Sheet U12805EJ1V0DS00
Figure 5-3. Connection of Flashpro II and Flashpro III Using UART Mode
Note
For input to X1, not CLK but a normal oscillator can also be used.
Figure 5-4. Connection of Flashpro II and Flashpro III Using Pseudo 3-Wire Serial I/O Mode
Note
For input to X1, not CLK but a normal oscillator can also be used.
V
V
PP
CLK
DD
RESET
SO
SI
V
SS
V
PP
V
X1
DD0
Note
V
DD1
V
SS1
V
SS0
RESET
RxD00
TxD00
PD78F0988
Flashpro II, III
(Serial data output)
V
V
CLK
PP
RESET
DD
SCK
SO
SI
V
SS
V
PP
V
X1
DD0
Note
V
DD1
P25
V
SS1
V
SS0
RESET
PD78F0988
Flashpro II, III
(Serial clock input)
(Serial data input)
P24
P26
PD78F0988
21
Preliminary Data Sheet U12805EJ1V0DS00
6.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25
C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
0.3 to +6.5
V
V
PP
0.3 to +10.5
V
AV
DD
0.3 to V
DD
+ 0.3
V
AV
REF
0.3 to V
DD
+ 0.3
V
AV
SS
0.3 to +0.3
V
Input voltage
V
I
P00 to P03, P10 to P17, P20 to P26, P30 to P37, P50
0.3 to V
DD
+ 0.3
V
to P57, P64 to P67, TO70 to TO75, X1, X2, RESET
Output voltage
V
O
0.3 to V
DD
+ 0.3
V
Analog input voltage
V
AN
P10 to P17 Analog input pin
AV
SS
0.3 to AV
REF
+ 0.3
V
and 0.3 to V
DD
+ 0.3
Output current, high
I
OH
Per pin
10
mA
P00, P01, P30 to P37, P40 to P47, P50 to P57, P64 to P67 total
15
mA
P02, P03, P20 to P26, TO70 to TO75 total
15
mA
Output current, low
I
OL
Note
P00 to P03, P10 to P17, P20 to P26,
Peak value
20
mA
P30 to P37, P40 to P47, P64 to P67 per pin
rms value
10
mA
P50 to P57, TO70 to TO75 per pin
Peak value
30
mA
rms value
15
mA
P00, P01, P30 to P37, P40 to P47, P64 to P67
Peak value
50
mA
total
rms value
20
mA
P02, P03, P20 to P26 total
Peak value
30
mA
rms value
15
mA
TO70 to TO75 total
Peak value
100
mA
rms value
70
mA
P50 to P57 total
Peak value
100
mA
rms value
70
mA
Operating ambient
T
A
40 to +85
C
temperature
Storage temperature
T
stg
40 to +125
C
Note
The rms value should be calculated as follows: [rms value] = [Peak value]
Duty
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
Capacitance (T
A
= 25
C, V
DD
= V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
IN
f = 1 MHz Unmeasured pins returned to 0 V
15
pF
I/O capacitance
C
IO
f = 1 MHz
P00 to P03, P20 to P26, P30
15
pF
Unmeasured pins to P37, P40 to P47, P50 to
returned to 0 V
P57, P64 to P67, TO70 to TO75
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
PD78F0988
22
Preliminary Data Sheet U12805EJ1V0DS00
System Clock Oscillator Characteristics (T
A
= 40 to +85
C, V
DD
= 4.0 to 5.5 V)
Resonator
Recommended
Parameter
Conditions
MIN.
TYP.
MAX.
Unit
Circuit
Ceramic
Oscillation
1.0
8.38
MHz
resonator
frequency (f
X
)
Note 1
Oscillation
After V
DD
reaches
4
ms
stabilization
oscillation
time
Note 2
voltage range MIN.
Crystal
Oscillation
1.0
8.38
MHz
resonator
frequency (f
X
)
Note 1
Oscillation
After V
DD
reaches
10
ms
stabilization
oscillation
time
Note 2
voltage range MIN.
External clock
X1 input frequency
1.0
8.38
MHz
(f
X
)
Note 1
X1 input high-/low-
50
500
ns
level width (t
XH
, t
XL
)
Notes
1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time.
2. Time required to stabilize oscillation after reset or STOP mode release.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines.
Do not route the wiring near a signal line through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS1
.
Do not ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
C2
X1
X2
V
PP
C1
X2
X1
PD74HCU04
C2
X1
X2
V
PP
C1
PD78F0988
23
Preliminary Data Sheet U12805EJ1V0DS00
Recommended Oscillator Constant
System clock: Ceramic resonator (T
A
= 40 to +85
C)
Manufacturer
Part Number
Frequency
Recommended Circuit Constant
Oscillation Voltage Range
(MHz)
C1 (pF)
C2 (pF)
MIN. (V)
MAX. (V)
Murata Mfg.
CSA2.00MG040
2.00
100
100
4.0
5.5
Co., Ltd.
CST2.00MG040
2.00
On-chip
On-chip
4.0
5.5
CSA3.58MG
3.58
30
30
4.0
5.5
CST3.58MGW
3.58
On-chip
On-chip
4.0
5.5
CSA4.00MG
4.00
30
30
4.0
5.5
CST4.00MGW
4.00
On-chip
On-chip
4.0
5.5
CSA4.19MG
4.19
30
30
4.0
5.5
CST4.19MGW
4.19
On-chip
On-chip
4.0
5.5
CSA4.91MG
4.91
30
30
4.0
5.5
CST4.91MGW
4.91
On-chip
On-chip
4.0
5.5
CSA5.00MG
5.00
30
30
4.0
5.5
CST5.00MGW
5.00
On-chip
On-chip
4.0
5.5
CSA7.37MTZ
7.37
30
30
4.0
5.5
CST7.37MTW
7.37
On-chip
On-chip
4.0
5.5
CSA8.00MTZ
8.00
30
30
4.0
5.5
CST8.00MTW
8.00
On-chip
On-chip
4.0
5.5
CSA8.38MTZ
8.38
30
30
4.0
5.5
CST8.38MTW
8.38
On-chip
On-chip
4.0
5.5
CSA10.0MTZ
10.0
30
30
4.0
5.5
CST10.0MTW
10.0
On-chip
On-chip
4.0
5.5
Caution
The oscillator constant and oscillation voltage range indicate conditions of stable oscillation.
Oscillation frequency precision is not guaranteed. For applications requiring oscillation frequency
precision, the oscillation frequency must be adjusted on the implementation circuit. For details,
please contact directly the manufacturer of the resonator you will use.
PD78F0988
24
Preliminary Data Sheet U12805EJ1V0DS00
DC Characteristics (T
A
= 40 to +85
C, V
DD
= 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage,
V
IH1
P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53,
0.7V
DD
V
DD
V
high
P64 to P67
V
IH2
RESET, P00 to P03, P20, P22, P24 to P26, P51, P52,
0.8V
DD
V
DD
V
P54 to P57
V
IH3
X1, X2
V
DD
0.5
V
DD
V
Input voltage, low
V
IL1
P10 to P17, P21, P23, P30 to P37, P40 to P47, P50, P53,
0
0.3V
DD
V
P64 to P67
V
IL2
RESET, P00 to P03, P20, P22, P24 to P26, P51, P52,
0
0.2V
DD
V
P54 to P57
V
IL3
X1, X2
0
0.4
V
Output voltage,
V
OH1
4.5 V
V
DD
5.5 V, I
OH
= 1 mA
V
DD
1.0
V
DD
V
high
I
OH
= 100
A
V
DD
0.5
V
DD
V
Output voltage,
V
OL1
P50 to P57, TO70 to TO75
5.0 V
V
DD
5.5 V,
0.4
2.0
V
low
I
OL
= 15 mA
P00 to P03, P20 to P26,
5.0 V
V
DD
5.5 V,
0.4
V
P30 to P37, P40 to P47,
I
OL
= 1.6 mA
P64 to P67
V
OL2
I
OL
= 400
A
0.5
V
Input leakage
I
LIH1
V
IN
= V
DD
P00 to P03, P10 to P17,
3
A
current, high
P20 to P26, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67,
TO70 to TO75, RESET
I
LIH2
X1, X2
20
A
Input leakage
I
LIL1
V
IN
= 0 V
P00 to P03, P10 to P17,
3
A
current, low
P20 to P26, P30 to P37,
P40 to P47, P50 to P57,
P64 to P67,
TO70 to TO75, RESET
I
LIL2
X1, X2
20
A
Output leakage
I
LOH
V
OUT
= V
DD
3
A
current, high
Output leakage
I
LOL
V
OUT
= 0 V
3
A
current, low
Software pull-up
R
2
V
IN
= 0 V
15
30
90
k
resistor
P00 to P03, P20 to P26, P30 to P37, P40 to P47, P50 to
P57, P64 to P67
Power supply
I
DD1
8.38-MHz crystal
V
DD
= 5.0 V
10%
Note 2
When A/D
15
30
mA
current
Note 1
oscillation
converter
operating mode
stopped
When A/D
16
32
mA
converter
operating
I
DD2
8.38-MHz crystal
V
DD
= 5.0 V
10%
Note 2
When peripheral
1.3
2.6
mA
oscillation HALT
function
mode
stopped
When peripheral
7.3
mA
function operating
I
DD3
STOP mode
V
DD
= 5.0 V
10%
0.1
30
A
Notes
1. Refers to the total current flowing to the internal power supply (V
DD0
and V
DD1
). The peripheral operation
current is included however, the current flowing to the pull-up resistor of ports and AV
REF
pin is not included.
2. High-speed mode operation (when processor clock control register (PCC) is set to 00H).
Remark
Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
PD78F0988
25
Preliminary Data Sheet U12805EJ1V0DS00
AC Characteristics
(1) Basic operation (T
A
= 40 to +85
C, V
DD
= 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Cycle time
T
CY
Operating with system clock
0.24
32
s
(Min. instruction
execution time)
TI000, TI001,
f
TI0
0
f
X
/64
MHz
TI010, TI011
input frequency
TI000, TI001,
t
TIH0
2/f
sam
+
s
TI010, TI011
t
TIL0
0.1
Note
input high-/
low-level width
TI50, TI51, TI52
f
TI5
8-/16-bit precision
0
4
MHz
input frequency
TI50, TI51, TI52
t
TIH5
8-/16-bit precision
100
ns
input high-/
t
TIL5
low-level width
Interrupt request
t
INTH
INTP0 to INTP7
1
s
input high-/
t
INTL
low-level width
TOFF input
t
TOFFH
2
s
high-/low-level
t
TOFFL
width
RESET input
t
RSL
10
s
low-level width
Note
Selection of f
sam
= f
X
, f
X
/4, f
X
/32 is possible with bits 0 and 1 (PRM000, PRM001) of prescaler mode register
00 (PRM00) or with bits 0 and 1 (PRM010, PRM011) of prescaler mode register 01 (PRM01). Note that when
selecting TI000 (TM00) or TI001 (TM01) valid edge as the count clock, f
sam
= f
X
/16.
PD78F0988
26
Preliminary Data Sheet U12805EJ1V0DS00
T
CY
VS
V
DD
(System clock operation)
5.0
1.0
2.0
0.24
0.1
Supply voltage V
DD
[V]
Cycle time T
CY
[ s]
0
10.0
1.0
2.0
3.0
4.0
5.0
6.0
5.5
32.0
10.0
Guaranteed
operation
range
PD78F0988
27
Preliminary Data Sheet U12805EJ1V0DS00
(2) Read/write operation (T
A
= 40 to +85
C, V
DD
= 4.0 to 5.5 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.3t
CY
ns
Address setup time
t
ADS
20
ns
Address hold time
t
ADH
6
ns
Data input time from address
t
ADD1
(2 + 2n)t
CY
54
ns
t
ADD2
(3 + 2n)t
CY
60
ns
Address output time from RD
t
RDAD
0
100
ns
Data input time from RD
t
RDD1
(2 + 2n)t
CY
87
ns
t
RDD2
(3 + 2n)t
CY
93
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.5 + 2n)t
CY
33
ns
t
RDL2
(2.5 + 2n)t
CY
33
ns
WAIT
input time from RD
t
RDWT1
t
CY
43
ns
t
RDWT2
t
CY
43
ns
WAIT
input time from WR
t
WRWT
0.5t
CY
25
ns
WAIT low-level width
t
WTL
(0.5 + 2n)t
CY
+ 10
(2 + 2n)t
CY
ns
Write data setup time
t
WDS
60
ns
Write data hold time
t
WDH
6
ns
WR low-level width
t
WRL
(1.5 + 2n)t
CY
15
ns
RD
delay time from ASTB
t
ASTRD
6
ns
WR
delay time from ASTB
t
ASTWR
2t
CY
15
ns
ASTB
delay time from RD
at external fetch
t
RDAST
0.8t
CY
15
1.2t
CY
ns
Write data output time from RD
t
RDWD
40
ns
Write data output time from WR
t
WRWD
10
60
ns
RD
delay time from WAIT
t
WTRD
0.8t
CY
2.5t
CY
+ 25
ns
WR
delay time from WAIT
t
WTWR
0.8t
CY
2.5t
CY
+ 25
ns
Remarks
1. t
CY
= T
CY
/4
2. n indicates the number of waits.
3. C
L
= 100 pF (C
L
is the load capacitance of AD0 to AD7, RD, WR, WAIT, and ASTB pins.)
PD78F0988
28
Preliminary Data Sheet U12805EJ1V0DS00
(3) Serial interface (T
A
= 40 to +85
C, V
DD
= 4.0 to 5.5 V)
(a) 3-wire serial I/O mode (SCK... Internal clock output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY1
954
ns
SCK high-/low-level width
t
KH1
t
KCY1
/2 50
ns
t
KL1
SI setup time (to SCK
)
t
SIK1
100
ns
SI hold time (from SCK
)
t
KSI1
400
ns
SO output delay time
t
KSO1
C = 100 pF
Note
300
ns
from SCK
Note
C is the load capacitance of the SCK and SO output lines.
(b) 3-wire serial I/O mode (SCK... External clock input)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
SCK cycle time
t
KCY2
800
ns
SCK high-/low-level width
t
KH2
400
ns
t
KL2
SI setup time (to SCK
)
t
SIK2
100
ns
SI hold time (from SCK
)
t
KSI2
400
ns
SO output delay time
t
KSO2
C = 100 pF
Note
300
ns
from SCK
Note
C is the load capacitance of the SCK and SO output lines.
(c) UART mode (UART00) (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
125000
bps
(d) UART mode (UART00) (Infrared data transfer mode)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
115200
bps
Bit rate allowable error
0.87
%
Output pulse width
1.2
0.24/fbr
Note
s
Input pulse width
4/f
X
s
Note
fbr: Set baud rate
(e) UART mode (UART01) (Dedicated baud rate generator output)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Transfer rate
38400
bps
PD78F0988
29
Preliminary Data Sheet U12805EJ1V0DS00
AC Timing Test Points (excluding X1 input)
Clock Timing
TI Timing
TOFF Timing
X1 input
V
IH3
(MIN.)
V
IL3
(MAX.)
1/f
X
t
XL
t
XH
TI000, TI001,
TI010, TI011
TI50, TI51, TI52
1/f
TI5
t
TIL5
t
TIH5
1/f
TI0
t
TIL0
t
TIH0
TOFF7
t
TOFFL
t
TOFFH
0.8V
DD
0.2V
DD
Test points
0.8V
DD
0.2V
DD
PD78F0988
30
Preliminary Data Sheet U12805EJ1V0DS00
Read/Write Operation
External fetch (no wait):
External fetch (wait insertion):
AD0 to AD7
ASTB
RD
8-bit address
t
ADD1
Hi-Z
t
ADS
t
ASTH
t
ADH
t
RDD1
t
RDAD
Operation code
t
RDAST
t
ASTRD
t
RDL1
t
RDH
AD0 to AD7
ASTB
RD
8-bit address
t
ADD1
Hi-Z
t
ADS
t
ASTH
t
ADH
t
RDAD
t
RDD1
Operation code
t
RDAST
t
ASTRD
t
RDL1
t
RDH
WAIT
t
RDWT1
t
WTL
t
WTRD
PD78F0988
31
Preliminary Data Sheet U12805EJ1V0DS00
External data access (no wait):
External data access (wait insertion):
Read data
AD0 to AD7
ASTB
RD
WR
Hi-Z
Hi-Z
8-bit address
Write data
t
ADD2
t
ADS
t
ASTH
t
ADH
t
RDAD
t
RDD2
t
RDH
t
ASTRD
t
RDL2
t
WDS
t
WDH
t
WRL
t
ASTWR
t
RDWD
t
WRWD
Read data
Hi-Z
Hi-Z
8-bit
address
Write data
t
ADD2
t
ADS
t
ASTH
t
ADH
t
RDAD
t
RDD2
t
RDH
t
ASTRD
t
RDL2
t
WDS
t
WDH
t
WRL
t
WTL
t
WTL
t
ASTWR
t
RDWD
t
RDWT2
t
WRWD
t
WRWT
t
WTWR
t
WTRD
AD0 to AD7
ASTB
RD
WR
WAIT
PD78F0988
32
Preliminary Data Sheet U12805EJ1V0DS00
Serial Transfer Timing
3-wire serial I/O mode:
m = 1, 2
SI
SO
t
KCYm
t
KLm
t
KHm
t
SIKm
t
KSIm
Input data
t
KSOm
Output data
SCK
PD78F0988
33
Preliminary Data Sheet U12805EJ1V0DS00
A/D Converter Characteristics (T
A
= 40 to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
10
10
bit
Overall error
Note
4.0 V
AV
REF
5.5 V
0.2
0.4
%FSR
2.7 V
AV
REF
<
4.0 V
0.3
0.6
%FSR
Conversion time
t
CONV
4.0 V
AV
REF
5.5 V
14
96
s
2.7 V
AV
REF
<
4.0 V
19
96
s
Zero-scale offset
Note
4.0 V
AV
REF
5.5 V
0.4
%FSR
2.7 V
AV
REF
<
4.0 V
0.6
%FSR
Full-scale offset
Note
4.0 V
AV
REF
5.5 V
0.4
%FSR
2.7 V
AV
REF
<
4.0 V
0.6
%FSR
Non-linearity error
4.0 V
AV
REF
5.5 V
2.5
LSB
2.7 V
AV
REF
<
4.0 V
4.5
LSB
Differential non-linearity error
4.0 V
AV
REF
5.5 V
1.5
LSB
2.7 V
AV
REF
<
4.0 V
2.0
LSB
Analog input voltage
V
IAN
0
AV
REF
V
Reference voltage
AV
REF
2.7
AV
DD
V
Resistance between AV
REF
R
REF
When A/D converter is not operating
20
40
k
and AV
SS
Note
Excludes quantization error (
1/2 LSB). It is indicated as a ratio to the full-scale value.
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
A
= 40 to +85
C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Data retention power
V
DDDR
2.0
5.5
V
supply voltage
Data retention
I
DDDR
V
DDDR
= 2.0 V
0.1
10
A
power supply current
Release signal set time
t
SREL
0
s
Oscillation stabilization
t
WAIT
Release by RESET
2
17
/f
X
ms
wait time
Release by interrupt request
Note
ms
Note
Selection of 2
12
/f
X
and 2
14
/f
X
to 2
17
/f
X
is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization
time select register (OSTS).
PD78F0988
34
Preliminary Data Sheet U12805EJ1V0DS00
Data Retention Timing (STOP mode release by RESET)
Data Retention Timing (Standby release signal: STOP mode release by interrupt request signal)
INTP0 to INTP7
t
INTL
t
INTH
RESET
t
RSL
V
DD
STOP instruction execution
RESET
STOP mode
Data retention mode
V
DDDR
Internal reset operation
HALT mode
Operation
mode
t
WAIT
t
SREL
Interrupt Request Input Timing
RESET Input Timing
V
DD
STOP instruction execution
Standby release signal
(interrupt request)
STOP mode
Data retention mode
V
DDDR
HALT mode
Operation
mode
t
SREL
t
WAIT
PD78F0988
35
Preliminary Data Sheet U12805EJ1V0DS00
Flash Memory Programming Characteristics (V
DD
= 4.0 to 5.5 V, V
SS
= 0 V, V
PP
= 9.7 to 10.3 V)
(1) Basic characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Operation frequency
f
X
1.0
8.38
MHz
Supply voltage
V
DD
4.0
5.5
V
V
PPL
When V
PP
low-level is detected
0
0.2V
DD
V
V
PP
When V
PP
high-level is detected
0.8V
DD
V
DD
1.2V
DD
V
V
PPH
When V
PP
high-voltage is detected
9.0
10.0
10.5
V
When programming
9.7
10.0
10.3
V
V
PP
power supply current
I
PP
V
PP
= 10.0 V
50
100
mA
Write time (per 1 byte)
T
WRT
50
500
s
Number of rewrites
C
WRT
20
Times
Erase time
T
ERASE
1
20
s
Programming temperature
T
PRG
10
40
C
(2) Serial write operation characteristics
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
PP
set time from V
DD
t
DRPSR
V
PP
high voltage
0
s
RESET
set time from V
PP
t
PSRRF
V
PP
high voltage
1.0
s
V
PP
count start time from RESET
t
RFCF
V
PP
high voltage
1.0
s
Count execution time
t
COUNT
20
ms
V
PP
counter high-level width
t
CH
8.0
s
V
PP
counter low-level width
t
CL
8.0
s
V
PP
counter noise elimination width
t
NFW
40
ns
Flash Write Mode Setting Timing
V
DD
V
DD
0 V
V
DD
RESET (input)
0 V
V
PPH
V
PPL
V
PP
V
PP
t
RFCF
t
PSRRF
t
DRPSR
t
CH
t
CL
t
COUNT
PD78F0988
36
Preliminary Data Sheet U12805EJ1V0DS00
7.
PACKAGE DRAWINGS
I
J
G
H
F
D
N
M
C
B
M
R
64
33
32
1
K
L
NOTES
1. Controlling dimension millimeter.
P64C-70-750A,C-3
ITEM
MILLIMETERS
INCHES
B
C
D
F
G
H
J
K
1.778 (T.P.)
3.2
0.3
0.51 MIN.
1.78 MAX.
L
M
0.17
0.25
19.05 (T.P.)
5.08 MAX.
17.0
0.2
N
0 to 15
0.50
0.10
0.9 MIN.
R
0.070 MAX.
0.020
0.035 MIN.
0.126
0.012
0.020 MIN.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0 to 15
+0.004
0.003
0.070 (T.P.)
+0.10
0.05
+0.004
0.005
64 PIN PLASTIC SHRINK DIP (750 mil)
2. Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
3. Item "K" to center of leads when formed parallel.
A
58.0
2.283
+0.028
0.008
+0.68
0.20
I
4.05
0.159
+0.011
0.008
+0.26
0.20
A
+0.009
0.008
PD78F0988
37
Preliminary Data Sheet U12805EJ1V0DS00
64 PIN PLASTIC QFP ( 14)
ITEM
MILLIMETERS
INCHES
I
J
0.8 (T.P.)
0.15
0.006
0.031 (T.P.)
A
17.6
0.4
0.693
0.016
B
14.0
0.2
0.551+0.009
0.008
C
14.0
0.2
0.551+0.009
0.008
D
17.6
0.4
0.693
0.016
F
G
1.0
1.0
0.039
0.039
H
0.37
0.015
P64GC-80-AB8-4
L
0.8
0.2
0.031+0.009
0.008
M
0.17
0.007
N
0.10
0.004
+0.08
0.07
+0.08
0.07
Q
0.1
0.1
0.004
0.004
R
S
2.85 MAX.
5
5
5
5
0.113 MAX.
+0.003
0.004
NOTE
1. Controlling dimension millimeter.
2. Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
M
Q
R
K
M
L
P
G
F
H
I
S
detail of lead end
K
1.8
0.2
0.071
0.008
P
2.55
0.1
0.100
0.004
+0.003
0.004
48
49
32
64
1
17
16
33
S
A
B
C D
J
N
S
PD78F0988
38
Preliminary Data Sheet U12805EJ1V0DS00
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the
PD780988 Subseries.
Also refer to (5) Cautions on Using Development Tools.
(1) Language Processing Software
RA78K/0
Assembler package common to 78K/0 Series
CC78K/0
C compiler package common to 78K/0 Series
DF780988
Device file for
PD780988 Subseries
CC78K/0-L
C compiler library source file common to 78K/0 Series
(2) Flash Memory Writing Tools
Flashpro II (part No. FL-PR2),
Flash programmer dedicated to on-chip flash memory microcontroller
Flashpro III (part No. FL-PR3,
PG-FP3)
FA-64CW
Adapter for flash memory writing
FA-64GC
(3) Debugging Tools
When IE-78K0-NS in-circuit emulator is used
IE-78K0-NS
In-circuit emulator common to 78K/0 Series
IE-70000-MC-PS-B
Power supply unit for IE-78K0-NS
IE-78K0-NS-PA
Note
Performance board for enhancement and expansion of IE-78K0-NS function
IE-70000-98-IF-C
Interface adapter when PC-9800 series PC (except notebook type) is used as
host machine (C bus supported)
IE-70000-CD-IF-A
PC card and interface cable when notebook PC is used as host machine
(PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT
TM
or compatible as host machine
(ISA bus supported)
IE-70000-PCI-IF
Adapter necessary when using PCI bus incorporated personal computer as host machine
IE-780988-NS-EM4
Emulation board to emulate
PD780988 Subseries
IE-78K0-NS-P01
I/O board necessary to emulate
PD780988 Subseries
NP-64CW
Emulation probe for 64-pin plastic shrink DIP (CW type)
NP-64GC
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
NP-64GC-TQ
EV-9200GC-64
Conversion socket to connect the NP-64GC and a target system board on which
the 64-pin plastic QFP (GC-AB8 type) can be mounted
TGC-064SAP
Conversion adapter to connect the NP-64GC-TQ and a target system board on which
the 64-pin plastic QFP (GC-AB8 type) can be mounted
ID78K0-NS
Integrated debugger for IE-78K0-NS
SM78K0
System simulator common to 78K/0 Series
DF780988
Device file for
PD780988 Subseries
Note
Under development
PD78F0988
39
Preliminary Data Sheet U12805EJ1V0DS00
When IE-78001-R-A in-circuit emulator is used
IE-78001-R-A
In-circuit emulator common to 78K/0 Series
IE-70000-98-IF-C
Interface adapter when PC-9800 series PC (except notebook type) is used as
host machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter when using IBM PC/AT or compatible as host machine
(ISA bus supported)
IE-70000-PCI-IF
Adapter necessary when using PCI bus incorporated personal computer as host machine
IE-78000-R-SV3
Interface adapter and cable when using EWS as host machine
IE-780988-NS-EM4
Emulation board to emulate
PD780988 Subseries
IE-78K0-NS-P01
I/O board necessary to emulate
PD780988 Subseries
IE-78K0-R-EX1
Emulation probe conversion board necessary when using IE-780988-NS-EM4
and IE-78K0-NS-P01 on IE-78001-R-A
EP-78240CW-R
Emulation probe for 64-pin plastic shrink DIP (CW type)
EP-78240GC-R
Emulation probe for 64-pin plastic QFP (GC-AB8 type)
EV-9200GC-64
Socket to be mounted on a target system board made for 64-pin plastic QFP (GC-AB8 type)
ID78K0
Integrated debugger for IE-78001-R-A
SM78K0
System simulator common to 78K/0 Series
DF780988
Device file for
PD780988 Subseries
(4) Real-time OS
RX78K/0
Real-time OS for 78K/0 Series
MX78K0
OS for 78K/0 Series
(5) Cautions on Using Development Tools
The ID78K0-NS, ID78K0, and SM78K0 are used in combination with the DF780988.
The CC78K/0 and RX78K/0 are used in combination with the RA78K/0 or DF780988.
The FL-PR2, FL-PR3, FA-64CW, FA-64GC, NP-64CW, NP-64GC, and NP-64GC-TQ are products made by
NAITO DENSEI MACHIDA MFG. CO., LTD. (TEL +81-44-822-3813). Contact an NEC distributor regarding
the purchase of these products.
The TGC-064SAP is a product made by TOKYO ELETECH CORPORATION.
For further information, contact: Daimaru Kogyo, Ltd.
Tokyo Electronics Department (TEL +81-3-3820-7112)
Osaka Electronics Department (TEL +81-6-6244-6672)
For third-party development tools, see the 78K/0 Series Selection Guide (U11126E).
The host machine and OS suitable for each software are as follows.
Host Machine
PC
EWS
[OS]
PC-9800 series [Windows
TM
]
HP9000 series 700
TM
[HP-UX
TM
]
IBM PC/AT and compatibles
SPARCstation
TM
[SunOS
TM
, Solaris
TM
]
Software
[Japanese/English Windows]
NEWS
TM
(RISC) [NEWS-OS
TM
]
RA78K/0
Note
CC78K/0
Note
ID78K0-NS
ID78K0
SM78K0
RX78K/0
Note
MX78K0
Note
Note
DOS-based software
PD78F0988
40
Preliminary Data Sheet U12805EJ1V0DS00
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name
Document No.
English
Japanese
PD780988 Subseries User's Manual
U13029E
U13029J
PD780982, 780983, 780984, 780986, 780988 Data Sheet
U12804E
U12804J
PD78F0988 Data Sheet
This manual
U12805J
PD780988 Subseries Inverter Control Application Note
U13119E
U13119J
PD780988 Subseries Special Function Register Table
U12806J
78K/0 Series Instructions User's Manual
U12326E
U12326J
78K/0 Series Instruction Table
U10903J
78K/0 Series Instruction Set
U10904J
Documents Related to Development Tools (User's Manuals)
Document Name
Document No.
English
Japanese
RA78K0 Assembler Package
Operation
U11802E
U11802J
Assembly Language
U11801E
U11801J
Structured Assembly Language
U11789E
U11789J
RA78K Series Structured Assembler Preprocessor
EEU-1402
U12323J
CC78K0 C Compiler
Operation
U11517E
U11517J
Language
U11518E
U11518J
CC78K0 C Compiler Application Note
Programming Know-How
U13034E
U13034J
IE-78K0-NS
To be prepared
To be prepared
IE-78001-R-A
To be prepared
To be prepared
IE-780988-NS-EM4
To be prepared
To be prepared
EP-78240
U10332E
EEU-986
SM78K0 System Simulator Windows Based Reference
U10181E
U10181J
SM78K Series System Simulator
External Part User Open
U10092E
U10092J
Interface Specifications
ID78K0-NS Integrated Debugger Windows Based
Reference
U12900E
U12900J
ID78K0 Integrated Debugger EWS Based
Reference
U11151J
ID78K0 Integrated Debugger PC Based
Reference
U11539E
U11539J
ID78K0 Integrated Debugger Windows Based
Guide
U11649E
U11649J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
PD78F0988
41
Preliminary Data Sheet U12805EJ1V0DS00
Documents Related to Embedded Software (User's Manuals)
Document Name
Document No.
English
Japanese
78K/0 Series Real-Time OS
Fundamental
U11537E
U11537J
Installation
U11536E
U11536J
78K/0 Series OS MX78K0
Fundamental
U12257E
U12257J
Other Related Documents
Document Name
Document No.
English
Japanese
SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535E
C10535J
Quality Grades on NEC Semiconductor Devices
C11531E
C11531J
NEC Semiconductor Device Reliability/Quality Control System
C10983E
C10983J
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) C11892E
C11892J
Guide to Microcomputer-Related Products by Third Party
U11416J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
PD78F0988
42
Preliminary Data Sheet U12805EJ1V0DS00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Produc-
tion process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD78F0988
43
Preliminary Data Sheet U12805EJ1V0DS00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
PD78F0988
The information contained in this document is being issued in advance of the production cycle for the
device. The parameters for the device may change before final production or NEC Corporation, at its own
discretion, may withdraw the device prior to its production.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M5 98. 8
FIP and IEBus are trademarks of NEC Corporation.
Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/
or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
PDF 
ZIP