Document Outline
- COVER
- DESCRIPTION
- FEATURES
- APPLICATIONS
- ORDERING INFORMATION
- 78K/IV SERIES LINEUP
- OVERVIEW OF FUNCTIONS
- 1. DIFFERENCES AMONG uPD784046 SUBSERIES
- 2. PIN CONFIGURATION (TOP VIEW)
- 3. SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL)
- 4. BLOCK DIAGRAM
- 5. PIN FUNCTIONS
- 5.1 Port Pins
- 5.2 Non-Port Pins
- 5.3 Pin I/O Circuits and Recommended Connection of Unused Pins
- 6. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
- 7. FLASH MEMORY PROGRAMMING
- 7.1 Selecting Communication Mode
- 7.2 Function of Flash Memory Programming
- 7.3 Connection of Flashpro II and Flashpro III
- 7.4 Cautions When Writing to Flash Memory
- 8. ELECTRICAL SPECIFICATIONS
- 9. PACKAGE DRAWING
- 10. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A. DEVELOPMENT TOOLS
- APPENDIX B. RELATED DOCUMENTS
1996, 2000
DATA SHEET
MOS INTEGRATED CIRCUIT
PD78F4046
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
PD78F4046 is a product of the
PD784046 Subseries in the 78K/IV Series.
The
PD78F4046 has flash memory in place of the internal ROM of the
PD784046. The incorporation of flash
memory allows a program to be written or erased while mounted on the target board.
Detailed function descriptions are provided in the following user's manuals. Be sure to read them before
designing.
PD784046 Subseries User's Manual Hardware: U11515E
78K/IV Series User's Manual Instruction:
U10905E
FEATURES
78K/IV Series
Pin compatible with
PD784044, 784046 (except V
PP
pin)
Flash memory:
64 KB
Internal RAM:
2048 bytes
Operable with the same supply voltage as that of the mask ROM version: V
DD
= 4.5 to 5.5 V
APPLICATIONS
Water heaters, vending machines, etc.
FA fields such as robots, automated machine tools, etc.
ORDERING INFORMATION
Part Number
Package
PD78F4046GC-3B9
80-pin plastic QFP (14
14 mm)
The mark shows major revised points.
Document No. U11447EJ2V0DS00 (2nd edition)
Date Published August 2000 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
PD78F4046
2
Data Sheet U11447EJ2V0DS00
78K/IV SERIES LINEUP
ASSP models
Standard models
Enhanced A/D, 16-bit timer,
power management
PD784026
PD784038Y
PD784054
PD784046
PD784038
PD784216/
PD784225Y
PD784218Y/
PD784956A
PD784938A
PD784908
PD784976A
PD784915
PD784928Y
I
2
C bus supported
Multimaster I
2
C
bus supported
On-chip 10-bit A/D
Multimaster I
2
C bus supported
80 pins, ROM correction added
Multimaster I
2
C bus supported
Expanded internal memory
capacity, ROM correction added
For DC inverter control
On-chip IEBus
TM
controller
On-chip VFD controller/driver
Software servo control,
on-chip analog circuit
for VCR, enhanced timer
Multimaster I
2
C bus supplied
PD784908 with enhanced functions,
expanded internal memory capacity,
ROM correction added
PD784915 with enhanced functions
Expanded internal memory capacity,
pin compatible with PD784026
100 pins, enhanced I/O, expanded
internal memory capacity
: Products in mass production
: Products under development
PD784225
PD784218/
PD784218A
PD784928
PD784216Y/
PD784216AY
PD784216A
PD784218AY
Enhanced functions of the
PD784938A, enhanced
I/O and internal memory
capacity
PD784967
PD78F4046
3
Data Sheet U11447EJ2V0DS00
OVERVIEW OF FUNCTIONS
Item
Function
Number of basic
113
instructions (mnemonics)
General-purpose registers
8 bits
16 registers
8 banks, or 16 bits
8 registers
8 banks (memory mapping)
Minimum instruction
125 ns (@16 MHz operation with internal clock)
execution time
Internal
Flash memory
64 KB
memory
RAM
2048 bytes
Memory space
1 MB with program/data combined
I/O ports
Total
65
Input
17
I/O
48
Pins with
Pins with
29
ancillary
pull-up
functions
Note
resistors
Real-time output port
4 bits
1
Timers
Timer 0:
Timer counter
1
Pulse output
(16 bits)
Capture/compare register
4
Toggle output
Set/reset output
Timer 1:
Timer counter
1
Pulse output
(16 bits)
Compare register
2
Toggle output
Set/reset output
Timer/event counter 2: Timer counter
1
Pulse output
(16 bits)
Compare register
2
Toggle output
PWM/PPG output
Timer/event counter 3: Timer counter
1
Pulse output
(16 bits)
Compare register
2
Toggle output
PWM/PPG output
Timer 4:
Timer counter
1
Pulse output
(16 bits)
Compare register
2
Real-time output (4 bits
1)
A/D converter
10-bit resolution
16 channels
Serial interface
UART/IOE (3-wire serial I/O): 2 channels (with baud rate generator)
Watchdog timer
1 channel
Interrupts Sources
27 (internal: 23, external: 8 (internal/external: 4)) + BRK instruction
Software
BRK instruction
Non-maskable
Internal: 1, external: 1
Maskable
Internal: 22, external: 7 (internal/external: 4)
4 programmable priority levels
3 service modes: vectored interrupt/macro service/context switching
Bus sizing
8-bit/16-bit external data bus width selectable
Standby
HALT/STOP/IDLE modes
Supply voltage
V
DD
= 4.5 to 5.5 V
Package
80-pin plastic QFP (14
14 mm)
Note
The pins with ancillary functions are included in the I/O pins.
PD78F4046
4
Data Sheet U11447EJ2V0DS00
CONTENTS
1.
DIFFERENCES AMONG
PD784046 SUBSERIES ........................................................................... 5
2.
PIN CONFIGURATION (TOP VIEW) ................................................................................................... 6
3.
SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL) .................................... 8
4.
BLOCK DIAGRAM ............................................................................................................................... 9
5.
PIN FUNCTIONS ................................................................................................................................ 10
5.1
Port Pins .................................................................................................................................................... 10
5.2
Non-Port Pins ............................................................................................................................................ 12
5.3
Pin I/O Circuits and Recommended Connection of Unused Pins ..................................................... 14
6.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ........................................................... 16
7.
FLASH MEMORY PROGRAMMING ................................................................................................. 17
7.1
Selecting Communication Mode ............................................................................................................ 17
7.2
Function of Flash Memory Programming ............................................................................................. 18
7.3
Connection of Flashpro II and Flashpro III ........................................................................................... 18
7.4
Cautions When Writing to Flash Memory ............................................................................................. 19
8.
ELECTRICAL SPECIFICATIONS ...................................................................................................... 21
9.
PACKAGE DRAWING ........................................................................................................................ 32
10. RECOMMENDED SOLDERING CONDITIONS ............................................................................... 33
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 34
APPENDIX B. RELATED DOCUMENTS ............................................................................................... 37
PD78F4046
5
Data Sheet U11447EJ2V0DS00
1. DIFFERENCES AMONG
PD784046 SUBSERIES
The only difference between the
PD784044 and
PD784046 is the internal memory capacity.
The
PD78F4046 is a version of the
PD784046 with the internal ROM replaced by flash memory.
The differences are shown in Table 1-1.
Table 1-1. Differences Among
PD784046 Subseries
Part Number
PD784044
PD784046
PD78F4046
Item
Internal ROM
32 KB
64 KB
64 KB
(mask ROM)
(mask ROM)
(flash memory)
Internal RAM
1024 bytes
2048 bytes
Function of pin 57
MODE
MODE/V
PP
PD78F4046
6
Data Sheet U11447EJ2V0DS00
2. PIN CONFIGURATION (TOP VIEW)
80-pin plastic QFP (14
14 mm)
PD78F4046GC-3B9
Caution Connect the MODE/V
PP
pin directly to V
SS
in normal operation mode.
P70/ANI0
P71/ANI1
P72/ANI2
P73/ANI3
P74/ANI4
P75/ANI5
P76/ANI6
P77/ANI7
AV
REF
AV
DD
V
SS
V
DD
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
P22/INTP1/TO01
BWD
P21/INTP0/TO00
MODE/V
PP
P20/NMI
V
SS
V
DD
P13/TO31
P12/TO30
P11/TO21
P10/TO20
P03/RTP3
P02/RTP2
P01/RTP1
P00/RTP0
P37/ASCK2/SCK2
P36/TxD2/SO2
P35/RxD2/SI2
P34/ASCK/SCK1
P33/TxD/SO1
P50/AD8
P51/AD9
P52/AD10
P53/AD11
P54/AD12
P55/AD13
P56/AD14
P57/AD15
P60/A16
P61/A17
P62/A18
P63/A19
P90/RD
P91/LWR
P92/HWR
P93/ASTB
P94/WAIT
P30/TO10
P31/TO11
P32/RxD/SI1
P87/ANI15
P86/ANI14
P85/ANI13
P84/ANI12
P83/ANI11
P82/ANI10
P81/ANI9
P80/ANI8
AV
SS
V
DD
X2
X1
V
SS
CLKOUT
P27/INTP6/TI3
P26/INTP5/TI2
P25/INTP4
P24/INTP3/TO03
RESET
P23/INTP2/TO02
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
PD78F4046
7
Data Sheet U11447EJ2V0DS00
P00 to P03:
Port 0
P10 to P13:
Port 1
P20 to P27:
Port 2
P30 to P37:
Port 3
P40 to P47:
Port 4
P50 to P57:
Port 5
P60 to P63:
Port 6
P70 to P77:
Port 7
P80 to P87:
Port 8
P90 to P94:
Port 9
RTP0 to RTP3:
Real-Time Port
NMI:
Nonmaskable Interrupt
INTP0 to INTP6:
Interrupt from Peripherals
TO00 to TO03, TO10, TO11:
Timer Output
TO20, TO21, TO30, TO31:
TI2, TI3:
Timer Input
RxD, RxD2:
Receive Data
TxD, TxD2:
Transmit Data
ASCK, ASCK2:
Asynchronous Serial Clock
SI1, SI2,:
Serial Input
SO1, SO2:
Serial Output
SCK1, SCK2:
Serial Clock
AD0 to AD15:
Address/Data Bus
A16 to A19:
Address Bus
RD:
Read Strobe
LWR:
Low Address Write Strobe
HWR:
High Address Write Strobe
ASTB:
Address Strobe
WAIT:
Wait
BWD:
Bus Width Definition
MODE:
Mode
CLKOUT:
Clock Out
X1, X2:
Crystal
RESET:
Reset
ANI0 to ANI15:
Analog Input
AV
REF
:
Analog Reference Voltage
AV
DD
:
Analog Power Supply
AV
SS
:
Analog Ground
V
DD
:
Power Supply
V
PP
:
Programming Power Supply
V
SS
:
Ground
PD78F4046
8
Data Sheet U11447EJ2V0DS00
3. SYSTEM CONFIGURATION EXAMPLE (AC SERVO MOTOR CONTROL)
UART
3-wire serial I/O
WDT
PD78F4046
Control panel
Display
Keypad
I/O port
External
tester
I/O
interface
circuit
CPU-to-CPU communication
Flash
memory
64 KB
RAM
2048 bytes
Macro
service
function
Port
INTP0 to INTP4
ANI8 to ANI15
TO10, TO11,
TO20, TO21
Port
ANI0 to ANI7
INTP5
AD0 to AD15
Limit switch
Driver/switching
circuit
Current/voltage
sensor signal
input circuit
AC motor
Rotary
encoder
Rotary
encoder
interface
Encoder
pulse
counter
PD78F4046
9
Data Sheet U11447EJ2V0DS00
4. BLOCK DIAGRAM
Programmable
interrupt
controller
INTP0 to INTP6
NMI
TO00 to TO03
INTP0 to INTP3
TO10, TO11
A/D
converter
AV
DD
AV
SS
AV
REF
INTP4
ANI0 to ANI15
Watchdog
timer
Timer 4
(16 bits)
Timer 1
(16 bits)
Timer 0
(16 bits)
78K/IV
CPU core
Flash memory
RAM
BUS I/F
BWD
AD0 to AD15
A16 to A19
RD
LWR, HWR
ASTB
WAIT
CLKOUT
RESET
MODE/V
PP
X1
X2
System
control
P00 to P03
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
P10 to P13
P20
P21 to P27
V
DD
V
SS
P30 to P37
P40 to P47
P50 to P57
P60 to P63
P70 to P77
P80 to P87
P90 to P94
Baud rate
generator
UART/IOE1
Baud rate
generator
UART/IOE2
TxD/SO1
RxD/SI1
ASCK/SCK1
TxD2/SO2
RxD2/SI2
ASCK2/SCK2
Timer/event
counter 2
(16 bits)
TO20, TO21
INTP5/TI2
TO30, TO31
INTP6/TI3
RTP0 to RTP3
Real-time
output port
Timer/event
counter 3
(16 bits)
PD78F4046
10
Data Sheet U11447EJ2V0DS00
5. PIN FUNCTIONS
5.1 Port Pins (1/2)
Pin Name
I/O
Alternate Function
Function
P00 to P03
I/O
RTP0 to RTP3
Port 0 (P0):
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P10
I/O
TO20
Port 1 (P1):
P11
TO21
4-bit I/O port
P12
TO30
Input/output can be specified in 1-bit units.
P13
TO31
P20
Input
NMI
Port 2 (P2):
Input only
P21
I/O
INTP0/TO00
8-bit I/O port
Input/output can be specified in
P22
INTP1/TO01
1-bit units.
P23
INTP2/TO02
P24
INTP3/TO03
P25
INTP4
P26
INTP5/TI2
P27
INTP6/TI3
P30
I/O
TO10
Port 3 (P3):
P31
TO11
8-bit I/O port
P32
RxD/SI1
Input/output can be specified in 1-bit units.
P33
TxD/SO1
P34
ASCK/SCK1
P35
RxD2/SI2
P36
TxD2/SO2
P37
ASCK2/SCK2
P40 to P47
I/O
AD0 to AD7
Port 4 (P4):
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P50 to P57
I/O
AD8 to AD15
Port 5 (P5):
8-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
P60 to P63
I/O
A16 to A19
Port 6 (P6):
4-bit I/O port
Input/output can be specified in 1-bit units.
When used as an input port, an on-chip pull-up resistor can be
specified by means of software.
PD78F4046
11
Data Sheet U11447EJ2V0DS00
5.1 Port Pins (2/2)
Pin Name
I/O
Alternate Function
Function
P70 to P77
Input
ANI0 to ANI7
Port 7 (P7):
8-bit input-only port
P80 to P87
Input
ANI8 to ANI15
Port 8 (P8):
8-bit input-only port
P90
I/O
RD
Port 9 (P9):
P91
LWR
5-bit I/O port
P92
HWR
Input/output can be specified in 1-bit units.
P93
ASTB
When used as an input port, an on-chip pull-up resistor can be
P94
WAIT
specified by means of software.
PD78F4046
12
Data Sheet U11447EJ2V0DS00
5.2 Non-Port Pins (1/2)
Pin Name
I/O
Alternate Function
Function
RTP0 to RTP3
Output
P00 to P03
Real-time output
NMI
Input
P20
Non-maskable interrupt request input
INTP0
P21/TO00
External interrupt
Capture trigger signal of CC00
INTP1
P22/TO01
request input
Capture trigger signal of CC01
INTP2
P23/TO02
Capture trigger signal of CC02
INTP3
P24/TO03
Capture trigger signal of CC03
INTP4
P25
Conversion start trigger input of A/D converter
INTP5
P26/TI2
INTP6
P27/TI3
TO00
Output
P21/INTP0
Timer output from timer
TO01
P22/INTP1
TO02
P23/INTP2
TO03
P24/INTP3
TO10
P30
TO11
P31
TO20
P10
TO21
P11
TO30
P12
TO31
P13
TI2
Input
P26/INTP5
External count clock input to timer/event counter 2
TI3
P27/INTP6
External count clock input to timer/event counter 3
RxD
P32/SI1
Serial data input (UART0)
RxD2
P35/SI2
Serial data input (UART2)
TxD
Output
P33/SO1
Serial data output (UART0)
TxD2
P36/SO2
Serial data output (UART2)
ASCK
Input
P34/SCK1
Baud rate clock input (UART0)
ASCK2
P37/SCK2
Baud rate clock input (UART2)
SI1
P32/RxD
Serial data input (3-wire serial I/O1)
SI2
P35/RxD2
Serial data input (3-wire serial I/O2)
SO1
Output
P33/TxD
Serial data output (3-wire serial I/O1)
SO2
P36/TxD2
Serial data output (3-wire serial I/O2)
SCK1
I/O
P34/ASCK
Serial clock input/output (3-wire serial I/O1)
SCK2
P37/ASCK2
Serial clock input/output (3-wire serial I/O2)
AD0 to AD7
P40 to P47
Lower multiplexed address/data bus for expanding memory externally
AD8 to AD15
Note
P50 to P57
When 8-bit bus is specified
Higher address bus for expanding memory externally
When external 16-bit bus is specified
Higher multiplexed address/data bus for expanding memory externally
A16 to A19
Note
Output
P60 to P63
Higher address bus for expanding memory externally
RD
P90
Read strobe to external memory
Note
The number of pins used as address bus pins differs depending on the external address space.
PD78F4046
13
Data Sheet U11447EJ2V0DS00
5.2 Non-Port Pins (2/2)
Pin Name
I/O
Alternate Function
Function
LWR
Output
P91
When external 8-bit bus is specified
Write strobe to external memory
When external 16-bit bus is specified
Write strobe to external memory located at lower address
HWR
P92
Write strobe to external memory located at higher address when external
16-bit bus is specified
ASTB
Output
P93
Timing signal output that externally latches address information output
from AD0 through AD15 pins to access external memory
WAIT
Input
P94
Wait insertion
BWD
Bus width setting
MODE
V
PP
Connect directly to V
SS
in normal operation mode
(for specification of IC test mode).
CLKOUT
Output
Clock output
X1
Input
Connecting crystal resonator for system clock oscillation
X2
(clock can be input to X1).
RESET
Input
Chip reset
ANI0 to ANI7
P70 to P77
Analog voltage input for A/D converter
ANI8 to ANI15
P80 to P87
AV
REF
Reference voltage application for A/D converter
AV
DD
Positive power supply for A/D converter
AV
SS
GND for A/D converter
V
DD
Positive power supply
V
PP
Input
MODE
Flash memory programming mode setting
Applying high-voltage for program write/verify.
V
SS
GND
PD78F4046
14
Data Sheet U11447EJ2V0DS00
5.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table
5-1.
For the I/O circuit configuration of each type, refer to Figure 5-1.
Table 5-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
P00/RTP0 to P03/RTP3
5-A
I/O
Input: Independently connect to V
DD
or V
SS
via a resistor.
P10/TO20
5
Output: Leave open.
P11/TO21
P12/TO30
P13/TO31
P20/NMI
2
Input
Connect to V
SS
.
P21/INTP0/TO00
8
I/O
Input: Independently connect to V
DD
or V
SS
via a resistor.
P22/INTP1/TO01
Output: Leave open.
P23/INTP2/TO02
P24/INTP3/TO03
P25/INTP4
P26/INTP5/TI2
P27/INTP6/TI3
P30/TO10
5
P31/TO11
P32/RxD/SI1
P33/TxD/SO1
P34/ASCK/SCK1
8
P35/RxD2/SI2
5
P36/TxD2/SO2
P37/ASCK2/SCK2
8
P40/AD0 to P47/AD7
5-A
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
9
Input
Connect to V
SS
.
P80/ANI8 to P87/ANI15
P90/RD
5-A
I/O
Input: Independently connect to V
DD
or V
SS
via a resistor.
P91/LWR
Output: Leave open.
P92/HWR
P93/ASTB
P94/WAIT
MODE
1
Input
RESET
2
CLKOUT
3
Output
Leave open.
AV
REF
Connect to V
SS
.
AV
SS
AV
DD
Connect to V
DD
.
Remark
Since type numbers are standardized among the 78K Series products, they are not sequential in some
models (i.e., some circuits are not provided).
PD78F4046
15
Data Sheet U11447EJ2V0DS00
Figure 5-1. Pin I/O Circuits
Type 2
Schmitt-triggered input with hysteresis characteristics
Type 1
P-ch
IN
V
DD
N-ch
IN
Type 3
Type 5
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
Type 5-A
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
Input
enable
P-ch
V
DD
Pullup
enable
Type 8
Data
Output
disable
P-ch
IN/OUT
V
DD
N-ch
IN
Comparator
+
V
REF
(Threshold voltage)
P-ch
N-ch
Input
enable
Type 9
P-ch
OUT
V
DD
N-ch
PD78F4046
16
Data Sheet U11447EJ2V0DS00
6. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
IMS is a register that is set by software and is used to specify a part of the internal memory that is not to
be used. By setting this register, the internal memory of the
PD78F4046 can be mapped identically to that
of a mask ROM version with a different internal memory (ROM and RAM) capacity.
IMS is set with an 8-bit memory manipulation instruction.
RESET input sets IMS to DEH.
Figure 6-1. Internal Memory Size Switching Register (IMS) Format
Table 6-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM
versions.
Table 6-1. Setting Values of Internal Memory Size Switching Register (IMS)
Target Mask ROM Version
IMS Setting Value
PD784044, 784054
CDH
Note
PD784046
DEH
Note When IMS is set to CDH, the peripheral RAM capacity of the
PD78F4046 is 768 bytes, but that of the
PD784044 or 784054 is
512 bytes. Consequently, when making a mask ROM version, be
sure not to use 0FA00H through 0FAFFH in the peripheral RAM area
of
PD78F4046 (upon the execution of the LOCATION 0H instruc-
tion).
7
1
6
1
5
ROM1
4
ROM0
3
1
2
1
1
RAM1
0
RAM0
IMS
ROM1
0
0
ROM0
0
1
Other than above
32 KB
64 KB
Setting prohibited
Internal ROM Capacity Selection
Address: 0FFFCH
After reset: DEH
R/W
RAM1
0
1
RAM0
1
0
Other than above
768 bytes
1.5 KB
Setting prohibited
Peripheral RAM Capacity Selection
PD78F4046
17
Data Sheet U11447EJ2V0DS00
7. FLASH MEMORY PROGRAMMING
The flash memory can be written with the
PD78F4046 mounted on the target board (on-board write). Writing
is performed with the dedicated flash programmer Flashpro II (part number: FL-PR2) and Flashpro III (part
number: FL-PR3, PG-FP3)) connected to the host machine and the target system.
Remark Flashpro II and III are products of Naito Densei Machida Mfg. Co., Ltd..
7.1 Selecting Communication Mode
Writing to flash memory is performed using the Flashpro II and III via a serial communication mode. Select
a serial communication mode from those listed in Table 7-1. The selection of the communication mode is made
by using the format shown in Figure 7-1. Each communication mode is selected by the number of V
PP
pulses
shown in Table 7-1.
Table 7-1. List of Communication Modes
Communication Mode
Number of Channels
Pins Used
Number of V
PP
Pulses
3-wire serial I/O
2
P34/ASCK/SCK1
0
P33/TxD/SO1
P32/RxD/SI1
P37/ASCK2/SCK2
1
P36/TxD2/SO2
P35/RxD2/SI2
UART
2
P33/TxD/SO1
8
P32/RxD/SI1
P36/TxD2/SO2
9
P35/RxD2/SI2
Figure 7-1. Format of Communication Mode Selection
10 V
MODE/V
PP
V
DD
V
SS
V
DD
V
SS
RESET
PD78F4046
18
Data Sheet U11447EJ2V0DS00
7.2 Function of Flash Memory Programming
Operations such as writing to flash memory are performed by various command/data transmission and
reception operations according to the selected communication mode. Table 7-2 shows the major functions of
flash memory programming.
Table 7-2. Major Functions of Flash Memory Programming
Function
Description
Batch erase
Erases the entire memory contents.
Block erase
Erases the contents of the specified memory block, with one memory block consisting of 16 KB.
Batch blank check
Checks the erasure status of the entire memory.
Block blank check
Checks the erasure status of the specified block.
Data write
Writes to the flash memory based on the write start address and the amount of data to be
written (number of bytes).
Batch verify
Compares the entire memory contents with the input data.
Block verify
Compares the contents of the specified memory block with the input data.
7.3 Connection of Flashpro II and Flashpro III
The connection of the dedicated flash programmer and the
PD78F4046 differs according to the communication
mode (3-wire serial I/O or UART). The connection for each communication mode is shown in Figures 7-2 and
7-3.
Figure 7-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode
Figure 7-3. Connection of Flashpro II and Flashpro III in UART Mode
V
PP
V
DD
RESET
SCK1 or SCK2
SI1 or SI2
SO1 or SO2
V
SS
Flashpro II,
Flashpro III
PD78F4046
V
PP
V
DD
RESET
RxD or RxD2
TxD or TxD2
V
SS
Flashpro II,
Flashpro III
PD78F4046
PD78F4046
19
Data Sheet U11447EJ2V0DS00
7.4 Cautions When Writing to Flash Memory
For writing data to the flash memory of the
PD78F4046, use the prewrite and ECC functions. Moreover,
set the flash programmer as follows when writing to flash memory using these functions. Either 1-bit or 8-bit
memory manipulation instructions can be used to make these settings.
(1) Using prewrite function
To improve flash memory rewrite characteristics, prewriting is necessary before erasing. Prewriting involves
writing 00H to all the data. This is performed to delete the bits that are already 1 in the data (erasure state),
and to prevent further erasure stress.
(2) Using ECC function
When writing to the
PD78F4046 and shipping it as a product, ECC data needs to be written in the ECC data
area of flash memory. By writing ECC data and setting the ECC function, data writing can be performed
correctly.
<1> Creating ECC data
Convert the EX file to an ECC-attached HEX file using the ECC generator included in the assembly package
(Ver. 1.20 or later for PC). Download this ECC-attached HEX file to the flash programmer, and then write.
[ECC data creating method]
Prepare the HEX file created by the object converter of the assembly package.
Convert it to the program data + HEX file using the ECC generator (ECCGEN.EXE) included in the assembly
package.
Example Convert the file "file.hex" to "file_ec.hex".
ec file.hex-ofile_ec.hex -a0ffffh, 10000h, 14000h, 14004h
<2> Flash programmer (Flashpro II, Flashpro III) setting and writing
Prewriting and ECC writing are performed by Flashpro II and Flashpro III. The setting method when using
an earlier version than Flashpro II Ver. 2.50 is described below.
Remark If using Flashpro II Ver. 2.50 or later or Flashpro III (PG-FP3 (Ver. 3.040 or later, products of NEC
Corporation)), setting is not necessary. Setting is performed automatically by reading parameter
files.
PD78F4046
20
Data Sheet U11447EJ2V0DS00
[When earlier version than Flashpro II Ver. 2.50 is used]
a. Connect the PC and FL-PR2, then start up the control software "flashpro.exex".
b. Press the CTRL + GRPH (ART) + P keys at the same time.
c. Check the check box of Pre-Write set.
Prewrite setting
d. Press the OK button.
e. Select Setting.
f. Select Option.
g. Check the ECC code area in the menu window.
h. Input 14004 to ECC END ADDRESS
ECC write setting
i.
Press the OK button.
j.
Press the TYPE button.
k. Input 14004 to END ADDRESS
l.
Press the OK button
[Writing method]
a. Download the ECC-attached HEX file to the flash programmer.
b. Set to chip mode and write using the E.P.V button.
Do not use the Program command, since this will disable writing to ECC.
PD78F4046
21
Data Sheet U11447EJ2V0DS00
8. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
A
= 25C)
Parameter
Symbol
Conditions
Ratings
Unit
Supply voltage
V
DD
0.5 to +7.0
V
AV
DD
0.5 to V
DD
+ 0.5
V
AV
SS
0.5 to +0.5
V
Input voltage
V
I1
Note 1
0.5 to V
DD
+ 0.5
7.0
V
V
I2
TEST/V
PP
pin in the programming mode
0.5 to +11.0
V
Output voltage
V
O
0.5 to V
DD
+ 0.5
V
Output current, low
I
OL
All output pins
15
mA
Total of all output pins
150
mA
Output current, high
I
OH
All output pins
10
mA
Total of all output pins
100
mA
Analog input voltage
V
IAN
Note 2 AV
DD
> V
DD
0.5 to V
DD
+ 0.5
V
V
DD
AV
DD
0.5 to AV
DD
+ 0.5
A/D converter reference
AV
REF
AV
DD
> V
DD
0.5 to V
DD
+ 0.5
V
input voltage
V
DD
AV
DD
0.5 to AV
DD
+ 0.5
Operating ambient
T
A
10 to +70
C
temperature
Storage temperature
T
stg
40 to +125
C
Notes 1. Pins other than the pins specified in Note 2.
2. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15
Caution
Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product is
on the verge of suffering physical damage, and therefore the product must be used under
conditions that the absolute maximum ratings are not exceeded.
Recommended Operating Conditions
Oscillation Frequency
T
A
V
DD
8 MHz
f
XX
32 MHz
10 to +70C
4.5 to 5.5 V
Capacitance (T
A
= 25C, V
SS
= V
DD
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input capacitance
C
I
f = 1 MHz
10
pF
Output capacitance
C
O
Unmeasured pins returned to 0 V.
10
pF
I/O capacitance
C
IO
10
pF
PD78F4046
22
Data Sheet U11447EJ2V0DS00
Flash Memory Specifications (T
A
= +10 to +40C (rewriting), T
A
= 10 to +70C (other than rewriting))
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
V
DD
supply voltage
V
DD
4.5
5.5
V
V
PP
supply voltage
V
PP
V
PP
high-voltage detection
9.7
10.0
10.3
V
Number of rewrites
Note
10
Times
Note
If the number of flash memory rewrites exceeds 10, operation is not guaranteed.
Oscillator Characteristics (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Resonator
Recommended Circuit
Parameter
MIN.
MAX.
Unit
Ceramic resonator or
Oscillation frequency (f
XX
)
8
32
MHz
crystal resonator
External clock
X1 input frequency (f
X
)
8
32
MHz
X1 input rise/fall time
0
5
ns
X1 input high-/low-level
20
105
ns
width
Note
When the EXTC bit of the oscillation stabilization time specification register (OSTS) = 0. Input the reverse
phase clock of pin X1 to pin X2 when the EXTC bit = 1.
Caution
When using the system clock oscillator, wire as follows in the area enclosed by the broken lines
in the above figures to avoid an adverse effect from wiring capacitance.
Keep the wiring length as short as possible.
Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line
through which a high fluctuating current flows.
Always make the ground point of the oscillator capacitor the same potential as V
SS
. Do not
ground the capacitor to a ground pattern through which a high current flows.
Do not fetch signals from the oscillator.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the
oscillation themselves or apply to the resonator manufacturer for evaluation.
C1
C2
V
SS
X1
X2
X1
X2
Open
Note
HCMOS inverter
PD78F4046
23
Data Sheet U11447EJ2V0DS00
DC Characteristics (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input voltage, low
V
IL
0
0.8
V
Input voltage, high
V
IH1
Note 1
2.2
V
DD
V
V
IH2
Note 2
0.8V
DD
V
DD
Output voltage, low
V
OL
I
OL
= 2.0 mA
0.45
V
Output voltage, high
V
OH
I
OH
= 400
A
V
DD
1.0
V
Input leakage current
I
LI
Note 3 0 V
V
I
V
DD
10
A
Analog pin input leakage current
I
LIAN
Note 4 0 V
V
I
AV
DD
1
A
Output leakage current
I
LO
0 V
V
O
V
DD
10
A
V
DD
supply current
I
DD1
Operating mode (f
XX
= 32 MHz)
50
80
mA
I
DD2
HALT mode (f
XX
= 32 MHz)
30
60
mA
I
DD3
IDLE mode (f
XX
= 32 MHz)
10
20
mA
Data retention voltage
V
DDDR
STOP mode
2.5
V
Data retention current
I
DDDR
STOP mode V
DDDR
= 2.5 V
2
15
A
V
DDDR
= 5 V
10%
15
50
A
Pull-up resistor
R
L
15
40
80
k
Notes 1. Pins other than the pins specified in Note 2
2. P20/NMI, P21/INTP0/TO00, P22/INTP1/TO01, P23/INTP2/TO02, P24/INTP3/TO03, P25/INTP4, P26/
INTP5/TI2, P27/INTP6/TI3, P34/ASCK/SCK1, P37/ASCK2/SCK2, X1, X2, RESET
3. Input and I/O pins (except X1 and X2, and P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 used as
analog inputs)
4. Pins P70/ANI0 to P77/ANI7, P80/ANI8 to P87/ANI15 (pins used as analog inputs, and only during a
non-sampling operation)
PD78F4046
24
Data Sheet U11447EJ2V0DS00
AC Characteristics (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Read/write operation
Parameter
Symbol
Expression
MIN.
MAX.
Unit
System clock cycle time
t
CYK
62.5
250
ns
Address setup time (to ASTB
)
t
SAST
(0.5 + a) T 20
11.2
ns
Address hold time (from ASTB
)
t
HSTA
0.5T 20
11.2
ns
ASTB high-level width
t
WSTH
(0.5 + a) T 17
14.2
ns
RD
delay time from address
t
DAR
(1 + a) T 15
47.5
ns
Address float time from RD
t
FRA
0
ns
Data input time from address
t
DAID
(2.5 + a + n) T 56
100.2
ns
Data input time from RD
t
DRID
(1.5 + n) T 48
45.7
ns
Delay time from ASTB
to
RD
t
DSTR
0.5T 16
15.3
ns
Data hold time (from RD
)
t
HRID
0
ns
Address active time from RD
t
DRA
0.5T 14
17.2
ns
RD low-level width
t
WRL
(1.5 + n) T 30
63.7
ns
Delay time from address to LWR, HWR
t
DAW
(1 + a) T 15
47.5
ns
Data output time from LWR, HWR
t
DWOD
15
ns
Delay time from ASTB
to LWR, HWR
t
DSTW
0.5T 16
15.3
ns
Data setup time (to LWR, HWR
)
t
SODW
(1.5 + n) T 25
68.7
ns
Data hold time (from LWR, HWR
)
t
HWOD
0.5T 14
17.2
ns
Delay time from LWR, HWR
to ASTB
t
DWST
1.5T 15
78.8
ns
LWR, HWR low-level width
t
WWL
(1.5 + n) T 36
57.7
ns
WAIT
input time from address
t
DAWT
(2 + a) T 50
75
ns
WAIT
input time from ASTB
t
DSTWT
1.5T 40
53.7
ns
WAIT hold time from ASTB
t
HSTWT
(1.5 + n) T + 5
98.8
ns
Delay time from ASTB
to WAIT
t
DSTWTH
(2.5 + n) T 40
116.2
Note
ns
WAIT
input time from RD
t
DRWT
T 40
22.5
ns
WAIT hold time from RD
t
HRWT
(1 + n) T + 5
67.5
ns
Delay time from RD
to WAIT
t
DRWTH
(1 + n) T 40
85
Note
ns
WAIT
input time from LWR, HWR
t
DWWT
T 40
22.5
ns
WAIT hold time from LWR, HWR
t
HWWT
(1 + n) T + 5
67.5
ns
Delay time from LWR, HWR
to WAIT
t
DWWTH
(1 + n) T 40
85
Note
ns
Note
Specification when an external wait is inserted
Remarks 1. T = t
CYK
= 1/f
CLK
(f
CLK
is internal system clock frequency)
2. a = 1 when an address wait is inserted, otherwise 0.
3. n indicates the number of the wait cycles as specified by the external wait pin (WAIT) or
programmable wait control registers 1, 2 (PWC1, PWC2). (n
0. n
1 for t
DSTWTH
, t
DRWTH
, t
DWWTH
).
4. Calculate values in the expression column with the system clock cycle time to be used because
these values depend on the system clock cycle time (t
CYK
= T). The values in the above expression
column are calculated based on T = 62.5 ns.
PD78F4046
25
Data Sheet U11447EJ2V0DS00
Serial Operation (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
Serial clock cycle time
t
CYSK
SCK1, SCK2 output
BRG
T
SFT
ns
SCK1, SCK2 input
External clock
500
ns
Serial clock low-level width
t
WSKL
SCK1, SCK2 output
BRG
0.5T
SFT
40
ns
SCK1, SCK2 input
External clock
210
ns
Serial clock high-level width
t
WSKH
SCK1, SCK2 output
BRG
0.5T
SFT
40
ns
SCK1, SCK2 input
External clock
210
ns
SI1, SI2 setup time
t
SSSK
80
ns
(to SCK1, SCK2
)
SI1, SI2 hold time
t
HSSK
80
ns
(from SCK1, SCK2
)
Delay time from SCK1, SCK2
t
DSBSK
R = 1 k
, C = 100 pF
0
150
ns
to SO1, SO2 output
Remarks 1. T
SFT
is a value set by software. The minimum value is t
CYK
8.
2. t
CYK
= 1/f
CLK
(f
CLK
is internal system clock frequency)
Other Operations (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= 0 V)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
NMI high-/low-level width
t
WNIH
, t
WNIL
10
s
INTP0 to INTP6 high-/low-level width t
WITH
, t
WITL
4
t
CYSMP
TI2, TI3 high-/low-level width
t
WTIH
, t
WTIL
4
t
CYSMP
RESET high-/low-level width
t
WRSH
, t
WRSL
10
s
Remarks 1. t
CYSMP
is a sampling clock set by software in the noise protection control register (NPC).
When NIn = 0, t
CYSMP
= t
CYK
When NIn = 1, t
CYSMP
= t
CYK
4
2. t
CYK
= 1/f
CLK
(f
CLK
is internal system clock frequency)
3. NIn: Bit n of NPC (n = 0 to 6)
AC Timing Test Points
V
DD
0 V
0.8V
DD
or 2.2 V
0.8 V
0.8V
DD
or 2.2 V
0.8 V
Test points
PD78F4046
26
Data Sheet U11447EJ2V0DS00
AD Converter Characteristics (T
A
= 10 to +70C, V
DD
= 4.5 to 5.5 V, V
SS
= AV
SS
= 0 V,
V
DD
0.5 V
AV
DD
V
DD
)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Resolution
10
bit
Overall error
Note 1
4.5 V
AV
REF
AV
DD
0.5
%FSR
Note 2
3.4 V
AV
REF
< 4.5 V
0.7
%FSR
Note 2
Quantization error
1/2
LSB
Conversion time
t
CONV
80 ns
t
CYK
250 ns
169
t
CYK
62.5 ns
t
CYK
< 80 ns
208
t
CYK
Sampling time
t
SAMP
80 ns
t
CYK
250 ns
20
t
CYK
62.5 ns
t
CYK
< 80 ns
24
t
CYK
Zero-scale error
Note 1
4.5 V
AV
REF
AV
DD
1.5
3.5
LSB
3.4 V
AV
REF
< 4.5 V
1.5
4.5
LSB
Full-scale error
Note 1
4.5 V
AV
REF
AV
DD
1.5
3.5
LSB
3.4 V
AV
REF
< 4.5 V
1.5
4.5
LSB
Integral linearity error
Note 1
4.5 V
AV
REF
AV
DD
1.5
2.5
LSB
3.4 V
AV
REF
< 4.5 V
1.5
4.5
LSB
Analog input voltage
V
IAN
0.3
AV
REF
+ 0.3
V
A/D converter reference input
AV
REF
3.4
AV
DD
V
voltage
AV
REF
current
AI
REF
1.0
3.0
mA
AV
DD
supply current
AI
DD
2.0
6.0
mA
A/D converter data retention
AI
DDDR
STOP AV
DDDR
= 2.5 V
2
10
A
current
mode
AV
DDDR
= 5 V
10%
10
50
A
Notes 1.
Excludes quantization error.
2.
Indicated as a ratio (%FSR) to the full-scale value.
Remark
t
CYK
= 1/f
CLK
(f
CLK
is the internal system clock frequency)
PD78F4046
27
Data Sheet U11447EJ2V0DS00
Read Operation (8 bits)
(CLK)
AD8 to AD15
(Output)
AD0 to AD7
(I/O)
ASTB
(Output)
RD
(Output)
WAIT
(Input)
Higher address
Higher address
Lower address (output)
Data (input)
Lower address (output)
t
CYK
t
WSTH
t
HSTA
t
DSTR
t
DAR
t
WRL
t
DSTWTH
t
HSTWT
t
DSTWT
t
DRWT
t
DAWT
t
HRWT
t
DRWTH
t
DRID
t
DRA
t
FRA
t
HRID
t
SAST
t
DAID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
PD78F4046
28
Data Sheet U11447EJ2V0DS00
Write Operation (8 bits)
(CLK)
AD8 to AD15
(Output)
AD0 to AD7
(Output)
ASTB
(Output)
LWR
(Output)
WAIT
(Input)
t
CYK
t
DSTWTH
t
HSTWT
t
DSTWT
t
DWWT
t
DAWT
t
HWWT
t
DWWTH
t
DSTW
t
HSTA
t
WSTH
t
SAST
t
HWOD
t
DWST
t
DWOD
t
SODW
t
DAW
t
WWL
Higher address
Higher address
Lower address (output)
Undefined
Data (output)
Lower address (output)
PD78F4046
29
Data Sheet U11447EJ2V0DS00
Read Operation (16 bits)
(CLK)
t
CYK
Address (output)
Data (input)
Address (output)
t
WSTH
t
HSTA
t
DSTR
t
DAR
t
WRL
t
DSTWTH
t
HSTWT
t
DSTWT
t
DRWT
t
DAWT
t
HRWT
t
DRWTH
t
DRID
t
DRA
t
FRA
t
HRID
t
SAST
t
DAID
Hi-Z
Hi-Z
Hi-Z
Hi-Z
AD8 to AD15
AD0 to AD7
(I/O)
ASTB
(Output)
RD
(Output)
WAIT
(Input)
PD78F4046
30
Data Sheet U11447EJ2V0DS00
Write Operation (16 bits)
(CLK)
AD8 to AD15
AD0 to AD7
(Output)
ASTB
(Output)
HWR, LWR
(Output)
WAIT
(Input)
t
CYK
t
DSTWTH
t
HSTWT
t
DSTWT
t
DWWT
t
DAWT
t
HWWT
t
DWWTH
t
DSTW
t
HSTA
t
WSTH
t
SAST
t
HWOD
t
DWST
t
DWOD
t
SODW
t
DAW
t
WWL
Address (output)
Data (output)
Undefined
Address (output)
PD78F4046
31
Data Sheet U11447EJ2V0DS00
Serial Operation
Interrupt Input Timing
Reset Input Timing
Timer Input Timing
SCK1, SCK2
SO1, SO2
SI1, SI2
t
CYSK
t
WSKL
t
DSBSK
t
SSSK
t
HSSK
t
WSKH
t
WNIH
t
WNIL
0.8V
DD
0.8 V
t
WITH
t
WITL
0.8V
DD
0.8 V
NMI
INTP0 to INTP6
t
WRSH
t
WRSL
0.8V
DD
0.8 V
RESET
t
WTIH
t
WTIL
0.8V
DD
0.8 V
TI2, TI3
PD78F4046
32
Data Sheet U11447EJ2V0DS00
9. PACKAGE DRAWING
80-PIN PLASTIC QFP (14x14)
NOTE
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
ITEM
MILLIMETERS
A
B
D
G
17.2
0.4
14.0
0.2
0.13
0.825
I
17.2
0.4
J
C
14.0
0.2
H
0.30
0.10
0.65 (T.P.)
K
1.6
0.2
L
0.8
0.2
F
0.825
S80GC-65-3B9-6
N
P
Q
0.10
2.7
0.1
0.1
0.1
R
S
5
5
3.0 MAX.
M
0.15
+
0.10
-
0.05
60
61
40
80
1
21
20
41
S
S
N
J
detail of lead end
C D
A
B
R
K
M
L
P
I
S
Q
G
F
M
H
PD78F4046
33
Data Sheet U11447EJ2V0DS00
10. RECOMMENDED SOLDERING CONDITIONS
The
PD78F4046 should be soldered and mounted under the following recommended conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device
Mounting Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC
representative.
Table 10-1. Surface Mounting Type Soldering Conditions
PD78F4046GC-3B9: 80-pin plastic QFP (14
14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Infrared reflow
Package peak temperature: 235
C, Time: 30 seconds max. (at 210
C or
IR35-207-2
higher), Count: Twice or less, Exposure limit: 7 days
Note
(after 7 days,
prebake at 125
C for 20 hours)
VPS
Package peak temperature: 215
C, Time: 40 seconds max. (at 200
C or
VP15-207-2
higher), Count: Twice or less, Exposure limit: 7 days
Note
(after 7 days,
prebake at 125
C for 20 hours)
Wave soldering
Solder bath temperature: 260
C max., Time: 10 seconds max., Count:
WS60-207-1
Once, Preheating temperature: 120
C max. (package surface
temperature), Exposure limit: 7 days
Note
(after 7 days, prebake at 125
C
for 20 hours)
Partial heating
Pin temperature: 300
C max., Time: 3 seconds max. (per pin row)
Note
After opening the dry pack, store it at 25
C or less and 65% RH or less for the allowable storage period.
Caution
Do not use different soldering methods together (except for partial heating).
PD78F4046
34
Data Sheet U11447EJ2V0DS00
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the
PD78F4046.
Refer to (5) Cautions on using development tools.
(1) Language processing software
RA78K4
Assembler package common to 78K/IV Series
CC78K4
C compiler package common to 78K/IV Series
DF784046
Device file for
PD784046 Subseries
CC78K4-L
C compiler library source file common to 78K/IV Series
(2) Flash memory writing tools
Flashpro II (Model FL-PR2),
Dedicated flash programmer for microcontrollers incorporating flash memory
Flashpro III (Model FL-PR3,
PG-FP3)
FA-80GC
Adapter for flash memory programming
(3) Debugging tools
When IE-78K4-NS in-circuit emulator is used
IE-78K4-NS
In-circuit emulator common to 78K/IV Series
IE-70000-MC-PS-B
Power supply unit for IE-78K4-NS
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series PC (except notebook PC) is used
as the host machine (C bus supported)
IE-70000-CD-IF
PC card and interface cable necessary when a PC-9800 series notebook PC is used as
the host machine (PCMCIA socket supported)
IE-70000-PC-IF-C
Interface adapter necessary when an IBM PC/AT
TM
-compatible is used as the host
machine (ISA bus supported)
IE-784046-NS-EM1
Emulation board for emulating
PD784046 Subseries
NP-80GC
Emulation probe for 80-pin plastic QFP (GC-3B9 type)
EV-9200GC-80
Socket to be mounted on the board of the target system for 80-pin plastic QFP (GC-3B9
type)
ID78K4-NS
Integrated debugger for IE-78K4-NS
SM78K4
System simulator common to 78K/IV Series
DF784046
Device file for the
PD784046 Subseries
PD78F4046
35
Data Sheet U11447EJ2V0DS00
When using the IE-784000-R in-circuit emulator
IE-784000-R
In-circuit emulator common to 78K/IV Series
IE-70000-98-IF-C
Interface adapter necessary when a PC-9800 series PC (except notebook
PC) is used as the host machine (C bus supported)
IE-70000-PC-IF-C
Interface adapter necessary when an IBM PC/AT-compatible is used
as the host machine (ISA bus supported)
IE-70000-PCI-IF
Interface adapter necessary when PC that incorporates PCI bus is used as host
machine
IE-78000-R-SV3
Interface adapter and cable necessary when an EWS is used as the host machine
IE-784000-R-EM
Emulation board common to 78K/IV Series
IE-784046-NS-EM1
Emulation board for emulating
PD784046 Subseries
IE-784046-R-EM1
IE-78K4-R-EX2
Emulation probe conversion board necessary when the IE-784046-NS-EM1 is used in
the IE-784000-R. Not necessary when the IE-784046-R-EM1 is used.
EP-78230GC-R
Emulation probe for 80-pin plastic QFP (GC-3B9 type)
EV-9200GC-80
Socket to be mounted on the board of the target system made for the 80-pin plastic
QFP (GC-3B9 type)
ID78K4
Integrated debugger for IE-784000-R
SM78K4
System simulator common to 78K/IV Series
DF784046
Device file for
PD784046 Subseries
(4) Real-time OS
RX78K/IV
Real-time OS for 78K/IV Series
MX78K4
OS for 78K/IV Series
PD78F4046
36
Data Sheet U11447EJ2V0DS00
(5) Cautions on using development tools
The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784046.
The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784046.
FL-PR2, FL-PR3, FA-80GC, and NP-80GC are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: +81-
44-822-3813).
The host machine and OS suitable for each software are as follows:
Host Machine [OS]
PC
EWS
PC-9800 series [Windows
TM
]
HP9000 series 700
TM
[HP-UX
TM
]
IBM PC/AT-compatible
SPARCstation
TM
[SunOS
TM
, Solaris
TM
]
Software
[Japanese/English Windows]
NEWS
TM
(RISC) [NEWS-OS
TM
]
RA78K4
Note
CC78K4
Note
ID78K4-NS
ID78K4
SM78K4
RX78K/IV
Note
MX78K4
Note
Note
DOS-based software
PD78F4046
37
Data Sheet U11447EJ2V0DS00
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document
Document No.
Japanese
English
PD784044, 784046 Data Sheet
U10951J
U10951E
PD78F4046 Data Sheet
U11447J
This manual
PD784046 Subseries User's Manual - Hardware
U11515J
U11515E
PD784046 Subseries Special Function Register Table
U10986J
78K/IV Series User's Manual - Instruction
U10905J
U10905E
78K/IV Series Instruction List
U10594J
78K/IV Series Instruction Set
U10595J
78K/IV Series Application Note - Software Basics
U10095J
U10095E
Documents Related to Development Tools (User's Manuals)
Document
Document No.
Japanese
English
RA78K4 Assembler Package
Operation
U11334J
U11334E
Language
U11162J
U11162E
RA78K4 Structured Assembler Preprocessor
U11743J
U11743E
CC78K4 C Compiler
Operation
U11572J
U11572E
Language
U11571J
U11571E
IE-78K4-NS
U13356J
U13356E
IE-784000-R
U12903J
U12903E
IE-784046-NS-EM1
U13744J
U13744E
IE-784046-R-EM1
U11677J
U11677E
EP-78230
EEU-985
EEU-1515
SM78K4 System Simulator Windows Based
Reference
U10093J
U10093E
SM78K Series System Simulator
External Part User Open U10092J
U10092E
Interface Specifications
ID78K4-NS Integrated Debugger PC Based
Reference
U12796J
U12796E
ID78K4 Integrated Debugger Windows Based
Reference
U10440J
U10440E
ID78K4 Integrated Debugger
Reference
U11960J
U11960E
HP-UX, SunOS, NEWS-OS Based
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
PD78F4046
38
Data Sheet U11447EJ2V0DS00
Documents Related to Embedded Software (User's Manuals)
Document
Document No.
Japanese
English
78K/IV Series Real-Time OS
Fundamentals
U10603J
U10603E
Installation
U10604J
U10604E
Debugger
U10364J
78K/IV Series OS MX78K4
Fundamental
U11779J
Other Documents
Document
Document No.
Japanese
English
SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)
X13769X
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Devices
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by
C11892J
C11892E
Electrostatic Discharge (ESD)
Guide to Microcomputer-Related Products by Third Parties
U11416J
Caution
The related documents listed above are subject to change without notice. Be sure to use the latest
version of each document for designing.
PD78F4046
39
Data Sheet U11447EJ2V0DS00
[MEMO]
PD78F4046
40
Data Sheet U11447EJ2V0DS00
[MEMO]
PD78F4046
41
Data Sheet U11447EJ2V0DS00
[MEMO]
PD78F4046
42
Data Sheet U11447EJ2V0DS00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Windows is either a registered trademark or a trademark of Microsoft Corporation in
the United States and/or other countries.
PC/AT is a trademark of International Business Machines Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems Inc.
NEWS and NEWS-OS are trademarks of Sony Corporation.
PD78F4046
43
Data Sheet U11447EJ2V0DS00
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
J00.7
PD78F4046
44
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
M8E 00. 4
The information in this document is current as of July, 2000. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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