MOS INTEGRATED CIRCUIT

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

16-BIT SINGLE-CHIP MICROCONTROLLERS

Document No. U14125EJ1V0DS00 (1st edition)
Date Published November 2000 N CP(K)
Printed in Japan

DATA SHEET

DESCRIPTION

The

PD78F4216A/78F4218A and 78F4216AY/78F4218AY are products of

PD784216A/784218A,

784216AY/784218AY Subseries in the 78K/IV Series.

The

PD78F4216A/78F4218A have flash memory in place of the internal ROM of the

PD784216A/784218A. The

incorporation of flash memory allows a program to be written or erased while mounted on the target board.

The

PD78F4216AY/78F4218AY are based on the

PD78F4216A/78F4218A Subseries with the addition of a

multimaster-supporting I

C bus interface.

Detailed function descriptions are provided in the following user's manuals. Be sure to read them before

designing.

µ
µ
µ
µ

PD784216A, 784216AY Subseries User's Manual Hardware: U13570E

µ
µ
µ
µ

PD784218A, 784218AY Subseries User's Manual Hardware: U12970E

78K/IV Series User's Manual Instructions:

U10905E

FEATURES

Pin compatible with the mask ROM products

Flash memory: 128 KB (

PD78F4216A/78F4216AY)

256 KB (

PD78F4218A/78F4218AY)

Internal RAM: 8,192 bytes (

PD78F4216A/78F4216AY)

12,800 bytes (

PD78F4218A/78F4218AY)

Supply voltage: V

= 1.9 to 5.5 V

APPLICATIONS

Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment

Unless otherwise specified, references in this document to the

µ
µ
µ
µ

PD78F4218AY refer to the

µ
µ
µ
µ

PD78F4216A,

78F4218A, 78F4216AY, and 78F4218AY.

2000

The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

78K/IV SERIES LINEUP

PD784026

PD784956A

PD784908

PD784915

PD784928

PD784928Y

PD784046

PD784054

PD784216A

PD784216AY

PD784038

PD784038Y

PD784225Y

PD784225

PD784218AY

PD784218A

Enhanced
A/D converter,
16-bit timer, and
power management

Enhanced internal memory capacity
Pin-compatible with the PD784026

Supports I

C bus

Supports multimaster I

C bus

80-pin, ROM correction added

Supports multimaster I

C bus

Enhanced internal memory
capacity, ROM correction added

100-pin, enhanced I/O and
internal memory capacity

On-chip 10-bit A/D converter

For DC inverter control

On-chip IEBus

controller

Software servo control
On-chip analog circuit for VCRs
Enhanced timer

Supports multimaster I

C bus

Enhanced functions
of the PD784915

Standard models

ASSP models

Supports multimaster I

C bus

: Products in mass-production

: Products under development

PD784976

On-chip VFD controller/driver

PD784938A

Enhanced functions of the
PD784908, enhanced
internal memory capacity,
ROM correction added.

PD784967

Enhanced functions of the
PD784938A, enhanced
I/O and internal memory
capacity.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

OVERVIEW OF FUNCTIONS (1/2)

Part Number

Item

PD78F4216A,

PD78F4216AY

PD78F4218A,

PD78F4218AY

Number of basic instructions (mnemonics)

113

General-purpose registers

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory

mapping)

Minimum instruction execution time

160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@f

= 12.5 MHz operation with

main system clock)

s (@f

= 32.768 kHz operation with subsystem clock)

Flash memory

128 KB

256 KB

Internal

memory

RAM

8,192 bytes

12,800 bytes

Memory space

1 MB with program and data spaces combined

Total

CMOS input

CMOS I/O

I/O ports

N-ch open-drain I/O

Pins with pull-up resistor

LED direct drive output

Pins with

additional

functions

Note 1

Middle-voltage pin

Real-time output port

4 bits

2 or 8 bits

Timer/event counter:

Timer counter

Pulse output

(16-bit)

Capture/compare register

PPG output

Square wave output

One-shot pulse output

Timer/event counter 1: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 2: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 5: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 6: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter 7: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Timer/event counter

Timer/event counter 8: Timer counter

Pulse output

(8-bit) Compare

PWM output

Square wave output

Serial interface

UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator)

CSI (3-wire serial I/O, multimaster supporting I

C bus

Note 2

): 1 channel

A/D converter

8-bit resolution

8 channels

D/A converter

8-bit resolution

2 channels

Notes 1. Pins with additional functions are included with the I/O pins.

PD78F4216AY, 78F4218AY only

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

OVERVIEW OF FUNCTIONS (2/2)

Part Number

Item

PD78F4216A,

PD78F4216AY

PD78F4218A,

PD78F4218AY

Clock output

Selectable from f

, f

/2, f

, f

Buzzer output

Selectable from f

, f

Watch timer

1 channel

Watchdog timer

1 channel

Standby

HALT/STOP/IDLE modes

In low power consumption mode (with subsystem clock): HALT/IDLE modes

Hardware sources

29 (internal: 20, external: 9)

Software sources

BRK instruction, BRKCS instruction, operand error

Non-maskable

Internal: 1, external: 1

Interrupt

Maskable

Internal: 19, external: 8

4 programmable priority levels

3 service modes: Vectored interrupt/macro service/context switching

Supply voltage

= 1.9 to 5.5 V

Package

100-pin plastic LQFP (fine pitch) (14

14)

100-pin plastic QFP (14

20)

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

CONTENTS

1. DIFFERENCES AMONG MODELS IN

µ
µ
µ
µ

PD784216A/784216AY, 784218A/784218AY

SUBSERIES ............................................................................................................................................. 7

2. PIN CONFIGURATION (TOP VIEW) ................................................................................................... 8

3. BLOCK DIAGRAM ............................................................................................................................... 11

4. PIN FUNCTIONS .................................................................................................................................. 12

4.1 Port Pins ..................................................................................................................................... 12

4.2 Non-Port Pins ............................................................................................................................. 14

4.3 Pin I/O Circuits and Recommended Connections of Unused Pins ....................................... 16

5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................ 20

6. PROGRAMMING FLASH MEMORY..................................................................................................... 22

6.1 Selecting Communication Mode .............................................................................................. 22

6.2 Flash Memory Programming Function .................................................................................... 23

6.3 Connecting Flashpro ll and Flashpro lll ................................................................................... 24

7. ELECTRICAL SPECIFICATIONS ........................................................................................................ 25

8. PACKAGE DRAWINGS ....................................................................................................................... 47

9. RECOMMENDED SOLDERING CONDITIONS .................................................................................. 49

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 50

APPENDIX B. RELATED DOCUMENTS ................................................................................................ 53

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

1. DIFFERENCES AMONG MODELS IN

µ
µ
µ
µ

PD784216A/784216AY, 784218A/784218AY SUBSERIES

The only difference among the

PD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal

memory capacity.

The

PD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I

C bus

control function.

The

PD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory

instead of the mask ROM of the above models.

These differences are summarized in Table 1-1.

Table 1-1. Differences Among Models in

µ
µ
µ
µ

PD784216A/784216AY, 784218A/784218AY Subseries

Part Number

Item

PD784214A,

PD784214AY

PD784215A,

PD784215AY

PD784216A,

PD784216AY

PD784217A,

PD784217AY

PD784218A,

PD784218AY

PD78F4216A,

PD78F4216AY

PD78F4218A,

PD78F4218AY

Internal ROM

96 KB

(Mask

ROM)

128 KB (Mask ROM)

192 KB

(Mask

ROM)

256 KB

(Mask

ROM)

128 KB

(Flash

memory)

256 KB

(Flash

memory)

Internal RAM

3,584 bytes

5,120 bytes

8,192 bytes

12,800 bytes

8,192

bytes

12,800

bytes

Internal memory size

switching register

(IMS)

Not provided

Provided

Note

ROM correction

Not provided

Provided

Not

provided

Provided

External access status

function

Not provided

Provided

Not

provided

Provided

Supply voltage

= 1.8 to 5.5 V

= 1.9 to 5.5 V

Electrical

specifications

Recommended

soldering conditions

Refer to the data sheet for each device.

EXA pin

Not provided

Provided

Not

provided

Provided

TEST pin

Provided

Not provided

Provided

Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory

size switching register (IMS).

Caution There are differences in noise immunity and noise radiation between the flash memory and mask

ROM versions. When pre-producing an application set with the flash memory version and then

mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the

commercial samples (not engineering samples) of the mask ROM version.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

2. PIN CONFIGURATION (TOP VIEW)

·
·
·
·

100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD78F4216AGC-8EU,

µ
µ
µ
µ

PD78F4218AGC-8EU,

µ
µ
µ
µ

PD78F4216AYGC-8EU,

µ
µ
µ
µ

PD78F4218AYGC-8EU

Notes 1. Connect the V

pin to V

directly or via a pull-down resistor in normal operation mode. Connect the

pin to V

via a pull-down resistor in a system in which the on-chip flash memory is written while

mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a

resistance ranging from 470

to 10 k

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are available in the

PD78F4216AY, 78F4218AY only.

5. The EXA pin is available in the

PD78F4218A, 78F4218AY only.

100

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Note 2

REF0

P10/ANI0

P62/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P95

P94

P93

P92

P91

P90

Note 1

P37/EXA

Note 5

P36/TI01

P35/TI00

P34/TI2

P33/TI1

P32/TO2

P31/TO1

P30/TO0

P103/TI8/TO8

P102/TI7/TO7

P101/TI6/TO6

P100/TI5/TO5

P67/ASTB

P66/WAIT

P65/WR

P64/RD

P63/A19

P11/ANI1

P12/ANI2

P13/ANI3

P14/ANI4

P15/ANI5

P16/ANI6

P17/ANI7

Note 3

P130/ANO0

P131/ANO1

REF1

P70/RxD2/SI2

P71/TxD2/SO2

P72/ASCK2/SCK2

P20/RxD1/SI1

P21/TxD1/SO1

P22/ASCK1/SCK1

P23/PCL

P24/BUZ

P25/SI0/SDA0

Note 4

P26/SO0

P27/SCK0/SCL0

Note 4

P80/A0

P81/A1

P82/A2

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

·
·
·
·

100-pin plastic QFP (14

×
×
×
×

20)

µ
µ
µ
µ

PD78F4216AGF-3BA,

µ
µ
µ
µ

PD78F4218AGF-3BA,

µ
µ
µ
µ

PD78F4216AYGF-3BA,

µ
µ
µ
µ

PD78F4218AYGF-3BA

Notes 1. Connect the V

pin to V

directly or via a pull-down resistor in normal operation mode. Connect the

pin to V

via a pull-down resistor in a system in which the on-chip flash memory is written while

mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a

resistance ranging from 470

to 10 k

2. Connect the AV

pin to V

3. Connect the AV

pin to V

4. The SCL0 and SDA0 pins are available in the

PD78F4216AY, 78F4218AY only.

5. The EXA pin is available in the

PD78F4218A, 78F4218AY only.

100

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

P42/AD2

P41/AD1

P40/AD0

P87/A7

P86/A6

P85/A5

P84/A4

P83/A3

P82/A2

P81/A1

P80/A0

P27/SCK0/SCL0

Note 4

P26/SO0

P25/SI0/SDA0

Note 4

P24/BUZ

P23/PCL

P22/ASCK1/SCK1

P21/TxD1/SO1

P20/RxD1/SI1

P72/ASCK2/SCK2

P71/TxD2/SO2

P70/RxD2/SI2

REF1

P131/ANO1

P130/ANO0

Note 3

P17/ANI7

P16/ANI6

P15/ANI5

P14/ANI4

P13/ANI3

P12/ANI2

P11/ANI1

P10/ANI0

REF0

Note 2

P60/A16

P61/A17

P62/A18

P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

P100/TI5/TO5

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

P30/TO0

P31/TO1

P32/TO2

P33/TI1

P34/TI2

P35/TI00

P36/TI01

P37/EXA

Note 5

Note 1

P90

P91

P92

P93

P94

P95

P120/RTP0

P121/RTP1

P122/RTP2

P123/RTP3

P124/RTP4

P125/RTP5

P126/RTP6

P127/RTP7

XT2

XT1

RESET

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3

P04/INTP4

P05/INTP5

P06/INTP6

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

A0 to A19:

Address Bus

P120 to P127:

Port 12

AD0 to AD7:

Address/Data Bus

P130, P131:

Port 13

ANI0 to ANI7:

Analog Input

PCL:

Programmable Clock

ANO0, ANO1:

Analog Output

RD:

Read Strobe

ASCK1, ASCK2:

Asynchronous Serial Clock

RESET:

Reset

ASTB:

Address Strobe

RTP0 to RTP7:

Real-time Output Port

Analog Power Supply

RxD1, RxD2:

Receive Data

REF0

, AV

REF1

Analog Reference Voltage

SCK0 to SCK2:

Serial Clock

Analog Ground

SCL0

Note 1

Serial Clock

BUZ:

Buzzer Clock

SDA0

Note 1

Serial Data

EXA

Note 2

External Access Status Output

SI0 to SI2:

Serial Input

INTP0 to INTP6:

Interrupt from Peripherals

SO0 to SO2:

Serial Output

NMI:

Non-maskable Interrupt

TI00, TI01,

P00 to P06:

Port 0

TI1, TI2, TI5 to TI8:

Timer Input

P10 to P17:

Port 1

TO0 to TO2, TO5 to TO8: Timer Output

P20 to P27:

Port 2

TxD1, TxD2:

Transmit Data

P30 to P37:

Port 3

Power Supply

P40 to P47:

Port 4

Programming Power Supply

P50 to P57:

Port 5

Ground

P60 to P67:

Port 6

WAIT:

Wait

P70 to P72:

Port 7

WR:

Write Strobe

P80 to P87:

Port 8

X1, X2:

Crystal (Main System Clock)

P90 to P95:

Port 9

XT1, XT2:

Crystal (Subsystem Clock)

P100 to P103:

Port 10

Notes 1. The SCL0 and SDA0 pins are available in the

PD78F4216AY, 78F4218AY only.

2. The EXA pin is available in the

PD78F4218A, 78F4218AY only.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

3. BLOCK DIAGRAM

Notes 1. This function supports the I

C bus interface and is available in the

PD78F4216AY, 78F4218AY only.

2. The EXA pin is available in the

PD78F4218A, 78F4218AY only.

INTP2/NMI

INTP0, INTP1,

INTP3 to INTP6

Programmable
interrupt
controller

Real-time
output port

Timer/event

counter 7

(8 bits)

Timer/event

counter 6

(8 bits)

Timer/event

counter 5

(8 bits)

Timer/event

counter 2

(8 bits)

Timer/event

counter 1

(8 bits)

Timer/event

counter

(16 bits)

Watch timer

Timer/event

counter 8

(8 bits)

Watchdog timer

TI00
TI01

TO0

TI1

TO1

TI2

TO2

TI5/TO5

TI6/TO6

TI7/TO7

TI8/TO8

NMI/INTP2

RTP0 to RTP7

Clock output
control

A/D
converter

PCL

BUZ

REF0

ANI0 to ANI7

D/A
converter

ANO0

P03/INTP3

REF1

ANO1

78K/IV

CPU core

Flash

memory

RAM

Baud-rate
generator

RxD1/SI1

TxD1/SO1

ASCK1/SCK1

RxD2/SI2

TxD2/SO2

ASCK2/SCK2

SI0/SDA0

Note 1

SO0
SCK0/SCL0

Note 1

Bus I/F

UART/IOE1

ASTB

WR
WAIT

A0 to A7

AD0 to AD7

A8 to A15

A16 to A19

Port 1

P10 to P17

Port 0

P00 to P06

Port 2

P20 to P27

Port 3

P30 to P37

Port 4

P40 to P47

Port 5

P50 to P57

Port 6

P60 to P67

Port 7

P70 to P72

Port 8

P80 to P87

Port 9

P90 to P95

Port 10

P100 to P103

Port 12

P120 to P127

Port 13

P130, P131

Buzzer output

System control

RESET

XT2

XT1

Clocked
serial
interface

Baud-rate
generator

UART/IOE2

EXA

Note 2

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4. PIN FUNCTIONS

4.1 Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

P00

INTP0

P01

INTP1

P02

INTP2/NMI

P03

INTP3

P04

INTP4

P05

INTP5

P06

I/O

INTP6

Port 0 (P0):

7-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P10 to P17

Input

ANI0 to ANI7

Port 1 (P1):

8-bit input only port

P20

RxD1/SI1

P21

TxD1/SO1

P22

ASCK1/SCK1

P23

PCL

P24

BUZ

P25

SI0/SDA0

Note 1

P26

SO0

P27

I/O

SCK0/SCL0

Note 1

Port 2 (P2):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P30

TO0

P31

TO1

P32

TO2

P33

TI1

P34

TI2

P35

TI00

P36

TI01

P37

I/O

EXA

Note 2

Port 3 (P3):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P40 to P47

I/O

AD0 to AD7

Port 4 (P4):

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be

specified by means of software.

LEDs can be driven directly.

P50 to P57

I/O

A8 to A15

Port 5 (P5):

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be

specified by means of software.

LEDs can be driven directly.

Notes 1. This SDA0 and SCL0 are available in the

PD78F4216AY, 78F4218AY only.

2. This function is available in the

PD78F4218A, 784218AY only.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.1 Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

P60

A16

P61

A17

P62

A18

P63

A19

P64

P65

P66

WAIT

P67

I/O

ASTB

Port 6 (P6):

8-bit I/O port

Input/output can be specified in 1-bit units.

When used as an input port, an on-chip pull-up resistor can be

specified by means of software.

P70

RxD2/SI2

P71

TxD2/SO2

P72

I/O

ASCK2/SCK2

Port 7 (P7):

3-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P80 to P87

I/O

A0 to A7

Port 8 (P8):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

The interrupt control flag (KRIF) is set to 1 when a falling edge is

detected at a pin of this port.

P90 to P95

I/O

Port 9 (P9):

N-ch open-drain middle-voltage I/O port

6-bit I/O port

Input/output can be specified in 1-bit units.

LEDs can be driven directly.

P100

TI5/TO5

P101

TI6/TO6

P102

TI7/TO7

P103

I/O

TI8/TO8

Port 10 (P10):

4-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P120 to P127

I/O

RTP0 to RTP7

Port 12 (P12):

8-bit I/O port

Input/output can be specified in 1-bit units.

Whether specifying input mode or output mode, an on-chip pull-up

resistor can be specified in 1-bit units by means of software.

P130, P131

I/O

ANO0, ANO1

Port 13 (P13):

2-bit I/O port

Input/output can be specified in 1-bit units.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.2

Non-Port Pins (1/2)

Pin Name

I/O

Alternate Function

Function

TI00

P35

External count clock input to 16-bit timer counter

TI01

P36

Capture trigger signal input to capture/compare register 00

TI1

P33

External count clock input to 8-bit timer counter 1

TI2

P34

External count clock input to 8-bit timer counter 2

TI5

P100/TO5

External count clock input to 8-bit timer counter 5

TI6

P101/TO6

External count clock input to 8-bit timer counter 6

TI7

P102/TO7

External count clock input to 8-bit timer counter 7

TI8

Input

P103/TO8

External count clock input to 8-bit timer counter 8

TO0

P30

16-bit timer output (shared by 14-bit PWM output)

TO1

P31

TO2

P32

TO5

P100/TI5

TO6

P101/TI6

TO7

P102/TI7

TO8

Output

P103/TI8

8-bit timer output (shared by 8-bit PWM output)

RxD1

P20/SI1

Serial data input (UART1)

RxD2

Input

P70/SI2

Serial data input (UART2)

TxD1

P21/SO1

Serial data output (UART1)

TxD2

Output

P71/SO2

Serial data output (UART2)

ASCK1

P22/SCK1

Baud rate clock input (UART1)

ASCK2

Input

P72/SCK2

Baud rate clock input (UART2)

SI0

P25/SDA0

Note

Serial data input (3-wire serial I/O 0)

SI1

P20/RxD1

Serial data input (3-wire serial I/O 1)

SI2

Input

P70/RxD2

Serial data input (3-wire serial I/O 2)

SO0

P26

Serial data output (3-wire serial I/O 0)

SO1

P21/TxD1

Serial data output (3-wire serial I/O 1)

SO2

Output

P71/TxD2

Serial data output (3-wire serial I/O 2)

SDA0

Note

P25/SI0

Serial data input/output (I

C bus)

SCK0

P27/SCL0

Note

Serial clock input/output (3-wire serial I/O 0)

SCK1

P22/ASCK1

Serial clock input/output (3-wire serial I/O 1)

SCK2

P72/ASCK2

Serial clock input/output (3-wire serial I/O 2)

SCL0

Note

I/O

P27/SCK0

Serial clock input/output (I

C bus)

NMI

P02/INTP2

Non-maskable interrupt request input

INTP0

P00

INTP1

P01

INTP2

P02/NMI

INTP3

P03

INTP4

P04

INTP5

P05

INTP6

Input

P06

External interrupt request input

Note This function is available in the

PD78F4216AY, 78F4218AY only.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.2 Non-Port Pins (2/2)

Pin Name

I/O

Alternate Function

Function

PCL

Output

P23

Clock output (for trimming main system clock and subsystem clock)

BUZ

Output

P24

Buzzer output

RTP0 to RTP7

Output

P120 to P127

Real-time output port that outputs data in synchronization with

trigger

AD0 to AD7

I/O

P40 to P47

Lower address/data bus for expanding memory externally

A0 to A7

P80 to P87

Lower address bus for expanding memory externally

A8 to A15

P50 to P57

Middle address bus for expanding memory externally

A16 to A19

Output

P60 to P63

Higher address bus for expanding memory externally

P64

Strobe signal output for reading from external memory

Output

P65

Strobe signal output for writing to external memory

WAIT

Input

P66

Wait insertion at external memory access

ASTB

Output

P67

Strobe output that externally latches address information output to

ports 4 through 6 and 8 to access external memory

EXA

Note

Output

P37

Status signal output at external memory access

RESET

Input

System reset input

Input

Connecting crystal resonator for main system clock oscillation

XT1

Input

XT2

Connecting crystal resonator for subsystem clock oscillation

ANI0 to ANI7

Input

P10 to P17

A/D converter analog input

ANO0, ANO1

Output

P130, P131

D/A converter analog output

REF0

A/D converter reference voltage input

REF1

D/A converter reference voltage input

A/D converter positive power supply. Connect to V

GND for A/D converter and D/A converter. Connect to V

Positive power supply

GND

Flash memory programming mode setting.

Applying high-voltage for program write/verify. Connect this pin to

directly or via a pull-down resistor in normal operation mode.

Connect the V

pin to V

via a pull-down resistor in a system in

which the on-chip flash memory is written while mounted on the

target board. For the pull-down connection, it is recommended to

use a resistor with a resistance ranging from 470

to 10 k

Note The EXA pin is available in the

PD78F4218A, 78F4218AY only.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

4.3 Pin I/O Circuits and Recommended Connections of Unused Pins

The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 4-1.
For each type of input/output circuit, refer to Figure 4-1.

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

P00/INTP0

P01/INTP1

P02/INTP2/NMI

P03/INTP3 to P06/INTP6

8-N

I/O

Input:

Independently connect to V

via a resistor

Output: Leave open

P10/ANI0 to P17/ANI7

Input

Connect to V

or V

P20/RxD1/SI1

10-K

P21/TxD1/SO1

10-L

P22/ASCK1/SCK1

10-K

P23/PCL

P24/BUZ

10-L

P25/SI0/SDA0

Note 1

10-K

P26/SO0

10-L

P27/SCK0/SCL0

Note 1

10-K

P30/TO0 to P32/TO2

12-E

P33/TI1, P34/TI2

8-N

P35/TI00, P36/TI01

10-M

P37/EXA

Note 2

12-E

P40/AD0 to P47/AD7

P50/A8 to P57/A15

P60/A16 to P63/A19

P64/RD

P65/WR

P66/WAIT

P67/ASTB

5-A

P70/RxD2/SI2

8-N

P71/TxD2/SO2

10-M

P72/ASCK2/SCK2

8-N

P80/A0 to P87/A7

12-E

P90 to P95

13-D

P100/TI5/TO5

P101/TI6/TO6

P102/TI7/TO7

P103/TI8/TO8

8-N

P120/RTP0 to P127/RTP7

12-E

P130/ANO0, P131/ANO1

12-F

I/O

Input:

Independently connect to V

via a resistor

Output: Leave open

Notes 1. The SDA0 and SCL0 pins are available in the

PD78F4216AY, 78F4218AY only.

2. The EXA pin is available in the

PD78F4218A, 78F4218AY only.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)

Pin Name

I/O Circuit Type

I/O

Recommended Connection of Unused Pins

RESET

2-G

XT1

Input

Connect to V

XT2

Leave open

REF0

Connect to V

REF1

Connect to V

Connect this pin to V

directly or via a pull-down resist in normal

operation mode. Connect the V

pin to V

via a pull-down

resistor in a system in which the on-chip flash memory is written

while mounted on the target board.

For the pull-down connection, it is recommended to use a resistor

with a resistance ranging from 470

to 10 k

Remark Because the circuit type numbers are standardized among the 78K Series products, they are not

sequential in some models (i.e., some circuits are not provided).

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Figure 4-1. Types of Pin I/O Circuits (1/2)

Pullup
enable

Data

Output
disable

Input
enable

P-ch

IN/OUT

N-ch

Pullup
enable

Data

Output
disable

P-ch

IN/OUT

N-ch

Pullup

enable

Data

Open drain

Output disable

P-ch

IN/OUT

N-ch

Pullup

enable

Data

Open drain

Output disable

P-ch

IN/OUT

N-ch

Pullup

enable

Data

P-ch

IN/OUT

N-ch

Pullup
enable

Data

Output
disable

Input
enable

P-ch

IN/OUT

N-ch

P-ch

N-ch

Comparator

P-ch

N-ch

Input
enable

Type 2-G

Type 5-A

Type 8-N

Type 9

(Threshold voltage)

Analog output
voltage

Type 12-E

Type 10-M

Type 10-L

Type 10-K

Schmitt-triggered input with hysteresis characteristics

REF

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

5. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)

IMS is a register that is set by software and is used to specify a part of the internal memory that is not to be used.

By setting this register, the internal memory of the

PD78F4218AY can be mapped identically to that of a mask ROM

version with a different internal memory (ROM and RAM) capacity.

IMS is set with an 8-bit memory manipulation instruction.

RESET input sets IMS to FFH.

(1)

µ
µ
µ
µ

PD78F4216A, 78F4216AY

Figure 5-1. Internal Memory Size Switching Register (IMS) Format

Address: 0FFFCH

After reset: FFH W

IMS

ROM1

ROM0

RAM1

RAM0

ROM1

ROM0

Internal ROM Capacity Selection

48 KB

64 KB

96 KB

128 KB

RAM1

RAM0

Peripheral RAM Capacity Selection

3,072 bytes

4,608 bytes

6,114 bytes

7,680 bytes

Caution IMS is not provided on the mask ROM versions (

µ
µ
µ
µ

PD784214A, 784215A, 784216A,

µ
µ
µ
µ

PD784214AY,

784215AY, and 784216AY).

Table 5-1 shows the IMS setting values to make the memory mapping the same as that of the mask ROM

versions.

Table 5-1. Setting Value of Internal Memory Size Switching Register (IMS)

Target Mask ROM Version

IMS Setting Value

PD784214A, 784214AY

ECH

PD784215A, 784215AY

FDH

PD784216A, 784216AY

FFH

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

(2)

µ
µ
µ
µ

PD78F4218A, 78F4218AY

Figure 5-2. Internal Memory Size Switching Register (IMS) Format

Address: 0FFFCH

After reset: FFH W

IMS

ROM1

ROM0

RAM1

RAM0

ROM1

ROM0

Internal ROM Capacity Selection

64 KB

128 KB

192 KB

256 KB

RAM1

RAM0

Peripheral RAM Capacity Selection

3,072 bytes

6,656 bytes

7,168 bytes

12,288 bytes

Caution IMS is not provided on the mask ROM versions (

µ
µ
µ
µ

PD784217A, 784218A, 784217AY, and

784218AY).

Table 5-2 shows the IMS setting values to make the memory mapping the same as that of the mask ROM

versions.

Table 5-2. Setting Value of Internal Memory Size Switching Register (IMS)

Target Mask ROM Version

IMS Setting Value

PD784217A, 784217AY

EFH

PD784218A, 784218AY

FFH

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

6. PROGRAMMING FLASH MEMORY

The flash memory can be written with the

PD78F4218AY mounted on the target board (on-board). To do so,

connect a dedicated flash programmer (Flashpro II (part number: FL-PR2), Flashpro III (part number: FL-PR3, PG-

FP3) to the host machine and target system.

Writing to flash memory can also be performed using flash memory writing adapter connected to Flashpro II or

Flashpro III.

Remark FL-PR2 and FL-PR3 are products of Naito Densei Machida Mfg. Co., Ltd.

6.1 Selecting Communication Mode

To write the flash memory, use Flashpro II and Flashpro III by serial communication. Select a serial

communication mode from those listed in Table 6-1 in the format shown in Figure 6-1. Each communication mode is

selected by the number of V

pulses shown in Table 6-1.

Table 6-1. Communication Modes

Communication

Mode

Number of

Channels

Pins Used

Number of

Pulses

SCK0/P27/SCL0

Note 1

SO0/P26

SI0/P25/SDA0

Note 1

SCK1/ASCK1/P22

SO1/TxD1/P21

SI1/RxD1/P20

3-wire serial I/O

SCK2/ASCK2/P72

SO2/TxD2/P71

SI2/RxD2/P70

Handshake

Note 2

SCK0/P27/SCL0

Note 1

SO0/P26

SI0/P25/SDA0

Note 1

P24/BUZ

TxD1/SO1/P21

RxD1/SI1/P20

UART

TxD2/SO2/P71

RxD2/SI2/P70

Notes 1. The SCL0 and SDA0 pins are available in the

PD78F4216AY, 78F4218AY only.

2. This made is available in the

PD78F4216A, 78F4216AY (other than I, K, E standard)

This made is available in the

PD78F4218A, 78F4218AY (other than I standard)

Caution Be sure to select a communication mode with the number of V

pulses shown in Table 6-1.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Figure 6-1. Communication Mode Selecting Format

6.2 Flash Memory Programming Function

The flash memory is written by transferring or receiving commands and data in a selected communication mode.

The major functions of flash memory programming are listed in Table 6-2.

Table 6-2. Major Functions of Flash Memory Programming

Function

Description

Batch erasure

Erases all contents of memory.

Block erasure

Erases contents of specified memory block with one memory block

consisting of 16 KB.

Batch blank check

Checks erased status of entire memory.

Block blank check

Checks erased status of specified block.

Data write

Writes flash memory based on write start address and number of

data to be written (in bytes).

Batch verify

Compares all contents of memory with input data.

Block verify

Compares contents of specified memory block with input data.

10 V

RESET

pulses

Flash programming mode

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

6.3 Connecting Flashpro II and Flashpro III

The Flashpro II, Flashpro III and

PD78F4218AY are connected differently depending on the selected

communication mode (3-wire serial I/O or UART). Figures 6-2 to 6-4 show the connections in the respective

communication modes.

Figure 6-2. Connection of Flashpro II and Flashpro III in 3-Wire Serial I/O Mode

Figure 6-3. Connection of Flashpro III in Handshake Mode

Figure 6-4. Connection of Flashpro II and Flashpro III in UART Mode

RESET

SCK0 or SCK1 or SCK2

SI0 or SI1 or SI2

SO0 or SO1 or SO2

Flashpro ll,
Flashpro lll

PD78F4218AY

RESET

SCK0

SI0

SO0

P24

Flashpro lll

PD78F4218AY

RESET

RxD1 or RxD2

TxD1 or TxD2

Flashpro ll,
Flashpro lll

PD78F4218AY

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

7. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25

°
°
°
°

Parameter

Symbol

Conditions

Ratings

Unit

0.3 to +6.5

0.3 to V

+ 0.3

0.3 to V

+ 0.3

REF0

A/D converter reference voltage input

0.3 to V

+ 0.3

Supply voltage

REF1

D/A converter reference voltage input

0.3 to V

+ 0.3

Other than P90 to P95

0.3 to V

+ 0.3

P90 to P95

N-ch open drain

0.3 to +12

Input voltage

pin for programming

0.3 to +10.5

Analog input voltage

Analog input pin

0.3 to AV

REF0

+ 0.3

Output voltage

0.3 to V

+ 0.3

Per pin

Total of P2, P4 to P8

Total of P0, P3, P9, P10, P12, P13

Output current, low

Total of all pins

100

Per pin

Output current, high

Total of all pins

Operating ambient

temperature

40 to +85

Storage temperature

stg

65 to +125

Caution

Product quality may suffer if the absolute maximum rating is exceeded even momentarily for

any parameter. That is, the absolute maximum ratings are rated values at which the product is

on the verge of suffering physical damage, and therefore the product must be used under

conditions that ensure that the absolute maximum ratings are not exceeded.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Operating Conditions

Operating ambient temperature (T

40 to +85

Supply voltage and clock cycle time: See Figure 7-1

Operating voltage with subsystem clock operation: V

= 1.9 to 5.5 V

Figure 7-1. Supply Voltage and Clock Cycle Time (CPU Clock Frequency: f

CPU

)

Capacitance (T

= 25

°
°
°
°

C, V

= V

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Other than Port 9

Input capacitance

Port 9

Other than Port 9

Output capacitance

Port 9

Other than Port 9

I/O capacitance

f = 1 MHz

Unmeasured pins

returned to 0 V.

Port 9

8,000

10,000

500

400

300

320

160

200

100

1.9

2.7

4.5

5.5

Supply voltage [V]

Clock cycle time t

CYK

[ns]

Guaranteed

operating range

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Main System Clock Oscillator Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

12.5

2.7 V

< 4.5 V

6.25

2.0 V

< 2.7 V

3.125

Ceramic

resonator

or crystal

resonator

X1 V

Oscillation frequency

)

1.9 V

< 2.0 V

MHz

4.5 V

5.5 V

12.5

2.7 V

< 4.5 V

6.25

2.0 V

< 2.7 V

3.125

X1 input frequency (f

)

1.9 V

< 2.0 V

MHz

X1 input high-/low-

level width (t

WXH

, t

WXL

)

250

4.5 V

5.5 V

2.7 V

< 4.5 V

2.0 V

< 2.7 V

External

clock

PD74HCU04

X1 input rising/falling

time (t

, t

)

1.9 V

< 2.0 V

Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

·
·
·
·

Keep the wiring length as short as possible.

·
·
·
·

Do not cross the wiring with other signal lines.

·
·
·
·

Do not route the wiring near a signal line through which a high fluctuating current flows.

·
·
·
·

Always make the ground point of the oscillator capacitor the same potential as V

·
·
·
·

Do not ground the capacitor to a ground pattern through which a high current flows.

·
·
·
·

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the system is operated by the subsystem clock,

the subsystem clock should be switched back to the main system clock after the oscillation

stabilization time is secured by the program.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Subsystem Clock Oscillator Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

Resonator

Recommended Circuit

Parameter

Conditions

MIN.

TYP.

MAX.

Unit

Oscillation frequency

)

32.768

kHz

4.5 V

5.5 V

1.2

Crystal

resonator

XT2

XT1

Oscillation

stabilization time

Note

1.9 V

< 4.5 V

XT1 input frequency

)

kHz

External

clock

XT2

XT1

PD74HCU04

XT1 input high-/low-

level width (t

XTH

, t

XTL

)

14.3

15.6

Note Time required to stabilize oscillation after applying supply voltage (V

Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the

broken lines in the above figures to avoid an adverse effect from wiring capacitance.

·
·
·
·

Keep the wiring length as short as possible.

·
·
·
·

Do not cross the wiring with other signal lines.

·
·
·
·

Do not route the wiring near a signal line through which a high fluctuating current flows.

·
·
·
·

Always make the ground point of the oscillator capacitor the same potential as V

·
·
·
·

Do not ground the capacitor to a ground pattern through which a high current flows.

·
·
·
·

Do not fetch signals from the oscillator.

2. When the main system clock is stopped and the device is operating on the subsystem clock,

wait until the oscillation stabilization time has been secured by the program before switching

back to the main system clock.

Remark For the resonator selection and oscillator constant, users are required to either evaluate the oscillation

themselves or apply to the resonator manufacturer for evaluation.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V) (1/3)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.2 V

5.5 V

0.3V

IL1

Note 1

1.9 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.2V

IL2

P00 to P06, P20, P22, P33,

P34, P70, P72,

P100 to P103, RESET

1.9 V

< 2.2 V

0.15V

2.2 V

5.5 V

0.3V

IL3

P90 to P95

(N-ch open drain)

1.9 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.3V

IL4

P10 to P17, P130, P131

1.9 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.2V

IL5

X1, X2, XT1, XT2

1.9 V

< 2.2 V

0.1V

2.2 V

5.5 V

0.3V

Input voltage, low

IL6

P25, P27

1.9 V

< 2.2 V

0.2V

2.2 V

5.5 V

0.7V

IH1

Note 1

1.9 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.8V

IH2

P00 to P06, P20, P22, P33,

P34, P70, P72,

P100 to P103, RESET

1.9 V

< 2.2 V

0.85V

2.2 V

5.5 V

0.7V

IH3

P90 to P95

(N-ch open drain)

1.9 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.7V

IH4

P10 to P17, P130, P131

1.9 V

< 2.2 V

0.8V

2.2 V

5.5 V

0.8V

IH5

X1, X2, XT1, XT2

1.9 V

< 2.2 V

0.85V

2.2 V

5.5 V

0.7V

Input voltage, high

IH6

P25, P27

1.9 V

< 2.2 V

0.8V

For pins other than

P40 to P47, P50 to P57,

P90 to P95 I

= 1.6 mA

Note 1

4.5 V

5.5 V

0.4

P40 to P47, P50 to P57

= 8 mA

Note 2

4.5 V

5.5 V

1.0

OL1

P90 to P95 I

= 15 mA

Note 2

4.5 V

5.5 V

0.8

2.0

Output voltage, low

OL2

= 400

Note 2

0.5

1 mA

Note 2

4.5 V

5.5 V

1.0

Output voltage, high

OH1

100

Note 2

0.5

LIL1

Except X1, X2, XT1,
XT2

Input leakage current, low

LIL2

= 0 V

X1, X2, XT1, XT2

LIH1

Except X1, X2, XT1,
XT2

LIH2

= V

X1, X2, XT1, XT2

Input leakage current, high

LIH3

= 12 V (N-ch open drain) P90 to P95

Output leakage current, low

LOL1

OUT

= 0 V

Output leakage current, high

LOH1

OUT

= V

Notes 1. P21, P23, P24, P26, P30 to P32, P35 to P37, P40 to P47, P50 to P57, P60 to P67, P71, P80 to P87,

P120 to P127

2. Per pin

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V) (2/3)

(1)

µ
µ
µ
µ

PD78F4216A, 78F4216AY

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD1

Operation

mode

= 2 MHz, V

= 2.0 V

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD2

HALT mode

= 2 MHz, V

= 2.0 V

0.4

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

0.5

1.3

DD3

IDLE mode

= 2 MHz, V

= 2.0 V

0.3

0.9

= 32 kHz, V

= 5.0 V

10%

130

500

= 32 kHz, V

= 3.0 V

10%

350

= 32 kHz, 2.0 V

2.7 V

300

DD4

Operation

mode

Note

= 32 kHz, 1.9 V

2.0 V

250

= 32 kHz, V

= 5.0 V

10%

200

= 32 kHz, V

= 3.0 V

10%

160

= 32 kHz, 2.0 V

2.7 V

120

DD5

HALT

mode

Note

= 32 kHz, 1.9 V

2.0 V

100

= 32 kHz, V

= 5.0 V

10%

190

= 32 kHz, V

= 3.0 V

10%

150

= 32 kHz, 2.0 V

2.7 V

110

Supply voltage

DD6

IDLE

mode

Note

= 32 kHz, 1.9 V

2.0 V

Data retention voltage

DDDR

HALT, IDLE modes

1.9

5.5

= 2.0 V

Data retention current

DDDR

STOP mode

= 5.0 V

10%

Pull-up resistor

= 0 V

100

Note When main system clock is stopped and subsystem clock is operating.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

DC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V) (3/3)

(2)

µ
µ
µ
µ

PD78F4218A, 78F4218AY

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD1

Operation

mode

= 3 MHz, V

= 2.0 V

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

DD2

HALT mode

= 3 MHz, V

= 2.0 V

0.5

= 12.5 MHz, V

= 5.0 V

10%

= 6 MHz, V

= 3.0 V

10%

0.5

1.3

DD3

IDLE mode

= 3 MHz, V

= 2.0 V

0.3

0.9

= 32 kHz, V

= 5.0 V

10%

140

500

= 32 kHz, V

= 3.0 V

10%

100

350

= 32 kHz, 2.0 V

2.7 V

300

DD4

Operation

mode

Note

= 32 kHz, 1.9 V

2.0 V

250

= 32 kHz, V

= 5.0 V

10%

200

= 32 kHz, V

= 3.0 V

10%

160

= 32 kHz, 2.0 V

2.7 V

120

DD5

HALT

mode

Note

= 32 kHz, 1.9 V

2.0 V

100

= 32 kHz, V

= 5.0 V

10%

190

= 32 kHz, V

= 3.0 V

10%

150

= 32 kHz, 2.0 V

2.7 V

110

Supply voltage

DD6

IDLE

mode

Note

= 32 kHz, 1.9 V

2.0 V

Data retention voltage

DDDR

HALT, IDLE modes

1.9

5.5

= 2.0 V

Data retention current

DDDR

STOP mode

= 5.0 V

10%

Pull-up resistor

= 0 V

100

Note When main system clock is stopped and subsystem clock is operating.

Remark Unless otherwise specified, the characteristics of alternate-function pins are the same as those of port

pins.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

AC Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

2.7 V

4.5 V

160

2.0 V

2.7 V

320

Cycle time

CYK

1.9 V

2.0 V

500

= 5.0 V

10%

(0.5

a)T

= 3.0 V

10%

(0.5

a)T

Address setup time (to ASTB

)

SAST

= 2.0 V

(0.5

a)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from ASTB

) t

HSTLA

= 2.0 V

0.5T

= 5.0 V

10%

(0.5

a)T

= 3.0 V

10%

(0.5

a)T

ASTB high-level width

WSTH

= 2.0 V

(0.5

a)T

110

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from RD

)

HRA

= 2.0 V

0.5T

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Delay time from address to RD

DAR

= 2.0 V

a)T

= 5.0 V

10%

= 3.0 V

10%

Address float time (from RD

)

FAR

= 2.0 V

= 5.0 V

10%

(2.5

n)T

= 3.0 V

10%

(2.5

n)T

Data input time from address

DAID

= 2.0 V

(2.5

n)T

120

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Data input time from ASTB

DSTID

= 2.0 V

n)T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Data input time from RD

DRID

= 2.0 V

(1.5

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to RD

DSTR

= 2.0 V

0.5T

= 5.0 V

10%

= 3.0 V

10%

Data hold time (from RD

)

HRID

= 2.0 V

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of waits (n

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

AC Characteristics

(1) Read/write operation (2/2)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address active time from RD

DRA

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from RD

to ASTB

DRST

= 2.0 V

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

RD low-level width

WRL

= 2.0 V

(1.5

n)T

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Delay time from address to WR

DAW

= 2.0 V

a)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Address hold time (from WR

)

HRD

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to data

output

DSTOD

= 2.0 V

0.5T

240

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WR

to data

output

DWOD

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from ASTB

to WR

DSTW

= 2.0 V

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Data setup time (to WR

)

SODWR

= 2.0 V

(1.5

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Data hold time (from WR

)

HWOD

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WR

to ASTB

DWST

= 2.0 V

0.5T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

WR low-level width

WWL

= 2.0 V

(1.5

n)T

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

AC Characteristics

(2) External wait timing

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

= 5.0 V

10%

a)T

= 3.0 V

10%

a)T

Input time from address to

WAIT

DAWT

= 2.0 V

a)T

300

= 5.0 V

10%

1.5T

= 3.0 V

10%

1.5T

Input time from ASTB

WAIT

DSTWT

= 2.0 V

1.5T

260

= 5.0 V

10%

(0.5

n)T

= 3.0 V

10%

(0.5

n)T

Hold time from ASTB

to WAIT

HSTWT

= 2.0 V

(0.5

n)T

= 5.0 V

10%

(1.5

n)T

= 3.0 V

10%

(1.5

n)T

Delay time from ASTB

WAIT

DSTWTH

= 2.0 V

(1.5

n)T

= 5.0 V

10%

= 3.0 V

10%

Input time from RD

to WAIT

DRWTL

= 2.0 V

= 5.0 V

10%

= 3.0 V

10%

Hold time from RD

to WAIT

HRWT

= 2.0 V

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Delay time from RD

to WAIT

DRWTH

= 2.0 V

n)T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Data input time from WAIT

DWTID

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WAIT

to RD

DWTR

= 2.0 V

0.5T

= 5.0 V

10%

0.5T

= 3.0 V

10%

0.5T

Delay time from WAIT

to WR

DWTW

= 2.0 V

0.5T

= 5.0 V

10%

= 3.0 V

10%

Input time from WR

to WAIT

DWWTL

= 2.0 V

= 5.0 V

10%

= 3.0 V

10%

Hold time from WR

to WAIT

HWWT

= 2.0 V

= 5.0 V

10%

n)T

= 3.0 V

10%

n)T

Delay time from WR

to WAIT

DWWTH

= 2.0 V

n)T

Remark T: t

CYK

= 1/f

: main system clock frequency)

a: 1 (during address wait), otherwise, 0

n: Number of wait states (n

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Serial Operation (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

(a) 3-wire serial I/O mode (SCK: Internal clock output)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

5.5 V

800

SCK cycle time

KCY1

3,200

2.7 V

5.5 V

350

SCK high-/low-level width

KH1

KL1

1,500

2.7 V

5.5 V

SI setup time (to SCK

)

SIK1

SI hold time (from SCK

)

KSI1

SO output delay time

(from SCK

)

KSO1

(b) 3-wire serial I/O mode (SCK: External clock input)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

2.7 V

5.5 V

800

SCK cycle time

KCY2

3,200

2.7 V

5.5 V

400

SCK high-/low-level width

KH2

KL2

1,600

2.7 V

5.5 V

SI setup time (to SCK

)

SIK2

SI hold time (from SCK

)

KSI2

SO output delay time

(from SCK

)

KSO2

(c) UART mode

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

417

2.7 V

< 4.5 V

833

ASCK cycle time

KCY3

1,667

4.5 V

5.5 V

208

2.7 V

< 4.5 V

416

ASCK high-/low-level width

KH3

KL3

833

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

(d) I

C bus mode

Standard Mode

High-Speed Mode

Parameter

Symbol

MIN.

MAX.

MIN.

MAX.

Unit

SCL0 clock frequency

CLK

100

400

kHz

Bus free time (between stop

and start conditions)

BUF

4.7

1.3

Hold time

Note1

HD : STA

4.0

0.6

Low-level width of SCL0 clock

LOW

4.7

1.3

High-level width of SCL0 clock

HIGH

4.0

0.6

Setup time of start/restart

conditions

SU : STA

4.7

0.6

When using CBUS-

compatible master

5.0

Data hold

time

When using I

C bus

HD : DAT

Note 2

0.9

Note 3

Data setup time

SU : DAT

250

100

Note 4

Rise time of SDA0 and SCL0

signals

1,000

20 + 0.1Cb

Note 5

300

Fall time of SDA0 and SCL0

signals

300

20 + 0.1Cb

Note 5

300

Setup time of stop condition

SU : STO

4.0

0.6

Pulse width of spike restricted

by input filter

Load capacitance of each bus

line

400

Notes 1. For the start condition, the first clock pulse is generated after the hold time.

2. To fill the undefined area of the SCL0 falling edge, it is necessary for the device to provide an internal

SDA0 signal (on V

IHmin.

) with at least 300 ns of hold time.

3. If the device does not extend the SCL0 signal low-level hold time (t

LOW

), only the maximum data hold

time t

HD : DAT

needs to be satisfied.

4. The high-speed mode I

C bus can be used in a standard mode I

C bus system. In this case, the

conditions described below must be satisfied.

If the device does not extend the SCL0 signal low-level hold time

SU : DAT

250 ns

If the device extends the SCL0 signal low-level hold time

Be sure to transmit the data bit to the SDA0 line before the SCL0 line is released (t

Rmax.

+ t

SU :

DAT

= 1,000 + 250 = 1,250 ns by standard mode I

C bus specification)

5. Cb: Total capacitance per bus line (unit: pF)

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Other Operations (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

NMI high-/low-level width

WNIL

WNIH

Interrupt input high-/low-level width

WITL

WITH

INTP0 to INTP6

100

RESET high-/low-level width

WRSL

WRSH

Clock Output Operation (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

PCL cycle time

CYCL

4.5 V

5.5 V, nT

31,250

PCL high-/low-level width

CLL

CLH

4.5 V

5.5 V, 0.5T

15,615

4.5 V

5.5 V

2.7 V

< 4.5 V

PCL rise/fall time

CLR

CLF

1.9 V

< 2.7 V

Remark T: t

CYK

= 1/f

: Main system clock frequency)

n: Divided frequency ratio set by software in the CPU

When using the main system clock: n = 1, 2, 4, 8, 16, 32, 64, 128

When using the subsystem clock: n = 1

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

A/D Converter Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

bits

2.7 V

5.5 V

2.2 V

REF0

1.2

%FSR

Overall error

Notes 1, 2

1.9 V

< 2.7 V

1.9 V

REF0

1.6

%FSR

Conversion time

CONV

144

Sampling time

SAMP

24/f

Analog input voltage

IAN

REF0

Reference voltage

REF0

1.9

Resistance between AV

REF0

and AV

AVREF0

When not A/D converting

Notes 1. Quantization error (

1/2 LSB) is not included.

2. Overall error is indicated as a ratio to the full-scale value.

Remark f

: Main system clock frequency

D/A Converter Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Resolution

Bits

R = 10 M

, 2.0 V

REF1

2.0 V

5.5 V

0.6

%FSR

Overall error

Notes 1, 2

R = 10 M

, 1.9 V

REF1

1.9 V

2.0 V

1.2

%FSR

4.5 V

REF1

5.5 V

2.7 V

REF1

< 4.5 V

Settling time

Load conditions:

C = 30 pF

1.9 V

REF1

< 2.7 V

Output resistance

DACS0, 1 = 55H

Reference voltage

REF1

1.9

REF1

current

REF1

For only 1 channel

2.5

Notes 1. Quantization error (

1/2 LSB) is not included.

2. Overall error is indicated as a ratio to the full-scale value.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Data Retention Characteristics (T

-
-
-
-

40 to +85

°
°
°
°

C, V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V)

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

Data retention voltage

DDDR

STOP mode

1.9

5.5

DDDR

= 5.0 V

10%

Data retention current

DDDR

= 2.0 V

rise time

RVD

200

fall time

FVD

200

hold time

(from STOP mode setting)

HVD

STOP release signal input time

DREL

Crystal resonator

Oscillation stabilization wait time

WAIT

Ceramic resonator

Low-level input voltage

0.1V

DDDR

High-level input voltage

RESET, P00/INTP0 to P06/INTP6

0.9V

DDDR

AC Timing Test Points

0.8V

or 1.9 V

0.8 V

0.8V

or 1.9 V

0.8 V

Test points

1 V

0.45 V

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Flash Memory Programming Characteristics (V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V, V

= 9.7

to 10.3 V)

(1) Basic characteristics

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

4.5 V

5.5 V

12.5

MHz

2.7 V

< 4.5 V

6.25

MHz

2.0 V

< 2.7 V

3.125

MHz

Operating frequency

1.9 V

< 2.0 V

MHz

1.9

5.5

PPL

Upon V

low-level detection

0.2V

Upon V

high-level detection

0.9V

1.1V

Supply voltage

Note 1

PPH

Upon V

high-voltage detection

9.7

10.3

supply current

= 10 V

100

Write count

WRT

Note2

Times

Operating temperature

Note 3

Storage temperature

Note 4

stg

125

Programming temperature

PRG

Notes 1.

PD78F4216A, 78F4216AY

K standard: 2.7 V

5.5 V, V

= 10.3

0.3 V

E standard: 2.7 V

5.5 V, V

= 10.0

0.3 V

2. Operation cannot be guaranteed when the number of writes exceeds 20 times. In the case of the

PD78F4216A and 78F4216AY with K standard, operation cannot be guaranteed when the number of

writes exceeds 5 times.

PD78F4216A, 78F4216AY K standard: T

10 to +60

PD78F4216A, 78F4216AY K standard: T

10 to +80

Cautions 1. If writing is not successful in write operation, execute the program command again, and

execute the verify command to confirm the normal completion of the write operation.

(

µ
µ
µ
µ

PD78F4216A, 78F4216AY: I, K, E, P standard)

2. Handshake mode is supported by the following products.

µ
µ
µ
µ

PD78F4216A, 78F4216AY: Other than I, K, E standard

µ
µ
µ
µ

PD78F4218A, 78F4218AY: Other than I standard

Remark The fifth alphabetic character from the left in the lot number indicates the standard of the product. After

executing the program command, execute the verify command to confirm the normal completion of the

write operation.

Handshake mode is the CSI write mode that uses P24.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Flash Memory Programming Characteristics (V

= AV

= 1.9 to 5.5 V, V

= AV

= 0 V, V

= 9.7

to 10.3 V)

(2) Serial write operation characteristics

Parameter

Symbol

Conditions

MIN.

TYP.

MAX.

Unit

setup time

PSRON

high voltage

1.0

setup time to V

DRPSR

high voltage

RESET

set up time to V

PSRRF

high voltage

1.0

count start time from RESET

RFCF

1.0

Count execution time

COUNT

1.0

counter high-level width

8.0

counter low-level width

8.0

counter noise elimination width

NFW

Flash Memory Write Mode Setting Timing

0 V

RESET (input)

0 V

PPH

PPL

RFCF

PSRON

PSRRF

DRPSR

COUNT

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

8. PACKAGE DRAWINGS

Remark The external dimensions and material of the ES version are the same as those of the mass-produced

version.

100-PIN PLASTIC LQFP (FINE PITCH) (14x14)

NOTE

Each lead centerline is located within 0.08 mm of
its true position (T.P.) at maximum material condition.

ITEM

MILLIMETERS

16.00

0.20

14.00

0.20

0.50 (T.P.)

1.00

16.00

0.20

14.00

0.20

0.08

1.00

0.20

0.50

0.20

1.00

0.08

1.40

0.05

0.10

0.05

S100GC-50-8EU, 8EA-2

1.60 MAX.

0.22

0.05

0.04

0.17

0.03

0.07

°+

100

detail of lead end

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

9. RECOMMENDED SOLDERING CONDITIONS

The

PD78F4218AY should be soldered and mounted under the following recommended conditions. For the

details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting

Technology Manual (C10535E).

For soldering methods and conditions other than those recommended below, contact your NEC sales

representative.

Table 9-1. Surface Mounting Type Soldering Conditions

(1)

µ
µ
µ
µ

PD78F4216AGC-8EU:100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD78F4218AGC-8EU:100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD78F4216AYGC-8EU:100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14)

µ
µ
µ
µ

PD78F4218AYGC-8EU: 100-pin plastic LQFP (fine pitch) (14

×
×
×
×

14)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or higher),

Count: Two times or less, Exposure limit: 7 days

Note

(after that, prebake at 125

for 10 hours)

IR35-107-2

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or higher),

Count: Two times or less, Exposure limit: 7 days

Note

(after that, prebake at 125

for 10 hours)

VP15-107-2

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Note After opening the dry pack, store it at 25

C or less and 65% RH or less for the allowable storage period.

Caution Do not use different soldering methods together (except for partial heating).

(2)

µ
µ
µ
µ

PD78F4216AGF-3BA:100-pin plastic QFP (14

×
×
×
×

20)

µ
µ
µ
µ

PD78F4218AGF-3BA:100-pin plastic QFP (14

×
×
×
×

20)

µ
µ
µ
µ

PD78F4216AYGF-3BA:100-pin plastic QFP (14

×
×
×
×

20)

µ
µ
µ
µ

PD78F4218AYGF-3BA: 100-pin plastic QFP (14

×
×
×
×

20)

Soldering Method

Soldering Conditions

Recommended

Condition Symbol

Infrared reflow

Package peak temperature: 235

C, Time: 30 seconds max. (at 210

C or higher),

Count: Two times or less

IR35-00-2

VPS

Package peak temperature: 215

C, Time: 40 seconds max. (at 200

C or higher),

Count: Two times or less

VP15-00-2

Wave soldering

Solder bath temperature: 260

C max., Time: 10 seconds max., Count: Once,

Preheating temperature: 120

C max. (package surface temperature)

WS60-00-1

Partial heating

Pin temperature: 300

C max., Time: 3 seconds max. (per pin row)

Caution Do not use different soldering methods together (except for partial heating).

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

APPENDIX A. DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78F4218AY. Also refer to

(5) Cautions on using development tools.

(1) Language processing software

RA78K4

Assembler package common to 78K/IV Series

CC78K4

C compiler package common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

CC78K4-L

C compiler library source file common to 78K/IV Series

(2) Flash memory writing tools

Flashpro II

(Part number: FL-PR2),

Flashpro III

(Part number: FL-PR3, PG-FP3)

Dedicated flash programmer for microcontroller incorporating flash memory

FA-100GF

Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Connection must be

performed in accordance with the target product.

FA-100GC

Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Connection must be

performed in accordance with the target product.

(3) Debugging tools

·
·
·
·

When IE-78K4-NS in-circuit emulator is used

IE-78K4-NS

In-circuit emulator common to 78K/IV Series

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter required when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-CD-IF-A

PC card and cable when PC-9800 series notebook PC is used as host machine (PCMCIA

socket supported)

IE-70000-PC-IF-C

Interface adapter required when using IBM PC/AT

compatibles as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter required when using PC that incorporates PCI bus as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784216A, 784216AY, 784218A, 784218AY Subseries

NP-100GF

Emulation probe for 100-pin plastic QFP (GF-3BA type)

NP-100GC

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the NP-100GC and a target system board on which a 100-pin

plastic LQFP (GC-8EU type) can be mounted

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

·
·
·
·

When IE-784000-R in-circuit emulator is used

IE-784000-R

In-circuit emulator common to 78K/IV Series

IE-70000-98-IF-C

Interface adapter required when PC-9800 series PC (except notebook type) is used as host

machine (C bus supported)

IE-70000-PC-IF-C

Interface adapter required when using IBM PC/AT and compatibles as host machine (ISA bus

supported)

IE-70000-PCI-IF

Interface adapter required when using PC that incorporates PCI bus as host machine

IE-78000-R-SV3

Interface adapter and cable required when EWS is used as host machine

IE-784225-NS-EM1

Emulation board to emulate

PD784216A, 784216AY, 784218A, 784218AY Subseries

IE-784000-R-EM

Emulation board common to 78K/IV Series

IE-78K4-R-EX3

Emulation probe conversion board required when using IE-784225-NS-EM1 on IE-784000-R.

EP-784218GF-R

Emulation probe for 100-pin plastic QFP (GF-3BA type)

EP-78064GC-R

Emulation probe for 100-pin plastic LQFP (GC-8EU type)

EV-9200GF-100

Socket to be mounted on a target system board made for 100-pin plastic QFP (GF-3BA type)

TGC-100SDW

Conversion adapter to connect the EP-78064GC-R and a target system board on which a

100-pin plastic LQFP (GC-8EU type) can be mounted

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator common to 78K/IV Series

DF784218

Device file common to

PD784216A, 784216AY, 784218A, 784218AY Subseries

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series

MX78K4

OS for 78K/IV Series

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

(5) Cautions on using development tools

The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784218.

The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784218.

The FL-PR2, FL-PR3, FA-100GF, FA-100GC, NP-100GF, and NP-100GC are products made by Naito

Densei Machida Mfg. Co., Ltd. (TEL: +81-44-822-3813).

The TGC-100SDW is a product made by TOKYO ELETECH CORPORATION.

For further information, contact Daimaru Kogyo, Ltd.

Tokyo Electronic Division (TEL: +81-3-3820-7112)

Osaka Electronic Division (TEL: +81-6-6244-6672)

For third party development tools, see the Single-Chip Microcontroller Development Tool Selection

Guide (U11069E).

The host machine and OS suitable for each software are as follows:

EWS

Host Machine

[OS]

Software

PC-9800 series [Windows]

IBM PC/AT and compatibles

[Japanese/English Windows]

HP9000 Series 700

[HP-UX

]

SPARCstation

[SunOS

, Solaris

]

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

Note DOS-based software

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

APPENDIX B. RELATED DOCUMENTS

Documents related to devices

Document Name

Document No.

PD784214A, 784215A, 784216A, 784217A, 784218A, 784214AY, 784215AY, 784216AY, 784217AY,

784218AY Data Sheet

U14121E

PD78F4216A, 78F4216AY, 78F4218A, 78F4218AY Data Sheet

This document

PD784216A, 784216AY Subseries User's Manual Hardware

U13570E

PD784218A, 784218AY Subseries User's Manual Hardware

U12970E

78K/IV Series User's Manual Instructions

U10905E

78K/IV Series Instruction Table

78K/IV Series Instruction Set

78K/IV Series Application Note Software Basics

Documents related to development tools (user's manuals)

Document Name

Document No.

Language

U11162E

RA78K4 Assembler Package

Operation

U11334E

RA78K Structured Assembler Preprocessor

U11743E

Language

U11571E

CC78K4 C Compiler

Operation

U11572E

IE-78K4-NS

U13356E

IE-784000-R

U12903E

IE-784218-R-EM1

U12155E

IE-784225-NS-EM1

U13742E

EP-78064

EEU-1469

SM78K4 System Simulator Windows Based

Reference

U10093E

SM78K Series System Simulator

External Part User Open

Interface Specifications

U10092E

ID78K4-NS Integrated Debugger PC Based

Reference

U12796E

ID78K4 Integrated Debugger Windows Based

Reference

U10440E

ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based

Reference

U11960E

Caution

The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Documents related to embedded software (user's manuals)

Document Name

Document No.

Fundamental

U10603E

Installation

U10604E

78K/IV Series Real-Time OS

Debugger

78K/IV Series OS MX78K4

Fundamental

Other documents

Document Name

Document No.

SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM)

X13769X

Semiconductor Device Mounting Technology Manual

C10535E

Quality Grades on NEC Semiconductor Devices

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983E

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892E

Guide to Microcomputer-Related Products by Third Party

Caution

The related documents listed above are subject to change without notice. Be sure to use the

latest version of each document for designing.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

IEBus is a trademark of NEC Corporation.

Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or

other countries.

PC/AT is a trademark of International Business Machines Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

Solaris and SunOS are trademarks of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of Sony Corporation.

Data Sheet U14125EJ1V0DS00

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.l.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Madrid Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951

NEC do Brasil S.A.

Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829

J00.7

µ
µ
µ
µ

PD78F4216A, 78F4218A, 78F4216AY, 78F4218AY

The related documents indicated in this publication may include preliminary versions. However, preliminary

versions are not marked as such.

Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use these components

in an I

C system, provided that the system conforms to the I

C Standard Specification as defined by Philips.

M8E 00. 4

The information in this document is current as of August, 2000. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots

"Special":

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

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