Document Outline

• Cover
• INTRODUCTION
• CHAPTER 1 GENERAL
  • 1.1 Features
  • 1.2 Ordering Information
  • 1.3 Pin Configuration (Top View)
    • 1.3.1 Normal operation mode
  • 1.4 Application System Configuration Example (Car Audio (Tuner, Deck))
  • 1.5 Block Diagram
  • 1.6 List of Functions
  • 1.7 Differences among Products in uPD784938 Subseries
  • 1.8 Main Differences with uPD784908 Subseries
• CHAPTER 2 PIN FUNCTIONS
  • 2.1 Pin Function Lists
    • 2.1.1 Normal operation mode
  • 2.2 Pin Functions
    • 2.2.1 Normal operation mode
  • 2.3 Input/Output Circuits and Connection of Unused Pins
  • 2.4 Cautions
• CHAPTER 3 CPU ARCHITECTURE
  • 3.1 Memory Space
  • 3.2 Internal ROM Area
  • 3.3 Base Area
    • 3.3.1 Vector table area
    • 3.3.2 CALLT instruction table area
    • 3.3.3 CALLF instruction entry area
  • 3.4 Internal Data Area
    • 3.4.1 Internal RAM area
    • 3.4.2 Special function register (SFR) area
    • 3.4.3 External SFR area
  • 3.5 External Memory Space
  • 3.6 uPD78F4938 Memory Mapping
  • 3.7 Control Registers
    • 3.7.1 Program counter (PC)
    • 3.7.2 Program status word (PSW)
    • 3.7.3 Use of RSS bit
    • 3.7.4 Stack pointer (SP)
  • 3.8 General-Purpose Registers
    • 3.8.1 Configuration
    • 3.8.2 Functions
  • 3.9 Special Function Registers (SFR)
  • 3.10 Cautions
• CHAPTER 4 CLOCK GENERATOR
  • 4.1 Configuration and Function
  • 4.2 Control Registers
    • 4.2.1 Standby control register (STBC)
    • 4.2.2 Oscillation stabilization time specification register (OSTS)
  • 4.3 Clock Generator Operation
    • 4.3.1 Clock oscillator
    • 4.3.2 Divider
  • 4.4 Cautions
    • 4.4.1 When an external clock is input
    • 4.4.2 When crystal/ceramic oscillation is used
• CHAPTER 5 REGULATOR
  • 5.1 Outline of Regulator
• CHAPTER 6 PORT FUNCTIONS
  • 6.1 Digital Input/Output Ports
  • 6.2 Port 0
    • 6.2.1 Hardware configuration
    • 6.2.2 I/O mode/control mode setting
    • 6.2.3 Operating status
    • 6.2.4 On-chip pull-up resistors
    • 6.2.5 Transistor drive
  • 6.3 Port 1
    • 6.3.1 Hardware configuration
    • 6.3.2 I/O mode/control mode setting
    • 6.3.3 Operating status
    • 6.3.4 On-chip pull-up resistors
    • 6.3.5 Direct LED drive
  • 6.4 Port 2
    • 6.4.1 Hardware configuration
    • 6.4.2 Input mode/control mode setting
    • 6.4.3 Operating status
    • 6.4.4 On-chip pull-up resistors
  • 6.5 Port 3
    • 6.5.1 Hardware configuration
    • 6.5.2 I/O mode/control mode setting
    • 6.5.3 Operating status
    • 6.5.4 On-chip pull-up resistors
  • 6.6 Port 4
    • 6.6.1 Hardware configuration
    • 6.6.2 I/O mode/control mode setting
    • 6.6.3 Operating status
    • 6.6.4 On-chip pull-up resistors
    • 6.6.5 Direct LED drive
  • 6.7 Port 5
    • 6.7.1 Hardware configuration
    • 6.7.2 I/O mode/control mode setting
    • 6.7.3 Operating status
    • 6.7.4 On-chip pull-up resistors
    • 6.7.5 Direct LED drive
  • 6.8 Port 6
    • 6.8.1 Hardware configuration
    • 6.8.2 I/O mode/control mode setting
    • 6.8.3 Operating status
    • 6.8.4 On-chip pul-up resistors
  • 6.9 Port 7
    • 6.9.1 Hardware configuration
    • 6.9.2 I/O mode/control mode setting
    • 6.9.3 Operating status
    • 6.9.4 On-chip pull-up resistors
    • 6.9.5 Caution
  • 6.10 Port 9
    • 6.10.1 Hardware configuration
    • 6.10.2 I/O mode/control mode setting
    • 6.10.3 Operating status
    • 6.10.4 On-chip pull-up resistors
  • 6.11 Port 10
    • 6.11.1 Hardware configuration
    • 6.11.2 I/O mode/control mode setting
    • 6.11.3 Operating status
    • 6.11.4 On-chip pull-up resistors
  • 6.12 Port Output Check Function
  • 6.13 Cautions
• CHAPTER 7 REAL-TIME OUTPUT FUNCTION
  • 7.1 Configuration and Function
  • 7.2 Real-time Output Port Control Register (RTPC)
  • 7.3 Real-time Output Port Accesses
  • 7.4 Operation
  • 7.5 Example of Use
  • 7.6 Cautions
• CHAPTER 8 OUTLINE OF TIMER
• CHAPTER 9 TIMER/EVENT COUNTER 0
  • 9.1 Functions
  • 9.2 Configuration
  • 9.3 Timer/Event Counter 0 Control Registers
  • 9.4 Timer Counter 0 (TM0) Operation
    • 9.4.1 Basic operation
    • 9.4.2 Clear operation
  • 9.5 External Event Counter Function
  • 9.6 Compare Register and Capture Register Operation
    • 9.6.1 Compare operations
    • 9.6.2 Capture operations
  • 9.7 Basic Operation of Output Control Circuit
    • 9.7.1 Basic operation
    • 9.7.2 Toggle output
    • 9.7.3 PWM output
    • 9.7.4 PPG output
    • 9.7.5 Software triggered one-shot pulse output
  • 9.8 Examples of Use
    • 9.8.1 Operation as interval timer (1)
    • 9.8.2 Operation as interval timer (2)
    • 9.8.3 Pulse width measurement operation
    • 9.8.4 Operation as PWM output
    • 9.8.5 Operation as PPG output
    • 9.8.6 Example of software triggered one-shot pulse output
  • 9.9 Cautions
• CHAPTER 10 TIMER/EVENT COUNTER 1
  • 10.1 Functions
  • 10.2 Configuration
  • 10.3 Timer/Event Counter 1 Control Registers
  • 10.4 Timer Counter 1 (TM1) Operation
    • 10.4.1 Basic operation
    • 10.4.2 Clear operation
  • 10.5 External Event Counter Function
  • 10.6 Compare Register and Capture/Compare Register Operation
    • 10.6.1 Compare operations
    • 10.6.2 Capture operations
  • 10.7 Examples of Use
    • 10.7.1 Operation as interval timer (1)
    • 10.7.2 Operation as interval timer (2)
    • 10.7.3 Pulse width measurement operation
  • 10.8 Cautions
• CHAPTER 11 TIMER/EVENT COUNTER 2
  • 11.1 Functions
  • 11.2 Configuration
  • 11.3 Timer/Event Counter 2 Control Registers
  • 11.4 Timer Counter 2 (TM2) Operation
    • 11.4.1 Basic operation
    • 11.4.2 Clear operation
  • 11.5 External Event Counter Function
  • 11.6 One-Shot Timer Function
  • 11.7 Compare Register, Capture/Compare Register, and Capture Register Operation
    • 11.7.1 Compare operations
    • 11.7.2 Capture operations
  • 11.8 Basic Operation of Output Control Circuit
    • 11.8.1 Basic operation
    • 11.8.2 Toggle output
    • 11.8.3 PWM output
    • 11.8.4 PPG output
  • 11.9 Examples of Use
    • 11.9.1 Operation as interval timer (1)
    • 11.9.2 Operation as interval timer (2)
    • 11.9.3 Pulse width measurement operation
    • 11.9.4 Operation as PWM output
    • 11.9.5 Operation as PPG output
    • 11.9.6 Operation as external event counter
    • 11.9.7 Operation as one-shot timer
  • 11.10 Cautions
• CHAPTER 12 TIMER 3
  • 12.1 Function
  • 12.2 Configuration
  • 12.3 Timer 3 Control Registers
  • 12.4 Timer Counter 3 (TM3) Operation
    • 12.4.1 Basic operation
    • 12.4.2 Clear operation
  • 12.5 Compare Register Operation
  • 12.6 Example of Use
  • 12.7 Cautions
• CHAPTER 13 WATCHDOG TIMER
  • 13.1 Configuration
  • 13.2 Watchdog Timer Mode Register (WDM)
  • 13.3 Operation
    • 13.3.1 Count operation
    • 13.3.2 Interrupt priorities
  • 13.4 Cautions
    • 13.4.1 General cautions on use of watchdog timer
    • 13.4.2 Cautions on uPD784938 Subseries watchdog timer
• CHAPTER 14 WATCH TIMER
• CHAPTER 15 PWM OUTPUT UNIT
  • 15.1 PWM Output Unit Configuration
  • 15.2 PWM Output Unit Control Registers
    • 15.2.1 PWM control register (PWMC)
    • 15.2.2 PWM prescaler register (PWPR)
    • 15.2.3 PWM modulo registers (PWM0, PWM1)
  • 15.3 PWM Output Unit Operation
    • 15.3.1 Basic PWM output operation
    • 15.3.2 PWM pulse output enabling/disabling
    • 15.3.3 PWM pulse active level specification
    • 15.3.4 PWM pulse width rewrite cycle specification
  • 15.4 Caution
• CHAPTER 16 A/D CONVERTER
  • 16.1 Configuration
  • 16.2 A/D Converter Mode Register (ADM)
  • 16.3 A/D Current Cut Select Register (IEAD)
  • 16.4 Operation
    • 16.4.1 Basic A/D converter operation
    • 16.4.2 Select mode
    • 16.4.3 Scan mode
    • 16.4.4 A/D conversion operation start by software
    • 16.4.5 A/D conversion operation start by hardware
  • 16.5 External Circuit of A/D Converter
  • 16.6 Cautions
• CHAPTER 17 OUTLINE OF SERIAL INTERFACE
• CHAPTER 18 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
  • 18.1 Switching between Asynchronous Serial Interface Mode and 3-Wire Serial I/O Mode
  • 18.2 Asynchronous Serial Interface Mode
    • 18.2.1 Configuration in asynchronous serial interface mode
    • 18.2.2 Asynchronous serial interface control registers
    • 18.2.3 Data format
    • 18.2.4 Parity types and operations
    • 18.2.5 Transmission
    • 18.2.6 Reception
    • 18.2.7 Receive errors
  • 18.3 3-Wire Serial I/O Mode
    • 18.3.1 Configuration in 3-wire serial I/O mode
    • 18.3.2 Clocked serial interface mode registers (CSIM1, CSIM2)
    • 18.3.3 Basic operation timing
    • 18.3.4 Operation when transmission only is enabled
    • 18.3.5 Operation when reception only is enabled
    • 18.3.6 Operation when transmission/reception is enabled
    • 18.3.7 Corrective action in case of slippage of serial clock and shift operations
  • 18.4 Baud Rate Generator
    • 18.4.1 Baud rate generator configuration
    • 18.4.2 Baud rate generator control register (BRGC, BRGC2)
    • 18.4.3 Baud rate generator operation
    • 18.4.4 Baud rate setting in asynchronous serial interface mode
  • 18.5 Cautions
• CHAPTER 19 3-WIRE SERIAL I/O MODE
  • 19.1 Function
  • 19.2 Configuration
  • 19.3 Control Registers
    • 19.3.1 Clocked serial interface mode register (CSIM, CSIM3)
  • 19.4 3-Wire Serial I/O Mode
    • 19.4.1 Basic operation timing
    • 19.4.2 Operation when transmission only is enabled
    • 19.4.3 Operation when reception only is enabled
    • 19.4.4 Operation when transmission/reception is enabled
    • 19.4.5 Corrective action in case of slippage of serial clock and shift operations
• CHAPTER 20 IEBus CONTROLLER
  • 20.1 IEBus Controller Function
    • 20.1.1 Communication protocol of IEBus
    • 20.1.2 Determination of bus mastership (arbitration)
    • 20.1.3 Communication mode
    • 20.1.4 Communication address
    • 20.1.5 Broadcasting communication
    • 20.1.6 Transmission format of IEBus
    • 20.1.7 Transmit data
    • 20.1.8 Bit format
  • 20.2 Simple IEBus Controller
  • 20.3 IEBus Controller Configuration
  • 20.4 Internal Registers of IEBus Controller
    • 20.4.1 Internal register list
    • 20.4.2 Description of internal registers
  • 20.5 Interrupt Operations of IEBus Controller
    • 20.5.1 Interrupt control block
    • 20.5.2 Interrupt source list
  • 20.6 Interrupt Generation Timing and Main CPU Processing
    • 20.6.1 Master transmission
    • 20.6.2 Master reception
    • 20.6.3 Slave transmission
    • 20.6.4 Slave reception
    • 20.6.5 Interval of occurrence of interrupt for IEBus control
  • 20.7 Cautions when Using IEBus Controller
• CHAPTER 21 CLOCK OUTPUT FUNCTION
  • 21.1 Configuration
  • 21.2 Clock Output Mode Register (CLOM)
  • 21.3 Operation
    • 21.3.1 Clock output
    • 21.3.2 1-bit output port
    • 21.3.3 Operation in standby mode
  • 21.4 Cautions
• CHAPTER 22 EDGE DETECTION FUNCTION
  • 22.1 Edge Detection Function Control Registers
    • 22.1.1 External interrupt mode registers (INTM0, INTM1)
    • 22.1.2 Sampling clock selection register (SCS0)
  • 22.2 Edge Detection for Pins P20, P25, and P26
  • 22.3 P21 Pin Edge Detection
  • 22.4 Pin Edge Detection for Pins P22 to P24
  • 22.5 Cautions
• CHAPTER 23 INTERRUPT FUNCTIONS
  • 23.1 Interrupt Request Sources
    • 23.1.1 Software interrupts
    • 23.1.2 Operand error interrupts
    • 23.1.3 Non-maskable interrupts
    • 23.1.4 Maskable interrupts
  • 23.2 Interrupt Service Modes
    • 23.2.1 Vectored interrupt service
    • 23.2.2 Macro service
    • 23.2.3 Context switching
  • 23.3 Interrupt Service Control Registers
    • 23.3.1 Interrupt control registers
    • 23.3.2 Interrupt mask registers (MK0/MK1)
    • 23.3.3 In-service priority register (ISPR)
    • 23.3.4 Interrupt mode control register (IMC)
    • 23.3.5 Watchdog timer mode register (WDM)
    • 23.3.6 Program status word (PSW)
  • 23.4 Software Interrupt Acknowledgment Operations
    • 23.4.1 BRK instruction software interrupt acknowledgment operation
    • 23.4.2 BRKCS instruction software interrupt (software context switching) acknowledgment operation
  • 23.5 Operand Error Interrupt Acknowledgment Operation
  • 23.6 Non-Maskable Interrupt Acknowledgment Operation
  • 23.7 Maskable Interrupt Acknowledgment Operation
    • 23.7.1 Vectored interrupt
    • 23.7.2 Context switching
    • 23.7.3 Maskable interrupt priority levels
  • 23.8 Macro Service Function
    • 23.8.1 Outline of macro service function
    • 23.8.2 Types of macro service
    • 23.8.3 Basic macro service operation
    • 23.8.4 Operation at end of macro service
    • 23.8.5 Macro service control registers
    • 23.8.6 Macro service type A
    • 23.8.7 Macro service type B
    • 23.8.8 Macro service type C
    • 23.8.9 Counter mode
  • 23.9 When Interrupt Requests and Macro Service are Temporarily Held Pending
  • 23.10 Instructions whose Execution is Temporarily Suspended by an Interrupt or Macro Service
  • 23.11 Interrupt and Macro Service Operation Timing
    • 23.11.1 Interrupt acknowledge processing time
    • 23.11.2 Processing time of macro service
  • 23.12 Restoring Interrupt Function to Initial State
  • 23.13 Cautions
• CHAPTER 24 LOCAL BUS INTERFACE FUNCTION
  • 24.1 Memory Expansion Function
    • 24.1.1 Memory expansion mode register (MM)
    • 24.1.2 Memory map with external memory expansion
    • 24.1.3 Basic operation of local bus interface
  • 24.2 Wait Function
    • 24.2.1 Wait function control registers
    • 24.2.2 Address waits
    • 24.2.3 Access waits
  • 24.3 Pseudo-Static RAM Refresh Function
    • 24.3.1 Control registers
    • 24.3.2 Operations
  • 24.4 Bus Hold Function
    • 24.4.1 Hold mode register (HLDM)
    • 24.4.2 Operation
  • 24.5 Cautions
• CHAPTER 25 STANDBY FUNCTION
  • 25.1 Configuration and Function
  • 25.2 Control Registers
    • 25.2.1 Standby control register (STBC)
    • 25.2.2 Oscillation stabilization time specification register (OSTS)
  • 25.3 HALT Mode
    • 25.3.1 HALT mode setting and operating status
    • 25.3.2 HALT mode release
  • 25.4 STOP Mode
    • 25.4.1 STOP mode setting and operating status
    • 25.4.2 STOP mode release
  • 25.5 IDLE Mode
    • 25.5.1 IDLE mode setting and operating status
    • 25.5.2 IDLE mode release
  • 25.6 Check Items when STOP Mode/IDLE Mode is Used
  • 25.7 Cautions
• CHAPTER 26 RESET FUNCTION 26.1 Reset Function
  • 26.1 Reset Function
  • 26.2 Caution
• CHAPTER 27 ROM CORRECTION
  • 27.1 ROM Correction Functions
  • 27.2 ROM Correction Configuration
  • 27.3 Control Register for ROM Correction
  • 27.4 Use of ROM Correction
  • 27.5 Conditions for Executing ROM Correction
• CHAPTER 28 uPD78F4938 PROGRAMMING
  • 28.1 Internal Memory Size Switching Register (IMS)
  • 28.2 Flash Memory Programming Using Flashpro II and Flashpro III
    • 28.2.1 Selecting communication mode
    • 28.2.2 Flash memory programming functions
    • 28.2.3 Connecting Flashpro II or Flashpro III
• CHAPTER 29 INSTRUCTION OPERATIONS
  • 29.1 Conventions
  • 29.2 List of Operations
  • 29.3 Instructions Listed by Type of Addressing
• APPENDIX A DEVELOPMENT TOOLS
  • A.1 Language Processing Software
  • A.2 Flash Memory Programming Tools
  • A.3 Debugging Tools
    • A.3.1 Hardware (1/2)
    • A.3.2 Software (1/2)
  • A.4 Drawings of Conversion Socket (EV-9200GF-100) and Recommended Board Mounting Pattern D C
  • A.5 Check Sheet for uPD784938 Subseries Development Tools
• APPENDIX B EMBEDDED SOFTWARE
• APPENDIX C REGISTER INDEX
  • C.1 Register Name Index
  • C.2 Register Symbol Index