Document Outline
- COVER
- 1. DIFFERENCES BETWEEN uPD78P014 AND MASK ROM VERSION
- 2. PIN FUNCTIONS
- 2.1 Normal Operating Mode Pins
- 2.2 PROM Programming Mode Pins
- 2.3 Pin Input/Output Circuits and Connection of Unused Pins
- 3. INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
- 4. PROM PROGRAMMING
- 4.1 Operating Modes
- 4.2 PROM Write Procedure
- 4.3 PROM Read Procedure
- 5. ERASURE PROCEDURE (uPD78P014DW ONLY)
- 6. OPAQUE FILM FOR ERASURE WINDOW ( uPD78P014DW ONLY)
- 7. ONE-TIME PROM VERSION SCREENING
- 8. ELECTRICAL SPECIFICATIONS
- 9. CHARACTERISTIC (FOR REFERENCE ONLY)
- 10. PACKAGE DRAWINGS
- 11. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A. DEVELOPMENT TOOLS
- APPENDIX B. RELATED DOCUMENTS
1992
DATA SHEET
DESCRIPTION
The
PD78P014 is a member of the
PD78014 subseries of 78K/0 series products. It uses a one-time-programmable
(OTP) ROM or EPROM instead of the mask ROM of the
PD78014.
Because the
PD78P014 can be programmed by users, it is ideally suited for applications involving the evaluation
of systems in development stages, small-scale production of many different products, and rapid development and time-
to-market of a new product.
Detailed information about product features and specifications can be found in the following document. Please
make sure to read this document before starting design.
PD78014, 78014Y Series User's Manual : IEU-1343
FEATURES
Pin compatible with mask ROM versions (except V
PP
pin)
Internal PROM: 32K bytes
Note
PD78P014DW
: Reprogrammable (ideal for system evaluation)
PD78P014CW, 78P014GC-AB8 : Programmable once only (ideal for small-scale production)
Internal high-speed RAM: 1024 bytes
Note
Buffer RAM: 32 bytes
Operable over same supply voltage range as mask ROM version (2.7 to 6.0 V)
Available for the QTOP
TM
microcomputer
Note The internal PROM and internal high-speed RAM size can be set by means of the memory size switching
register.
Remark
The QTOP microcomputer is the general term for a single-chip microcomputer with on-chip one-time
PROM. NEC supports its program writing, marking, screening, and verification.
MOS INTEGRATED CIRCUIT
ORDERING INFORMATION
Part No.
Package
Internal ROM
PD78P014CW
64-pin plastic shrink DIP (750 mil)
One-time PROM
PD78P014DW
64-pin ceramic shrink DIP (with window) (750 mil)
EPROM
PD78P014GC-AB8
64-pin plastic QFP (14
14 mm)
One-time PROM
In this document, the common parts of the one-time PROM version and EPROM version are represented by PROM.
Differences from mask ROM versions are as follows:
The same memory mapping as on a mask ROM version is possible by setting the memory size
switching register.
There is no function for incorporating pull-up resistors by means of a mask option in P60 to P63
pins.
PD78P014
8-BIT SINGLE-CHIP MICROCOMPUTER
Document No. IC-3098C
(O. D. No. IC-8111C)
Date Published January 1995 P
Printed in Japan
The mark 5 shows revised points.
The information in this document is subject to change without notice.
2
PD78P014
78K/0 SERIES DEVELOPMENT
5
PD78002Y Subseries
PD78014Y Subseries
PD78054Y Subseries
PD78044A Subseries
PD78064Y Subseries
PD78002 Subseries
PD78014 Subseries
PD78014 Subseries
PD78064 Subseries
PD78054 Subseries
PD78098 Subseries
PD78024 Subseries
PD78044 Subseries
Products in Volume Production
Products under Development
Y subseries are products compatible with I C bus.
64-pin package
64-pin package
A/D converter,
16-bit timer/event counter,
SIO with automatic transmission/
reception function added
Multiply/divide instructions
added
64-pin package
A/D converter,
16-bit timer/event counter,
FIP
TM
controller/driver,
multiply/divide instructions
added
80-pin package
UART, D/A converter,
real-time output port added
16-bit timer/event counter
function enhanced
80-pin package
Automatic transmission/reception
function added
6-bit up/down counter added
FIP controller/driver function
enhanced
PD78018F Subseries
64-pin package
Capable of low voltage and
high-speed operation
100-pin package
LCD controller/driver,
UART added
16-bit timer/event counter
function enhanced
PD78078Y Subseries
100-pin package
8-bit timer/event counter
added
External expansion function
enhanced
80-pin package
IEBus
TM
controller added
PD78083 Subseries
42/44-pin package
UART, A/D converter,
8-bit timer/event counter
function
PD780208 Subseries
100-pin package
FIP controller/driver function
enhanced
2
PD78078 Subseries
PD78018FY Subseries
3
PD78P014
OUTLINE OF FUNCTION
PROM
: 32K bytes
Note
RAM
Internal high-speed RAM : 1024 bytes
Note
Buffer RAM
: 32 bytes
64K bytes
8 bits
32 registers (8 bits
8 registers
4 banks)
On-chip instruction execution time cycle modification function
0.4
s/0.8
s/1.6
s/3.2
s/6.4
s (at 10.0 MHz operation)
122
s (at 32.768 kHz operation)
16-bit operation
Multiply/divide (8 bits
8 bits,16 bits
8 bits)
Bit manipulate (set, reset, test, Boolean operation)
BCD correction, etc.
Total
:
53
CMOS input
:
2
CMOS I/O
:
47
N-channel open-drain I/O (15 V withstand voltage) :
4
8-bit resolution
8 channels
Operable over a wide power supply voltage range: V
DD
= 2.7 to 6.0 V
3-wire/SBI/2-wire mode selectable
: 1 channel
3-wire mode (on-chip max. 32 bytes automatic data transmit/receive function) : 1 channel
16-bit timer/event counter : 1 channel
8-bit timer/event counter
: 2 channels
Clock timer
: 1 channel
Watchdog timer
: 1 channel
3 (14-bit PWM output : 1)
39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz (at main system clock 10.0 MHz operation)
32.768 kHz (at subsystem clock 32.768 kHz operation)
2.4 kHz, 4.9 kHz, 9.8 kHz (at main system clock 10.0 MHz operation)
Internal : 8, External : 4
Internal : 1
Internal : 1
Internal : 1
External : 1
V
DD
= 2.7 to 6.0 V
40 to +85
C
64-pin plastic shrink DIP (750 mil)
64-pin plastic QFP (14
14 mm)
64-pin ceramic shrink DIP (with window) (750 mil)
Item
Function
Main system clock
selected
Subsystem clock
selected
Note The capacity of the internal PROM and internal high-speed RAM can be set by means of the memory size
switching register.
Maskable
interrupts
Non-maskable
interrupt
Software
interrupt
Internal memory
Memory space
General registers
Instruction cycle
Instruction set
I/O ports
A/D converter
Serial interface
Timer
Timer output
Clock output
Buzzer output
Vectored
interrupts
Test input
Operating voltage range
Operating temperature
range
Package
4
PD78P014
PIN CONFIGURATION (Top View)
(1)
Normal operating mode
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window) (750 mil)
PD78P014CW
PD78P014DW
Cautions 1. V
PP
pin should be connected to V
SS
directly.
2. AV
DD
pin should be connected to V
DD
.
3. AV
SS
pin should be connected to V
SS
.
1
P20/SI1
2
P21/SO1
3
P22/SCK1
4
P23/STB
5
P24/BUSY
6
P25/SI0/SB0
7
P26/SO0/SB1
8
P27/SCK0
9
P30/TO0
10
P31/TO1
11
P32/TO2
12
P33/TI1
13
P34/TI2
14
P35/PCL
15
P36/BUZ
16
P37
17
V
SS
18
P40/AD0
19
P41/AD1
20
P42/AD2
21
P43/AD3
22
P44/AD4
23
P45/AD5
24
P46/AD6
25
P47/AD7
26
P50/A8
27
P51/A9
28
P52/A10
29
P53/A11
30
P54/A12
31
P55/A13
32
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AV
REF
AV
DD
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AV
SS
P04/XT1
XT2
V
PP
X1
X2
V
DD
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
P65/WR
P64/RD
P63
P62
P61
P60
P57/A15
P56/A14
5
PD78P014
64-pin plastic QFP (14
14 mm)
PD78P014GC-AB8
Cautions 1. V
PP
pin should be connected to V
SS
directly.
2. AV
DD
pin should be connected to V
DD
.
3. AV
SS
pin should be connected to V
SS
.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P11/ANI1
P10/ANI0
AV
SS
P04/XT1
XT2
V
PP
X1
X2
V
DD
P03/INTP3
P02/INTP2
P01/INTP1
P00/INTP0/TI0
RESET
P67/ASTB
P66/WAIT
P37
V
SS
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P40/AD0
P41/AD1
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P27/SCK0
P26/SO0/SB1
P25/SI0/SB0
P24/BUSY
P23/STB
P22/SCK1
P21/SO1
P20/SI1
AV
REF
AV
DD
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P47/AD7
P50/A8
P51/A9
P52/A10
P53/A11
P54/A12
P55/A13
V
SS
P56/A14
P57/A15
P60
P61
P62
P63
P64/RD
P65/WR
6
PD78P014
AD0 to AD7
: Address/Data Bus
A8 to A15
: Address Bus
RD
: Read Strobe
WR
: Write Strobe
WAIT
: Wait
ASTB
: Address Strobe
X1, X2
: Crystal (Main System Clock)
XT1, XT2
: Crystal (Subsystem Clock)
RESET
: Reset
ANI0 to ANI7
: Analog Input
AV
DD
: Analog Power Supply
AV
SS
: Analog Ground
AV
REF
: Analog Reference Voltage
V
DD
: Power Supply
V
PP
: Programming Power Supply
V
SS
: Ground
P00 to P04
: Port 0
P10 to P17
: Port 1
P20 to P27
: Port 2
P30 to P37
: Port 3
P40 to P47
: Port 4
P50 to P57
: Port 5
P60 to P67
: Port 6
INTP0 to INTP3 : Interrupt From Peripherals
TI0 to TI2
: Timer Input
TO0 to TO2
: Timer Output
SB0, SB1
: Serial Bus
SI0, SI1
: Serial Input
SO0, SO1
: Serial Output
SCK0, SCK1
: Serial Clock
PCL
: Programmable Clock
BUZ
: Buzzer Clock
STB
: Strobe
BUSY
: Busy
7
PD78P014
Cautions 1. (L)
: Connect to V
SS
individually via a pull-down resistor.
2. V
SS
: Connect to ground.
3. RESET : Set to low level.
4. Open
: Do not make any connection.
(2)
PROM programming mode
64-pin plastic shrink DIP (750 mil)
64-pin ceramic shrink DIP (with window) (750 mil)
PD78P014CW
PD78P014DW
1
2
3
4
5
6
7
8
9
D0
10
D1
11
D2
12
D3
13
D4
14
D5
15
D6
16
D7
17
V
SS
18
A0
19
A1
20
A2
21
A3
22
A4
23
A5
24
A6
25
A7
26
A8
27
(L)
28
A10
29
A11
30
A12
31
A13
32
V
SS
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SS
V
DD
V
SS
(L)
Open
V
PP
(L)
Open
V
DD
A9
RESET
CE
OE
A14
(L)
(L)
(L)
(L)
(L)
8
PD78P014
Cautions 1. (L)
: Connect to V
SS
individually with a pull-down resistor.
2. V
SS
: Connect to ground.
3. RESET : Set to low level.
4. Open
: Do not make any connection.
64-pin plastic QFP (14
14 mm)
RESET
: Reset
V
DD
: Power Supply
V
PP
: Programming Power Supply
V
SS
: Ground
A0 to A14
: Address Bus
D0 to D7
: Data Bus
CE
: Chip Enable
OE
: Output Enable
PD78P014GC-AB8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
SS
(L)
Open
V
PP
(L)
Open
V
DD
A9
RESET
D7
V
SS
D0
D1
D2
D3
D4
D5
D6
A0
A1
A2
A3
A4
A5
A6
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
V
SS
V
DD
A7
A8
(L)
A10
A11
A12
A13
V
SS
A14
OE
CE
(L)
(L)
(L)
(L)
(L)
(L)
9
PD78P014
BLOCK DIAGRAM
P10-P17
P01-P03
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
AD0/P40-
AD7/P47
A8/P50-
A15/P57
RD/P64
WR/P65
W
AIT/P66
P00
P04
ASTB/P67
POR
T0
POR
T1
POR
T2
POR
T3
POR
T4
POR
T5
POR
T6
EXTERNAL
ACCESS
GENERAL
REG.
RAM
DA
T
A
MEMOR
Y
1056
8
DECODE
AND
CONTROL
PROM
PROGRAM
MEMOR
Y
32768
8
PROGRAM COUNTER
16-bit TIMER/
EVENT
COUNTER
8-bit TIMER/
EVENT
COUNTER 1
8-bit TIMER/
EVENT
COUNTER 2
W
A
TCHDOG TIMER
W
A
TCH TIMER
SERIAL
INTERF
ACE 0
SERIAL
INTERF
ACE 1
A/D CONVER
TER
INTERRUPT
CONTROL
T
O0/P30
ALU
PSW
SP
BUZZER
OUTPUT
CLOCK
OUTPUT
CONTROL
CLOCK
DIVIDER
CLOCK GENERA
T
O
R
SUB
MAIN
ST
AND BY
CONTROL
BUZ/P36
PCL/P35
P04/XT1 XT2
X1
X2
RESET
V
PP
V
SS
TI0/INTP0/P00
T
O1/P31
TI1/P33
T
O2/P32
TI2/P34
SI0/SB0/P25
SI1/P20
SO1/P21
SCK1/P22
STB/P23
BUSY/P24
ANI0/P10
-ANI7/P17
AV
DD
AV
SS
AV
REF
INTP0/P00
-INTP3/P03
V
DD
SO0/SB1/P26
SCK0/P27
10
PD78P014
CONTENTS
1.
DIFFERENCES BETWEEN
PD78P014 AND MASK ROM VERSION ...................................................
11
2.
PIN FUNCTIONS .......................................................................................................................................
12
2.1
Normal Operating Mode Pins ......................................................................................................................... 12
2.2
PROM Programming Mode Pins ..................................................................................................................... 15
2.3
Pin Input/Output Circuits and Connection of Unused Pins ........................................................................ 16
3.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ...................................................................
18
4.
PROM PROGRAMMING ...........................................................................................................................
19
4.1
Operating Modes .............................................................................................................................................. 19
4.2
PROM Write Procedure .................................................................................................................................... 20
4.3
PROM Read Procedure ..................................................................................................................................... 22
5.
ERASURE PROCEDURE (
PD78P014DW ONLY) ...................................................................................
23
6.
OPAQUE FILM FOR ERASURE WINDOW (
PD78P014DW ONLY) ......................................................
23
7.
ONE-TIME PROM VERSION SCREENING ..............................................................................................
23
8.
ELECTRICAL SPECIFICATIONS ...............................................................................................................
24
9.
CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................................
49
10. PACKAGE DRAWINGS .............................................................................................................................
53
11. RECOMMENDED SOLDERING CONDITIONS ........................................................................................
56
APPENDIX A. DEVELOPMENT TOOLS ......................................................................................................... 57
APPENDIX B. RELATED DOCUMENTS ........................................................................................................ 59
11
PD78P014
1.
DIFFERENCES BETWEEN
PD78P014 AND MASK ROM VERSION
The
PD78P014 incorporates one-time PROM which can be written to once only, or EPROM to which programs
can be written, erased and rewritten.
By setting the internal memory size switching register, it is possible to make the functions of this device, except
for the PROM specification and mask option for pins P60 to P63, identical to those of a mask ROM version.
The differences between
PD78P014 and mask ROM versions are shown in Table 1-1.
Table 1-1. Differences Between
PD78P014 and Mask ROM Version
PD78P014
IC pin
V
PP
pin
Mask option for pins P60 to P63
No
Yes
No mask option for incorporation of pull-
up resistor
Yes
No
Pull-up resistor incorporation possible by
means of mask option
Item
Mask ROM Version
Caution In the
PD78P014, the capacity of the internal PROM and internal high-speed RAM can be changed by using
the internal memory size switching register.
RESET input sets internal PROM to 32K bytes and internal high-speed RAM to 1K bytes.
12
PD78P014
2.
PIN FUNCTIONS
2.1
Normal Operating Mode Pins
(1)
Port pins (1/2)
Alternate
Function
Function
Pin Name
Port 1
8-bit input/output port.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by
software.
Note 2
Input only
Input only
Input
After Reset
Input
Input
Notes 1. When P04/XT1 pins are used as the input ports, set processor clock control register bit 6 (FRC) to 1. (Do
not use the on-chip feedback resistor of the subsystem clock oscillation circuit.)
2. When P10/ANI0 to P17/ANI7 pins are used as the analog inputs for A/D converter, the pull-up resistor is
automatically disabled.
P00
P01
P02
P03
P04
Note 1
P10 to P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
I/O
INTP0/TI0
INTP1
INTP2
INTP3
XT1
ANI0 to
ANI7
SI1
SO1
SCK1
STB
BUSY
SI0/SB0
SO0/SB1
SCK0
TO0
TO1
TO2
TI1
TI2
PCL
BUZ
AD0 to AD7
Input/
output
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can
be used by software.
Port 0
5-bit I/O port
Input
Input
Input
Input/
output
Input/
output
Port 2
8-bit input/output port.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
Input
Input
Port 3
8-bit input/output port.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
Input/
output
Port 4
8-bit input/output port.
Input/output can be specified in 8-bit unit.
When used as an input port, pull-up resistor can be used by software.
(Test input flag (KRIF) is set to 1 by falling edge detection.)
Input/
output
Input
13
PD78P014
Alternate
Function
A8 to A15
--
RD
WR
WAIT
ASTB
(1)
Port pins (2/2)
P60
P61
P62
P63
P64
P65
P66
P67
Function
Pin Name
I/O
After Reset
Port 5
8-bit input/output port.
LED can be driven directly.
Input/output can be specified in 1-bit unit.
When used as an input port, pull-up resistor can be used by software.
Input
Input/
output
P50 to P57
Port 6
8-bit input/output port. Input/output can
be specified in 1-bit unit.
Input/
output
N-ch open-drain input/
output port.
LED can be driven
directly.
Input
When used as an input
port, pull-up resistor can
be used by software.
14
PD78P014
P00/TI0
P01
P02
P03
P25/SB0
P20
P26/SB1
P21
P25/SI0
P26/SO0
P27
P22
P23
P24
P00/INTP0
P33
P34
P30
P31
P32
P35
P36
P40 to P47
P50 to P57
P64
P65
P66
P67
(2)
Non port pins (1/2)
Altrnate
Function
Function
Pin Name
I/O
Falling edge detection external interrupt input.
After Reset
Input
Output
Serial interface automatic transmission/reception strobe output.
Input
Input
Serial interface automatic transmission/reception busy input.
INTP0
INTP1
INTP2
INTP3
SI0
SI1
SO0
SO1
SB0
SB1
SCK0
SCK1
STB
BUSY
TI0
TI1
TI2
TO0
TO1
TO2
PCL
BUZ
AD0 to AD7
A8 to A15
RD
WR
WAIT
ASTB
Clock output (for trimming main system clock or subsystem clock).
Buzzer output.
Low address/data bus when memory is expanded externally.
High address bus when memory is expanded externally.
External memory read operation strobe signal output.
External memory write operation strobe signal output.
Wait insertion at external memory access.
Output of strobe which externally latches address information to be
output to ports 4 and 5 when accessing external memory.
Input
Output
Output
Input
Output
Input
Input
External interrupt input with specifiable valid edge (rising edge, falling
edge, or both rising and falling edges).
Input
Input
Serial interface serial data input.
Input
Output
Serial interface serial data output.
Input
Input
Serial interface serial data input/output.
Input/
output
Serial interface serial clock input/output.
Input/
output
Input of external count clock to 16-bit timer (TM0).
Input of external count clock to 8-bit timer (TM1).
Input of external count clock to 8-bit timer (TM2).
16-bit timer (TM0) output (alternate function with 14-bit PWM output).
8-bit timer (TM1) output.
8-bit timer (TM2) output.
Input
Input
Input
Output
Input/
output
Input
Input
Input
Input
Output
Input
Input
Output
15
PD78P014
Pin Name
RESET
V
PP
A0 to A14
D0 to D7
CE
OE
V
DD
V
SS
Input
Input
--
--
Input
Input
--
Input
--
--
--
--
Alternate
Function
Function
Pin Name
I/O
ANI0 to ANI7
AV
REF
AV
DD
AV
SS
RESET
X1
X2
XT1
XT2
V
DD
V
PP
V
SS
P10 to P17
--
--
--
--
--
--
P04
--
--
--
--
(2)
Non port pins (2/2)
After Reset
Function
A/D converter analog input.
A/D converter reference voltage input.
A/D converter analog power supply. Connect to V
DD
.
A/D converter ground potential. Connect to V
SS
.
System reset input.
Main system clock oscillation crystal connection.
Subsystem clock oscillation crystal connection.
Positive power supply.
(High voltage application for program write/verify. Directly connected
to V
SS
in normal operating mode.)
Ground potential
Input
--
--
--
--
--
--
Input
--
--
--
--
I/O
Input
Input
Input
Input/
output
Input
Input
--
--
PROM programming mode setting.
When +5 V or +12.5 V is applied to the V
PP
pin and a low-level signal to the RESET pin, the PROM
programming mode is set.
PROM programming mode setting and high voltage application for program write/verify.
Address bus.
Data bus.
PROM enable input/program pulse input.
PROM read strobe input.
Positive power supply.
Ground potential.
2.2
PROM Programming Mode Pins
16
PD78P014
2.3
Pin Input/Output Circuits and Connection of Unused Pins
The input/output circuit type of each pin and the recommended connection of unused pins are shown in Table
2-1.
The configuration of each type of input/output circuit is shown in Figure 2-1.
Table 2-1. Type of Pin Input/Output Circuits
Input/Output
Circuit Type
I/O
Pin Name
Recommended Connection for Used Pins
Connect to V
SS
.
Input
: Connect to V
SS
.
Output
: Leave open.
Connected to V
SS
.
Input
Input/output
Input
Input/output
Input/output
Input/output
Input/output
Input/output
Input
--
Input
: Connect to V
DD
or V
SS
.
Output
: Leave open.
2
8-A
16
11
8-A
5-A
8-A
5-A
8-A
10-A
5-A
8-A
5-A
5-E
5-A
13
5-A
2
16
--
P00/INTP0/TI0
P01/INTP1
P02/INTP2
P03/INTP3
P04/XT1
P10/ANI0 to P17/ANI7
P20/SI1
P21/SO1
P22/SCK1
P23/STB
P24/BUSY
P25/SI0/SB0
P26/SO0/SB1
P27/SCK0
P30/TO0
P31/TO1
P32/TO2
P33/TI1
P34/TI2
P35/PCL
P36/BUZ
P37
P40/AD0 to P47/AD7
P50/A8 to P57/A15
P60 to P63
P64/RD
P65/WR
P66/WAIT
P67/ASTB
RESET
XT2
AV
REF
AV
DD
AV
SS
V
PP
Input
: Connect to V
DD
or V
SS
.
Output
: Leave open.
Input
: Connect to V
DD
or V
SS
.
Output
: Leave open.
Input
: Connect to V
DD
or V
SS
.
Output
: Leave open.
Input
: Connect to V
DD
or V
SS
.
Output
: Leave open.
--
Leave open.
Connect to V
SS
.
Connect to V
DD
.
Connect to V
SS
.
Directly connect to V
SS
.
17
PD78P014
Figure 2-1. Pin Input/Output Circuits
Type 10-A
pullup
enable
data
output
disable
IN/OUT
N-ch
V
REF
input
enable
DD
pullup
enable
data
output disable
V
P-ch
N-ch
P-ch
IN/OUT
DD
V
DD
Type 11
open-drain
Type 13
data
output disable
N-ch
IN/OUT
Middle-High Voltage Input Buffer
(Threshold Voltage)
V
P-ch
N-ch
P-ch
DD
V
P-ch
+
Comparator
Type 2
IN
pullup
enable
data
output
disable
V
P-ch
N-ch
P-ch
IN/OUT
DD
V
DD
Type 5-A
input
enable
Type 5-E
pullup
enable
data
output
disable
V
P-ch
N-ch
P-ch
IN/OUT
DD
V
DD
Schmitt-Triggered Input with Hysteresis Characteristic
Type 8-A
pullup
enable
data
output
disable
V
P-ch
N-ch
P-ch
IN/OUT
DD
V
DD
Type 16
XT1
feedback
cut-off
P-ch
XT2
18
PD78P014
3.
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS)
This register is used to prevent part of the internal memory from being used by software. Setting the internal
memory size switching register (IMS) enables memory mapping identical to that of a mask ROM version with
different internal memory (ROM and RAM) to be used.
The IMS register is set by an 8-bit memory manipulation instruction.
RESET input sets this register to C8H.
Figure 3-1. Internal Memory Size Switching Register Format
7
6
5
4
3
2
1
0
Address
At Reset
R/W
FFF0H
C8H
W
IMS
RAM2 RAM1 RAM0
0
ROM3 ROM2 ROM1 ROM0
The IMS set values to make the memory map identical to various mask ROM versions are shown in Table 3-1.
Table 3-1. Examples of Internal Memory Size Switching Register Settings
IMS Set Value
Target Mask ROM Version
IMS Set Value
Target Mask ROM Version
PD78001B
PD78002B
PD78011B
ROM3 ROM2 ROM1 ROM0
Internal ROM Capacity Selection
0
0
0
1
4 K bytes
0
0
1
0
8 K bytes
0
1
0
0
16 K bytes
0
1
1
0
24 K bytes
1
0
0
0
32K bytes
Setting prohibited
RAM2 RAM1 RAM0
Internal High-Speed RAM Capacity Selec-
tion
0
0
0
768 bytes
0
0
1
640 bytes
0
1
0
512 bytes
0
1
1
384 bytes
1
0
0
256 bytes
1
0
1
Setting prohibited
1
1
0
1024 bytes
1
1
1
896 bytes
Other than above
44H
C6H
C8H
PD78012B
PD78013
PD78014
82H
64H
42H
19
PD78P014
4.
PROM PROGRAMMING
The
PD78P014 incorporates a 32K-byte PROM as program memory. When programming the
PD78P014, the
PROM programming mode is set by means of the V
PP
and RESET pins. For the connection of unused pins, see
"PIN
CONFIGURATION (2) PROM programming mode".
4.1
Operating Modes
When +5 V or +12.5 V is applied to the V
PP
pin and a low-level signal is applied to the RESET pin, the
PD78P014
enters the programming mode. This is one of the operating modes shown in Table 4-1 below according to the setting
of the CE and OE pins.
Also, the PROM contents can be read by setting the read mode.
Data input
Data output
High-impedance
Data output
High-impedance
High-impedance
Operating Mode
H
L
H
L
H
L/H
L
H
H
L
L
H
Program write
Program verify
Program inhibit
Read
Output disable
Standby
Pins
Table 4-1. PROM Programming Operating Modes
RESET
V
PP
V
DD
D0 to D7
CE
OE
+6 V
+12.5 V
+5 V
+5 V
L
20
PD78P014
4.2
PROM Write Procedure
The PROM write procedure is as shown below, allowing high-speed writing.
(1)
Fix the RESET pin low. Supply +5 V to the V
PP
pin. Unused pins are handled as shown in "PIN CONFIGURATION
(2) PROM programming mode".
(2)
Supply +6 V to the V
DD
pin and +12.5 V to the V
PP
pin.
(3)
Supply the initial address.
(4)
Supply the write data.
(5)
Supply a 1 ms program pulse (active low) to the CE pin.
(6)
Verify mode. If written, go to (8); if not written, repeat (4) through (6). When the write operation has been
repeated 25 times, go to (7).
(7)
Halt write operation due to defective device.
(8)
Supply write data and supply (times repeated in (4) through (6))
3 ms program pulse (additional write).
(9)
Increment the address.
(10) Repeat (4) through (9) until the final address.
Timing for steps (2) through (8) above is shown in Figure 4-1.
Figure 4-1. PROM Write/Verify Timing
Write
A 0 - A 1 4
V
P P
C E ( I n p u t )
D 0 - D 7
+ 6 V
O E ( I n p u t )
V
D D
+ 1 2 . 5 V
V
D D
V
D D
R e p e a t e d X T i m e s
Data Input
Address Input
Verify
3Xms
H i - Z
H i - Z
Data
Output
H i - Z
H i - Z
Data Input
Additional
Write
21
PD78P014
Figure 4-2. Write Procedure Flowchart
S t a r t w r i t e
Supply power supply voltage
Supply initial address
Supply write data
V e r i f y m o d e
Supply program pulse
Write Not Possible
(Less than 25 Times)
Write Not Possible
(25th Times)
Additional write (3X ms pulse)
Address increment
F i n a l a d d r e s s
W r i t e c o m p l e t e d
Write OK
X: Number of Write
Repetitions
D e f e c t i v e d e v i c e
>Final Address
(1)
(2)
(3)
(4)
(5)
(6)
(8)
(9)
(10)
(7)
Final Address
22
PD78P014
4.3
PROM Read Procedure
PROM contents can be read onto the external data bus (D0 to D7) using the following procedure.
(1)
Fix the RESET pin low. Supply +5 V to the V
PP
pin. Unused pins are handled as shown in "PIN CONFIGURATION
(2) PROM programming mode".
(2)
Supply +5 V to the V
DD
and V
PP
pins.
(3)
Input address of data to be read to pins A0 through A14.
(4)
Read mode .
(5)
Output data to pins D0 through D7.
Timing for steps (2) through (5) above is shown in Figure 4-3.
Figure 4-3. PROM Read Timing
A0-A14
Address Input
CE (Input)
OE (Input)
D0-D7
Data Output
H i - Z
H i - Z
23
PD78P014
5.
ERASURE PROCEDURE (
PD78P014DW ONLY)
With the
PD78P014DW, it is possible to erase (set to FFH) data written to the program memory, and rewrite the
memory.
The data can be erased by exposing the window to light with a wavelength of approximately 400 nm or less.
Usually, exposure is performed with ultraviolet light with a wavelength of 254 nm. The amount of exposing required
for complete erasure is shown below.
UV intensity x erasure time: 15 W
s/cm
2
or more
Erasure time: 15 to 20 minutes (using a 12,000
W/cm
2
ultraviolet lamp. A longer erasure time may be
required in case of deterioration of the ultraviolet lamp or dirt on the erasure window).
Erasure should be carried out with the ultraviolet lamp placed at a distance of 2.5 cm or less from the window.
If the ultraviolet lamp is fitted with a filter, this should be removed before performing exposure.
6.
OPAQUE FILM FOR ERASURE WINDOW (
PD78P014DW ONLY)
An opaque film should be applied to the erasure window except when erasing the EPROM contents, in order to
prevent the EPROM contents from being unintentionally erased by light other than from the erasure lamp, and the
internal circuits other than EPROM from misoperation due to light.
7.
ONE-TIME PROM VERSION SCREENING
One-time PROM versions (
PD78P014CW and
PD78P014GC-AB8) cannot be fully tested and shipped by NEC for
reasons related to their structure. It is recommended that after writing the necessary data and storing at high
temperature under the following conditions, screening should be conducted to verify the PROM.
Storage Temperature
Storage Time
125
C
24 hours
NEC provides charged services for one-time PROM writing, marking, screening, and verification, under the name
"QTOP Microcomputer". Contact NEC for details.
5
24
PD78P014
Symbol
V
DD
V
PP
AV
DD
AV
REF
AV
SS
V
I1
V
I2
V
I3
V
O
V
AN
I
OH
I
OL
Note
T
opt
T
stg
8.
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (T
a
= 25
C)
Parameter
Supply voltage
Input voltage
Output voltage
Analog input voltage
Output current high
Output current low
Operating temperature
Storage temperature
Ratings
Unit
0.3 to +7.0
V
0.3 to +13.5
V
0.3 to V
DD
+ 0.3
V
0.3 to V
DD
+ 0.3
V
0.3 to + 0.3
V
0.3 to V
DD
+ 0.3
V
0.3 to +16
V
0.3 to +13.5
V
0.3 to V
DD
+ 0.3
V
AV
SS
0.3 to AV
REF
+ 0.3
V
10
mA
15
mA
15
mA
30
mA
15
mA
100
mA
70
mA
100
mA
70
mA
50
mA
20
mA
50
mA
20
mA
40 to +85
C
65 to +150
C
Test Conditions
P00 to P04, P10 to P17, P20 to P27,
P30 to P37, P40 to P47, P50 to P57,
P64 to P67, X1, X2, XT2
P60 to P63
Open-drain
A9
PROM programming mode
P10 to P17
Analog input pins
1 pin
Total for P10 to P17, P20 to P27, P30 to P37
Total for P01 to P03, P40 to P47, P50 to P57,
P60 to P67
1 pin
Peak value
R.m.s. value
Total for P40 to P47,
Peak value
P50 to P55
R.m.s. value
Total for P01 to P03,
Peak value
P56, P57, P60 to P67
R.m.s. value
Total for P01 to P03,
Peak value
P64 to P67
R.m.s. value
Total for P10 to P17,
Peak value
P20 to P27, P30 to P37
R.m.s. value
Note The r.m.s. value should be calculated as follows: [R.m.s. value] = [Peak value] x
Duty
Caution Product quality may suffer if the absolute maximum rating is exceeded for even a single parameter, even
momentarily. In other words, the absolute maximum ratings are rated values at which the product is on
the verge of suffering physical damage, and therefore the product must be used under conditions which
ensure that the absolute maximum ratings are not exceeded.
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
25
PD78P014
Main System Clock Oscillator Characteristics (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
Recommended
Circuit
Resonator
Ceramic
resonator
Crystal
resonator
External clock
Parameter
Oscillation frequency
(f
X
)
Note 1
Oscillation stabiliza-
tion time
Note 2
Oscillation frequency
(f
X
)
Note 1
Oscillation stabiliza-
tion time
Note 2
X1 input frequency
(f
X
)
Note 1
X1 input high-/low-
level width (t
XH
/t
XL
)
MIN.
TYP.
MAX.
Unit
1
10
MHz
4
ms
1
8.38
10
MHz
10
ms
30
1.0
10.0
MHz
42.5
500
ns
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. This is the time required for oscillation to stabilize after a reset or STOP mode release.
Cautions 1. When the main system clock oscillator is used, the following should be noted concerning wiring in
the area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
The wiring should be kept as short as possible.
No other signal lines should be crossed.
Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as V
SS
.
Do not connect to a ground pattern carrying a high current.
A signal should not be taken from the oscillator.
2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until
the oscillation stabilization time has been secured by the program before switching back to the main
system clock.
Test Conditions
V
DD
= Oscillation voltage
range
After V
DD
has reached
MIN. of oscillation
voltage range
V
DD
= 4.5 to 6.0 V
X1
X2
C1
C2
R1
V
ss
X1
X2
C2
C1
V
ss
X1
X2
PD74HCU04
26
PD78P014
Subsystem Clock Oscillator Characteristics (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
MIN.
TYP.
MAX.
Unit
32
32.768
35
kHz
1.2
2
s
10
32
100
kHz
5
15
s
Recommended
Circuit
Parameter
Oscillation frequency
(f
XT
)
Note 1
Oscillation stabiliza-
tion time
Note 2
XT1 input frequency
(f
XT
)
Note 1
XT1 input high-/low-
level width (t
XTH
/t
XTL
)
Resonator
Crystal
resonator
External clock
Notes 1. Only the oscillator characteristics are shown. Refer to AC characteristics for instruction execution times.
2. Time required to stabilize oscillation after V
DD
reaches MIN. of oscillation voltage range.
Cautions 1. When the subsystem clock oscillator is used, the following should be noted concerning wiring in the
area in the figure enclosed by a dotted line to prevent the influence of wiring capacitance, etc.
The wiring should be kept as short as possible.
No other signal lines should be crossed.
Keep away from lines carrying a high fluctuating current.
The oscillator capacitor grounding point should always be at the same potential as V
SS
.
Do not connect to a ground pattern carrying a high current.
A signal should not be taken from the oscillator.
2. The subsystem clock oscillator is a circuit with a low amplification level, more prone to misoperation
due to noise than the main system clock. When using the subsystem clock, special care is needed
regarding the wiring method.
Test Conditions
V
DD
= 4.5 to 6.0 V
XT1 XT2
C3
C4
R2
V
ss
XT1 XT2
27
PD78P014
Recommended Oscillator
Oscillation Voltage
Constant
Range
C3 (pF)
C4 (pF)
R2 (k
)
MIN. (V)
MAX. (V)
10
10
100
2.7
6.0
Manufacturer
Murata Mfg.
Product Name
CSB1000J
CSB
J
CSA
.
MK
CSA
.
MG093
CST
.
MG093
CSA
.
MG
CST
.
MGW
CSA
.
MGU
CST
.
MGWU
CSA
.
MT
CST
.
MTW
Frequency
(kHz)
32.768
Product Name
DT-38 (1TA632E00,
load capacitance 6.3 pF)
Manufacturer
Daishinku Corp.
MIN.
TYP.
MAX.
Unit
15
pF
15
pF
20
pF
Test Conditions
f = 1 MHz Unmeasured pins returned to 0 V
P01 to P03, P10 to P17,
f = 1 MHz Unmeasured
P20 to P27, P30 to P37,
pins returned to 0 V
P40 to P47, P50 to P57,
P64 to P67
P60 to P63
Symbol
C
IN
C
IO
Parameter
Input capacitance
Input/output capacitance
Frequency
(MHz)
1.00
1.01 to 1.25
1.26 to 1.79
1.80 to 2.44
2.45 to 4.18
4.19 to 6.00
6.01 to 10.0
Recommended Oscillation Constants
Main System Clock: Ceramic Resonator (T
a
= 40 to +85
C)
Capacitance (T
a
= 25
C, V
DD
= V
SS
= 0 V)
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
Remark
.
,
.
and
indicate frequency.
Subsystem Clock: Crystal Resonator (T
a
= 40 to +60
C)
Recommended Oscillator
Oscillation Voltage
Constant
Range
C1 (pF)
C2 (pF)
R1 (k
)
MIN. (V)
MAX. (V)
100
100
6.8
2.8
6.0
100
100
4.7
2.8
6.0
100
100
0
2.8
6.0
100
100
0
2.7
6.0
Incorporated
Incorporated
0
2.7
6.0
30
30
0
2.7
6.0
Incorporated
Incorporated
0
2.7
6.0
30
30
0
2.7
6.0
Incorporated
Incorporated
0
2.7
6.0
30
30
0
3.0
6.0
Incorporated
Incorporated
0
3.0
6.0
28
PD78P014
Test Conditions
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
P60 to P63
Open-drain
X1, X2
XT1/P04, XT2
V
DD
= 4.5 to 6.0 V
P10 to P17, P21, P23, P30 to P32, P35 to P37,
P40 to P47, P50 to P57, P64 to P67
P00 to P03, P20, P22, P24 to P27, P33, P34, RESET
P60 to P63
V
DD
= 4.5 to 6.0 V
X1, X2
XT1/P04, XT2
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V, I
OH
= 1 mA
I
OH
= 100
A
P50 to P57, P60 to P63
V
DD
= 4.5 to 6.0 V,
I
OL
= 15 mA
P01 to P03, P10 to P17,
P20 to P27, P30 to P37,
V
DD
= 4.5 to 6.0 V,
P40 to P47, P64 to P67
I
OL
= 1.6 mA
V
DD
= 4.5 to 6.0 V,
SB0, SB1, SCK0
open-drain, pulled
high (R = 1 k
)
I
OL
= 400
A
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
V
IN
= V
DD
P40 to P47, P50 to P57,
P60 to P67, RESET
X1, X2, XT1/P04, XT2
V
IN
= 15 V
P60 to P63
P00 to P03, P10 to P17,
P20 to P27, P30 to P37,
V
IN
= 0 V
P40 to P47, P50 to P57,
P60 to P67, RESET
X1, X2, XT1/P04, XT2
Symbol
V
IH1
V
IH2
V
IH3
V
IH4
V
IH5
V
IL1
V
IL2
V
IL3
V
IL4
V
IL5
V
OH1
V
OL1
V
OL2
V
OL3
I
LIH1
I
LIH2
I
LIH3
I
LIL1
I
LIL2
DC Characteristics (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
Parameter
Input voltage high
Input voltage low
Output voltage high
Output voltage low
Input leakage current
high
Input leakage current low
MIN.
TYP.
MAX.
Unit
0.7 V
DD
V
DD
V
0.8 V
DD
V
DD
V
0.7 V
DD
15
V
V
DD
0.5
V
DD
V
V
DD
0.5
V
DD
V
V
DD
0.3
V
DD
V
0
0.3 V
DD
V
0
0.2 V
DD
V
0
0.3 V
DD
V
0
0.2 V
DD
V
0
0.4
V
0
0.4
V
0
0.3
V
V
DD
1.0
V
V
DD
0.5
V
0.4
2.0
V
0.4
V
0.2 V
DD
V
0.5
V
3
A
20
A
80
A
3
A
20
A
29
PD78P014
Test Conditions
V
OUT
= V
DD
V
OUT
= 0 V
V
IN
= 0 V, P01 to P03,
P10 to P17, P20 to P27,
4.5 V
V
DD
6.0 V
P30 to P37, P40 to P47,
P50 to P57, P64 to P67
2.7 V
V
DD
< 4.5 V
8.38 MHz crystal oscilla-
V
DD
= 5.0 V
10%
Note 1
tion operating mode
V
DD
= 3.0 V
10%
Note 2
8.38 MHz crystal oscilla-
V
DD
= 5.0 V
10%
tion HALT mode
V
DD
= 3.0 V
10%
32.768 kHz crystal oscilla- V
DD
= 5.0 V
10%
tion operating mode
V
DD
= 3.0 V
10%
32.768 kHz crystal oscilla- V
DD
= 5.0 V
10%
tion HALT mode
V
DD
= 3.0 V
10%
XT1 = 0 V
V
DD
= 5.0 V
10%
STOP mode
V
DD
= 3.0 V
10%
Feedback resistor used
XT1 = 0 V
V
DD
= 5.0 V
10%
STOP mode
Feedback resistor
V
DD
= 3.0 V
10%
not used
DC Characteristics (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
MIN.
TYP.
MAX.
Unit
3
A
3
A
15
40
90
k
20
500
k
9
27
mA
1
3
mA
1.4
4.2
mA
550
1650
A
90
180
A
50
100
A
25
50
A
5
10
A
1
30
A
0.5
10
A
0.1
30
A
0.05
10
A
Symbol
I
LOH1
I
LOL
R
2
I
DD1
I
DD2
I
DD3
I
DD4
I
DD5
I
DD6
Parameter
Output leakage current
high
Output leakage current
low
Software pull-up resistor
Supply current
Note 3
Notes 1. High-speed mode operation (when processor clock control register is set to 00H).
2. Low-speed mode operation (when processor clock control register is set to 04H).
3. Not including AV
REF
currents or port currents
Remark Unless otherwise specified, alternate function pin characteristics are the same as port pin characteristics.
30
PD78P014
Test Conditions
V
DD
= 4.5 to 6.0 V
Operating with main
T
a
= 40 to +40
C
system clock
V
DD
= 4.75 to 6.0 V
T
a
= 40 to +40
C
Operating with subsystem clock
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
INTP0
INTP1 to INTP3
KR0 to KR7
AC Characteristics
(1)
Basic operation (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
Symbol
T
CY
f
TI
t
TIH
t
TIL
t
INTH
t
INTL
t
RSL
MIN.
TYP.
MAX.
Unit
0.48
64
s
1.91
64
s
0.4
64
s
0.96
64
s
40
122
125
s
0
4
MHz
0
275
kHz
100
ns
1.8
s
8/f
sam
Note
s
10
s
10
s
10
s
Parameter
Cycle time
(Min. instruction
execution time)
TI input frequency
TI input high-/low-level
width
Interrupt input high-/low-
level width
RESET low-level width
Note In combination with bits 0 (SCS0) and 1 (SCS1) of sampling clock select register, selection of f
sam
is possible
between f
X
/2
N+1
, f
X
/64, and f
X
/128 (N = 0 to 4).
T
CY
VS
V
DD
(At main system clock operation)
Caution When T
a
= 40 to +40
C, the operation guaranteed range is extended to the dotted line.
60
10
2.0
1.0
1
0
2
3
4
5
6
0.5
0.4
Supply Voltage V
DD
[V]
Cycle Time T
CY
[ s]
Operation Guaranteed
Range
(T
a
= 40 to +85
C)
31
PD78P014
Remarks
1.
t
CY
= T
CY
/4
2.
n indicates number of waits.
3.
C
L
= 100 pF (C
L
indicates the load capacitance of pins P40/AD0 to P47/AD7, P50/A8 to P57/A15, P64/
RD, P65/WR, P66/WAIT, P67/ASTB.)
t
RDAST
t
CY
10
t
CY
+ 40
ns
t
RDADH
t
CY
t
CY
+ 50
ns
Parameter
Symbol
Test Conditions
MIN.
MAX.
Unit
ASTB high-level width
t
ASTH
0.5t
CY
ns
Address setup time
t
ADS
0.5t
CY
30
ns
Address hold time
t
ADH
Load resistance
5 k
10
ns
Data input time from address
t
ADD1
(2 + 2n)t
CY
50
ns
t
ADD2
5
(3 + 2n)t
CY
100
ns
Data input time from RD
t
RDD1
(1 + 2n)t
CY
25
ns
t
RDD2
(2.5 + 2n)t
CY
100
ns
Read data hold time
t
RDH
0
ns
RD low-level width
t
RDL1
(1.5 + 2n)t
CY
20
ns
t
RDL2
(2.5 + 2n)t
CY
20
ns
WAIT
input time from RD
t
RDWT1
0.5t
CY
ns
t
RDWT2
1.5t
CY
ns
WAIT
input time from WR
t
WRWT
0.5t
CY
ns
WAIT low-level width
t
WTL
(0.5 + 2n)t
CY
+ 10
(2 + 2n)t
CY
ns
Write data setup time
t
WDS
100
ns
Write data hold time
t
WDH
5
ns
WR low-level width
t
WRL1
(2.5 + 2n)t
CY
20
ns
RD
delay time from ASTB
t
ASTRD
0.5t
CY
30
ns
WR
delay time from ASTB
t
ASTWR
1.5t
CY
30
ns
ASTB
delay time from
RD
in external fetch
Address hold time from
RD
in external fetch
Write data output time from RD
t
RDWD
10
ns
WR
delay time from write data
V
DD
= 4.5 to 6.0 V
0.5t
CY
120
0.5t
CY
ns
0.5t
CY
170
0.5t
CY
ns
Address hold time from WR
V
DD
=4.5 to 6.0 V
t
CY
t
CY
+ 60
ns
t
CY
t
CY
+ 100
ns
RD
delay time from WAIT
t
WTRD
0.5t
CY
2.5t
CY
+ 80
ns
WR
delay time from WAIT
t
WTWR
0.5t
CY
2.5t
CY
+ 80
ns
(2)
Read/write operation (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
t
WDWR
t
WRADH
32
PD78P014
Parameter
SCK cycle time
SCK high-/low-level
width
SI setup time (to SCK
)
SI hold time (from SCK
)
SO output delay time
from SCK
Parameter
SCK cycle time
SCK high-/low-level
width
SI setup time (to SCK
)
SI hold time (from SCK
)
SO output delay time
from SCK
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
(3)
Serial interface (T
a
= 40 to +85
C, V
DD
= 2.7 to 6.0 V)
(a)
3-wire serial I/O mode (SCK... Internal clock output)
Symbol
t
KCY1
t
KH1
t
KL1
t
SIK1
t
KSI1
t
KSO1
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
t
KCY1
/2 50
ns
t
KCY1
/2 150
ns
100
ns
400
ns
300
ns
1000
ns
Note C is the load capacitance of SO output line.
(b)
3-wire serial I/O mode (SCK...External clock input)
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
400
ns
300
ns
1000
ns
Symbol
t
KCY2
t
KH2
t
KL2
t
SIK2
t
KSI2
t
KSO2
When using the external device
expansion function
When using the
16-bit timer
output function
When not using
the 16-bit timer
output function
When using the external device
expansion function
When not using the external
device expansion function
160
700
1000
160
1000
ns
ns
ns
ns
ns
When not
using the
external device
expansion
function
t
R2
t
F2
t
R2
t
F2
SCK rise and fall times
(For serial interface
channel 1)
SCK rise and fall times
(For serial interface
channel 0)
5
5
5
5
5
Note C is the load capacitance of SO output line.
33
PD78P014
Parameter
SCK cycle time
SCK high-/low-level
width
SB0, SB1 setup time
(to SCK
)
SB0, SB1 hold time
(from SCK
)
SB0, SB1 output
delay time from SCK
SB0, SB1
from SCK
SCK
from SB0, SB1
SB0, SB1 high-level
width
SB0, SB1 low-level
width
(c)
SBI mode (SCK...Internal clock output)
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
t
KCY3
/2 - 50
ns
t
KCY3
/2 - 150
ns
100
ns
300
ns
t
KCY3
/2
ns
0
250
ns
0
1000
ns
t
KCY3
ns
t
KCY3
ns
t
KCY3
ns
t
KCY3
ns
Symbol
t
KCY3
t
KH3
t
KL3
t
SIK3
t
KSI3
t
KSO3
t
KSB
t
SBK
t
SBH
t
SBL
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
R = 1 k
,
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
34
PD78P014
Parameter
SCK cycle time
SCK high-/low-level
width
SB0, SB1 setup time
(to SCK
)
SB0, SB1 hold time
(from SCK
)
SB0, SB1 output
delay time from SCK
SB0, SB1
from SCK
SCK
from SB0, SB1
SB0, SB1 high-level
width
SB0, SB1 low-level
width
(d)
SBI mode (SCK...External clock input)
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
300
ns
t
KCY4
/2
ns
0
300
ns
0
1000
ns
t
KCY4
ns
t
KCY4
ns
t
KCY4
ns
t
KCY4
ns
Symbol
t
KCY4
t
KH4
t
KL4
t
SIK4
t
KSI4
t
KSO4
t
KSB
t
SBK
t
SBH
t
SBL
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
R = 1 k
,
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
When using the external device
expansion function
When using the
16-bit timer
output function
When not using
the 16-bit timer
output function
160
700
1000
ns
ns
ns
When not
using the
external device
expansion
function
t
R4
t
F4
5
5
5
SCK rise and fall
times
Note R and C are the load resistance and load capacitance of the SB0 and SB1 output line.
35
PD78P014
Test Conditions
V
DD
= 4.5 to 6.0 V
R = 1 k
, C = 100 pF
Note
R = 1 k
,
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
Symbol
t
KCY5
t
KH5
t
KL5
t
SIK5
t
KSI5
t
KSO5
Parameter
SCK cycle time
SCK high-level width
SCK low-level width
SB0, SB1 setup time (to SCK
)
SB0, SB1 hold time (from SCK
)
SB0, SB1 output delay time
from SCK
When not
using the
external device
expansion
function
When using the external device
expansion function
When using the
16-bit timer
output function
When not using
the 16-bit timer
output function
Test Conditions
V
DD
= 4.5 to 6.0 V
R = 1 k
,
V
DD
= 4.5 to 6.0 V
C = 100 pF
Note
Symbol
t
KCY6
t
KH6
t
KL6
t
SIK6
t
KSI6
t
KSO6
Parameter
SCK cycle time
SCK high-level width
SCK low-level width
SB0, SB1 setup time (to SCK
)
SB0, SB1 hold time (from SCK
)
SB0, SB1 output delay time
from SCK
(e)
2-wire serial I/O mode (SCK... Internal clock output)
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
(f)
2-wire serial I/O mode (SCK... External clock input)
5
5
5
Note R and C are the load resistance and load capacitance of the SCK0, SB0 and SB1 output line.
MIN.
TYP.
MAX.
Unit
1600
ns
3800
ns
650
ns
800
ns
100
ns
t
KCY6
/2
ns
0
300
ns
0
1000
ns
SCK rise and fall times
t
R6
t
F6
ns
ns
ns
160
700
1000
MIN.
TYP.
MAX.
Unit
1600
ns
3800
ns
t
KCY5
/2 50
ns
t
KCY5
/2 50
ns
300
ns
600
ns
0
250
ns
0
1000
ns
36
PD78P014
Parameter
SCK cycle time
SCK high/low-level
width
SI setup time (to SCK
)
SI hold time (from SCK
)
SO output delay time
from SCK
(g)
3-wire serial I/O mode with automatic transmit/receive function (SCK...Internal clock output)
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
t
KCY7
/2 50
ns
t
KCY7
/2 150
ns
100
ns
400
ns
300
ns
1000
ns
400
t
KCY7
ns
t
KCY7
30
t
KCY7
+ 30
ns
100
ns
100
ns
2t
KCY7
ns
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
Note
V
DD
= 4.5 to 6.0 V
C = 100 pF
Symbol
t
KCY7
t
KH7
t
KL7
t
SIK7
t
KSI7
t
KSO7
t
SBD
t
SBW
t
BYS
t
BYH
t
SPS
Parameter
SCK cycle time
SCK high/low-level
width
SI setup time (to SCK
)
SI hold time (from SCK
)
SO output delay time
from SCK
STB
from SCK
Strobe signal high-
level width
Busy signal setup time
(to busy signal
detection timing)
Busy signal hold time
(from busy signal
detection timing)
SCK
from busy
inactive
Note C is the load capacitance of the SO output line.
(h)
3-wire serial I/O mode with automatic transmit/receive function (SCK...External clock input)
MIN.
TYP.
MAX.
Unit
800
ns
3200
ns
400
ns
1600
ns
100
ns
400
ns
300
ns
1000
ns
Symbol
t
KCY8
t
KH8
t
KL8
t
SIK8
t
KSI8
t
KSO8
Test Conditions
V
DD
= 4.5 to 6.0 V
V
DD
= 4.5 to 6.0 V
Note
V
DD
= 4.5 to 6.0 V
C = 100 pF
When using the external device
expansion function
When not using the external
device expansion function
160
1000
ns
ns
t
R8
t
F8
SCK rise and fall times
5
5
Note C is the load capacitance of the SO output line.
37
PD78P014
A/D Converter Characteristics (T
a
= 40 to +85
C, AV
DD
= V
DD
= 2.7 to 6.0 V, AV
SS
= V
SS
= 0 V)
Test Conditions
Symbol
t
CONV
t
SAMP
V
IAN
AV
REF
I
REF
Parameter
Resolution
Overall error
Note
Conversion time
Sampling time
Analog input voltage
Reference voltage
AV
REF
current
MIN.
TYP.
MAX.
Unit
8
8
8
bit
0.6
%
19.1
200
s
24/f
x
s
AV
SS
AV
REF
V
2.7
AV
DD
V
0.5
1.5
mA
Note Excluding quantization error (
1/2LSB). Shown as a percentage of the full scale value.
38
PD78P014
AC Timing Test Point (Excluding X1 and XT1 Input)
Clock Timing
TI Timing
0.8 V
DD
0.2 V
DD
0.8 V
DD
0.2 V
DD
Point of
measurement
t
XL
t
XH
1/f
X
V
DD
- 0.5 V
0.4V
t
XTL
t
XTH
1/f
XT
V
DD
- 0.5 V
0.4V
X1 Input
XT1 Input
t
TIL
t
TIH
1/f
TI
TI0-TI2
39
PD78P014
Read/Write Operation
External fetch (no wait):
External fetch (wait insertion):
t
ASTH
t
ADH
t
ADD1
Hi-z
t
ADS
t
RDD1
t
RDADH
t
RDAST
t
ASTRD
t
RDL1
t
RDH
A8-A15
AD0-AD7
ASTB
RD
Upper 8-Bit Address
Operation
Code
Lower 8-Bit
Address
t
ASTH
t
ADH
t
ADD1
Hi-z
t
ADS
t
RDADH
t
RDAST
t
ASTRD
t
RDL1
t
RDH
A8-A15
AD0-AD7
ASTB
RD
t
WTRD
t
WTL
t
RDWT1
WAIT
t
RDD1
Upper 8-Bit Address
Operation
Code
Lower 8-Bit
Address
40
PD78P014
External data access (no wait):
External data access (wait insertion):
t
RDWD
t
WDH
t
ASTH
t
ADH
t
ADD2
Hi-z
t
ADS
t
ASTRD
t
RDL2
A8-A15
AD0-AD7
ASTB
RD
t
WDS
t
WRL1
WR
t
RDD2
t
RDH
Hi-z
t
WDWR
t
ASTWR
Upper 8-Bit Address
Write Data
Read Data
Lower
8-Bit
Address
t
WRADH
t
ASTRD
t
ASTH
t
ADH
t
ADD2
Hi-z
t
ADS
t
RDL2
A8-A15
AD0-AD7
ASTB
RD
t
WDS
t
WRL1
WR
t
RDH
Hi-z
t
WDWR
t
ASTWR
t
WRADH
Upper 8-Bit Address
Write Data
Read Data
Lower
8-Bit
Address
t
RDD2
t
WDH
t
RDWT2
t
WTL
t
WRWT
t
WTWR
t
WTL
WAIT
t
WTRD
t
RDWD
41
PD78P014
5
5
5
Serial Transfer Timing
3-wire serial I/O mode:
SBI mode (bus release signal transfer):
SBI mode (command signal transfer):
t
KCY 1.2
t
KL1.2
t
KH1.2
SCK
SI
SO
t
SIK1.2
t
KSI1.2
t
KSO1.2
Input Data
Output Data
t
R2
t
F2
t
SIK3.4
t
KCY3.4
t
KL3.4
t
KH3.4
SCK
t
SBL
t
SBH
t
KSB
t
SBK
t
KSI3.4
t
KSO3.4
SB0, SB1
t
R4
t
F4
t
SIK3.4
t
KCY3.4
t
KL3.4
t
KH3.4
SCK
t
KSB
t
SBK
t
KSI3.4
t
KSO3.4
SB0, SB1
t
R4
t
F4
42
PD78P014
2-wire serial I/O mode:
3-wire serial I/O mode with automatic transmit/receive function (Busy processing):
3-wire serial I/O mode with automatic transmit/receive function:
Note The signal is not actually low here, but is represented in this way to show the timing.
5
5
t
KSO5.6
t
SIK5.6
t
KCY5.6
t
KL5.6
t
KH5.6
SCK
t
KSI5.6
SB0, SB1
t
R6
t
F6
t
SBW
t
SBD
t
KCY7.8
t
F8
t
KSI7.8
t
KSO7.8
t
SIK7.8
D2
D1
D0
D7
D7
D2
D1
D0
SO
SI
SCK
STB
t
R8
t
KH7.8
t
KL7.8
t
BYS
SCK
t
SPS
BUSY
(Active high)
7
8
9
Note
10
Note
10+n
Note
1
t
BYH
43
PD78P014
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (T
a
= 40 to +85
C)
Parameter
Data retention power
supply voltage
Data retention power
supply current
Release signal set time
Oscillation
stabilization wait time
Symbol
V
DDDR
I
DDDR
t
SREL
t
WAIT
Note In combination with bits 0 to 2 (OSTS0 to OSTS2) of oscillation stabilization time select register, selection
of 2
13
/f
x
and 2
15
/f
x
to 2
18
/f
x
is possible.
MIN.
TYP.
MAX.
Unit
2.0
6.0
V
0.1
10
A
0
s
2
18
/f
x
ms
Note
ms
Test Conditions
V
DDDR
= 2.0 V
Subsystem clock stop and
feedback resistor disconnected
Release by RESET
Release by interrupt
Data Retention Timing (STOP Mode Release by RESET)
Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal)
t
SREL
t
WAIT
V
DD
RESET
Stop Instruction Execution
STOP Mode
Data Retention Mode
Internal Reset Operation
HALT Mode
Operating Mode
V
DDDR
t
SREL
t
WAIT
V
DD
Stop Instruction Execution
STOP Mode
Data Retention Mode
HALT Mode
Operating Mode
Standby Release Signal
(Interrupt Request)
V
DDDR
44
PD78P014
Interrupt Input Timing
RESET Input Timing
t
INTL
t
INTH
t
INTL
INTP0-INTP2
INTP3
t
RSL
RESET
45
PD78P014
Test Conditions
0
V
I
V
DDP
I
OH
= 400
A
I
OH
= 100
A
I
OL
= 2.1 mA
0
V
O
V
DDP
, OE = V
IH
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
CE = V
IL
, V
I
= V
IH
Program memory write mode
CE = V
IL
, OE = V
IH
Program memory read mode
DC Programming Characteristics (T
a
= 25
5
C, V
SS
= 0 V)
MIN.
TYP.
MAX.
Unit
0.7 V
DDP
V
DDP
V
0
0.3 V
DDP
V
10
A
2.4
V
V
DD
0.7
V
0.45
V
10
A
5.75
6.0
6.25
V
4.5
5.0
5.5
V
12.5
12.5
12.8
V
V
PP
= V
DDP
5
30
mA
5
30
mA
5
30
mA
1
100
A
Parameter
Input voltage
high
Input voltage
low
Input leakage
current
Output
voltage high
Output
voltage low
Output
leakage
current
V
DDP
supply
voltage
V
PP
supply
voltage
V
DDP
supply
current
V
PP
supply
current
Note Corresponding
PD27C256A symbol.
Symbol
Symbol
Note
V
IH
V
IH
V
IL
V
IL
I
LIP
I
LI
V
OH1
V
OH1
V
OH2
V
OH2
V
OL
V
OL
I
LO
--
V
DDP
V
CC
V
PP
V
PP
I
DD
I
CC
I
PP
I
PP
46
PD78P014
Program Operation
AC Characteristics (T
a
= 25
5
C, V
DD
= 6.0
0.25 V, V
PP
=
12.5
0.3 V, V
SS
= 0 V)
Note Corresponding
PD27C256A symbol.
MIN.
TYP.
MAX.
Unit
2
s
2
s
2
s
2
s
2
s
0
130
ns
1
ms
1
ms
0.95
1.0
1.05
ms
2.85
78.75
ms
1
s
Parameter
Address setup time (to CE
)
OE
delay time from data
Input data setup time (to CE
)
Address hold time (from CE
)
Input data hold time
(from CE
)
Output data hold time
(from OE
)
V
PP
setup time (to CE
)
V
DDP
setup time (to CE
)
Initial program pulse width
Additional program pulse width
Data output time from OE
Symbol
t
SAC
t
DDOO
t
SIDC
t
HCA
t
HCID
t
HOOD
t
SVPC
t
SVDC
t
WL1
t
WL2
t
DOOD
Note Corresponding
PD27C256A symbol.
PROM Mode Setting
AC Characteristics (T
a
= 25
5
C, V
SS
= 0 V)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
PROM mode setup time
t
SMA
10
s
Read Operation
AC Characteristics (T
a
= 25
5
C, V
DD
= 5.0
0.5 V, V
PP
= V
DD
, V
SS
= 0 V)
Symbol
Symbol
Note
t
DAOD
t
ACC
t
DCOD
t
CE
t
DOOD
t
OE
t
HCOD
t
DF
t
HAOD
t
OH
Parameter
Data output time from address
Data output time from CE
Data output time from OE
Data hold time (from OE
)
Data hold time (from address)
MIN.
TYP.
MAX.
Unit
200
ns
200
ns
75
ns
0
60
ns
0
ns
Symbol
Note
t
AS
t
OES
t
DS
t
AH
t
DH
t
DF
t
VPS
t
VDS
t
PW
t
OPW
t
OE
Test Conditions
Test Conditions
47
PD78P014
PROM Write Mode Timing
Cautions 1. V
DDP
should be applied before V
PP
, and cut after V
PP
.
2. V
PP
should not reach +13V or above including overshoot.
A 0 - A 1 4
V a l i d A d d r e s s
t
SAC
Data Input
D 0 - D 7
V
D D P
V
D D P
V
I L
V
I L
Data Output
Data Input
t
SIDC
t
HCID
t
HOOD
t
SVPC
t
SVDC
t
WL1
t
DOOD
t
WL2
t
DDOO
t
SIDC
t
HCID
t
HCA
V
P P
C E
O E
V
D D P
+ 1
V
I H
V
I H
V
D D P
V
P P
48
PD78P014
PROM Read Mode Timing
PROM Mode Setting Timing
Hi-z
A 0 - A 1 4
V a l i d A d d r e s s
t
DOOD
C E
O E
D 0 - D 7
D a t a O u t p u t
t
DAOO
Hi-z
t
DCOD
t
HAOD
t
HCOD
0
V a l i d A d d r e s s
R E S E T
A 0 - A 1 4
t
SMA
V
D D
V
D D P
0
V
P P
V
D D P
49
PD78P014
9.
CHARACTERISTIC CURVES (FOR REFERENCE ONLY)
I
DD
vs V
DD
(Main System Clock : 8.38 MHz)
0
2
3
4
5
6
7
8
f
X
= 8.38 MHz
f
XT
= 32.768 kHz
PCC=B0H
PCC=00H
PCC=01H
PCC=02H
PCC=03H
(T
a
= 25
C)
10.0
5.0
1.0
0.5
0.1
0.05
0.01
0.005
Supply Voltage V [V]
Supply Current I [mA]
DD
DD
STOP (X1 Stop, XT1
Oscillation) and Reset
PCC=04H
PCC=30H
0.001
and HALT (X1 Oscillation,
XT1 Oscillation)
HALT (X1 Stop,
XT1 Oscillation)
50
PD78P014
I
DD
vs V
DD
(Main System Clock : 4.19 MHz)
0
2
3
4
5
6
7
8
f
X
= 4.19 MHz
f
XT
= 32.768 kHz
PCC=B0H
PCC=01H
PCC=02H
(T
a
= 25
C)
10.0
5.0
1.0
0.5
0.1
0.05
0.01
0.005
Supply Voltage V [V]
Supply Current I [mA]
DD
DD
0.001
PCC=00H
PCC=04H
PCC=30H
HALT (X1 Oscillation,
XT1 Oscillation)
PCC=03H
HALT (X1 Stop,
XT1 Oscillation)
STOP (X1 Stop, XT1
Oscillation)
51
PD78P014
V
OL
vs I
OL
(Port 1)
V
OL
vs I
OL
(Ports 0 , 2 to 5, P64 to P67)
(T
a
= 25
C)
V
DD
= 6 V
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 3 V
30
20
10
0
0
0.5
1.0
Output Current Low I
OL
[mA]
Output Voltage Low V
OL
[V]
(T
a
= 25
C)
V
DD
= 6 V
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 3 V
30
20
10
0
0
0.5
1.0
Output Current Low I
OL
[mA]
Output Voltage Low V
OL
[V]
52
PD78P014
V
OL
vs I
OL
(P60 to P63)
V
OH
vs I
OH
(Ports 0 to 5, P64 to P67)
(T
a
= 25
C)
(T
a
= 25
C)
V
DD
= 6 V
V
DD
= 6 V
V
DD
= 5 V
V
DD
= 5 V
V
DD
= 4 V
V
DD
= 4 V
V
DD
= 3 V
V
DD
= 3 V
30
20
10
10
5
0
0
0
0
0.5
1.0
Output Current Low I
OL
[mA]
Output Current High I
OH
[mA]
Output Voltage Low V
OL
[V]
0.5
1.0
Output Voltage High V
DD
V
OH
[V]
53
PD78P014
10. PACKAGE DRAWINGS
A
I
J
G
H
F
D
N
M
C
B
M
R
64
33
32
1
K
L
NOTE
Each lead centerline is located within 0.17 mm (0.007 inch) of
its true position (T.P.) at maximum material condition.
P64C-70-750A,C-1
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
58.68 MAX.
1.778 (T.P.)
3.2
0.3
0.51 MIN.
4.31 MAX.
1.78 MAX.
L
M
0.17
0.25
19.05 (T.P.)
5.08 MAX.
17.0
N
0~15
0.50
0.10
0.9 MIN.
R
2.311 MAX.
0.070 MAX.
0.020
0.035 MIN.
0.126
0.012
0.020 MIN.
0.170 MAX.
0.200 MAX.
0.750 (T.P.)
0.669
0.010
0.007
0~15
+0.004
0.003
0.070 (T.P.)
1)
Item "K" to center of leads when formed parallel.
2)
+0.10
0.05
+0.004
0.005
64 PIN PLASTIC SHRINK DIP (750 mil)
54
PD78P014
64 PIN CERAMIC SHRINK DIP (750 mil)
D
N
M
I
J
G
P64DW-70-750A
33
32
A
M
S
64
1
F
CB
K
L
0 to 15
H
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
3.5
3.0
1.78 MAX.
0.031 MIN.
0.138
0.118
0.200 MAX.
2.310 MAX.
NOTES
M
N
S
5.08 MAX.
0.010
0.01
0.350
1) Each lead centerline is located within 0.25 mm
(0.010 inch) of its true position (T.P.) at maxi-mum
material condition.
2) Item "K" to center of leads when formed
parallel.
0.750 (T.P.)
0.039 MIN.
0.070 (T.P.)
18.8
0.740
0.018
0.46
0.8 MIN.
58.68 MAX.
1.778 (T.P.)
1.0 MIN.
19.05 (T.P.)
0.25
0.25
8.89
+0.05
0.070 MAX.
+0.002
0.003
+0.05
+0.3
+0.002
+0.012
55
PD78P014
N
A
M
F
B
48
49
32
K
L
64 PIN PLASTIC QFP ( 14)
64
1
17
16
33
D
C
detail of lead end
S
Q
5
5
P
M
I
H
J
G
P64GC-80-AB8-3
ITEM
MILLIMETERS
INCHES
A
B
C
D
F
G
H
I
J
K
L
17.6
0.4
14.0
0.2
1.0
0.35
0.10
0.15
14.0
0.2
0.693
0.016
0.039
0.039
0.006
0.031 (T.P.)
0.551
NOTE
M
N
0.10
0.15
1.8
0.2
0.8 (T.P.)
0.004
0.006
+0.004
0.003
Each lead centerline is located within 0.15
mm (0.006 inch) of its true position (T.P.) at
maximum material condition.
0.071
0.008
0.014
0.551
0.8
0.2
0.031
P
2.55
0.100
0.693
0.016
17.6
0.4
1.0
+0.009
0.008
Q
0.1
0.1
0.004
0.004
S
2.85 MAX.
0.112 MAX.
+0.10
0.05
+0.009
0.008
+0.004
0.005
+0.009
0.008
56
PD78P014
11. RECOMMENDED SOLDERING CONDITIONS
The
PD78P014 should be soldered and mounted under the conditions recommended in the table below.
For detail of recommended soldering conditions, refer to the information document "Semiconductor Device
Mounting Technology Manual" (IEI-1207).
For soldering methods and conditions other than those recommended below, contact our salesman.
Table 11-1. Surface Mounted Type Soldering Conditions
PD78P014GC-AB8: 64-pin plastic QFP (14
14 mm)
Soldering Method
Soldering Conditions
Package peak temperature: 230
C
Infrared ray reflow
Duration: 30 sec. max. (at 210
C or above) Number of times: Once
IR30-202-1
Time limit: 2 days
Note
(thereafter 20 hours prebaking required at 125
C)
Package peak temperature: 215
C
VPS
Duration: 40 sec. max. (at 200
C or above) Number of times: Once
VP15-202-1
Time limit: 2 days
Note
(thereafter 20 hours prebaking required at 125
C)
Pin partial heating
Pin temperature: 300
C max. Duration: 3 sec. max.
(Per side of the device)
Note For the storage period after dry-pack decapsulation, storage conditions are max. 25
C, 65% RH.
Caution Use of more than one soldering method should be avoided (except in the case of pin partial heating).
Table 11-2. Insert Type Soldering Conditions
PD78P014CW: 64-pin plastic shrink DIP (750 mil)
PD78P014DW: 64-pin ceramic shrink DIP (with window) (750 mil)
Soldering Method
Soldering Conditions
Solder bath temperature : 260
C max. Duration: 10 sec. max.
Pin partial heating
Pin temperature: 300
C max. Duration: 3 sec. max (per 1 pin).
Wave soldering
(Pin only)
Caution The wave soldering applies to the pin only. Ensure that no solder touches the body directly.
5
Symbol
57
PD78P014
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the
PD78P014.
Language Processing Software
78K/0 series common assembler package
78K/0 series common C compiler package
PD78014 subseries device file
78K/0 series common C compiler library source file
RA78K/0
Note 1, 2, 3
CC78K/0
Note 1, 2, 3
DF78014
Note 1, 2, 3
CC78K/0-L
Note 1, 2, 3
Real-Time OS
Debugging Tools
PROM Writing Tools
PROM programmer
Programmer adapter connected to PG-1500
PG-1500 control program
PG-1500
PA-78P014CW
PA-78P014GC
PG-1500 controller
Note 1, 2
78K/0 series common in-circuit emulators
78K/0 series common break board
PD78002/78014 subseries evaluation emulation boards
PD78244 subseries common emulation probes
Socket to be mounted on a user system board made for 64-pin plastic QFP
IE-78000-R screen debugger
78K/0 series common system simulator
PD78014 subseries device file
RX78K/0
Note 1, 2, 3
MX78K/0
Note 1, 2, 3, 6
78K/0 series common real-time OS
78K/0 series common OS
5
IE-78000-R
IE-78000-R-BK
IE-78014-R-EM
EP-78240CW-R
EP-78240GC-R
EV-9200GC-64
SD78K/0
Note 1, 2
SM78K/0
Note 3, 4, 5, 6
DF78014
Note 1, 2, 3, 4, 5
5
5
58
PD78P014
Fuzzy Inference Development Support System
FE9000
Note 1
/FE9200
Note 5
FT9080
Note 1
/FT9085
Note 2
FI78K0
Note 1, 2
FD78K0
Note 1, 2
Notes 1. PC-9800 series (MS-DOS
TM
) based
2. IBM PC/AT
TM
(PC DOS
TM
) based
3. HP9000 series 300
TM
, HP9000 series 700
TM
(HP-UX
TM
) based, SPARCstation
TM
(SunOS
TM
) based, EWS-4800
series (EWS-UX/V) based
4. PC-9800 series (MS-DOS+Windows
TM
) based
5. IBM PC/AT (PC DOS + Windows) based
6. Under development
Remarks 1. For third party development tools, see the 78K/0 Series Selection Guide (IF-1185).
2. RA78K/0, CC78K/0, SD78K/0, and SM78K/0 are used together with the DF78014.
Fuzzy knowledge data creation tool
Translator
Fuzzy inference module
Fuzzy inference debugger
5
5
59
PD78P014
APPENDIX B. RELATED DOCUMENTS
Device Related Documents
Development Tool Related Documents (User's Manual)
Caution The above related documents are subject to change without notice. For design purposes, etc., be
sure to use the latest documents.
Other Related Documents
Document Name
Document No. (Japanese)
Document No. (English)
PD78014/78014Y Series User's Manual
IEU-780
IEU-1343
78K/0 Series User's Manual Instructions
IEU-849
IEU-1372
Basic I
IEA-715
IEA-1288
78K/0 Series Application Notes
Basic II
IEA-740
IEA-1299
Electronic Notebook
IEA-744
IEA-1301
Document Name
Document No. (Japanese)
Document No. (English)
Operation
EEU-809
EEU-1399
Language
EEU-815
EEU-1404
RA78K Series Structured Assembler Preprocessor
EEU-817
EEU-1402
Operation
EEU-656
EEU-1280
Language
EEU-655
EEU-1284
PG-1500 PROM Programmer
EEU-651
EEU-1335
PG-1500 Controller
EEU-704
EEU-1291
IE-78000-R
EEU-810
EEU-1398
IE-78000-R-BK
EEU-867
EEU-1427
SD78K/0 Screen Debugger
Basic
EEU-852
EEU-1414
Reference
EEU-816
EEU-1413
CC78K Series C Compiler
RA78K Series Assembler Package
Document Name
Document No. (Japanese)
Document No. (English)
Package Manual
IEI-635
IEI-1213
Semiconductor Device Mounting Technology Manual
IEI-616
IEI-1207
Quality Grades on Semiconductor Devices
IEI-620
IEI-1209
Semiconductor Devices Quality Guarantee Guide
MEI-603
MEI-1202
60
PD78P014
[MEMO]
61
PD78P014
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction
of the gate oxide and ultimately degrade the device operation. Steps must
be taken to stop generation of static electricity as much as possible, and
quickly dissipate it once, when it has occurred. Environmental control must
be adequate. When it is dry, humidifier should be used. It is recommended
to avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools
including work bench and floor should be grounded. The operator should
be grounded using wrist strap. Semiconductor devices must not be touched
with bare hands. Similar precautions need to be taken for PW boards with
semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of
CMOS devices must be fixed high or low by using a pull-up or pull-down
circuitry. Each unused pin should be connected to V
DD
or GND with a
resistor, if it is considered to have a possibility of being an output pin. All
handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed imme-
diately after power-on for devices having reset function.
PD78P014
FIP is a trademark of NEC Corporation.
IEBus and QTOP are trademarks of NEC Corporation.
MS-DOS and Windows are trademarks of Microsoft Corporation.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 300, HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear
reactor control systems and life support systems. If customers intend to use NEC devices for above applications
or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact
our sales people in advance.
Application examples recommended by NEC Corporation
Standard: Computer, Office equipment, Communication equipment, Test and Measurement equipment,
Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc.
Special:
Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime
systems, etc.
M4 92.6
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