Document Outline

COVER
FEATURES
APPLICATION FIELDS
ORDERING INFORMATION
QUALITY GRADE
DIFFERENCES AMONG uPD78P324, 78P324(A), 78P324(A1), AND 78P324(A2)
PIN CONFIGURATION (Top View)
INTERNAL BLOCK DIAGRAM
1. LIST OF PIN FUNCTIONS
- 1.1 NORMAL OPERATION MODE
- 1.2 PROM PROGRAMMING MODE (RESET# = H, AVDD = L)
- 1.3 PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING
2. DIFFERENCES BETWEEN uPD78P324 AND uPD78324
3. PROM PROGRAMMING
- 3.1 OPERATION MODE
- 3.2 PROCEDURE FOR PROM WRITE
- 3.3 PROCEDURE FOR PROM
4. ERASURE CHARACTERISTICS (uPD78P324KC/KD ONLY)
5. ERASURE WINDOW SEAL (uPD78P324KC/KD ONLY)
6. ONE-TIME PROM PRODUCT SCREENING
7. ELECTRICAL SPECIFICATIONS
8. PACKAGE DRAWINGS
9. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE INSTALLATION PATTERN
APPENDIX B. TOOLS
- B.1 DEVELOPMENT TOOLS
- B.2 EVALUATION TOOLS
- B.3 EMBEDDED SOFTWARE

PD78P324, 78P324(A)

MOS INTEGRATED CIRCUIT

The information in this document is subject to change without notice.

16-/8-Bit Single-Chip Microcomputers

1991, 1995

DATA SHEET

The

PD78P324 is a product in which the

PD78324's internal mask ROM is replaced by a one-time PROM

or EPROM. The one-time PROM product, which enables writing only once, is effective for multiple-device

small production of sets or early start of mass-production. The EPROM product, which enables program

writing, deletion, and rewriting, is the most suitable for system evaluation.

The

PD78P324(A) is more reliable than the

PD78P324. The

PD78P324(A) is a product resulting from

the

PD78324(A) whose internal mask ROM is replaced by a one-time PROM.

For details of functions, please refer to the following User's Manual. Reading this manual is indispensable

especially for designing work.

PD78322 User's Manual: IEU-1248

FEATURES

PD78324 compatible

· For mass-production, this can be replaced by the

PD78324 incorporated in the mask ROM.

q Minimum instruction run time: 250 ns (with the external clock operating at 16 MHz):

PD78P324 & 78P324(A)

320 ns (with the external clock operating at 12.5 MHz):

PD78P324(A1) &

78P324(A2)

q Internal PROM: 32768 x 8 bits

· Writing enabled only once (windowless one-time PROM product)

· Elimination by ultraviolet light and electrical rewriting enabled (EPROM product with window):

PD78P324

only

q ECC circuit incorporated

· High internal PROM content reliablility possible

q PROM programming characteristic:

PD27C1001A compatible

q QTOP

microcomputer compatible

Remark

A QTOP microcomputer is a single-chip microcomputer with one-time PROM for which program

writing, marking, screening, and verifying is completely supported by NEC.

APPLICATION FIELDS

PD78P324: Fields dealing with motor control equipment.

PD78P324(A), 78P324(A1), and 78P324(A2): Automotive and transportation equipments, etc.

This document describes the

PD78P324, 78P324(A),

PD78P324(A1), and

PD78P324(A2) as well. However,

unless there are particular differences, the

PD78P324 is described as a representative product. PROM is

the representative term used for the part common to both the one-time PROM product and the EPROM

product.

Document No. IC-2857

(O. D. No. IC-8315)

Date Published January 1995 P
Printed in Japan

PD78P324, 78P324(A)

ORDERING INFORMATION

Part No.

Package

Internal ROM

Operating Temperature (T

)

PD78P324GJ-5BJ

74-pin plastic QFP(20 x 20 mm)

One-time PROM

10 to +70

PD78P324LP

68-pin plastic QFJ(

950 mil)

One-time PROM

10 to +70

PD78P324KC

68-pin ceramic WQFN

EPROM

10 to +70

PD78P324KD

74-pin ceramic WQFN

EPROM

10 to +70

PD78P324GJ(A)-5BJ

74-pin plastic QFP(20 x 20 mm)

One-time PROM

40 to +85

PD78P324GJ(A1)-5BJ

74-pin plastic QFP(20 x 20 mm)

One-time PROM

40 to +110

PD78P324GJ(A2)-5BJ

74-pin plastic QFP(20 x 20 mm)

One-time PROM

40 to +125

PD78P324LP(A)

68-pin plastic QFJ(

950 mil)

One-time PROM

40 to +85

PD78P324LP(A1)

68-pin plastic QFJ(

950 mil)

One-time PROM

40 to +110

PD78P324LP(A2)

68-pin plastic QFJ(

950 mil)

One-time PROM

40 to +125

QUALITY GRADE

Part No.

Quality Grade

PD78P324GJ-5BJ

Standard

PD78P324LP

Standard

PD78P324KC

Standard

PD78P324KD

Standard

PD78P324GJ(A)-5BJ

Special

PD78P324GJ(A1)-5BJ

Special

PD78P324GJ(A2)-5BJ

Special

PD78P324LP(A)

Special

PD78P324LP(A1)

Special

PD78P324LP(A2)

Special

Please refer to "Quality grade on NEC Semiconductor Devices" (Document number IEI-1209) published by
NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

PD78P324, 78P324(A)

DIFFERENCES AMONG

PD78P324, 78P324(A), 78P324(A1), AND 78P324(A2)

Product Name

Parameter

Quality grade

Operating ambient tempera-
ture (T

)

Operating frequency

Minimum instruction
execution time

Permissible pin injection
current characteristics on
overvoltage application

DC characteristics

AC characteristics

A/D converter characteristics

One-time PROM product

EPROM product

PD78P324

PD78P324(A)

PD78P324(A1)

PD78P324(A2)

Standard

Special

10 to +70

40 to +85

40 to +110

40 to +125

8 to 16 MHz

8 to 12.5 MHz

250 ns (when operated at 16 MHz)

320 ns (when operated at 12.5 MHz)

None

Provided

Differ in the analog pin input leak current, the V

supply current, and the data retention

current.

Differ in the bus timing.

Differ in the analog input voltage and the A/D converter data retention current.

Provided

None

PD78P324, 78P324(A)

PIN CONFIGURATION (Top View)

(1) Normal operation mode

(a) 74-pin plastic QFP(20 x 20 mm); 74-pin ceramic WQFN

P43/AD3

P44/AD4

P45/AD5

P46/AD6

P47/AD7

P50/A8

P51/A9

P52/A10

P53/A11

P54/A12

P55/A13

P56/A14

P57/A15

P70/AN0

P71/AN1

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58

P 0/RTP0

WDTO

RESET

P85/TO11

P84/TO10

P83/TO03

P82/TO02

P81/TO01

P80/TO00

P34/SCK

P33/SI/SB1

P32/SO/SB0

P31/R

P30/T

P42/AD2

P41/AD1

P40/AD0

ASTB

P90/RD

P91/WR

P92/TAS

P93/TMD

P07/RTP7

P06/RTP6

P05/RTP5

P04/RTP4

P03/RTP3

P02/RTP2

P01/RTP1

P72/AN2

P73/AN3

P74/AN4

P75/AN5

P76/AN6

P77/AN7

REF

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2

P24/INTP3

P25/INTP4

P26/INTP5

P27/INTP6

PD78P324GJ-5BJ

PD78P324KD

PD78P324GJ(A)-5BJ

PD78P324GJ(A1)-5BJ

PD78P324GJ(A2)-5BJ

Caution

As a measure against noise, please connect the NC pin to V

. (It is also possible to leave this pin

unconnected.)

Remark

Pin-compatible with

PD78324GJ.

PD78P324, 78P324(A)

(b) 68-pin plastic QFJ(

950 mil); 68-pin ceramic WQFN

P71/AN1

P70/AN0

P57/A15

P56/A14

P55/A13

P54/A12

P53/A11

P52/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44/AD4

P43/AD3

PD78P324LP

PD78P324KC

PD78P324LP(A)

PD78P324LP(A1)

PD78P324LP(A2)

P30/T

P31/R

P32/SO/SB0

P33/SI/SB1

P34/SCK

P80/TO00

P81/TO01

P82/TO02

P83/TO03

P84/TO10

P85/TO11

RESET

WDTO

RTP /P00

1 68 67 66 65 64 63 62 61

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

P01/RTP1

P02/RTP2

P03/RTP3

P04/RTP4

P05/RTP5

P06/RTP6

P07/RTP7

P93/TMD

P92/TAS

P91/WR

P90/RD

ASTB

P40/AD0

P41/AD1

P42/AD2

P27/INTP6/T1

P26/INTP5

P25/INTP4

P24/INTP3

P23/INTP2

P22/INTP1

P21/INTP0

P20/NMI

REF

P77/AN7

P76/AN6

P75/AN5

P74/AN4

P73/AN3

P72/AN2

µ
µ
µ
µ
µ

Remark

Pin-compatible with

PD78324LP.

PD78P324, 78P324(A)

P00-P07

: Port0

P20-P27

: Port2

P30-P34

: Port3

P40-P47

: Port4

P50-P57

: Port5

P70-P77

: Port7

P80-P85

: Port8

P90-P93

: Port9

NMI

: Nonmakable Interrupt

INTP0-INTP6

: Interrupt from Peripherals

RTP0-RTP7

: Realtime Port

: Timer Input

: Transmit Data

: Receive Data

SB0/SO

: Serial Bus/Serial Output

SB1/SI

: Serial Bus/Serial Input

SCK

: Serial Clock

TO00-TO03

TO10, TO11

RESET

: Reset

X1, X2

: Crystal

WDTO

: Watchdog Timer Output

: External Access

TMD

: Turbo Mode

TAS

: Turbo Access Strobe

: Write Strobe

: Read Strobe

ASTB

: Address Strobe

AD0-AD7

: Address/Data Bus

A8-A15

: Address Bus

AN0-AN7

: Analog Input

REF

: Analog Reference Voltage

: Analog V

: Power Supply

: Ground

: Non-connection

Timer Output

PD78P324, 78P324(A)

(2) PROM programming mode (RESET = H, AV

= L)

(a) 74-pin plastic QFP (20 x 20 mm); 74-pin ceramic WQFN

Cautions

1. Codes marked by brackets refer to processing by pins unused in PROM programming mode.

: Connect to V

individually via a resistor.

: Connect to V

Open

: Do not connect anything.

2. As a measure against noise, please connect the NC pin to V

. (It is also possible to leave this pin

unconnected.)

(Open)

(L)

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

(Open)

(G)

(Open)

RESET

A14

A13

A12

A11

A10

A16

A15

PGM

PD78P324GJ-5BJ

PD78P324KD

PD78P324GJ(A)-5BJ

PD78P324GJ(A1)-5BJ

PD78P324GJ(A2)-5BJ

19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37

(L)

(G)

(L)

PD78P324, 78P324(A)

(b) 68-pin plastic QFJ(

950 mil); 68-pin ceramic WQFN

Caution

Codes marked by brackets refer to processing by pins unused in PROM programming mode.

: Connect to V

individually via a resistor.

: Connect to V

Open

: Do not connect anything.

A0-A16

: Address Bus

D0-D7

: Data Bus

: Chip Enable

: Output Enable

PGM

: Programming Mode

RESET

: Programming Power Supply

: Non-connection

Programming Mode Set

(L)

(G)

1 68 67 66 65 64 63 62 61

PD78P324LP

PD78P324KC

PD78P324LP(A)

PD78P324LP(A1)

PD78P324LP(A2)

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

(Open)

(L)

(G)

(L)

PGM

A15

A16

A10

A11

A12

A13

A14

RESET

(Open)

(G)

(Open)

µ
µ
µ
µ
µ

PD78P324, 78P324(A)

INTERNAL BLOCK DIAGRAM

Remark

*: When in PROM programming mode

(P20) NMI

INTP0-INTP5

(P21-P26)

(P80) TO00
(P81) TO01
(P82) TO02
(P83) TO03
(P84) TO10
(P85) TO11

(P27) T1/INTP6

(P34) SCK

(P32) SO/SB0

(P33) SI/SB1

(P30) T

(P31) R

PROGRAMMABLE

INTERRUPT

CONTROLLER

TINER/COUNTER UNIT

(REAL TIME PULSE UNIT)

SERIAL INTERFFACE

(SBI)

(UART)

EXU

PROM

Peripheral RAM

BCU

Main RAM

ALU

ECC

32K

bytes

768

bytes

SYSTEM

CONTROL

BUS

CONTROL

PREFETCH

CONTROL

PORT

WDT

GENERAL

REGISTERS

128 bytes

DATA

MEMORY

128 bytes

MICRO

SEQUENCE

CONTROL

MICRO ROM

A/D CONVERTER

(10 BITS)

RESET

ASTB

TAS

TMD

EA/V

A8-A15 (P50-P57)

AD0-AD7 (P40-P47)

A0-A16*

D0-D7*
PGM*
CE*
OE*

P00-P07 (REALTIME PORT)

P20-P27

P30-P34

P40-P47

P50-P57

P70-P77

P80-P85

P90-P93

WDTO

REF

AN0-AN7

(P70-P77)

PD78P324, 78P324(A)

TABLE OF CONTENTS

LIST OF PIN FUNCTIONS ...........................................................................................................

1.1

NORMAL OPERATION MODE ...........................................................................................................

1.2

PROM PROGRAMMING MODE (RESET = H, AV

= L) .................................................................

1.3

PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING .......................................................................

DIFFERENCE BETWEEN

PD78P324 AND

PD78324 ..............................................................

PROM PROGRAMMING ..............................................................................................................

3.1

OPERATION MODE ............................................................................................................................

3.2

PROCEDURE FOR PROM WRITE ......................................................................................................

3.3

PROCEDURE FOR PROM READ ........................................................................................................

ERASURE CHARACTERISTICS (

PD78P324KC/KD ONLY) .....................................................

ERASURE WINDOW SEAL (

PD78P324KC/KD ONLY) ...........................................................

ONE-TIME PROM PRODUCT SCREENING ................................................................................

ELECTRICAL SPECIFICATIONS ..................................................................................................

PACKAGE DRAWINGS ................................................................................................................

RECOMMENDED SOLDERING CONDITIONS ...........................................................................

APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND

RECOMMENDED SUBSTRATE INSTALLATION PATTERN ..................................

APPENDIX B. TOOLS .........................................................................................................................

B.1

DEVELOPMENT TOOLS .....................................................................................................................

B.2

EVALUATION TOOLS ........................................................................................................................

B.3

EMBEDDED SOFTWARE ....................................................................................................................

PD78P324, 78P324(A)

LIST OF PIN FUNCTIONS

1.1

NORMAL OPERATION MODE

(1) Port pins

Pin Name

P00-P07

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34

P40-P47

P50-P57

P70-P77

P80

P81

P82

P83

P84

P85

P90

P91

P92

P93

Function

Port 0.
8-bit I/O port.
I/O specifiable per bit.
(Operable as a real-time output port as well.)

Port 2.
8-bit input-only port.

Port 3.
5-bit I/O port.
I/O specifiable per bit.

Port 4.
8-bit I/O port.
I/O specifiable in units of eight bits.

Port 5.
8-bit I/O port.
I/O specifiable per bit.

Port 7.
8-bit input-only port.

Port 8.
6-bit I/O port.
I/O specifiable per bit.

Port 9.
4-bit I/O port.
I/O specifiable per bit.

Shared Pin Name

RTP0-RTP7

NMI

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6/TI

SO/SB0

SI/SB1

SCK

AD0-AD7

A8-A15

AN0-AN7

TO00

TO01

TO02

TO03

TO10

TO11

TAS

TMD

I/O

Input

I/O

Input

I/O

PD78P324, 78P324(A)

(2) Pins other than ports (1/2)

I/O

Output

Input

Output

Input

Output

I/O

Output

Function

Real-time output port performing pulse outputs synchro-
nously with the trigger symbols from the real-time pulse
unit (RPU).

External interrupt request input of edge detection.
A valid edge can be selected by the external interrupt
mode register.

Non-maskable interrupt request input of edge detection.
A valid edge can be selected by the external interrupt
mode register.

External counter clock input to Timer 1 (TM1).

Serial data input of the asynchronous serial interface
(UART).

Serial data output of the asynchronous serial interface
(UART).

Serial data input in three-wire mode of the clock synchro-
nous serial interface.

Serial data output in three-wire mode of the clock
synchronous serial interface.

Serial clock I/O of the clock synchronous serial interface.

Address data bus for accessing external memory.

Address bus for accessing external memory.

Read signal output to external memory.

Write signal output to external memory.

Control signal output for accessing the turbo access
manager (

PD71P301)

Note

Output from the real-time pulse unit.

Shared Pin Name

P00-P07

P21

P22

P23

P24

P25

P26

P27/TI

P20

P27/INTP6

P31

P30

P33/SB1

P32/SB0

P32/SO

P33/SI

P34

P40-P47

P50-P57

P90

P91

P92

P93

P80

P81

P82

P83

P84

P85

Pin Name

RTP0-RTP7

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

INTP6

NMI

SB0

SB1

SCK

AD0-AD7

A8-A15

TAS

TMD

TO00

TO01

TO02

TO03

TO10

TO11

Note

The turbo access manager (

PD71P301) is a maintenance product.

PD78P324, 78P324(A)

(2) Pins other than ports (2/2)

I/O

Output

Input

Function

Access to external memory. Timing signal output for
externally latching the lower address which is output
from the AD0-AD7 pin.

Output of the signal which indicates that the watchdog
timer generated a non-maskable interrupt.

Normally, the EA pin is connected to V

. By connecting

the EA pin to Vss, the system is placed in ROM-less mode
to access external memory. The level of the EA pin
cannot be switched over during operation.

Analog input to the A/D converter

Reference voltage input of the A/D converter.

Analog power of the A/D converter.

Ground of the A/D converter.

Input of the system reset.

Connection of the crystal oscillator for system clock
generation. When clocks are supplied externally, they are
input to the X1 pin and their reverse signals are input to
the X2 pin. (The X2 pin can also be left unconnected.)

Positive power voltage.

Ground.

Internally unconnected. Please connect this to Vss. (It can
also be left unconnected.)

Shared Pin Name

P70-P77

Pin Name

ASTB

WDTO

AN0-AN7

REF

RESET

1.2

PROM PROGRAMMING MODE (RESET = H, AV

= L)

I/O

Input

I/O

Input

Function

PROM programming mode setting

Address bus

Data bus

Program input

PROM enable input

Read strobe to PROM

Write power

Positive power voltage

Ground

Internally unconnected. Please connect this to V

. (It can also be left uncon-

nected.)

Pin Name

RESET

A0-A16

D0-D7

PGM

PD78P324, 78P324(A)

1.3

PIN I/O CIRCUIT AND UNUSED-PIN PROCESSING

The I/O circuits of the pins are shown in Table 1-1 and Figure 1-1 some of them in a simplified form.

Table 1-1. I/O Circuit Types of Pins and Recommended Connection Methods When Unused

Pin Name

P00/RTP0-P07/RTP7

P20/NMI

P21/INTP0-P26/INTP5

P27/INTP6/TI

P30/T

P31/R

P32/SO/SB0

P33/SI/SB1

P34/SCK

P40/AD0-P47/AD7

P50/A8-P57/A15

P70/AN0-P77/AN7

P80/TO00-P83/TO03

P84/TO10, P85/TO11

P90/RD

P91/WR

P92/TAS

P93/TMD

WDTO

ASTB

RESET

REF

I/O Circuit Type

Recommended Connection Method When Unused

Input status: Connected to V

or V

via a resistor individually.

Output status: No connection required.

Connected to V

Input status: Connected to V

or V

via a resistor individually.

Output status: No connection required.

Connected to Vss.

Input status: Connected to V

or Vss via a resistor individually.

Output status: No connection required.

No connection required.

Connected to V

. (It is also possible to leave this unconnected.)

PD78P324, 78P324(A)

DIFFERENCES BETWEEN

PD78P324 AND

PD78324

The

PD78P324 is a product in which the

PD78324's internal mask ROM is replaced by a 32KB PROM.

Therefore, these two products share the same functions, except for differences deriving from the ROM

specifications (for example, Write and Verify, etc.). Their differences are shown in Table 2-1 below.

Table 2-1. Differences between

PD78P324 and

PD78324

Product Name

Parameter

Internal program memory
(Electric write)

ECC circuit

PROM programming pin

Package

Electrical characteristics

Others

Cautions

1. The PROM product and the mask ROM product differ in their noise resistance volume and noise

reflection. If replacement of the PROM product with the mask ROM product in the process of trial

to mass production is being considered, ensure to make a sufficient evaluation with the CS

product (not ES product) of the mask ROM product.

2. The

PD78P324(A)/(A1)/(A2) are one-time PROM products only. The differences between the

PD78P324(A)/(A1)/(A2) and the

PD78324(A)/(A1)/(A2) are the same as those shown in the table

above, except in terms of the EPROM product.

PD78P324

PD78324

One-time PROM

EPROM

Mask ROM

(Write enabled only once)

(Rewrite enabled)

With

Without

With

Without

· 68-pin plastic QFJ

· 68-pin ceramic WQFN

· 68-pin plastic QFJ

· 74-pin plastic QFP

· 74-pin ceramic WQFN

· 74-pin plastic QFP

Differ in current consumption, etc.

As they differ in their circuit size and mask layout, their noise resistance volume and
noise reflection differ.

PD78P324, 78P324(A)

PROM PROGRAMMING

The

PD78P324 incorporates an electrically writable 32768-by-8-bit program PROM and an 8192-by-6-bit

ECC (error correcting code) PROM.

ECC corrects the errors in codes written in the program PROM, thus improving the reliability of the PROM

content. Figure 3-1 shows the memory map in programming mode.

Figure 3-1. Memory Map in Programming Mode

ECC (for ECW)

ECW

(4 x 8)

PROM for ECC

Note

(8192 x 6)

Program PROM

(32768 x 8)

A004H
A003H

A000H
9FFFH

8000H
7FFFH

0000H

Note

On the ECC PROM, the lower 6 bits are valid.

When programming, set the RESET pin and the AV

pin to PROM programming mode. The programming

characteristics of the

PD78P324 are compatible with the

PD27C1001A. However, the programming mode

is compatible only with the byte program mode of the

PD27C1001A. For setting on the PROM programmer,

please select the byte program mode of the 27C1001A mode.

When using the ECC circuit, reset the lowest bit (A000.0) of the lowest byte of the ECW (ECC control word)

to enable the operation of the ECC circuit. ECW is a 4-byte register which controls the operation of the ECC

circuit. ECC and ECW are generated automatically with the ECCGEN (ECC generator) which comes with the

RA78K3 assembler package. (ECC is generated in the lower 6 bits; and the upper 2 bits are fixed to 1.)

PD78P324, 78P324(A)

Table 3-1. Pin Functions in Programming Mode

Function

Normal Operation Mode

Programming Mode

Address input

P00-P07, P80, P20, P81-P85, P33, P34

A0-A16

Data input

P40-P47

D0-D07

Program pulse

P32

PGM

Chip enable

P31

Output enable

P30

Program voltage

Mode voltage

RESET, AV

3.1

OPERATION MODE

When placing the microcomputer in programming Write/Verify mode, set it to RESET = H and AV

= L.

In this mode, an operation mode in Table 3-2 can be selected by further setting the CE and OE pins.

When reading the content of the PROM, set it to Read mode. Process the unused pins in accordance with

the instructions in the PIN CONFIGURATION.

Table 3-2. Operation Mode of PROM Programming

Mode

Program Write

Program verify

Program inhibit

Read

Output disable

Standby

RESET

Remark

x: L or H

PGM

+12.5 V

+5 V

+6.5 V

+5 V

D0-D7

Data input

Data output

High impedance

Data output

High impedance

PD78P324, 78P324(A)

3.2

PROCEDURE FOR PROM WRITE

The procedure for writing into the PROM is as follows (see Figure 3-3).

(1) Fix to RESET = H; and AV

= L. Other unused pins are processed as directed by the PIN CONFIGURATION.

(2) Supply +6.5 V to the V

pin; and +12.5 V to the V

pin. Enter the low level into the CE pin.

(3) Enter the initial address into A0-A16.

(4) Enter the Write data into D0-D7.

(5) Enter the 0.1 ms program pulse (active low) into the PGM pin.

(6) Verify mode. Check if the Write data has been written or not.

Enter the active low pulse into the OE pin and read the Write data from D0-D7.

· When written: Move to (8).

· When not able to write: Repeat (4) to (6). If it is not possible to write even when the repetition has been

made ten times, move to (7).

(7) Stop the Write operation as a defective device.

(8) Increment the address.

(9) Repeat (4) to (8) until the final address.

The timing of the above (2) to (7) steps is shown in Figure 3-2.

Figure 3-2. PROM Write/Verify Timing

Hi-Z

Program

Program verify

Address input

Data input

Data output

A0-A16

D0-D7

CE (input)

PGM (input)

OE (input)

+ 12.5V

+ 6.5V

PD78P324, 78P324(A)

3.3

PROCEDURE FOR PROM READ

The PROM content is read to the external data bus (D0-D7) in accordance with the following procedure:

(1) Fix to RESET = H; and AV

= L. Other unused pins are processed as directed by the PIN CONFIGURATION.

(2) Supply +5 V to the V

and V

pins.

(3) Enter the address of the data read into the A0-A16 pin.

(4) Read mode (CE = L; OE = L)

(5) Data is output to the D0-D7 pin.

The timing of the above (2) to (5) is shown in Figure 3-4.

Figure 3-4. PROM Read Timing

Address input

Data output

A0-A14

CE (input)

OE (input)

D0-D7

Hi-Z

PD78P324, 78P324(A)

ERASURE CHARACTERISTICS (

PD78P324KC/KD ONLY)

The

PD78P324KC/KD can erase (FFH) the content of the data written in the program memory and perform

rewriting.

The data content is erased by radiating light with a wavelength shorter than about 400 nm on the erasure

window. Normally, ultraviolet light with a wavelength of 254 nm is radiated. The volume of light required

for erasing the data content completely is as follows:

· Ultraviolet ray intensity x erasure time: 15 W·s/cm

or more

· Erasure time: 15 to 20 mins (This is so when using an ultraviolet lamp of 12,000

W/cm

. However, a

longer time may be required due to performance degradation of the ultraviolet ray lamp or dirt

deposited on the erasure window, etc.)

For erasure, make sure to place the ultraviolet ray lamp at a location within 2.5 cm from the erasure

window. If the ultraviolet ray lamp is equipped with a filter, make sure that the filter is removed for radiation.

ERASURE WINDOW SEAL (

PD78P324KC/KD ONLY)

If the erasure window part of the

PD78P324KC/KD is exposed to sunlight or fluorescent light for too long,

the EPROM data may be erased or the internal circuits may malfunction. To prevent such an accident, please

ensure that the erasure window part is covered with a protective seal except when the data is going to be

erased.

The EPROM package with window is shipped with a protective seal that is NEC's guarantee of quality.

ONE-TIME PROM PRODUCT SCREENING

Structurally, it is not possible for NEC to test the one-time PROM products (

PD78P324GJ-5BJ/(A)/(A1)/

(A2) and 78P324LP/(A)/(A1)/(A2) completely before shipment. Therefore, it recommended that, after writing

the required data, the screening be implemented to verify the PROM after storing the product in the

following temperature and condition.

Storage Temperature

Storage Time

125

24 hrs

NEC provides at a charge services including the one-time PROM writing, sealing, screening and verifying

under the title of QTOP microcomputer. For further details, please contact an NEC salesperson.

PD78P324, 78P324(A)

ELECTRICAL SPECIFICATIONS

(1)

PD78P324 Electrical Specifications (1/9)

Absolute Maximum Ratings (T

= 25

Parameter

Supply voltage

Input voltage

Output voltage

Low-level output current

High-level output current

Analog input voltage

A/D converter reference input voltage

Operating ambient temperature

Storage temperature

Unit

Rating

0.5 to +7.0

0.5 to V

+0.5

0.5 to +13.5

0.5 to +0.5

0.5 to V

+0.5

0.5 to V

+0.5

4.0

1.0

0.5 to V

+0.5

0.5 to AV

+0.5

0.5 to V

+0.5

0.5 to AV

+0.5

10 to +70

65 to +150

Symbol

IAN

REF

stg

Condition

Note 1

All output pins

Total of all output pins

All output pins

Total of all output pins

> V

Note 2

> V

Notes 1. Except P70/AN0-P77/AN7.

2. P70/AN0-P77/AN7 pins.

Caution

If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. In other words, the product may be physically damaged

if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding

these ratings.

Recommended Operating Range

Oscillation Frequency

8MHz

16MHz

10 to +70

+5.0 V

10 %

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

Condition

f = 1 MHz;
0 V except measured pins

MIN.

TUP.

MAX.

Unit

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (2/9)

Oscillator Characteristics (T

= 10 to +70

C, V

= +5 V

10 %, V

= 0 V)

Oscillator

Ceramic oscillator or
crystal oscillator

External clock

Recommended Circuit

Parameter

Oscillation frequency (f

)

X1 input frequency (f

)

X1 input rise time, fall time
(t

, t

)

X1 input high-/low-level
width (t

WXH

, t

WXL

)

MIN.

MAX.

Unit

MHz

Caution

When using the system clock oscillation circuit, wire the part encircled in the dotted line in the

following manner to avoid the influence of the wiring capacity, etc.

· Make the wiring as short as possible.

· Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating

currents run.

· Make sure that the grounding point of the oscillation circuit capacitor always has the same

electrical potential as V

. Avoid grounding with a grand pattern in which very high currents run.

· Do not fetch signals from the oscillation circuit.

HCMOS
inverter

No connection

required

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (4/9)

DC Characteristics (T

= 10 to +70

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Low-level input voltage

High-level input voltage

Low-level output voltage

High-level output voltage

Input leakage current

Analog pin input leakage current

Output leakage current

supply current

Data retention voltage

Data retention current

MIN.

TYP.

MAX.

Unit

0.8

2.2

0.8 V

0.45

1.0

2.5

Symbol

IH1

IH2

LIAN

DD1

DD2

DDDR

Condition

Note 1

Note 2

= 2.0mA

= 400

Note 3

0 V

Note 4

0 V

IAN

REF

0 V

Operation mode

HALT mode

STOP mode

DDDR

= 2.5 V

STOP mode

DDDR

=5.0 V

10%

Notes 1. Pins other than pins in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/

INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.

3. Pins except P20/NMI, EA/V

, X1, X2

4. When not sampling the analog input

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (5/9)

AC Characteristics (T

= 10 to +70

C, V

= +5 V

10%, V

= 0 V, C

= 100pF)

Non-serial Read/Write Operation (when connecting general-purpose memory)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

System clock cycle time

CYK

125

250

Address setup time (vs. ASTB

)

SAST

Address hold time (vs. ASTB

)

HSTA

Address

delay time

DAR

address float time

FRA

Address

data input time

DAID

222

data input time

DRID

112

ASTB

delay time

DSTR

Data hold time (vs. RD

)

HRID

address active time

DRA

RD low-level width

WRL

147

ASTB high-level width

WSTH

Address

delay time

DAW

ASTB

data output time

DSTOD

102

data output time

DWOD

ASTB

delay time

DSTW

Data setup time (vs. WR

)

SODW

147

Data hold time (vs. WR

)

HWOD

ASTB

delay time

DWST

WR low-level width

WWL

147

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (6/9)

CYK

-dependent Bus Timing Definition

Symbol

Calculation formula

MIN./MAX.

Unit

SAST

0.5T30

MIN.

HSTA

0.5T30

MIN.

DAR

T40

MIN.

DAID

(2.5+n) T90

MAX.

DRID

(1.5+n) T75

MAX.

DSTR

0.5T20

MIN.

DRA

0.5T12

MIN.

WRL

(1.5+n) T40

MIN.

WSTH

0.5T25

MIN.

DAW

T40

MIN.

DSTOD

0.5T+40

MAX.

DSTW

0.5T20

MIN.

SODW

1.5T40

MIN.

HWOD

0.5T30

MIN.

DWST

0.5T20

MIN.

WWL

(1.5+n) T40

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. n refers to the count of weight cycles defined by the user software.

3. Among the parameters for bus timing, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (7/9)

Serial Operation (T

= 10 to +70

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

Serial clock cycle time

CYSK

SCK input

External clock

SCK output

Internal divide-by-eight

420

Serial clock low-level width

WSKL

SCK input

External clock

420

SCK output

Internal divide-by-eight

420

Serial clock high-level width

WSKH

SCK input

External clock

420

SI setup time (vs. SCK

)

SRXSK

SI hold time (vs. SCK

)

HSKRX

SCK

SO delay time

DSKTX

R = 1 k

, C = 100pF

210

CYK

-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

CYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKL

SCK input

External clock

4T80

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKH

SCK input

External clock

4T80

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (8/9)

Other Operations (T

= 10 to +70

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

NMI high-/low-level width

WNIH

, t

WNIL

Analog noises removed

INTP0 high-/low-level width

WIOH

, t

WIOL

INTP1 high-/low-level width

WI1H

, t

WI1L

INTP2 high-/low-level width

WI2H

, t

WI2L

INTP3 high-/low-level width

WI3H

, t

WI3L

INTP4 high-/low-level width

WI4H

, t

WI4L

INTP5 high-/low-level width

WI5H

, t

WI5L

INTP6 high-/low-level width

WI6H

, t

WI6L

RESET high-/low-level width

WRSH

, t

WRSL

Analog noises removed

3.5

TI high-/low-level width

WTIH

, t

WTIL

rise/fall time

RVD

, t

FVD

200

Other t

CYK

-dependent Operations

Symbol

Calculation formula

MIN./MAX.

Unit

WIOH

MIN.

WIOL

MIN.

WI1H

MIN.

WI1L

MIN.

WI2H

MIN.

WI2L

MIN.

WI3H

MIN.

WI3L

MIN.

WI4H

MIN.

WI4L

MIN.

WI5H

MIN.

WI5L

MIN.

WI6H

MIN.

WI6L

MIN.

WTIH

MIN.

WTIL

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Only the parameters listed in this table depend on t

CYK

PD78P324, 78P324(A)

(1)

PD78P324 Electrical Specifications (9/9)

AC Timing Test Point

A/D Converter Characteristics (T

= 10 to +70

C, V

= +5 V

10 %, V

= AV

= 0 V, V

0.5 V

)

Parameter

Resolution

Total error

Note1

Quantization error

Conversion time

Sampling time

Zero-scale error

Note1

Full-scale error

Note 1

Non-linear error

Note 1

Analog input voltage

Note 2

Analog input impedance

Reference voltage

REF

current

supply current

A/D converter data retention current

MIN.

TYP.

MAX.

Unit

bit

0.4

%FSR

0.7

%FSR

1/2

LSB

144

CYK

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

Note 3

3.4

1.0

3.0

2.0

6.0

Symbol

CONV

SAMP

IAN

REF

DDDR

Condition

4.5 V

REF

3.5 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

When not sampled

When sampled

Operation mode

DDDR

= 2.5 V

STOP mode

DDDR

=5 V

10%

Notes 1. Quantization error excluded.

2. When 0.3 V

IAN

0 V, the conversion result becomes 000H.

When 0 V < V

IAN

< AV

REF

, the conversion is performed at a resolution of 10 bits.

When AV

REF

IAN

, the conversion result is 3FFH.

3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram

below. (The values in the diagram are TYP. values; therefore, they are not assured.)

0.8V

or 2.2V

0.8V

or 2.2V

0.8V

Test point

20k

10pF

30pF

Analog input pin

( input
capacitance
included )

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (1/9)

Absolute Maximum Ratings (T

= 25

Parameter

Supply voltage

Input voltage

Output voltage

Low-level output current

High-level output current

Analog input voltage

A/D converter reference input voltage

Operating ambient temperature

Storage temperature

Unit

Rating

0.5 to +7.0

0.5 to V

+0.5

0.5 to +13.5

0.5 to +0.5

0.5 to V

+0.5

0.5 to V

+0.5

4.0

1.0

0.5 to V

+0.5

0.5 to AV

+0.5

0.5 to V

+0.5

0.5 to AV

+0.5

40 to +85

65 to +150

Symbol

IAN

REF

stg

Condition

Notes 1, 2

All output pins

Total of all output pins

All output pins

Total of all output pins

> V

Notes 2, 3

> V

Notes 1. Except P70/AN0-P77/AN7.

2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application

is excluded.

3. P70/AN0-P77/AN7 pins.

Caution

If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. In other words, the product may be physically damaged

if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding

these ratings.

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (2/9)

Permissible Pin Injection Current Characteristics in Overvoltage Application (T

= 40 to +85

C, V

= +5 V

10%, V

= 0 V)

Parameter

Positive
injection
current
(V

> V

)

Negative
injection
current
(V

< V

)

Symbol

IJH1

IJH2

IJH

IJL1

IJL2

IJL

MIN.

TYP.

MAX.

Unit

0.5

100

0.4

0.3

Condition

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Cautions

1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion

result of the analog input contiguous to the current injection pin has the value of the standard

in which the injection current is not running plus

2LSB.

2. The mean value (absolute value) of the pin injected current is as follows:

Mean value = ((1/T)

| i(t) |

3/2

dt)

2/3

In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value.

Recommended Operating Range

Oscillation Frequency

8MHz

16MHz

40 to +85

+5.0 V

10 %

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

Condition

f = 1 MHz;
0 V except measured pins

MIN.

TUP.

MAX.

Unit

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (3/9)

Oscillator Characteristics (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

Oscillator

Ceramic oscillator or
crystal oscillator

External clock

Recommended Circuit

Parameter

Oscillation frequency (f

)

X1 input frequency (f

)

X1 input rise time, fall time
(t

, t

)

X1 input high-/low-level
width (t

WXH

, t

WXL

)

MIN.

MAX.

Unit

MHz

Caution

When using the system clock oscillation circuit, wire the part encircled in the dotted line in the

following manner to avoid the influence of the wiring capacity, etc.

· Make the wiring as short as possible.

· Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating

currents run.

· Make sure that the grounding point of the oscillation circuit capacitor always has the same

electrical potential as V

. Avoid grounding with a grand pattern in which very high currents run.

· Do not fetch signals from the oscillation circuit.

HCMOS
inverter

No connection

required

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (4/9)

DC Characteristics (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Low-level input voltage

High-level input voltage

Low-level output voltage

High-level output voltage

Input leakage current

Analog pin input leakage current

Output leakage current

supply current

Data retention voltage

Data retention current

MIN.

TYP.

MAX.

Unit

0.8

2.2

0.8 V

0.45

1.0

2.5

Symbol

IH1

IH2

LIAN

DD1

DD2

DDDR

Condition

Note 1

Note 2

= 2.0mA

= 400

Note 3

0 V

Note 4

0 V

IAN

REF

0 V

Operation mode

HALT mode

STOP mode

DDDR

= 2.5 V

STOP mode

DDDR

=5.0 V

10%

Notes 1. Pins other than pins in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/

INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.

3. Pins except P20/NMI, EA/V

, X1, X2

4. When not sampling the analog input

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (5/9)

AC Characteristics (T

= 40 to +85

C, V

= +5 V

10%, V

= 0 V, C

= 100pF)

Non-serial Read/Write Operation (when connecting general-purpose memory)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

System clock cycle time

CYK

125

250

Address setup time (vs. ASTB

)

SAST

Address hold time (vs. ASTB

)

HSTA

Address

delay time

DAR

address float time

FRA

Address

data input time

DAID

222

data input time

DRID

112

ASTB

delay time

DSTR

Data hold time (vs. RD

)

HRID

address active time

DRA

RD low-level width

WRL

147

ASTB high-level width

WSTH

Address

delay time

DAW

ASTB

data output time

DSTOD

102

data output time

DWOD

ASTB

delay time

DSTW

Data setup time (vs. WR

)

SODW

147

Data hold time (vs. WR

)

HWOD

ASTB

delay time

DWST

WR low-level width

WWL

147

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (6/9)

CYK

-dependent Bus Timing Definition

Symbol

Calculation formula

MIN./MAX.

Unit

SAST

0.5T30

MIN.

HSTA

0.5T30

MIN.

DAR

T40

MIN.

DAID

(2.5+n) T90

MAX.

DRID

(1.5+n) T75

MAX.

DSTR

0.5T20

MIN.

DRA

0.5T12

MIN.

WRL

(1.5+n) T40

MIN.

WSTH

0.5T25

MIN.

DAW

T40

MIN.

DSTOD

0.5T+40

MAX.

DSTW

0.5T20

MIN.

SODW

1.5T40

MIN.

HWOD

0.5T30

MIN.

DWST

0.5T20

MIN.

WWL

(1.5+n) T40

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. n refers to the count of weight cycles defined by the user software.

3. Among the parameters for bus timing, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (7/9)

Serial Operation (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

Serial clock cycle time

CYSK

SCK input

External clock

SCK output

Internal divide-by-eight

420

Serial clock low-level width

WSKL

SCK input

External clock

420

SCK output

Internal divide-by-eight

420

Serial clock high-level width

WSKH

SCK input

External clock

420

SI setup time (vs. SCK

)

SRXSK

SI hold time (vs. SCK

)

HSKRX

SCK

SO delay time

DSKTX

R = 1 k

, C = 100pF

210

CYK

-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

CYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKL

SCK input

External clock

4T80

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKH

SCK input

External clock

4T80

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (8/9)

Other Operations (T

= 40 to +85

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

NMI high-/low-level width

WNIH

, t

WNIL

Analog noises removed

INTP0 high-/low-level width

WIOH

, t

WIOL

INTP1 high-/low-level width

WI1H

, t

WI1L

INTP2 high-/low-level width

WI2H

, t

WI2L

INTP3 high-/low-level width

WI3H

, t

WI3L

INTP4 high-/low-level width

WI4H

, t

WI4L

INTP5 high-/low-level width

WI5H

, t

WI5L

INTP6 high-/low-level width

WI6H

, t

WI6L

RESET high-/low-level width

WRSH

, t

WRSL

Analog noises removed

3.5

TI high-/low-level width

WTIH

, t

WTIL

rise/fall time

RVD

, t

FVD

200

Other t

CYK

-dependent Operations

Symbol

Calculation formula

MIN./MAX.

Unit

WIOH

MIN.

WIOL

MIN.

WI1H

MIN.

WI1L

MIN.

WI2H

MIN.

WI2L

MIN.

WI3H

MIN.

WI3L

MIN.

WI4H

MIN.

WI4L

MIN.

WI5H

MIN.

WI5L

MIN.

WI6H

MIN.

WI6L

MIN.

WTIH

MIN.

WTIL

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Only the parameters listed in this table depend on t

CYK

PD78P324, 78P324(A)

(2)

PD78P324(A) Electrical Specifications (9/9)

AC Timing Test Point

A/D Converter Characteristics (T

= 40 to +85

C, V

= +5 V

10 %, V

= AV

= 0 V, V

0.5 V

)

Parameter

Resolution

Total error

Note 1

Quantization error

Conversion time

Sampling time

Zero-scale error

Note 1

Full-scale error

Note 1

Non-linear error

Note 1

Analog input voltage

Note 2

Analog input impedance

Reference voltage

REF

current

supply current

A/D converter data retention current

MIN.

TYP.

MAX.

Unit

bit

0.4

%FSR

0.7

%FSR

1/2

LSB

144

CYK

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

Note 3

3.4

1.0

3.0

2.0

6.0

Symbol

CONV

SAMP

IAN

REF

DDDR

Condition

4.5 V

REF

3.5 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

When not sampled

When sampled

Operation mode

DDDR

= 2.5 V

STOP mode

DDDR

=5 V

10%

Notes 1. Quantization error excluded.

2. When V

IAN

= 0 V, the conversion result becomes 000H.

When 0 V < V

IAN

< AV

REF

, the conversion is performed at a resolution of 10 bits.

When AV

REF

IAN

, the conversion result is 3FFH.

3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram

below. (The values in the diagram are TYP. values; therefore, they are not assured.)

20k

10pF

30pF

Analog input pin

( input
capacitance
included )

0.8V

or 2.2V

0.8V

or 2.2V

0.8V

Test point

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (1/9)

Absolute Maximum Ratings (T

= 25

Parameter

Supply voltage

Input voltage

Output voltage

Low-level output current

High-level output current

Analog input voltage

A/D converter reference input voltage

Operating ambient temperature

Storage temperature

Unit

Rating

0.5 to +7.0

0.5 to V

+0.5

0.5 to +13.5

0.5 to +0.5

0.5 to V

+0.5

0.5 to V

+0.5

4.0

1.0

0.5 to V

+0.5

0.5 to AV

+0.5

0.5 to V

+0.5

0.5 to AV

+0.5

40 to +110

65 to +150

Symbol

IAN

REF

stg

Condition

Notes 1, 2

All output pins

Total of all output pins

All output pins

Total of all output pins

> V

Notes 2, 3

> V

Notes 1. Except P70/AN0-P77/AN7.

2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application

is excluded.

3. P70/AN0-P77/AN7 pins.

Caution

If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. In other words, the product may be physically damaged

if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding

these ratings.

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (2/9)

Permissible Pin Injection Current Characteristics in Overvoltage Application (T

= 40 to +110

C, V

= +5 V

10%, V

= 0 V)

Parameter

Positive
injection
current
(V

> V

)

Negative
injection
current
(V

< V

)

Symbol

IJH1

IJH2

IJH

IJL1

IJL2

IJL

MIN.

TYP.

MAX.

Unit

0.5

100

0.4

0.3

Condition

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Cautions

1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion

result of the analog input contiguous to the current injection pin has the value of the standard

in which the injection current is not running plus

2LSB.

2. The mean value (absolute value) of the pin injected current is as follows:

Mean value = ((1/T)

| i(t) |

3/2

dt)

2/3

In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value.

Recommended Operating Range

Oscillation Frequency

8MHz

12.5 MHz

40 to +110

+5.0 V

10 %

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Input capacitance

Output capacitance

I/O cpapacitance

Symbol

Condition

f = 1 MHz;
0 V except measured pins

MIN.

TUP.

MAX.

Unit

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (3/9)

Oscillator Characteristics (T

= 40 to +110

C, V

= +5 V

10 %, V

= 0 V)

Oscillator

Ceramic oscillator or
crystal oscillator

External clock

Recommended Circuit

Parameter

Oscillation frequency (f

)

X1 input frequency (f

)

X1 input rise time, fall time
(t

, t

)

X1 input high-/low-level
width (t

WXH

, t

WXL

)

MIN.

MAX.

Unit

12.5

MHz

12.5

MHz

100

Caution

When using the system clock oscillation circuit, wire the part encircled in the dotted line in the

following manner to avoid the influence of the wiring capacity, etc.

· Make the wiring as short as possible.

· Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating

currents run.

· Make sure that the grounding point of the oscillation circuit capacitor always has the same

electrical potential as V

. Avoid grounding with a grand pattern in which very high currents run.

· Do not fetch signals from the oscillation circuit.

HCMOS
inverter

No connection

required

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (4/9)

DC Characteristics (T

= 40 to +110

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Low-level input voltage

High-level input voltage

Low-level output voltage

High-level output voltage

Input leakage current

Analog pin input leakage current

Output leakage current

supply current

Data retention voltage

Data retention current

MIN.

TYP.

MAX.

Unit

0.8

2.2

0.8 V

0.45

1.0

2.5

100

1000

Symbol

IH1

IH2

LIAN

DD1

DD2

DDDR

Condition

Note 1

Note 2

= 2.0mA

= 400

Note 3

0 V

Note 4

0 V

IAN

REF

0 V

Operation mode

HALT mode

STOP mode

DDDR

= 2.5 V

STOP mode

DDDR

=5.0 V

10%

Notes 1. Pins other than pins in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/

INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.

3. Pins except P20/NMI, EA/V

, X1, X2

4. When not sampling the analog input

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (5/9)

AC Characteristics (T

= 40 to +110

C, V

= +5 V

10%, V

= 0 V, C

= 100pF)

Non-serial Read/Write Operation (when connecting general-purpose memory)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

System clock cycle time

CYK

160

250

Address setup time (vs. ASTB

)

SAST

Address hold time (vs. ASTB

)

HSTA

Address

delay time

DAR

120

address float time

FRA

Address

data input time

DAID

310

data input time

DRID

165

ASTB

delay time

DSTR

Data hold time (vs. RD

)

HRID

address active time

DRA

RD low-level width

WRL

191

ASTB high-level width

WSTH

Address

delay time

DAW

120

ASTB

data output time

DSTOD

120

data output time

DWOD

ASTB

delay time

DSTW

Data setup time (vs. WR

)

SODW

191

Data hold time (vs. WR

)

HWOD

ASTB

delay time

DWST

WR low-level width

WWL

195

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (6/9)

CYK

-dependent Bus Timing Definition

Symbol

Calculation formula

MIN./MAX.

Unit

SAST

0.5T40

MIN.

HSTA

0.5T30

MIN.

DAR

T40

MIN.

DAID

(2.5+n) T90

MAX.

DRID

(1.5+n) T75

MAX.

DSTR

0.5T20

MIN.

DRA

0.5T12

MIN.

WRL

(1.5+n) T49

MIN.

WSTH

0.5T25

MIN.

DAW

T40

MIN.

DSTOD

0.5T+40

MAX.

DSTW

0.5T20

MIN.

SODW

1.5T49

MIN.

HWOD

0.5T30

MIN.

DWST

0.5T20

MIN.

WWL

(1.5+n) T45

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. n refers to the count of weight cycles defined by the user software.

3. Among the parameters for bus timing, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (7/9)

Serial Operation (T

= 40 to +110

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

1280

Serial clock cycle time

CYSK

SCK input

External clock

1280

SCK output

Internal divide-by-eight

560

Serial clock low-level width

WSKL

SCK input

External clock

560

SCK output

Internal divide-by-eight

560

Serial clock high-level width

WSKH

SCK input

External clock

560

SI setup time (vs. SCK

)

SRXSK

SI hold time (vs. SCK

)

HSKRX

SCK

SO delay time

DSKTX

R = 1 k

, C = 100pF

210

CYK

-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

CYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKL

SCK input

External clock

4T80

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKH

SCK input

External clock

4T80

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (8/9)

Other Operations (T

= 40 to +110

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

NMI high-/low-level width

WNIH

, t

WNIL

Analog noises removed

INTP0 high-/low-level width

WIOH

, t

WIOL

1280

INTP1 high-/low-level width

WI1H

, t

WI1L

1280

INTP2 high-/low-level width

WI2H

, t

WI2L

1280

INTP3 high-/low-level width

WI3H

, t

WI3L

1280

INTP4 high-/low-level width

WI4H

, t

WI4L

1280

INTP5 high-/low-level width

WI5H

, t

WI5L

1280

INTP6 high-/low-level width

WI6H

, t

WI6L

1280

RESET high-/low-level width

WRSH

, t

WRSL

Analog noises removed

3.5

TI high-/low-level width

WTIH

, t

WTIL

1280

rise/fall time

RVD

, t

FVD

200

Other t

CYK

-dependent Operations

Symbol

Calculation formula

MIN./MAX.

Unit

WIOH

MIN.

WIOL

MIN.

WI1H

MIN.

WI1L

MIN.

WI2H

MIN.

WI2L

MIN.

WI3H

MIN.

WI3L

MIN.

WI4H

MIN.

WI4L

MIN.

WI5H

MIN.

WI5L

MIN.

WI6H

MIN.

WI6L

MIN.

WTIH

MIN.

WTIL

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Only the parameters listed in this table depend on t

CYK

PD78P324, 78P324(A)

(3)

PD78P324(A1) Electrical Specifications (9/9)

AC Timing Test Point

A/D Converter Characteristics (T

= 40 to +110

C, V

= +5 V

10 %, V

= AV

= 0 V, V

0.5 V

)

Parameter

Resolution

Total error

Note 1

Quantization error

Conversion time

Sampling time

Zero-scale error

Note 1

Full-scale error

Note 1

Non-linear error

Note 1

Analog input voltage

Note 2

Analog input impedance

Reference voltage

REF

current

supply current

A/D converter data retention current

MIN.

TYP.

MAX.

Unit

bit

0.4

%FSR

0.7

%FSR

1/2

LSB

144

CYK

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

Note 3

3.4

1.0

3.0

2.0

6.0

100

1000

Symbol

CONV

SAMP

IAN

REF

DDDR

Condition

4.5 V

REF

3.5 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

When not sampled

When sampled

Operation mode

DDDR

= 2.5 V

STOP mode

DDDR

=5 V

10%

Notes 1. Quantization error excluded.

2. When V

IAN

= 0 V, the conversion result becomes 000H.

When 0 V < V

IAN

< AV

REF

, the conversion is performed at a resolution of 10 bits.

When AV

REF

IAN

, the conversion result is 3FFH.

3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram

below. (The values in the diagram are TYP. values; therefore, they are not assured.)

0.8V

or 2.2V

0.8V

or 2.2V

0.8V

Test point

20k

10pF

30pF

Analog input pin

( input
capacitance
included )

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (1/9)

Absolute Maximum Ratings (T

= 25

Parameter

Supply voltage

Input voltage

Output voltage

Low-level output current

High-level output current

Analog input voltage

A/D converter reference input voltage

Operating ambient temperature

Storage temperature

Unit

Rating

0.5 to +7.0

0.5 to V

+0.5

0.5 to +13.5

0.5 to +0.5

0.5 to V

+0.5

0.5 to V

+0.5

4.0

1.0

0.5 to V

+0.5

0.5 to AV

+0.5

0.5 to V

+0.5

0.5 to AV

+0.5

40 to +125

65 to +150

Symbol

IAN

REF

stg

Condition

Notes 1, 2

All output pins

Total of all output pins

All output pins

Total of all output pins

> V

Notes 2, 3

> V

Notes 1. Except P70/AN0-P77/AN7.

2. The overvoltage condition of the allowable pin injectioncurrent characteristics in overvoltage application

is excluded.

3. P70/AN0-P77/AN7 pins.

Caution

If the absolute maximum rating of any one of the parameters is exceeded even momentarily, the

quality of the product may be degraded. In other words, the product may be physically damaged

if any of the absolute maximum ratings is exceeded. Be sure to use the product without exceeding

these ratings.

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (2/9)

Permissible Pin Injection Current Characteristics in Overvoltage Application (T

= 40 to +125

C, V

= +5 V

10%, V

= 0 V)

Parameter

Positive
injection
current
(V

> V

)

Negative
injection
current
(V

< V

)

Symbol

IJH1

IJH2

IJH

IJL1

IJL2

IJL

MIN.

TYP.

MAX.

Unit

0.5

100

0.4

0.3

Condition

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Peak value

Mean value

1 pin

Peak value

Mean value

Peak value

Total of all input pins

Mean value

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Input ports other
than ANn (n = 0-7)

ANn (n = 0-7)

Cautions. 1. When the injection current has run into the analog input pin (ANn: n = 0-7), the A/D conversion

result of the analog input contiguous to the current injection pin has the value of the standard

in which the injection current is not running plus

2LSB.

2. The mean value (absolute value) of the pin injected current is as follows:

Mean value = ((1/T)

| i(t) |

3/2

dt)

2/3

In this, i(t) refers to the pin injected current. The maximum value of |i(t)| is the peak value.

Recommended Operating Range

Oscillation Frequency

8MHz

12.5 MHz

40 to +125

+5.0 V

10 %

Capacitance (T

= 25

C, V

= V

= 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

Condition

f = 1 MHz;
0 V except measured pins

MIN.

TUP.

MAX.

Unit

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (3/9)

Oscillator Characteristics (T

= 40 to +125

C, V

= +5 V

10 %, V

= 0 V)

Oscillator

Ceramic oscillator or
crystal oscillator

External clock

Recommended Circuit

Parameter

Oscillation frequency (f

)

X1 input frequency (f

)

X1 input rise time, fall time
(t

, t

)

X1 input high-/low-level
width (t

WXH

, t

WXL

)

MIN.

MAX.

Unit

12.5

MHz

12.5

MHz

100

Caution

When using the system clock oscillation circuit, wire the part encircled in the dotted line in the

following manner to avoid the influence of the wiring capacity, etc.

· Make the wiring as short as possible.

· Avoid intersecting other signal conductors. Avoid approaching lines in which very high fluctuating

currents run.

· Make sure that the grounding point of the oscillation circuit capacitor always has the same

electrical potential as V

. Avoid grounding with a grand pattern in which very high currents run.

· Do not fetch signals from the oscillation circuit.

HCMOS
inverter

No connection

required

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (4/9)

DC Characteristics (T

= 40 to +125

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Low-level input voltage

High-level input voltage

Low-level output voltage

High-level output voltage

Input leakage current

Analog pin input leakage current

Output leakage current

supply current

Data retention voltage

Data retention current

MIN.

TYP.

MAX.

Unit

0.8

2.2

0.8 V

0.45

1.0

2.5

100

1000

Symbol

IH1

IH2

LIAN

DD1

DD2

DDDR

Condition

Note 1

Note 2

= 2.0mA

= 400

Note 3

0 V

Note 4

0 V

IAN

REF

0 V

Operation mode

HALT mode

STOP mode

DDDR

= 2.5 V

STOP mode

DDDR

=5.0 V

10%

Notes 1. Pins other than pins in Note 2.

2. RESET, X1, X2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2, P24/INTP3, P25/INTP4, P26/INTP5, P27/

INTP6/TI, P32/SO/SB0, P33/SI/SB1, P34/SCK pins.

3. Pins except P20/NMI, EA/V

, X1, X2

4. When not sampling the analog input

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (5/9)

AC Characteristics (T

= 40 to +125

C, V

= +5 V

10%, V

= 0 V, C

= 100pF)

Non-serial Read/Write Operation (when connecting general-purpose memory)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

System clock cycle time

CYK

160

250

Address setup time (vs. ASTB

)

SAST

Address hold time (vs. ASTB

)

HSTA

Address

delay time

DAR

120

address float time

FRA

Address

data input time

DAID

310

data input time

DRID

165

ASTB

delay time

DSTR

Data hold time (vs. RD

)

HRID

address active time

DRA

RD low-level width

WRL

191

ASTB high-level width

WSTH

Address

delay time

DAW

120

ASTB

data output time

DSTOD

120

data output time

DWOD

ASTB

delay time

DSTW

Data setup time (vs. WR

)

SODW

191

Data hold time (vs. WR

)

HWOD

ASTB

delay time

DWST

WR low-level width

WWL

195

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (6/9)

CYK

-dependent Bus Timing Definition

Symbol

Calculation formula

MIN./MAX.

Unit

SAST

0.5T40

MIN.

HSTA

0.5T30

MIN.

DAR

T40

MIN.

DAID

(2.5+n) T90

MAX.

DRID

(1.5+n) T75

MAX.

DSTR

0.5T20

MIN.

DRA

0.5T12

MIN.

WRL

(1.5+n) T49

MIN.

WSTH

0.5T25

MIN.

DAW

T40

MIN.

DSTOD

0.5T+40

MAX.

DSTW

0.5T20

MIN.

SODW

1.5T49

MIN.

HWOD

0.5T30

MIN.

DWST

0.5T20

MIN.

WWL

(1.5+n) T45

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. n refers to the count of weight cycles defined by the user software.

3. Among the parameters for bus timing, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (7/9)

Serial Operation (T

= 40 to +125

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

SCK output

Internal divide-by-eight

1280

Serial clock cycle time

CYSK

SCK input

External clock

1280

SCK output

Internal divide-by-eight

560

Serial clock low-level width

WSKL

SCK input

External clock

560

SCK output

Internal divide-by-eight

560

Serial clock high-level width

WSKH

SCK input

External clock

560

SI setup time (vs. SCK

)

SRXSK

SI hold time (vs. SCK

)

HSKRX

SCK

SO delay time

DSKTX

R = 1 k

, C = 100pF

210

CYK

-dependent Serial Operation

Symbol

Condition

Calculation Formula

MIN./MAX.

Unit

SCK output

Internal divide-by-eight

MIN.

CYSK

SCK input

External clock

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKL

SCK input

External clock

4T80

MIN.

SCK output

Internal divide-by-eight

4T80

MIN.

WSKH

SCK input

External clock

4T80

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Among the parameters for serial operation, only those listed in this table are dependent on t

CYK

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (8/9)

Other Operations (T

= 40 to +125

C, V

= +5 V

10 %, V

= 0 V)

Parameter

Symbol

Condition

MIN.

MAX.

Unit

NMI high-/low-level width

WNIH

, t

WNIL

Analog noises removed

INTP0 high-/low-level width

WIOH

, t

WIOL

1280

INTP1 high-/low-level width

WI1H

, t

WI1L

1280

INTP2 high-/low-level width

WI2H

, t

WI2L

1280

INTP3 high-/low-level width

WI3H

, t

WI3L

1280

INTP4 high-/low-level width

WI4H

, t

WI4L

1280

INTP5 high-/low-level width

WI5H

, t

WI5L

1280

INTP6 high-/low-level width

WI6H

, t

WI6L

1280

RESET high-/low-level width

WRSH

, t

WRSL

Analog noises removed

3.5

TI high-/low-level width

WTIH

, t

WTIL

1280

rise/fall time

RVD

, t

FVD

200

Other t

CYK

-dependent Operations

Symbol

Calculation formula

MIN./MAX.

Unit

WIOH

MIN.

WIOL

MIN.

WI1H

MIN.

WI1L

MIN.

WI2H

MIN.

WI2L

MIN.

WI3H

MIN.

WI3L

MIN.

WI4H

MIN.

WI4L

MIN.

WI5H

MIN.

WI5L

MIN.

WI6H

MIN.

WI6L

MIN.

WTIH

MIN.

WTIL

MIN.

Remarks

1. T = t

CYK

= 1/f

CLK

refers to the internal system clock frequency)

2. Only the parameters listed in this table depend on t

CYK

PD78P324, 78P324(A)

(4)

PD78P324(A2) Electrical Specifications (9/9)

AC Timing Test Point

A/D Converter Characteristics (T

= 40 to +125

C, V

= +5 V

10 %, V

= AV

= 0 V, V

0.5 V

)

Parameter

Resolution

Total error

Note 1

Quantization error

Conversion time

Sampling time

Zero-scale error

Note 1

Full-scale error

Note 1

Non-linear error

Note 1

Analog input voltage

Note 2

Analog input impedance

Reference voltage

REF

current

supply current

A/D converter data retention current

MIN.

TYP.

MAX.

Unit

bit

0.4

%FSR

0.7

%FSR

1/2

LSB

144

CYK

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

1.5

2.5

LSB

1.5

4.5

LSB

Note 3

3.4

1.0

3.0

2.0

6.0

100

1000

Symbol

CONV

SAMP

IAN

REF

DDDR

Condition

4.5 V

REF

3.5 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

4.5 V

REF

3.4 V

REF

When not sampled

When sampled

Operation mode

DDDR

= 2.5 V

STOP mode

DDDR

=5 V

10%

Notes 1. Quantization error excluded.

2. When V

IAN

= 0 V, the conversion result becomes 000H.

When 0 V < V

IAN

< AV

REF

, the conversion is performed at a resolution of 10 bits.

When AV

REF

IAN

, the conversion result is 3FFH.

3. The analog input impedance in sampling is the same as the equivalent circuit shown in the diagram

below. (The values in the diagram are TYP. values; therefore, they are not assured.)

0.8V

or 2.2V

0.8V

or 2.2V

0.8V

Test point

20k

10pF

30pF

Analog input pin

( input
capacitance
included )

PD78P324, 78P324(A)

Non-serial Read Operation

Non-serial Write Operation

(CLK)

P50-P57

(Output)

Hi-Z

P40-P47

(Input/Output)

ASTB

(Output)

Data (Input)

Lower address(Output)

Upper address

(Output)

(CLK)

P50-P57

(Output)

P40-P47

(Input/Output)

ASTB

(Output)

Upper address

Undfined

Lower address(Output)

Data (Output)

Lower address(Output)

WSTH

DAID

SAST

HSTA

HRID

FRA

DSTR

DAR

CYK

DRA

DRID

WRL

SAST

WSTH

HSTA

DSTOD

DSTW

DAW

DWOD

SODW

HWOD

DWST

WWL

PD78P324, 78P324(A)

Parameter

High-level input voltage

Low-level input voltage

Input leakage current

High-level output voltage

Low-level output voltage

Input current

Output leakage current

DDP

supply voltage

DDP

supply current

Symbol

Note 1

Condition

DDP

Note 2

= 400

= 2.0

A9(P20/NMI) pin, 0

DDP

, OE = V

Program memory Write mode

Program memory Read mode

Program memory Write mode

Program memory Read mode

Program memory Write mode

Program memory Read mode

Program memory Write mode
CE = PGM

Program memory Read mode
V

= V

DC Programming Characteristics (T

= 25

C, V

= 0 V)

MIN.

TYP.

MAX.

Unit

2.4

DDP

+0.3

0.3

0.8

2.4

0.45

6.25

6.75

4.5

5.0

5.5

12.2

12.5

12.8

= V

DDP

100

Notes 1. Refers to the symbol of the corresponding

PD27C1001A.

2. V

DDP

refers to the V

pin in programming.

Symbol

DDP

PD78P324, 78P324(A)

AC Programming Characteristics (T

= 25

C, V

= 0 V)

In PROM Write Mode

Parameter

Address setup time

CE set time

Input data setup time

Address hold time

Input data hold time

Output data hold time

setup time

DDP

setup time

Initial program pulse width

OE set time

valid data delay time

MIN.

TYP.

MAX.

Unit

130

0.095

0.1

0.105

200

Symbol

Note1

CES

VPS

VDS

Note 2

OES

Condition

Notes 1. Corresponds to the symbol of

PD27C1001A (t

VDS

excluded).

2. The symbol of t

VDS

PD27C1001A is t

VCS

In PROM Read Mode

Parameter

Address

data output time

Data hold time
(vs. OE

, CE

)

Note 2

Data hold time (vs. address)

MIN.

TYP.

MAX.

Unit

130

Symbol

Note1

ACC

Condition

CE = OE = V

OE = V

CE = V

or OE = V

CE = OE = V

Notes 1. Corresponds to the symbol of

PD27C1001A.

2. t

refers to the time when either OE or CE became V

first.

PD78P324, 78P324(A)

PROM Write Mode Timing

Cautions

1. Ensure to apply V

DDP

before V

, and disconnect it after V

2. Ensure that V

does not exceed +13.5 V even when the overshoot is included.

3. Taking out or putting in while +12.5 V is applied to V

may cause adverse effects on the reliability.

PROM Read Mode Timing

Notes 1. To read within the range of t

ACC

, please make sure that the delay time from CE's falling edge of the

OE input is up to t

ACC

-t

2. t

refers to the time when either OE or CE became V

first.

A0-A16

D0-D7

DDP

+ 1.5

DDP

PGM

Hi-Z

Program

Program verify

VPS

VDS

CES

Data output

Data input

Hi-Z

OES

Note 1

Note 2

A0-A16

D0-D7

Vailed address

Hi-Z

ACC

Data output

Hi-Z

Note 1

PD78P324, 78P324(A)

PACKAGE DRAWINGS

74-Pin Plastic QFP(

20)

ITEM

MILLIMETERS

INCHES

2.0

1.0

0.20

0.079

0.039

0.008

S74GJ-100-5BJ-3

NOTE

Each lead centerline is located within 0.20 mm (0.008 inch) of
its true position (T.P.) at maximum material condition.

20.0±0.2

0.787

0.15

0.006

0.1±0.1

0.004±0.004

+0.004

0.003

+0.009

0.008

23.2±0.4

0.913

0.40±0.10

0.016+0.004

0.005

0.8±0.2

0.031+0.009

0.008

0.10

0.004

3.7

0.146

4.0 MAX.

0.158 MAX.

+0.10

0.05

20.0±0.2

0.787+0.009

0.008

+0.017

0.016

1.0 (T.P.)

0.039 (T.P.)

±5

23.2±0.4

0.913+0.017

0.016

2.0

1.0

0.079

0.039

1.6±0.2

0.063±0.008

detail of lead end

Remark

The package and material of the ES product

are equivalent to those for mass production.

PD78P324, 78P324(A)

P68L-50A1-2

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

+0.007

0.006

25.2±0.2

24.20

25.2±0.2

1.94±0.15

0.6

4.4±0.2

2.8±0.2

0.9 MIN.

3.4

1.27 (T.P.)

0.40±1.0

0.12

23.12±0.20

0.15

R 0.8

0.20

+0.10

0.05

0.992±0.008

0.953

0.992±0.008

0.076

0.024

0.173

0.110

0.035 MIN.

0.134

0.050 (T.P.)

0.016

0.005

0.910

0.006

R 0.031

0.008

+0.009

0.008

+0.009

0.008

+0.004

0.005

+0.004

0.002

+0.009

0.008

68 PIN PLASTIC QFJ ( 950 mil)

Remark

The package and material

of the ES product are

equivalent to those for mass

production.

PD78P324, 78P324(A)

74 PIN CERAMIC WQFN

X74KW-100A-1

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.

20.0±0.4

18.0

20.0±0.4

1.94

2.14

4.0 MAX.

0.51±0.10

0.10

1.0 (T.P.)

1.0±0.2

C 0.3

2.0

R 2.0

10.0

0.7±0.2

C 1.5

0.787

0.709

0.787

0.076

0.084

0.158 MAX.

0.020±0.004

0.004

0.039 (T.P.)

0.039

C 0.012

0.079

R 0.079

0.394

0.028

C 0.059

+0.017

0.016

+0.017

0.016

+0.009

0.008

+0.008

0.009

Remark

The package and material of the

ES product are equivalent to

those for mass production.

PD78P324, 78P324(A)

68 PIN CERAMIC WQFN

X68KW-50A-1

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.12
mm (0.005 inch) of its true position (T.P.) at
maximum material condition.

24.13±0.4

21.5

24.13±0.4

1.65

2.03

3.50 MAX.

0.64±0.10

0.12

1.27 (T.P.)

1.27±0.2

2.16±0.2

R 0.2

C 1.02

1.905

R 3.0

12.0

C 0.5

0.950±0.016

0.846

0.950±0.016

0.065

0.080

0.138 MAX.

0.025

0.005

0.05 (T.P.)

0.05±0.008

0.085±0.008

R 0.008

C 0.04

0.075

R 0.118

0.472

C 0.020

+0.005

0.004

Remark

The package and material of the

ES product are equivalent to those

for mass production.

PD78P324, 78P324(A)

RECOMMENDED SOLDERING CONDITIONS

Please solder the package of this product under the conditions recommended as follows.

For details of the recommended conditions for soldering, please refer to the information document

"Semiconductor Device Mounting Technology Manual" (IEI-1207).

For soldering methods and conditions other than those recommended below, please contact NEC sales

personnel.

Table 9-1. Soldering Conditions for Surface-Mount Type (1)

PD78P324GJ-5BJ

: 74-pin plastic QFP (20 x 20 mm)

PD78P324LP

: 68-pin plastic QFJ (

950 mil)

PD78P324LP(A)

: 68-pin plastic QFJ (

950 mil)

PD78P324LP(A1)

: 68-pin plastic QFJ (

950 mil)

PD78P324LP(A2)

: 68-pin plastic QFJ (

950 mil)

Soldering Method

Soldering Condition

Infrared reflow

Package peak temperature : 230

C; time : within 30 secs (210

C or more);

Note

(hereafter, pre-baked for 36 hrs at 125

VPS

Package peak temperature : 215

C; time : within 40 secs (200

C or more);

Note

(hereafter, pre-baked for 36 hrs at 125

Wave soldering

Solder bath temperature: no more than 260

C; time : within 10 secs; count:

once; preheating temperature : 120

C max. (package surface temperature);

day limit : 7 days

Note

(hereafter, pre-baked for 36 hours at 125

Pin part heating

Pin temperature : no more than 300

C; time : within 3 secs (per device side)

Recommended

Condition Symbol

IR30-367-1

VP15-367-1

WS60-367-1

Note

Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25

and no more than 65 %RH.

Caution

Avoid using multiple soldering methods at the same time (except the pin part heating method).

PD78P324, 78P324(A)

Table 9-2. Soldering Conditions for Surface-Mount Type (2)

PD78P324GJ(A)-5BJ

: 74-pin plastic QFP (20 x 20 mm)

PD78P324GJ(A1)-5BJ

: 74-pin plastic QFP (20 x 20 mm)

PD78P324GJ(A2)-5BJ

: 74-pin plastic QFP (20 x 20 mm)

Soldering Method

Soldering Condition

Infrared reflow

Package peak temperature: 235

C; time: within 30 secs (210

C or more);

Note

(hereafter, pre-baked for 36 hrs at 125

<Caution>
(1) The second reflow should be started after the temperature of the device

which would have been changed by the first reflow has returned to
normal.

(2) Please avoid flux water washing after the first reflow.

VPS

Package peak temperature: 215

C; time: within 40 secs (200

C or more);

Note

(hereafter, pre-baked for 36 hrs at

125

<Caution>
(1) The second reflow should be started after the temperature of the device

which would have been changed by the first reflow has returned to
normal.

(2) Please avoid flux water washing after the first reflow.

Wave soldering

Solder bath temperature: no more than 260

C; time: within 10 secs; count:

once; preheating temperature: up to 120

C (package surface temperature);

day limit: 7 days

Note

(hereafter, pre-baked for 36 hours at 125

Pin part heating

Pin temperature: no more than 300

C; time: within 3 secs (per device side)

Recommended

Condition Symbol

IR35-367-2

VP15-367-2

WS60-367-1

Note

Refers to the number of days for storage after the dry pack is opened. The storage conditions are 25

and no more than 65 %RH.

Caution

Avoid using two or more soldering methods at the same time (except the pin part heating method).

PD78P324, 78P324(A)

APPENDIX A. CONVERSION SOCKET PACKAGE DRAWING AND RECOMMENDED SUBSTRATE

INSTALLATION PATTERN

Figure A-1. Conversion Socket (EV-9200G-74) Package Drawing (Reference)

C 1.5

EV-9200G-74

No.1 pin index

EV-9200G-74-G0

ITEM

MILLIMETERS

INCHES

25.0

20.35

25.0

4-C 2.8

1.0

11.0

22.0

24.7

5.0

22.0

24.7

8.0

7.8

2.5

2.0

1.35

0.35±0.1

2.3

1.5

0.984

0.801

0.984

4-C 0.11

0.039

0.433

0.866

0.972

0.197

0.866

0.972

0.315

0.307

0.098

0.079

0.053

0.014

0.091

0.059

+0.004

0.005

PD78P324, 78P324(A)

Figure A-2. Recommended Pattern for Conversion Socket (EV-9200G-74)

Substrate Installation (Reference)

0.039

0.709=0.709

0.039

0.709=0.709

EV-9200G-74-P0

ITEM

MILLIMETERS

INCHES

25.7

21.0

25.7

11.00±0.08

5.00±0.08

0.6±0.02

2.36±0.03

1.57±0.03

1.012

0.827

1.012

0.433

0.197

0.024

0.093

0.062

1.0±0.02

18=18.0±0.05

1.0±0.02

18=18.0±0.05

+0.002

0.001

+0.002

0.003

+0.002

0.001

+0.002

0.003

+0.004

0.003

+0.003

0.004

+0.001

0.002

+0.001

0.002

+0.001

0.002

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY
MANUAL" (IEI-1207).

Caution

PD78P324, 78P324(A)

APPENDIX B. TOOLS

B.1

DEVELOPMENT TOOLS

The following development tools have been made available for development of the system using the

PD78P324.

Language Processors

78K/III series relocatable assem-
bler (RA78K/III)

78K/III series C compiler (CC78K/III)

Refers to the relocatable assembler which can be used commonly for the 78K/III
series. Equipped with the macro function, the relocatable assembler is aimed at
improved development efficiency. The assembler is also accompanied by the
structured assembler which can describe the program control structure explicitly,
thus making it possible to improve the productivity and the maintainability of the
program.

Host machine

PC-9800 series

IBM PC/AT

and

its compatible
machine

HP9000 series
300

SPARCstation

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Cartridge tape
(QIC-24)

Part number

S5A13RA78K3

S5A10RA78K3

S7B13RA78K3

S7B10RA78K3

S3H15RA78K3

S3K15RA78K3

MS-DOS

PC DOS

HP-UX

SunOS

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

HP9000 series 300

SPARCstation

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Cartridge tape
(QIC-24)

Part number

S5A13CC78K3

S5A10CC78K3

S7B13CC78K3

S7B10CC78K3

S3H15CC78K3

S3K15CC78K3

MS-DOS

PC DOS

HP-UX

SunOS

Refers to the C compiler which can be commonly used in the 78K/III series. This
compiler is a program converting the programs written in the C language to those
object codes which are executable by microcomputers. When using this compiler,
the 78K/III series relocatable assembler (RA78K/III) is required.

Remark

Relocatable assembler and C compiler operations are assured only on the host machine and the OS

above.

PD78P324, 78P324(A)

PG-1500

UNISITE
2900
3900

Note

PA-78P324GJ

PA-78P324LP

PA-78P324KC

PA-78P324KD

PG-1500 controller

PROM Write Tools

This PROM programmer is capable of programming by manipulating a PROM-
incorporated single-chip microcomputer from a stand-alone or host machine after
connecting the accompanying board and the separately available programmer
adapter.
It can also program representative PROMs ranging from 256 Kbits to 4 Mbits.

These are PROM programmers made by Data I/O Japan.

These are the PROM programmer adapters for writing programs into the

PD78P324 on general-purpose PROM programmer such as PG-1500.

PA-78P324GJ: for

PD78P324GJ

PA-78P324LP: for

PD78P324LP

PA-78P324KC: for

PD78P324KC

PA-78P324KD: for

PD78P324KD

A PG-1500 and a host machine are connected with the serial interface or the parallel
interface to control the PG-1500 on the host machine.

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13PG1500

S5A10PG1500

S7B13PG1500

S7B10PG1500

MS-DOS

PC DOS

Hardware

Software

Note

Being evaluated.

Remark

The PG-1500 controller operation is assured only on the host machine and the OS above.

PD78P324, 78P324(A)

Debugging Tools

IE-78327-R

IE-78320-R

Note

EP-78320GJ-R

EP-78320L-R

IE-78327-R
control program
(IE controller)

IE-78320-R
control program

Note

(IE controller)

These are the in-circuit emulators which can be used for the development and
debugging of application systems. Debugging is performed by connecting them to a
host machine. The IE-78327-R can be used commonly for both the

PD78322

subseries and the

PD78328 subseries.

The IE-78320-R can be used for the

PD78322 subseries.

These are the emulation probes for connecting the IE-78327-R or IE-78320-R to a
target system.
EP-78320GJ-R: for 74-pin plastic QFP
EP-78320L-R: for 68-pin plastic QFJ

This program is for controlling the IE-78327-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.

Hardware

Software

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13IE78327

S5A10IE78327

S7B13IE78327

S7B10IE78327

MS-DOS

PC DOS

This program is for controlling the IE-78320-R from a host machine. It can execute
commands automatically, thus enabling more efficient debugging.

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

5-inch 2HC

Part number

S5A13IE78320

S5A10IE78320

S7B10IE78320

MS-DOS

PC DOS

Remarks

1. The operation of each software is assured only on the host machine and the OS above.

PD78322 subseries:

PD78320, 78322, 78P322, 78323, 78324, 78P324, 78320(A), 78320(A1),

78320(A2), 78322(A), 78322(A1), 78322(A2), 78323(A), 78323(A1), 78323(A2),

78324(A), 78324(A1), 78324(A2), 78P324(A), 78P324(A1), 78P324(A2)

PD78328 subseries:

PD78327, 78328, 78P328, 78327(A), 78328(A)

Note

The existing product IE-78320-R is a maintenance product. If you are going to newly purchase an in-circuit

emulator, please use the alternative product IE-78327-R.

PD78P324, 78P324(A)

Development Tool Configurations

Note

The socket is supplied with the emulation probe.

Remarks

1. It is also possible to use the host machine and the PG-1500 by connecting them directly by the RS-

232-C.

2. In the diagram above, representative software supply media and 3.5-inch FDs.

Host machine

PC-9800 series
IBM PC/AT or its compatible machine

Software

Relocatable assembler

(With structured assembler)

PG-1500

controller

IE controller

PD78P324GJ

PD78P324LP

PD78P324KD

PD78P324KC

PA-78P324GJ

PA-78P324LP

PA-78P324KC
PA-78P324KD

Programmer adapters

PROM-incorporated products

RS-232-C

IE-78327-R
in-circuit emulator

RS-232-C

PG-1500

PROM programmer

Emulation probes

Socket for connecting the emulation probe
and the target system

EP-78320GJ-R

EP-78320L-R

EV-9200G-74

Socket for plastic QFJ

Target system

Note

PD78P324, 78P324(A)

B.2

EVALUATION TOOLS

To evaluate the functions of the

PD78P324, the following tools are made available.

Part Number

EB-78320-98

EB-78320-PC

Function

By connecting to a host machine, it is possible
to evaluate the functions equipped by the

PD78P324 in a simple manner. The com-

mand system of this product basically
conforms to that of IE-78327-R and IE-78320-
R. Therefore, it is easy to move to the
development work of application systems by
IE-78327-R or IE-78320-R. In addition a turbo
access manager (

PD71P301)

Note

can be

mounted on the board.

Note

The turbo access manager (

PD71P301) is a maintenance product.

Cautions

1. This product is not a development tool of

PD78P324 application systems.

2. This product is not equipped with the emulation function for executing the PROM incorporated

in the

PD78P324.

B.3

EMBEDDED SOFTWARE

The following embedded software programs are available to perform program development and

maintenance more efficiently.

Eeal-time OS

Host Machine

PC-9800 series

IBM PC/AT or its compatible
machine

Real-time OS (RX78K/III)

The RX78K/III is designed to provide a multi-task environment in the field of control
application where real-time operation is required. By using this real-time OS, the
performance of the whole system can be improved by allocating CPU's idle time to
other processings.
The RX78K/III provides the system call based on the

ITRON specifications.

The RX78K/III package provides tools (configurators) for creating RX78K/III's nucleus
and multiple information table.

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13RX78320

S5A10RX78320

S7B13RX78320

S7B10RX78320

MS-DOS

PC DOS

Caution

To purchase the operating system above, you need to fill in a purchase application form beforehand

and sign a contract allowing you to use the software.

Remark

When using the real-time OS RX78K/III, you need the assembler package RA78K/III (optional) as well.

PD78P324, 78P324(A)

Fuzzy knowledge data creation
tools (FE9000, FE9200)

Translator (FT78K3)

Note

Fuzzy inference module
(FI78K/III)

Note

Fuzzy inference debugger
(FD78K/III)

This program supports inputting/editing/evaluating (through simulation) of the fuzzy
knowledge data (fuzzy rules and membership functions).

Fuzzy Inference Development Support System

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13FE9000

S5A10FE9000

S7B13FE9000

S7B10FE9000

MS-DOS

PC DOS Winsows

This program converts the fuzzy knowledge data obtained with fuzzy knowledge
data creation tools to an assembler source program for RA78K/III.

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13FT78K3

S5A10FT78K3

S7B13FT78K3

S7B10FT78K3

MS-DOS

PC DOS

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13FI78K3

S5A10FI78K3

S7B13FI78K3

S7B10FI78K3

MS-DOS

PC DOS

Supply medium

3.5-inch 2HD

5-inch 2HD

3.5-inch 2HC

5-inch 2HC

Part number

S5A13FD78K3

S5A10FD78K3

S7B13FD78K3

S7B10FD78K3

MS-DOS

PC DOS

Note

Under development

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

This program executes fuzzy inference. Fuzzy inference is executed by being linked
to the fuzzy knowledge data converted by the translator.

This is a support software program for evaluating and adjusting the fuzzy knowl-
edge data at a hardware level by using the in-circuit emulator.

Host machine

PC-9800 series

IBM PC/AT and its
compatible
machine

PD78P324, 78P324(A)

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be
taken to stop generation of static electricity as much as possible, and quickly
dissipate it once, when it has occurred. Environmental control must be
adequate. When it is dry, humidifier should be used. It is recommended to
avoid using insulators that easily build static electricity. Semiconductor
devices must be stored and transported in an anti-static container, static
shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded
using wrist strap. Semiconductor devices must not be touched with bare
hands. Similar precautions need to be taken for PW boards with semiconductor
devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input
level may be generated due to noise, etc., hence causing malfunction. CMOS
device behave differently than Bipolar or NMOS devices. Input levels of CMOS
devices must be fixed high or low by using a pull-up or pull-down circuitry. Each
unused pin should be connected to V

or GND with a resistor, if it is considered

to have a possibility of being an output pin. All handling related to the unused
pins must be judged device by device and related specifications governing the
devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset
function have not yet been initialized. Hence, power-on does not guarantee
out-pin levels, I/O settings or contents of registers. Device is not initialized
until the reset signal is received. Reset operation must be executed immedi-
ately after power-on for devices having reset function.

QTOP is a trademark of NEC Corporation.

MS-DOS and Windows are trademarks of Microsoft Corp.

PC/AT and PC DOS are trademarks of IBM Corp.

HP9000 series 300 and HP-UX are trademarks of Hewlett-Packard.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems Inc.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

License not needed:

PD78P324KC, 78P324KD

The customer must judge the need for license:

PD78P324GJ-5BJ/(A)/(A1)/(A2)/,

78P324LP/(A)/(A1)/(A2)

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact NEC Sales Representative in advance.
Anti-radioactive design is not implemented in this product.

M4 94.11

PD78P324, 78P324(A)

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD78P324LPA1

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD78P324LPA1