Document Outline

COVER
FEATURES
ORDERING INFORMATION
QUALITY GRADE
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
FUNCTIONS
1. DIFFERENCES BETWEEN uPD78P4038Y AND MASKED ROM PRODUCTS
2. PIN CONFIGURATION (TOP VIEW)
3. BLOCK DIAGRAM
4. LIST OF PIN FUNCTIONS
- 4.1 Pins for Normal Operating Mode
- 4.2 Pins for PROM Programming Mode (Vpp Greater or equal to +5V or +12.5V, RESET# = L)
  - 4.2.1 Pin functions
  - 4.2.2 Pin functions
- 4.3 I/O Circuits for Pins and Handling of Unused Pins
5. INTERNAL MEMORY SWITCHING (IMS) REGISTER
6. PROM PROGRAMMING
- 6.1 Operation Mode
- 6.2 PROM Write Sequence
- 6.3 PROM Read Sequence
7. ERASURE CHARACTERISTICS (uPD78P4038YKK-T ONLY)
8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (uPD78P4038YKK-T ONLY)
9. QUALITY
10. SCREENING ONE-TIME PROM PRODUCTS
11. ELECTRICAL CHARACTERISTICS
12. PACKAGE DRAWINGS
13. RECOMMENDED SOLDERING CONDITIONS
APPENDIX A DEVELOPMENT TOOLS
APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW)
APPENDIX C RELATED DOCUMENTS

DATA SHEET

MOS INTEGRATED CIRCUIT

PD78P4038Y

The

PD78P4038Y, 78K/IV Series' product, is a one-time PROM or EPROM version of the

PD784035Y,

PD784036Y,

PD784037Y, and

PD784038Y with internal masked ROM.

Since user programs can be written to PROM, this microcontroller is best suited for evaluation in system

development, manufacture of small quantities of multiple products, and fast start-up of applications.

For specific functions and other detailed information, consult the following user's manual.

This manual is required reading for design work.

PD784038, 784038Y Sub-Series User's Manual, Hardware : U11316E

78K/IV Series User's Manual, Instruction

: U10905E

FEATURES

Compatible with the

PD78P238,

PD78P4026, and

PD78P4038

Internal PROM: 128 Kbytes

PD78P4038YKK-T

: EPROM (best suited for system evaluation)

PD78P4038YGC-3B9 : PROM (best suited for manufacture of small quantities)

PD78P4038YGC-8BT : PROM (best suited for manufacture of small quantities)

PD78P4038YGK-BE9 : PROM (best suited for manufacture of small quantities)

Internal RAM:

4,352 bytes

Supply voltage: V

= 2.7 to 5.5 V

QTOP

microcomputer

Remark The QTOP microcomputer is a microcomputer with a built-in one-time PROM that is totally supported

by NEC. The support includes writing application programs, marking, screening, and verification.

ORDERING INFORMATION

Part number

Package

Internal ROM

PD78P4038YGC-3B9

80-pin plastic QFP (14

2.7 mm)

One-time PROM

PD78P4038YGC-8BT

80-pin plastic QFP (14

1.4 mm)

One-time PROM

PD78P4038YGC-

×××

-3B9

80-pin plastic QFP (14

14 mm)

One-time PROM (QTOP microcomputer)

PD78P4038YGK-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

One-time PROM

PD78P4038YGK-

×××

-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

One-time PROM (QTOP microcomputer)

PD78P4038YKK-T

80-pin ceramic WQFN (14

14 mm)

EPROM

In this reference, all ROM components that are common to one-time PROM and EPROM are referred to as

PROM.

The mark shows major revised points.

The information in this document is subject to change without notice.

16/8-BIT SINGLE-CHIP MICROCONTROLLER

Document No.

U10742EJ2V0DS00 (2nd edition)

Date Published July 1998 J CP(K)
Printed in Japan

1995

PD78P4038Y

QUALITY GRADE

Part number

Package

Quality grade

PD78P4038YGC-3B9

80-pin plastic QFP (14

2.7 mm)

Standard (for general electronic equipment)

PD78P4038YGC-8BT

80-pin plastic QFP (14

1.4 mm)

Standard (for general electronic equipment)

PD78P4038YGC-

×××

-3B9

80-pin plastic QFP (14

1.4 mm)

Standard (for general electronic equipment)

PD78P4038YGK-BE9

80-pin plastic TQFP (fine pitch) (12

12 mm)

Standard (for general electronic equipment)

PD78P4038YGK-

×××

-BE9 80-pin plastic TQFP (fine pitch) (12

12 mm)

Standard (for general electronic equipment)

PD78P4038YKK-T

80-pin ceramic WQFN (14

14 mm)

Not applied (for function evaluation)

Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation

to know the specification of quality grade on the devices and its recommended applications.

Caution The EPROM versions of the

PD78P4038Y are not intended for use in mass-produced products;

they do not have reliability high enough for such purposes. Their use should be restricted to

functional evaluation in experiment or trial manufacture.

Remark

×××

is ROM code suffix.

PD78P4038Y

78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM

: Product under mass production

: Product under preparation

Standard Products Development

ASSP Development

PD784026

A/D converters,
16-bit timers, and
power management
functions have been
enhanced.

Internal memory has been expanded.
Pin-compatible with the PD784026

PD784038Y

PD784038

Connectable to the I

C bus

100 pins
I/O has been enhanced.
Internal memory has been expanded.

PD784216Y

PD784216

Connectable to the multimaster I

C bus

PD784054

Built-in 10-bit A/D converter

PD784046

80 pins
ROM correction function has been added.

PD784225Y

PD784225

Connectable to the multimaster I

C bus

Internal memory has been expanded.
ROM correction function has been added.

PD784218Y

PD784218

Connectable to the multimaster I

C bus

µ
µ

PD784908

Built-in IEBus

controller

Functions of the PD784915 have been enhanced.

PD784928Y

PD784928

Connectable to the multimaster I

C bus

PD784955

DC inverter control

PD784915

Software servo control
Built-in analog circuit for VCR
Timers have been enhanced.

Functions of the PD784908 have been enhanced.
Internal memory has been expanded.
ROM correction function has been added.

PD784937

PD78P4038Y

FUNCTIONS

(1/2)

Note

Additional function pins are included in the I/O pins.

Item

Number of basic instructions

(mnemonics)

General-purpose register

Minimum instruction

execution time

Internal

memory

Memory space

I/O ports

Additional

function

pins

Note

Real-time output ports

Timer/counter

PWM outputs

Serial interface

A/D converter

D/A converter

Functions

113

8 bits

16 registers

8 banks, or 16 bits

8 registers

8 banks (memory mapping)

125 ns/250 ns/500 ns/1,000 ns (at 32 MHz)

128 Kbytes (Can be changed to 48 K, 64 K, or 96 Kbytes by software)

4,352 bytes (Can be changed to 2,048 or 3,584 bytes by software)

Program and data: 1 Mbyte

4 bits

2, or 8 bits

Timer/counter 0: Timer register

Pulse output capability

Capture register

Toggle output

Compare register

PWM/PPG output

One-shot pulse output

Timer/counter 1: Timer register

Pulse output capability

Capture register

Real-time output (4 bits

Capture/compare register

Compare register

Timer/counter 2: Timer register

Pulse output capability

Capture register

Toggle output

Capture/compare register

PWM/PPG output

Compare register

Timer 3

: Timer register

Compare register

12-bit resolution

2 channels

UART/IOE (3-wire serial I/O): 2 channels (incorporating baud rate generator)

CSI (3-wire serial I/O, 2-wire serial I/O, I

C bus): 1 channel

8-bit resolution

8 channels

8-bit resolution

2 channels

PROM

RAM

Total

Input

Input/output

Pins with pull-

up resistor

LED direct

drive outputs

Transistor

direct drive

PD78P4038Y

Item

Clock output

Watchdog timer

Standby

Interrupt

Supply voltage

Package

(2/2)

Functions

Selected from f

CLK

, f

CLK

/2, f

CLK

/4, f

CLK

/8, or f

CLK

/16 (can be used as a 1-bit output port)

1 channel

HALT/STOP/IDLE mode

24 (17 internal, 7 external (sampling clock variable input: 1))

BRK instruction, BRKCS instruction, operand error

1 internal, 1 external

16 internal, 6 external

4-level programmable priority

3 operation statuses: vectored interrupt, macro service, context switching

= 2.7 to 5.5 V

80-pin plastic QFP (14

2.7 mm)

80-pin plastic QFP (14

1.4 mm)

80-pin plastic TQFP (fine pitch) (12

12 mm)

80-pin ceramic WQFN (14

14 mm)

Hardware source

Software source

Nonmaskable

Maskable

PD78P4038Y

CONTENTS

DIFFERENCES BETWEEN

PD78P4038Y AND MASKED ROM PRODUCTS ....................

PIN CONFIGURATION (TOP VIEW) .........................................................................................

BLOCK DIAGRAM .....................................................................................................................

LIST OF PIN FUNCTIONS .........................................................................................................

4.1

Pins for Normal Operating Mode .................................................................................................

4.2

Pins for PROM Programming Mode (V

+5 V or +12.5 V, RESET = L) ..............................

4.2.1

Pin functions ..................................................................................................................

4.2.2

Pin functions ..................................................................................................................

4.3

I/O Circuits for Pins and Handling of Unused Pins ..................................................................

INTERNAL MEMORY SWITCHING (IMS) REGISTER ............................................................

PROM PROGRAMMING ............................................................................................................

6.1

Operation Mode ..............................................................................................................................

6.2

PROM Write Sequence ..................................................................................................................

6.3

PROM Read Sequence ..................................................................................................................

ERASURE CHARACTERISTICS (

PD78P4038YKK-T ONLY) ...............................................

PROTECTIVE FILM COVERING THE ERASURE WINDOW (

PD78P4038YKK-T ONLY) ..

QUALITY .....................................................................................................................................

10. SCREENING ONE-TIME PROM PRODUCTS ..........................................................................

11. ELECTRICAL CHARACTERISTICS .........................................................................................

12. PACKAGE DRAWINGS .............................................................................................................

13. RECOMMENDED SOLDERING CONDITIONS ........................................................................

APPENDIX A DEVELOPMENT TOOLS ..........................................................................................

APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER

(TGK-080SDW)..........................................................................................................

APPENDIX C RELATED DOCUMENTS ..........................................................................................

PD78P4038Y

1. DIFFERENCES BETWEEN

PD78P4038Y AND MASKED ROM PRODUCTS

The

PD78P4038Y is produced by replacing the masked ROM in the

PD784035Y,

PD784036Y,

PD784037Y,

PD784038Y with PROM to which data can be written. The functions of the

PD78P4038Y are the same as those

of the

PD784035Y,

PD784036Y,

PD784037Y, or

PD784038Y except for the PROM specification such as writing

and verification, except that the PROM size can be changed to 48 K, 64 K, or 96 Kbytes, and except that the internal

RAM size can be changed to 2,048 or 3,584 bytes.

Table 1-1 shows the differences between these products.

Table 1-1. Differences between the

PD78P4038Y and Masked ROM Products

Product Name

Item

Internal program

memory

Internal RAM

Package

PD78P4038Y

128-Kbyte

PROM

Can be changed

to 48 K, 64 K, or

96 Kbytes by

IMS

4,352-byte

internal RAM

Can be changed

to 2,048 or 3,584

bytes by IMS

PD784038Y

128-Kbyte

masked ROM

4,352-byte

internal RAM

PD784037Y

96-Kbyte

masked ROM

3,584-byte

internal RAM

PD784036Y

64-Kbyte

masked ROM

PD784035Y

48-Kbyte

masked ROM

2,048-byte internal RAM

80-pin plastic QFP (14

2.7 mm)

80-pin plastic QFP (14

1.4 mm)

80-pin plastic TQFP (fine pitch) (12

12 mm)

80-pin ceramic

WQFN

(14

14 mm)

PD78P4038Y

2. PIN CONFIGURATION (TOP VIEW)

(1) Normal operating mode

· 80-pin plastic QFP (14

2.7 mm)

PD78P4038YGC-3B9,

PD78P4038YGC-

×××

-3B9

· 80-pin plastic QFP (14

1.4 mm)

PD78P4038YGC-8BT

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD78P4038YGK-BE9,

PD78P4038YGK-

×××

-BE9

· 80-pin ceramic WQFN (14

14 mm)

PD78P4038YKK-T

Note

Connect the TEST pin to V

SS0

directly.

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

DD0

P17

P16

P15

P14/T

D2/SO2

P13/R

D2/SI2

P12/ASCK2/SCK2

P11/PWM1

P10/PWM0

TEST

Note

SS0

ASTB/CLKOUT

P40/AD0

P41/AD1

P42/AD2

P32/SCK0/SCL

P33/SO0/SDA

P34/ TO0

P35/ TO1

P36/ TO2

P37/ TO3

RESET

DD1

SS1

P00

P01

P02

P03

P04

P05

P06

P07

P67/REFRQ/HLDAK

P66/

WAIT/HLDRQ

P65/

P64

/RD

P63/A19

P62

/A18

P61/A17

P60/A16

P57/A15

P56/A14

P55/A13

P54

/A12

P53/A11

P52

/A10

P51/A9

P50/A8

P47/AD7

P46/AD6

P45/AD5

P44

/AD4

P43/AD3

P31/

TxD/SO1

P30/RxD/SI1

P27/SI0

P26/INTP5

P25/INTP4

/ASCK/SCK1

P24

/INTP3

P23/INTP2

/CI

P22

/INTP1

P21/INTP0

P20/NMI

REF3

REF2

ANO1

ANO0

REF1

P77/ANI7

P76/ANI6

P75/ANI5

PD78P4038Y

P60-P67

: Port 6

P70-P77

: Port 7

PWM0, PWM1 : Pulse width modulation output

: Read strobe

REFRQ

: Refresh request

RESET

: Reset

RxD, RxD2

: Receive data

SCK0-SCK2

: Serial clock

SCL

: Serial clock

SDA

: Serial data

SI0-SI2

: Serial input

SO0-SO2

: Serial output

TEST

: Test

TO0-TO3

: Timer output

TxD, TxD2

: Transmit data

DD0

, V

DD1

: Power supply

SS0

, V

SS1

: Ground

WAIT

: Wait

: Write strobe

X1, X2

: Crystal

A8-A19

: Address bus

AD0-AD7

: Address/data bus

ANI0-ANI7

: Analog input

ANO0, ANO1

: Analog output

ASCK, ASCK2 : Asynchronous serial clock

ASTB

: Address strobe

: Analog power supply

REF1

-AV

REF3

: Reference voltage

: Analog ground

: Clock input

CLKOUT

: Clock output

HLDAK

: Hold acknowledge

HLDRQ

: Hold request

INTP0-INTP5

: Interrupt from peripherals

NMI

: Non-maskable interrupt

P00-P07

: Port 0

P10-P17

: Port 1

P20-P27

: Port 2

P30-P37

: Port 3

P40-P47

: Port 4

P50-P57

: Port 5

PD78P4038Y

(2) PROM programming mode

· 80-pin plastic QFP (14

2.7 mm)

PD78P4038YGC-3B9,

PD78P4038YGC-

×××

-3B9

· 80-pin plastic QFP (14

1.4 mm)

PD78P4038YGC-8BT

· 80-pin plastic TQFP (fine pitch) (12

12 mm)

PD78P4038YGK-BE9,

PD78P4038YGK-

×××

-BE9

· 80-pin ceramic WQFN (14

14 mm)

PD78P4038YKK-T

Caution L

: Connect these pins separately to the V

pins through 10-k

pull-down resistors.

: To be connected to the ground.

Open : Nothing should be connected on these pins.

RESET: Set a low-level input.

A0-A16

: Address bus

RESET

: Reset

: Chip enable

: Power supply

D0-D7

: Data bus

: Programming power supply

: Output enable

: Ground

PGM

: Program

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

Open

RESET

Open

(L)

PGM

A15

A14

A13

A12

A11

A10

A16

(L)

Open

(L)

Open

PD78P4038Y

3. BLOCK DIAGRAM

Note

In the PROM programming mode.

NMI

INTP0-INTP5

INTP3

TO0
TO1

INTP0

INTP1

INTP2/CI

TO2
TO3

P00-P03

P04-P07

PWM0

PWM1

ANO0

ANO1

REF2

REF3

ANI0-ANI7

REF1

INTP5

A/D
converter

D/A
converter

Real-time
output port

PWM

UART/IOE2

D/SI1

D/SO1

ASCK/SCK1

D2/SI2

D2/SO2

ASCK2/SCK2

SCK0/SCL
SO0/SDA
SI0

ASTB/CLKOUT

AD0-AD7

A8-A15

A16-A19

P20-P27

P30-P37

P40-P47

P50-P57

P60-P67

P70-P77

RESET

TEST

X1
X2

Note

DD0

, V

DD1

SS0

, V

SS1

RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
D0-D7

Note

A0-A16

Note

PGM

Note

P00-P07

P10-P17

Baud-rate
generator

Clock output

UART/IOE1

Bus
interface

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 7

System
control

Watchdog
timer

Baud-rate
generator

Clocked
serial
interface

Timer 3

(16 bits)

PROM

(128 Kbytes)

RAM

(3,840 bytes)

78 K/IV

CPU core

(RAM 512 bytes)

Timer/counter 2

(16 bits)

Timer/counter 1

(16 bits)

Timer/counter 0

(16 bits)

Programmable
interrupt
controller

PD78P4038Y

P00-P07

P10

P11

P12

P13

P14

P15-P17

P20

P21

P22

P23

P24

P25

P26

P27

P30

P31

P32

P33

P34-P37

P40-P47

I/O

Input

I/O

Alternate-Function

PWM0

PWM1

ASCK2/SCK2

D2/SI2

D2/SO2

NMI

INTP0

INTP1

INTP2/CI

INTP3

INTP4/ASCK/SCK1

INTP5

SI0

D/SI1

D/SO1

SCK0/SCL

SO0/SDA

TO0-TO3

AD0-AD7

Function

Port 0 (P0):

8-bit I/O port.

Functions as a real-time output port (4 bits

2).

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive a transistor.

Port 1 (P1):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

Port 2 (P2):

8-bit input-only port.

P20 does not function as a general-purpose port (nonmaskable

interrupt). However, the input level can be checked by an interrupt

service routine.

The use of the pull-up resistors can be specified by software for pins

P22 to P27 (in units of 6 bits).

The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by

CSIM1.

Port 3 (P3):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 4 (P4):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

4. LIST OF PIN FUNCTIONS

4.1 Pins for Normal Operating Mode

(1) Port pins (1/2)

PD78P4038Y

(1) Port pins (2/2)

P50-P57

P60-P63

P64

P65

P66

P67

P70-P77

I/O

Function

Port 5 (P5):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Can drive LED.

Port 6 (P6):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

The use of the pull-up resistors can be specified by software for the pins

in the input mode together.

Port 7 (P7):

8-bit I/O port.

Inputs and outputs can be specified bit by bit.

Alternate-Function

A8-A15

A16-A19

WAIT/HLDRQ

REFRQ/HLDAK

ANI0-ANI7

PD78P4038Y

(2) Non-port pins (1/2)

TO0-TO3

ASCK

ASCK2

SDA

SI0

SI1

SI2

SO0

SO1

SO2

SCK0

SCK1

SCK2

SCL

NMI

INTP0

INTP1

INTP2

INTP3

INTP4

INTP5

AD0-AD7

A8-A15

A16-A19

WAIT

REFRQ

HLDRQ

HLDAK

ASTB

CLKOUT

I/O

Output

Input

Output

Input

I/O

Input

Output

I/O

Input

I/O

Output

Input

Output

Input

Output

Function

Timer output

Input of a count clock for timer/counter 2

Serial data input (UART0)

Serial data input (UART2)

Serial data output (UART0)

Serial data output (UART2)

Baud rate clock input (UART0)

Baud rate clock input (UART2)

Serial data I/O (2-wire serial I/O, I

C bus)

Serial data input (3-wire serial I/O0)

Serial data input (3-wire serial I/O1)

Serial data input (3-wire serial I/O2)

Serial data output (3-wire serial I/O0)

Serial data output (3-wire serial I/O1)

Serial data output (3-wire serial I/O2)

Serial clock I/O (3-wire serial I/O0)

Serial clock I/O (3-wire serial I/O1)

Serial clock I/O (3-wire serial I/O2)

Serial clock I/O (2-wire serial I/O, I

C bus)

External interrupt request

Input of a count clock for timer/counter 1

Capture/trigger signal for CR11 or CR12

Input of a count clock for timer/counter 2

Capture/trigger signal for CR22

Input of a count clock for timer/counter 2

Capture/trigger signal for CR21

Input of a count clock for timer/counter 0

Capture/trigger signal for CR02

Input of a conversion start trigger for A/D converter

Time multiplexing address/data bus (for connecting external memory)

High-order address bus (for connecting external memory)

High-order address bus during address expansion (for connecting external memory)

Strobe signal output for reading the contents of external memory

Strobe signal output for writing on external memory

Wait signal insertion

Refresh pulse output to external pseudo static memory

Input of bus hold request

Output of bus hold response

Latch timing output of time multiplexing address (A0-A7) (for connecting

external memory)

Clock output

Alternate-Function

P34-P37

P23/INTP2

P30/SI1

P13/SI2

P31/SO1

P14/SO2

P25/INTP4/SCK1

P12/SCK2

P33/SO0

P27

P30/R

P13/R

P33/SDA

P31/T

P14/T

P32/SCL

P25/INTP4/ASCK

P12/ASCK2

P32/SCK0

P20

P21

P22

P23/CI

P24

P25/ASCK/SCK1

P26

P40-P47

P50-P57

P60-P63

P64

P65

P66/HLDRQ

P67/HLDAK

P66/WAIT

P67/REFRQ

CLKOUT

ASTB

PD78P4038Y

(2) Non-port pins (2/2)

RESET

ANI0-ANI7

ANO0, ANO1

REF1

REF2

, AV

REF3

DD0

Note 1

DD1

Note 1

SS0

Note 2

SS1

Note 2

TEST

I/O

Input

Output

Function

Chip reset

Crystal input for system clock oscillation (A clock pulse can also be input

to the X1 pin.)

Analog voltage inputs for the A/D converter

Analog voltage inputs for the D/A converter

Application of A/D converter reference voltage

Application of D/A converter reference voltage

Positive power supply for the A/D converter

Ground for the A/D converter

Positive power supply of the port part

Positive power supply except for the port part

Ground of the port part

Ground except for the port part

Directly connect to V

SS0

. (The TEST pin is for the IC test.)

Alternate-Function

P70-P77

Pin Name

RESET

A0-A16

D0-D7

PGM

I/O

Input

I/O

Input

Function

PROM programming mode selection

High voltage input during program write or verification

PROM programming mode selection

Address bus

Data bus

PROM enable input/program pulse input

Read strobe input to PROM

Program/program inhibit input during PROM programming mode

Positive power supply

GND

Notes 1. The potential of the V

DD0

pin must be equal to that of the V

DD1

pin.

2. The potential of the V

SS0

pin must be equal to that of the V

SS1

pin.

4.2 Pins for PROM Programming Mode (V

+5 V or +12.5 V, RESET = L)

4.2.1 Pin functions

PD78P4038Y

4.2.2 Pin functions

(1) V

(Programming power supply): Input

Input pin for setting the

PD78P4038Y to the PROM programming mode. When the input voltage on this pin

is +5 V or more and when RESET input goes low, the

PD78P4038Y enters the PROM programming mode.

When CE is made low for V

= +12.5 V and OE = high, program data on D0 to D7 can be written into the internal

PROM cell selected by A0 to A16.

(2) RESET (Reset): Input

Input pin for setting the

PD78P4038Y to the PROM programming mode. When input on this pin is low, and

when the input voltage on the V

pin goes +5 V or more, the

PD78P4038Y enters the PROM programming

mode.

(3) A0 to A16 (Address bus): Input

Address bus that selects an internal PROM address (0000H to 1FFFFH)

(4) D0 to D7 (Data bus): I/O

Data bus through which a program is written on or read from internal PROM

(5) CE (Chip enable): Input

This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or

read.

(6) OE (Output enable): Input

This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a one-

byte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.

(7) PGM (Program): Input

The input pin for the operation mode control signal of the internal PROM.

Upon activation, writing to the internal PROM is enabled.

Upon inactivation, reading from the internal PROM is enabled.

(8) V

Positive power supply pin

(9) V

Ground potential pin

PD78P4038Y

4.3 I/O Circuits for Pins and Handling of Unused Pins

Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.

Figure 4-1 shows the configuration of these various types of I/O circuits.

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)

P00-P07

P10/PWM0

P11/PWM1

P12/ASCK2/SCK2

P13/R

D2/SI2

P14/T

D2/SO2

P15-P17

P20/NMI

P21/INTP0

P22/INTP1

P23/INTP2/CI

P24/INTP3

P25/INTP4/ASCK/SCK1

P26/INTP5

P27/SI0

P30/R

D/SI1

P31/T

D/SO1

P32/SCK0/SCL

P33/SO0/SDA

P34/TO0-P37/TO3

P40/AD0-P47/AD7

P50/A8-P57/A15

P60/A16-P63/A19

P64/RD

P65/WR

P66/WAIT/HLDRQ

P67/REFRQ/HLDAK

P70/ANI0-P77/ANI7

ANO0, ANO1

ASTB/CLKOUT

Recommended Connection Method for Unused Pins

Input state:

To be connected to V

DD0

Output state: To be left open

To be connected to V

DD0

or V

SS0

To be connected to V

DD0

Input state:

To be connected to V

DD0

Output state: To be left open

To be connected to V

DD0

Input state:

To be connected to V

DD0

Output state: To be left open

Input state:

To be connected to V

DD0

or V

SS0

Output state: To be left open

To be left open

I/O Circuit Type

5-H

8-C

5-H

2-C

8-C

2-C

5-H

10-B

5-H

20-A

4-B

I/O

Input

I/O

Input

I/O

Output

PD78P4038Y

Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)

Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to V

DD0

through a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin

becomes higher than that of the low level input at power-on or when I/O is switched by software).

Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each

product. (Some circuits are not included.)

Recommended Connection Method for Unused Pins

To be connected to V

SS0

directly

To be connected to V

SS0

To be connected to V

DD0

I/O

Input

RESET

TEST

REF1

-AV

REF3

I/O Circuit Type

1-A

PD78P4038Y

Figure 4-1. I/O Circuits for Pins

Type 1-A

Type 2-C

Type 2

Type 4-B

Type 8-C

Type 10-B

Type 5-H

Type 12

Type 20-A

DD0

SS0

Schmitt trigger input with hysteresis characteristics

DD0

Pull-up
enable

Data

DD0

SS0

OUT

Output
disable

Push-pull output which can output high impedance
(both the positive and negative channels are off.)

Data

DD0

SS0

IN/OUT

Output
disable

DD0

Pull-up
enable

Input
enable

Data

DD0

SS0

IN/OUT

Output
disable

DD0

Pull-up
enable

Analog output
voltage

OUT

Data

DD0

SS0

IN/OUT

Output
disable

DD0

Pull-up
enable

Open
drain

Data

Comparator

DD0

SS0

REF

(Threshold voltage)

IN/OUT

Output
disable

Input
enable

PD78P4038Y

5. INTERNAL MEMORY SWITCHING (IMS) REGISTER

This register enables the software to avoid using part of the internal memory. The IMS register can be set to

establish the same memory mapping as used in ROM products that have different internal memory (ROM and RAM)

configurations.

The IMS register is set using 8-bit memory operation instructions.

A RESET input sets the IMS register to FFH.

Figure 5-1. Internal Memory Switching (IMS) Register

The IMS is not contained in a mask ROM product (

PD784035Y,

PD784036Y,

PD784037Y, or

PD784038Y).

But the action is not affected if the write command to the IMS is executed to the mask ROM product.

IMS

IMS7

IMS6

IMS5

IMS4

IMS3

IMS2

IMS1

IMS0

0FFFCH

Address

FFH

After Reset

R/W

IMS0-7

FFH

EEH

DCH

Same as the PD784038Y

Memory Size

CCH

Same as the PD784037Y

Same as the PD784036Y

Same as the PD784035Y

PD78P4038Y

6. PROM PROGRAMMING

The

PD78P4038Y has an on-chip 128-KB PROM device for use as program memory. When programming, set

the V

and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused

pins.

6.1 Operation Mode

PROM programming mode is selected when +5 V or +12.5 V is added to the V

pin or low-level input is added

to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin, and PGM pin as shown

in Table 6-1 below.

In addition, the PROM contents can be read by setting read mode.

Table 6-1. PROM Programming Operation Mode

RESET

PGM

D0-D7

Operation Mode

Page data latch

+12.5 V

+6.5 V

Data input

Page write

High impedance

Byte write

Data input

Program verify

Data output

Program inhibit

High impedance

Read

+5 V

Data output

Output disable

High impedance

Standby

High impedance

Remark

= L or H

PD78P4038Y

(1) Read mode

Set CE to L and OE to L to set read mode.

(2) Output disable mode

Set OE to H to set high impedance for data output and output disable mode.

Consequently, if several

PD78P4038Y devices are connected to a data bus, the OE pins can be controlled to

select data output from any of the devices.

(3) Standby mode

Set CE to H to set standby mode.

In this mode, data output is set to high impedance regardless of the OE setting.

(4) Page data latch mode

At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.

In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.

(5) Page write mode

After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program

pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting

both CE and OE to L causes program verification to be executed.

If programming is not completed after one program pulse, the write and verify operations may be repeated X times

(where X

10).

(6) Byte write mode

Adding a 0.1 ms program pulse (active, low) to the PGM pin with both CE and OE set to H causes byte write

to be executed. Later, setting OE to L causes program verification to be executed.

If programming is not completed after one program pulse, the write and verify operations may be repeated X times

(where X

10).

(7) Program verify mode

Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each

write operation.

(8) Program inhibit mode

Program inhibit mode is used to write to a single device when several

PD78P4038Y devices are connected in

parallel to OE , V

, and D0 to D7 pins.

Use the page write mode or byte write mode described above for each write operation. Write operations cannot

be done for devices in which the PGM pin has been set to H.

PD78P4038Y

7. ERASURE CHARACTERISTICS (

PD78P4038YKK-T ONLY)

Data written in the

PD78P4038YKK-T program memory can be erased (FFH); therefore users can write other

data in the memory.

To erase the written data, expose the erasure window to light with a wavelength shorter than approx. 400 nm. Normally,

ultraviolet light with a wavelength of 254 nm is employed. The amount of light required to completely erase the data

is as follows:

· Intensity of ultraviolet light

erasing time: 57.6 W·s/cm

min.

· Erasing time: About 80 minutes (When using a 12,000

W/cm

ultraviolet lamp. It may, however, take more time

due to lamp deterioration, dirt on the erasure window, or the like.)

The ultraviolet lamp should be placed within 2.5 cm from the erasure window during erasure. In addition, if a filter

is attached to the ultraviolet lamp, remove the filter before erasure.

8. PROTECTIVE FILM COVERING THE ERASURE WINDOW (

PD78P4038YKK-T ONLY)

To prevent EPROM from being erased inadvertently by light other than that from the lamp used for erasing EPROM,

or to prevent the internal circuits other than EPROM from malfunctioning by light, stick a protective film on the erasure

window except when EPROM is to be erased.

9. QUALITY

The

PD78P4038YKK-T is not intended for use in mass-produced products; they do not have reliability high enough

for such purposes. Their use should be restricted to functional evaluation in experiment or trial manufacture.

10. SCREENING ONE-TIME PROM PRODUCTS

NEC cannot execute a complete test of one-time PROM products (

PD78P4038YGC-3B9,

PD78P4038YGC-

8BT, and

PD78P4038YGK-BE9) due to their structure before shipment. It is recommended that you screen (verify)

PROM products after writing necessary data into them and storing them at 125

C for 24 hours.

PD78P4038Y

11. ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS (T

= 25

Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the

product; if the rated value of any of the parameters in the above table is exceeded, even

momentarily, the quality of the product may deteriorate. Always use the product within its rated

values.

D/A converter reference input

voltage

Parameter

Symbol

Conditions

Rating

Unit

Supply voltage

0.5 to +7.0

to V

+ 0.5

0.5 to +0.5

Input voltage

0.5 to V

+ 0.5

TEST/V

pin and

0.5 to +13.5

P21/INTP0/A9 pin in PROM

programming mode

Output voltage

0.5 to V

+ 0.5

Output low current

At one pin

Total of all output pins

100

Output high current

At one pin

Total of all output pins

100

A/D converter reference input

REF1

0.5 to V

+ 0.3

voltage

REF2

0.5 to V

+ 0.3

REF3

0.5 to V

+ 0.3

Operating ambient temperature

40 to +85

Storage temperature

stg

65 to +150

PD78P4038Y

OPERATING CONDITIONS

· Operating ambient temperature (T

)

: 40 to +85

· Rise time and fall time (t

, t

) (at pins which are not specified) : 0 to 200

· Power supply voltage and clock cycle time

: See Figure 11-1.

Figure 11-1. Power Supply Voltage and Clock Cycle Time

CAPACITANCE (T

= 25

C, V

= V

= 0 V)

Parameter

Input capacitance

Output capacitance

I/O capacitance

Symbol

Conditions

f = 1 MHz

0 V on pins other than measured pins

MIN.

TYP.

MAX.

Unit

10,000

4,000

1,000

125

100

62.5

Guaranteed
operating
range

Power supply voltage [V]

Clock cycle time t

CYK

[ns]

PD78P4038Y

OSCILLATOR CHARACTERISTICS (T

= 40 to +85

C, V

= +4.5 to 5.5 V, V

= 0 V)

Caution When using the system clock generator, run wires in the portion surrounded by broken lines

according to the following rules to avoid effects such as stray capacitance:

· Minimize the wiring.

· Never cause the wires to cross other signal lines.

· Never cause the wires to run near a line carrying a large varying current.

· Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

as V

SS1

. Never connect the capacitor to a ground pattern carrying a large current.

· Never extract a signal from the oscillator.

Resonator

Ceramic resonator

or crystal

External clock

Recommended Circuit

Parameter

Oscillator frequency (f

)

X1 input frequency (f

)

X1 input rise and fall times

, t

)

X1 input high-level and low-

level widths (t

WXH

, t

WXL

)

MIN.

MAX.

125

Unit

MHz

SS1

HCMOS
inverter

PD78P4038Y

OSCILLATOR CHARACTERISTICS (T

= 40 to +85

C, V

= +2.7 to 5.5 V, V

= 0 V)

Caution When using the system clock generator, run wires in the portion surrounded by broken lines

according to the following rules to avoid effects such as stray capacitance:

Minimize the wiring.

Never cause the wires to cross other signal lines.

Never cause the wires to run near a line carrying a large varying current.

Cause the grounding point of the capacitor of the oscillator circuit to have the same potential

as V

SS1

. Never connect the capacitor to a ground pattern carrying a large current.

Never extract a signal from the oscillator.

Resonator

Ceramic resonator

or crystal

External clock

Recommended Circuit

Parameter

Oscillator frequency (f

)

X1 input frequency (f

)

X1 input rise and fall times

, t

)

X1 input high-level and low-

level widths (t

WXH

, t

WXL

)

MIN.

MAX.

125

Unit

MHz

SS1

HCMOS
inverter

PD78P4038Y

DC CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V) (1/2)

Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,

P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, TEST

2. P40/AD0 to P47/AD7, P50/A8 to P57/A15

3. P60/A16 to P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK

4. P00 to P07

5. P10 to P17

6. P32/SCK0/SCL, P33/SO0/SDA

Parameter

Input low voltage

Input high voltage

Output low voltage

Output high voltage

X1 input low current

X1 input high current

Symbol

IL1

IL2

IL3

IH1

IH2

IH3

OL1

OL2

OL3

OH1

OH2

Conditions

For pins other than those described in

Notes 1, 2, 3, 4, and 6

For pins described in Notes 1, 2, 3, 4,

and 6

= +5.0 V

10%

For pins described in Notes 2, 3, and 4

For pins other than those described in

Notes 1 and 6

For pins described in Notes 1 and 6

= +5.0 V

10%

For pins described in Notes 2, 3, and 4

= 2 mA

For pins other than those described in

Note 6

= 3 mA

For pins described in Note 6

= 6 mA

For pins described in Note 6

= +5.0 V

10%

= 8 mA

For pins described in Notes 2 and 5

= 2 mA

= +5.0 V

10%

= 5 mA

For pins described in Note 4

EXTC = 0

0 V

IL2

EXTC = 0

IH2

MIN.

0.3

0.7V

0.8V

2.2

1.0

1.4

TYP.

MAX.

0.3V

0.2V

+0.8

+ 0.3

0.4

0.6

1.0

+30

Unit

PD78P4038Y

DC CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V) (2/2)

Parameter

Input leakage current

Output leakage current

supply current

Pull-up resistor

Symbol

DD1

DD2

DD3

Conditions

0 V

For pins other than X1 when EXTC = 0

0 V

Operation mode

= 32 MHz

= +5.0 V

10%

= 16 MHz

= +2.7 to 3.3 V

HALT mode

= 32 MHz

= +5.0 V

10%

= 16 MHz

= +2.7 to 3.3 V

IDLE mode

= 32 MHz

(EXTC = 0)

= +5.0 V

10%

= 16 MHz

= +2.7 to 3.3 V

= 0 V

MIN.

TYP.

MAX.

Unit

PD78P4038Y

AC CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V)

(1) Read/write operation (1/2)

Remarks T:

CYK

(system clock cycle time)

1 (during address wait), otherwise, 0

Number of wait states (n

Unit

Parameter

Address setup time

ASTB high-level width

Address hold time (to ASTB

)

Address hold time (to RD

)

Delay from address to RD

Address float time (to RD

)

Delay from address to data input

Delay from ASTB

to data input

Delay from RD

to data input

Delay from ASTB

to RD

Data hold time (to RD

)

Delay from RD

to address active

Delay from RD

to ASTB

RD low-level width

Address hold time (to WR

)

Delay from address to WR

Delay from ASTB

to data output

Delay from WR

to data output

Delay from ASTB

to WR

Symbol

SAST

WSTH

HSTLA

HRA

DAR

FRA

DAID

DSTID

DRID

DSTR

HRID

DRA

DRST

WRL

HWA

DAW

DSTOD

DWOD

DSTW

MIN.

(0.5 + a) T 15

(0.5 + a) T 31

(0.5 + a) T 17

(0.5 + a) T 40

0.5T 24

0.5T 34

0.5T 14

(1 + a) T 9

(1 + a) T 15

0.5T 9

0.5T 8

0.5T 12

1.5T 8

1.5T 12

0.5T 17

(1.5 + n) T 30

(1.5 + n) T 40

0.5T 14

(1 + a) T 5

(1 + a) T 15

0.5T 9

MAX.

(2.5 + a + n) T 37

(2.5 + a + n) T 52

(2 + n) T 40

(2 + n) T 60

(1.5 + n) T 50

(1.5 + n) T 70

0.5T + 19

0.5T + 35

0.5T 11

After program

is read

After data is

read

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

PD78P4038Y

(1) Read/write operation (2/2)

Note

The hold time includes the time during which V

OH1

and V

OL1

are held under the load conditions of

= 50 pF and R

= 4.7 k

Remarks T:

CYK

(system clock cycle time)

Number of wait states (n

(2) Bus hold timing

Remarks T:

CYK

(system clock cycle time)

1 (during address wait), otherwise, 0

Number of wait states (n

Unit

Parameter

Data setup time (to WR

)

Data hold time (to WR

)

Note

Delay from WR

to ASTB

WR low-level width

Symbol

SODW

HWOD

DWST

WWL

MIN.

(1.5 + n) T 30

(1.5 + n) T 40

0.5T 5

0.5T 25

0.5T 12

(1.5 + n) T 30

(1.5 + n) T 40

MAX.

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

Unit

Parameter

Delay from HLDRQ

to float

Delay from HLDRQ

to HLDAK

Delay from float to HLDAK

Delay from HLDRQ

to HLDAK

Delay from HLDAK

to active

MIN.

1T 20

1T 30

MAX.

(6 + a + n) T + 50

(7 + a + n) T + 30

(7 + a + n) T + 40

1T + 30

2T + 40

2T + 60

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

Symbol

FHQC

DHQHHAH

DCFHA

DHQLHAL

DHAC

PD78P4038Y

(3) External wait timing

Remarks T:

CYK

(system clock cycle time)

1 (during address wait), otherwise, 0

Number of wait states (n

(4) Refresh timing

Remark T: t

CYK

(system clock cycle time)

Parameter

Delay from address to WAIT

input

Delay from ASTB

to WAIT

input

Hold time from ASTB

to WAIT

Delay from ASTB

to WAIT

Delay from RD

to WAIT

input

Hold time from RD

to WAIT

Delay from RD

to WAIT

Delay from WAIT

to data input

Delay from WAIT

to WR

Delay from WAIT

to RD

Delay from WR

to WAIT

input

Hold time from WR

to WAIT

Delay from WR

to WAIT

Unit

MIN.

(0.5 + n) T + 5

(0.5 + n) T +10

nT + 5

nT + 10

0.5T

nT + 5

nT + 10

MAX.

(2 + a) T 40

(2 + a) T 60

1.5T 40

1.5T 60

(1.5 + n) T 40

(1.5 + n) T 60

T 50

T 70

(1 + n) T 40

(1 + n) T 60

0.5T 5

0.5T 10

T 50

T 75

(1 + n) T 40

(1 + n) T 70

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

Symbol

DAWT

DSTWT

HSTWTH

DSTWTH

DRWTL

HRWT

DRWTH

DWTID

DWTW

DWTR

DWWTL

HWWT

DWWTH

Unit

Parameter

Random read/write cycle time

REFRQ low-level pulse width

Delay from ASTB

to REFRQ

Delay from RD

to REFRQ

Delay from WR

to REFRQ

Delay from REFRQ

to ASTB

REFRQ high-level pulse width

MAX.

MIN.

1.5T 25

1.5T 30

0.5T 9

1.5T 9

0.5T 15

1.5T 25

1.5T 30

Symbol

WRFQL

DSTRFQ

DRRFQ

DWRFQ

DRFQST

WRFQH

Conditions

= +5.0 V

10%

= +5.0 V

10%

PD78P4038Y

SERIAL OPERATION (T

= 40 to +85

C, V

= +2.7 to 5.5 V, AV

= V

= 0 V)

(1) CSI

Remarks 1. The values in this table are those when C

is 100 pF.

2. T

Serial clock cycle set by software. The minimum value is 16/f

3. f

Oscillator frequency

(2) I

Unit

Parameter

Serial clock cycle time (SCK0)

Serial clock low-level width

(SCK0)

Serial clock high-level width

(SCK0)

SI0 setup time (to SCK0

)

SI0 hold time (to SCK0

)

SO0 output delay time

(to SCK0

)

MIN.

10/f

+ 380

5/f

+ 150

0.5T 40

5/f

+ 150

0.5T 40

5/f

+ 40

MAX.

5/f

+ 150

5/f

+ 400

Conditions

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

Input

External clock

When SCK0 and SO0 are CMOS I/O

Output

CMOS push-pull output

(3-wire serial I/O mode)

Open-drain output

(2-wire serial I/O mode), R

= 1 k

Symbol

CYSK0

WSKL0

WSKH0

SSSK0

HSSK0

DSBSK1

DSBSK2

Parameter

SCL clock frequency

Time to hold low SCL clock

Time to hold high SCL clock

Data hold time

Data setup time

Rise time of SDA or SCL

signal

Fall time of SDA or SCL signal

Load capacitance of each bus

line

Symbol

SCL

LOW

HIGH

; DAT

Unit

kHz

C Bus in Standard Mode

= 4 to 32 MHz

MIN.

MAX.

100

4.7

4.0

300

250

1,000

300

400

C Bus in Standard Mode

= 8 to 32 MHz

MIN.

MAX.

400

1.3

0.6

300

900

100

20 + 0.1Cb

300

20 + 0.1Cb

300

400

PD78P4038Y

Parameter

Serial clock cycle time

(SCK1, SCK2)

Serial clock low-level width

(SCK1, SCK2)

Serial clock high-level width

(SCK1, SCK2)

Setup time for SI1 and SI2

(to SCK1, SCK2

)

Hold time for SI1 and SI2

(to SCK1, SCK2

)

Output delay time for SO1 and

SO2 (to SCK1, SCK2

)

Output hold time for SO1 and

SO2 (to SCK1, SCK2

)

(3) IOE1, IOE2

Remarks 1. The values in this table are those when C

is 100 pF.

2. T: Serial clock cycle set by software. The minimum value is 16/f

(4) UART, UART2

Unit

MIN.

250

500

210

0.5T 40

210

0.5T 40

0.5t

CYSK1

MAX.

Symbol

CYSK1

WSKL1

WSKH1

SSSK1

HSSK1

DSOSK

HSOSK

Conditions

Input

= +5.0 V

10%

Output

Internal, divided by 16

Input

= +5.0 V

10%

Output

Internal, divided by 16

Input

= +5.0 V

10%

Output

Internal, divided by 16

When data is transferred

Unit

Parameter

ASCK clock input cycle time

ASCK clock low-level width

ASCK clock high-level width

Symbol

CYASK

WASKL

WASKH

MIN.

125

250

52.5

MAX.

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

PD78P4038Y

CLOCK OUTPUT OPERATION

Remarks n:

Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)

CYK

(system clock cycle time)

OTHER OPERATIONS

Remarks t

CYSMP

: Sampling clock set by software

CYCPU

: CPU operation clock set by software in the CPU

Unit

Parameter

CLKOUT cycle time

CLKOUT low-level width

CLKOUT high-level width

CLKOUT rise time

CLKOUT fall time

MIN.

0.5t

CYCL

0.5t

CYCL

0.5t

CYCL

0.5t

CYCL

MAX.

Conditions

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

= +5.0 V

10%

Symbol

CYCL

CLL

CLH

CLR

CLF

Unit

Parameter

NMI low-level width

NMI high-level width

INTP0 low-level width

INTP0 high-level width

Low-level width for INTP1-

INTP3 and CI

High-level width for INTP1-

INTP3 and CI

Low-level width for INTP4 and

INTP5

High-level width for INTP4 and

INTP5

RESET low-level width

RESET high-level width

Symbol

WNIL

WNIH

WIT0L

WIT0H

WIT1L

WIT1H

WIT2L

WIT2H

WRSL

WRSH

MIN.

CYSMP

CYCPU

MAX.

Conditions

PD78P4038Y

A/D CONVERTER CHARACTERISTICS

= 40 to +85

C, V

= AV

REF1

= +2.7 to 5.5 V, V

= AV

= 0 V)

Note

Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.

Remark t

CYK

: System clock cycle time

Conditions

FR = 1

FR = 0

FR = 1

FR = 0

= 32 MHz, CS = 1

STOP mode, CS = 0

MIN.

120

180

0.3

TYP.

1,000

0.5

2.0

1.0

MAX.

1.0

0.8

1/2

REF1

+ 0.3

1.5

5.0

Symbol

CONV

SAMP

IAN

REF1

DD1

DD2

Parameter

Resolution

Total error

Note

Linearity calibration

Note

Quantization error

Conversion time

Sampling time

Analog input voltage

Analog input impedance

REF1

current

supply current

= AV

= +5.0 V

10%

= AV

= +2.7 to 4.5 V

= -10 to +85

Unit

bit

LSB

CYK

PD78P4038Y

D/A CONVERTER CHARACTERISTICS (T

= 40 to +85

C, V

= AV

= +2.7 to 5.5 V, V

= AV

= 0 V)

Parameter

Resolution

Total error

Settling time

Output resistance

Analog reference voltage

Resistance of AV

REF2

and

REF3

Reference power supply

input current

Symbol

REF2

REF3

AIREF

REF2

REF3

Conditions

Load conditions:

= AV

REF2

4 M

, 30 pF

= +2.7 to 5.5 V

REF3

= 0 V

= AV

= +2.7 to 5.5 V

REF2

= 0.75V

REF3

= 0.25V

Load conditions:

= AV

REF2

2 M

, 30 pF

= +2.7 to 5.5 V

REF3

= 0 V

= AV

= +2.7 to 5.5 V

REF2

= 0.75V

REF3

= 0.25V

Load conditions: 2 M

, 30 pF

DACS0, 1 = 55 H

MIN.

0.75V

TYP.

MAX.

0.6

0.8

1.0

0.25V

Unit

bit

PD78P4038Y

DATA RETENTION CHARACTERISTICS (T

= 40 to +85

Note

RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1,

P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins

AC TIMING TEST POINTS

Parameter

Data retention voltage

Data retention current

rise time

fall time

hold time

(to STOP mode setting)

STOP clear signal input time

Oscillation settling time

Input low voltage

Input high voltage

Conditions

STOP mode

DDDR

= +2.7 to 5.5 V

DDDR

= +2.5 V

Crystal

Ceramic resonator

Specific pins

Note

MIN.

2.5

200

0.9V

DDDR

TYP.

MAX.

5.5

0.1V

DDDR

Unit

Symbol

DDDR

RVD

FVD

HVD

DREL

WAIT

0.8V

or 2.2 V

0.8 V

0.8V

or 2.2 V

0.8 V

Test points

- 1 V

0.45 V

PD78P4038Y

Parameter

High-level input

voltage

Low-level input

voltage

Input leakage current

High-level output

voltage

Low-level output

voltage

Output leakage

current

DDP

supply voltage

DDP

supply current

Symbol

LIP

DDP

Symbol

Note 1

DC PROGRAMMING CHARACTERISTICS (T

= 25

C, V

= 0 V)

MIN.

2.2

-0.3

2.4

6.25

4.5

12.2

TYP.

6.5

5.0

12.5

1.0

MAX.

DDP

+ 0.3

0.8

0.45

6.75

5.5

12.8

100

Unit

Conditions

DDP

Note 2

= 400

= 2.1 mA

DDP

, OE = V

Program memory write mode

Program memory read mode

Program memory write mode

Program memory read mode

Program memory write mode

Program memory read mode

Program memory write mode

Program memory read mode

= V

DDP

Notes 1. Symbols for the corresponding

PD27C1001A

2. The V

DDP

represents the V

pin as viewed in the programming mode.

PD78P4038Y

Notes 1. These symbols (except t

VDS

) correspond to those of the corresponding

PD27C1001A.

2. For

PD27C1001A, read t

VDS

as t

VCS

AC PROGRAMMING CHARACTERISTICS (T

= 25

C, V

= 0 V)

PROM Write Mode (Page Program Mode)

Parameter

Address setup time

CE set time

Input data setup time

Address hold time

Input data hold time

Output data hold time

setup time

DDP

setup time

Initial program pulse width

OE set time

Valid data delay time from OE

OE pulse width in the data latch

PGM setup time

CE hold time

OE hold time

Symbol

Note 1

CES

AHL

AHV

VPS

VDS

Note 2

OES

PGMS

CEH

OEH

MIN.

0.095

TYP.

0.1

MAX.

130

0.105

Unit

Conditions

PD78P4038Y

Notes 1. These symbols (except t

VDS

) correspond to those of the corresponding

PD27C1001A.

2. For

PD27C1001A, read t

VDS

as t

VCS

PROM Read Mode

Notes 1. These symbols correspond to those of the corresponding

PD27C1001A.

2. t

is the time measured from when either OE or CE reaches V

, whichever is faster.

PROM Write Mode (Byte Program Mode)

Parameter

Address setup time

CE set time

Input data setup time

Address hold time

Input data hold time

Output data hold time

setup time

DDP

setup time

Initial program pulse width

OE set time

Valid data delay time from OE

Symbol

Note 1

CES

VPS

VDS

Note 2

OES

Symbol

Note 1

ACC

Unit

Conditions

MAX.

130

0.105

TYP.

0.1

MIN.

0.095

TYP.

MIN.

CE = OE = V

OE = V

CE = V

or OE = V

CE = OE = V

Conditions

Parameter

Data output time from address

Delay from CE

to data output

Delay from OE

to data output

Data hold time to OE

or CE

Note 2

Data hold time to address

Unit

MAX.

200

PD78P4038Y

PROM Write Mode Timing (Byte Program Mode)

Cautions 1. V

DDP

must be applied before V

, and must be cut after V

2. V

including overshoot must not exceed +13.5 V.

3. Plugging in or out the board with the V

pin supplied with 12.5 V may adversely affect its

reliability.

PROM Read Mode Timing

Notes 1. For reading within t

ACC

, the delay of the OE input from falling edge of CE must be within t

ACC

-t

2. t

is the time measured from when either OE or CE reaches V

, whichever is faster.

Program

Program verify

A0-A16

DDP

+ 1.5

DDP

PGM

Hi-Z

D0-D7

VPS

VDS

CES

OES

Data input

Data output

A0-A16

Hi-Z

D0-D7

Data output

Valid address

ACC

Note 1

Note 2

PD78P4038Y

12. PACKAGE DRAWINGS

80 PIN PLASTIC QFP (14x14)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

0.8

0.2

0.031+0.009

0.008

0.15

0.006

0.10

0.004

17.2

0.4

0.677

0.016

14.0

0.2

0.551+0.009

0.008

14.0

0.2

0.551+0.009

0.008

17.2

0.4

0.677

0.016

0.825

0.032

0.825

0.032

0.30

0.10

0.012+0.004

0.005

0.13

0.005

0.65 (T.P.)

0.026 (T.P.)

0.1

0.004

°±

+0.10

0.05

+0.004

0.003

detail of lead end

1.6

0.2

0.063

0.008

C D

S80GC-65-3B9-5

3.0 MAX.

0.119 MAX.

2.7

0.1

0.106+0.005

0.004

PD78P4038Y

80 PIN PLASTIC QFP (14

14)

ITEM

MILLIMETERS

INCHES

NOTE

Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.

P80GC-65-8BT

0.825

0.032

14.00

0.20

0.551+0.009

0.008

1.70 MAX.

0.067 MAX.

0.17

0.007+0.001

0.003

+0.03

0.07

+0.009

0.008

14.00

0.20

0.551+0.009

0.008

17.20

0.20

0.677

0.008

0.825

0.032

0.32

0.06

0.013+0.002

0.003

0.13

0.005

0.65 (T.P.)

0.026 (T.P.)

1.60

0.20

0.063

0.008

0.80

0.20

0.031+0.009

0.008

0.10

0.004

1.40

0.10

0.055

0.004

0.125

0.075

0.005

0.003

17.20

0.20

0.677

0.008

detail of lead end

PD78P4038Y

80 PIN PLASTIC TQFP (FINE PITCH) (12

12)

ITEM

MILLIMETERS

INCHES

0.50 (T.P.)

0.10

0.004

0.020 (T.P.)

NOTE

Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.

14.00

0.20

0.551

0.008

12.00

0.20

0.472+0.009

0.008

12.00

0.20

0.472+0.009

0.008

14.00

0.20

0.551

0.008

1.25

0.049

0.22

0.009

0.002

P80GK-50-BE9-5

1.27 MAX.

0.050 MAX.

1.00

0.20

0.039+0.009

0.008

0.50

0.20

0.020+0.008

0.009

0.145

0.006

0.002

0.10

0.004

1.05

0.041

0.10

0.05

0.004

0.002

°±

+0.05

0.04

+0.055

0.045

detail of lead end

PD78P4038Y

X80KW-65A-1

ITEM

MILLIMETERS

INCHES

14.0

0.2

13.6

3.6 MAX.

0.06

13.6

0.551

0.008

0.072

0.142 MAX.

0.003

0.024 (T.P.)

0.535

NOTE

0.825

0.65 (T.P.)

0.032

Each lead centerline is located within 0.06
mm (0.003 inch) of its true position (T.P.) at
maximum material condition.

0.018

0.535

R 2.0

R 0.079

0.551

0.008

14.0

0.2

1.84

9.0

0.354

2.1

0.083

+0.004
0.005

0.10

0.004

0.45

0.10

0.039

+0.007
0.006

1.0

0.15

C 0.3

C 0.012

0.75

0.15

0.030

+0.006
0.007

80 PIN CERAMIC WQFN

PD78P4038Y

13. RECOMMENDED SOLDERING CONDITIONS

The conditions listed below shall be met when soldering the

PD78P4038Y.

For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting

Technology Manual (C10535E).

Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under

different conditions.

Table 13-1. Soldering Conditions for Surface-Mount Devices (1/2)

(1)

PD78P4038YGC-3B9: 80-pin plastic QFP (14

2.7 mm)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

(2)

PD78P4038YGC-8BT: 80-pin plastic QFP (14

1.4 mm)

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

Soldering Process

Soldering Conditions

Symbol

Infrared ray reflow

Peak package's surface temperature: 235

IR35-00-2

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 2

VPS

Peak package's surface temperature: 215

VP15-00-2

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 2

Wave soldering

Solder temperature: 260

C or less

WS60-00-1

Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature

: 120

C max. (measured on the package surface)

Partial heating method

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

Soldering Process

Soldering Conditions

Symbol

Infrared ray reflow

Peak package's surface temperature: 235

IR35-00-3

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 3

VPS

Peak package's surface temperature: 215

VP15-00-3

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 3

Wave soldering

Solder temperature: 260

C or less

WS60-00-1

Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature

: 120

C max. (measured on the package surface)

Partial heating method

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

PD78P4038Y

Table 13-1. Soldering Conditions for Surface-Mount Devices (2/2)

(3)

PD78P4038YGK-BE9: 80-pin plastic TQFP (fine pitch) (12

12 mm)

Note

Maximum number of days during which the product can be stored at a temperature of 25

C and a relative

humidity of 65% or less after dry-pack package is opened.

Caution Do not apply two or more different soldering methods to one chip (except for partial heating

method for terminal sections).

Soldering Process

Infrared ray reflow

VPS

Partial heating method

Symbol

IR35-107-2

VP15-107-2

Soldering Conditions

Peak package's surface temperature: 235

Reflow time: 30 seconds or less (210

C or more)

Maximum allowable number of reflow processes: 2

Exposure limit: 7 days

Note

(10 hours of pre-baking is required at 125

afterward)

Non-heat-resistant trays, such as magazine and taping trays, cannot be

baked before unpacking.

Peak package's surface temperature: 215

Reflow time: 40 seconds or less (200

C or more)

Maximum allowable number of reflow processes: 2

Exposure limit: 7 days

Note

(10 hours of pre-baking is required at 125

afterward)

Non-heat-resistant trays, such as magazine and taping trays, cannot be

baked before unpacking.

Terminal temperature: 300

C or less

Heat time: 3 seconds or less (for one side of a device)

PD78P4038Y

APPENDIX A DEVELOPMENT TOOLS

The following development tools are available for system development using the

PD78P4038Y.

See also (5).

(1) Language processing software

RA78K4

Assembler package for all 78K/IV Series models

CC78K4

C compiler package for all 78K/IV Series models

DF784038

Device file for

PD784038Y Subseries models

CC78K4-L

C compiler library source file for all 78K/IV Series models

(2) PROM write tools

PG-1500

PROM programmer

PA-78P4026GC

Programmer adaptor, connects to PG-1500

PA-78P4038GK

PA-78P4026KK

PG-1500 controller

Control program for PG-1500

(3) Debugging tools

· When using the in-circuit emulator IE-78K4-NS

IE-78K4-NS

In-circuit emulator for all 78K/IV Series models

IE-70000-MC-PS-B

Power supply unit for IE-78K4-NS

IE-70000-98-IF-C

Interface adapter when the PC-9800 series computer (other than a notebook)

is used as the host machine

IE-70000-CD-IF

PC card and interface cable when a PC-9800 series notebook is used as the

host machine

IE-70000-PC-IF-C

Interface adapter when the IBM PC/AT

or compatible is used as the host

machine

IE-784038-NS-EM1

Note

Emulation board for evaluating

PD784038Y Subseries models

NP-80GC

Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)

NP-80GK

Note

Emulation probe for 80-pin plastic TQFP (GK-BE9 type)

EV-9200GC-80

Socket for mounting on target system board made for 80-pin plastic QFP

(GC-3B9 and GC-8BT types)

TGK-080SDW

Adapter for mounting on target system board made for 80-pin plastic TQFP

(fine pitch) (GK-BE9 type)

EV-9900

Tool used to remove the

PD78P4038YKK-T from the EV-9200GC-80

ID78K4-NS

Integrated debugger for IE-78K4-NS

SM78K4-NS

System simulator for all 78K/IV Series models

DF784038

Device file for

PD784038Y Subseries models

Note

Under development

PD78P4038Y

· When using the in-circuit emulator IE-784000-R

IE-784000-R

In-circuit emulator for all 78K/IV Series models

IE-70000-98-IF-B

Interface adapter when the PC-9800 series computer (other than a notebook)

IE-70000-98-IF-C

is used as the host machine

IE-70000-98N-IF

Interface adapter and cable when a PC-9800 series notebook is used as the

host machine

IE-70000-PC-IF-B

Interface adapter when the IBM PC/AT or compatible is used as the host

IE-70000-PC-IF-C

machine

IE-78000-R-SV3

Interface adapter and cable when the EWS is used as the host machine

IE-784038-NS-EM1

Note

Emulation board for evaluating

PD784038Y Subseries models

IE-784038-R-EM1

IE-78400-R-EM

Emulation board for all 78K/IV Series models

IE-78K4-R-EX2

Note

Conversion board for 80 pins to use the IE-784038-NS-EM1 on the

IE-784000-R. The board is not needed when the conventional product

IE-784038-R-EM1 is used.

EP-78230GC-R

Emulation probe for 80-pin plastic QFP (GC-3B9 and GC-8BT types)

EP-78054GK-R

Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) for all

PD784038Y Subseries

EV-9200GC-80

Socket for mounting on target system board made for 80-pin plastic QFP

(GC-3B9 and GC-8BT types)

TGK-080SDW

Adapter for mounting on target system board made for 80-pin plastic TQFP

(fine pitch) (GK-BE9 type)

EV-9900

Tool used to remove the

PD78P4038YKK-T from the EV-9200GC-80

ID78K4

Integrated debugger for IE-784000-R

SM78K4

System simulator for all 78K/IV Series models

DF784038

Device file for

PD784038Y Subseries models

Note Under development

(4) Real-time OS

RX78K/IV

Real-time OS for 78K/IV Series models

MX78K4

OS for 78K/IV Series models

PD78P4038Y

(5) Notes when using development tools

· The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038.

· The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784038.

· The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales

representative for purchasing.

· The TGK-080SDW is a product from TOKYO ELETECH CORPORATION.

Refer to: Daimaru Kogyo, Ltd.

Tokyo Electronic Components Division (03-3820-7112)

Osaka Electronic Components Division (06-244-6672)

· The host machines and operating systems corresponding to each software are shown below.

Host Machine

EWS

[OS]

PC-9800 Series [Windows

]

HP9000 Series 700

[HP-UX

]

IBM PC/AT and Compatibles [Windows] SPARCstation

[SunOS

]

Software

NEWS

(RISC) [NEWS-OS

]

RA78K4

Note

CC78K4

Note

PG-1500 controller

Note

ID78K4-NS

ID78K4

SM78K4

RX78K/IV

Note

MX78K4

Note

Note Software under MS-DOS

PD78P4038Y

APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW)

(1) Conversion socket (EV-9200GC-80) package drawings and recommended pattern to mount the socket

Connect the

PD78P4038YKK-T (80-pin ceramic WQFN (14

14 mm)) and EP-78230GC-R to the circuit board

in combination with the EV-9200GC-80.

Figure B-1. Package Drawings of EV-9200GC-80 (Reference) (unit: mm)

No.1 pin index

EV-9200GC-80

EV-9200GC-80-G0E

ITEM

MILLIMETERS

INCHES

18.0

14.4

18.0

4-C 2.0

0.8

6.0

16.0

18.7

6.0

16.0

18.7

8.2

8.0

2.5

2.0

0.35

2.3

1.5

0.709

0.567

0.709

4-C 0.079

0.031

0.236

0.63

0.736

0.236

0.63

0.736

0.323

0.315

0.098

0.079

0.014

0.091

0.059

Based on EV-9200GC-80
(1) Package drawing (in mm)

PD78P4038Y

Figure B-2. Recommended Pattern to Mount EV-9200GC-80 on a Substrate (Reference) (unit: mm)

0.026

0.748=0.486

0.026

0.748=0.486

EV-9200GC-80-P1E

ITEM

MILLIMETERS

INCHES

19.7

15.0

19.7

6.0

0.05

6.0

0.05

0.35

0.02

2.36

0.03

2.3

1.57

0.03

0.776

0.591

0.776

0.236

0.014

0.093

0.091

0.062

0.65

0.02

19=12.35

0.05

0.65

0.02

19=12.35

0.05

+0.001
0.002

+0.003
0.002

+0.001
0.002

+0.003
0.002

+0.001
0.001

+0.001
0.002

Based on EV-9200GC-80
(2) Pad drawing (in mm)

Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).

Caution

PD78P4038Y

(2) Conversion adapter (TGK-080SDW) package drawings

Connect the EP-78054GK-R to the circuit board in combination with the TGK-080SDW.

Figure B-3. Package Drawings of TGK-080SDW (Reference) (unit: mm)

ITEM

MILLIMETERS

INCHES

0.25

0.010

5.3

0.209

0.5x19=9.5

0.10

0.020x0.748=0.374

0.004

5.3

0.209

1.85

0.2

0.073

0.008

3.5

0.138

2.0

0.079

1.3

0.051

3.55

0.3

0.012

0.140

ITEM

MILLIMETERS

INCHES

0.5x19=9.5

0.020x0.748=0.374

18.0

0.709

1.58

0.062

1.2

0.047

0.5x19=9.5

0.020x0.748=0.374

11.77

0.463

7.64

0.301

1.2

0.047

1.2

0.047

1.58

0.062

3.55

0.140

1.58

0.062

1.2

7.64

0.301

0.047

6.8

0.268

8.24

0.324

14.8

0.583

C 2.0

C 0.079

12.31

10.17

0.400

0.485

1.4

0.2

0.055

0.008

0.5

1.58

0.020

0.062

18.0

0.709

3.0

0.118

1.4

0.2

0.055

0.008

1.4

0.2

0.055

0.008

h=1.8 1.3

h=0.071 0.051

0.25

14.0

0.551

0.010

0~5

0.000~0.197

11.77

0.5

0.463

0.020

TGK-080SDW-G1E

2.4

0.094

2.7

0.106

3.9

0.154

5.9

0.8

0.031

0.232

TGK-080SDW (TQPACK080SD + TQSOCKET080SDW)
Package dimension (unit: mm)

I J J J

L L LM

B
C

M2 screw

X
Y

Protrusion : 4 places

note: Product by TOKYO ELETECH CORPORATION.

PD78P4038Y

APPENDIX C RELATED DOCUMENTS

Documents Related to Devices

Document Name

Document No.

English

Japanese

PD784031Y Data Sheet

U11504E

U11504J

PD784035Y, 784036Y, 784037Y, 784038Y Data Sheet

U10741E

U10741J

PD78P4038Y Data Sheet

This manual

U10742J

PD784038, 784038Y Sub-Series User's Manual, Hardware

U11316E

U11316J

PD784038Y Sub-Series Special Function Registers

U11090J

78K/IV Series User's Manual, Instruction

U10905E

U10905J

78K/IV Series Instruction Summary Sheet

U10594J

78K/IV Series Instruction Set

U10595J

78K/IV Series Application Note, Software Basic

U10095J

Documents Related to Development Tools (User's Manual)

Document Name

Document No.

English

Japanese

RA78K4 Assembler Package

Operation

U11334E

U11334J

Language

U11162E

U11162J

RA78K Series Structured Assembler Preprocessor

U11743E

U11743J

CC78K4 Series

Operation

U11572E

U11572J

Language

U11571E

U11571J

CC78K Series Library Source File

U12322E

U12322J

PG-1500 PROM Programmer

U11940E

U11940J

PG-1500 Controller PC-9800 Series (MS-DOS

) Base

EEU-1291

EEU-704

PG-1500 Controller IBM PC Series (PC DOS

) Base

U10540E

EEU-5008

IE-78K4-NS

To be released

U13356J

soon

IE-784000-R

EEU-1534

U12903J

IE-784038-NS-EM1

Planned

IE-784038-R-EM1

U11383E

U11383J

EP-78230

EEU-1515

EEU-985

EP-78054GK-R

EEU-1468

EEU-932

SM78K4 System Simulator Windows Base

Reference

U10093E

U10093J

SM78K Series System Simulator

External Parts User Open

U10092E

U10092J

Interface Specifications

ID78K4-NS Integrated Debugger

Reference

U12796E

U12796J

ID78K4 Integrated Debugger Windows Base

Reference

U10440E

U10440J

ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base

Reference

U11960E

U11960J

Caution The above documents may be revised without notice. Use the latest versions when you design

application systems.

PD78P4038Y

Documents Related to Software to Be Incorporated into the Product (User's Manual)

Document Name

Document No.

English

Japanese

78K/IV Series Real-Time OS

Basic

U10603E

U10603J

Installation

U10604E

U10604J

Debugger

U10364J

OS for 78K/IV Series MX78K4

Basic

U11779J

Other Documents

Document Name

Document No.

English

Japanese

IC PACKAGE MANUAL

C10943X

Semiconductor Device Mounting Technology Manual

C10535E

C10535J

Quality Grades on NEC Semiconductor Device

C11531E

C11531J

NEC Semiconductor Device Reliability/Quality Control System

C10983E

C10983J

Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)

C11892E

C11892J

Semiconductor Device Quality Control/Reliability Handbook

C12769J

Guide for Products Related to Microcomputer: Other Companies

U11416J

Caution The above documents may be revised without notice. Use the latest versions when you design

application systems.

PD78P4038Y

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of

the gate oxide and ultimately degrade the device operation. Steps must be taken

to stop generation of static electricity as much as possible, and quickly dissipate

it once, when it has occurred. Environmental control must be adequate. When

it is dry, humidifier should be used. It is recommended to avoid using insulators

that easily build static electricity. Semiconductor devices must be stored and

transported in an anti-static container, static shielding bag or conductive

material. All test and measurement tools including work bench and floor should

be grounded. The operator should be grounded using wrist strap. Semiconduc-

tor devices must not be touched with bare hands. Similar precautions need to

be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input level

may be generated due to noise, etc., hence causing malfunction. CMOS device

behave differently than Bipolar or NMOS devices. Input levels of CMOS devices

must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V

or GND with a resistor, if it is considered to have

a possibility of being an output pin. All handling related to the unused pins must

be judged device by device and related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production

process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset function

have not yet been initialized. Hence, power-on does not guarantee out-pin

levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after

power-on for devices having reset function.

PD78P4038Y

Caution This product contains an I

C bus interface circuit.

When using the I

C bus interface, notify its use to NEC when ordering custom code. NEC can

guarantee the following only when the customer informs NEC of the use of the interface:
Purchase of NEC I

C components conveys a license under the Philips I

C Patent Rights to use

these components in an I

C system, provided that the system conforms to the I

C Standard

Specification as defined by Philips.

IEBus and QTOP are trademarks of NEC Corporation.

MS-DOS and Windows are registered trademarks or trademarks of Microsoft Corporation in the United States

and/or other countries.

PC/AT and PC DOS are trademarks of IBM Corporation.

HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.

SPARCstation is a trademark of SPARC International, Inc.

SunOS is a trademark of Sun Microsystems, Inc.

NEWS and NEWS-OS are trademarks of SONY Corporation.

PD78P4038Y

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 011-6465-6829

J98. 2

PD78P4038Y

Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.

License not needed

PD78P4038YKK-T

The customer must judge the need for license

PD78P4038YGC-3B9,

PD78P4038YGC-

×××

-3B9,

PD78P4038YGC-8BT

PD78P4038YGK-BE9,

PD78P4038YGK-

×××

-BE9

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96. 5

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