Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- 78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
- FUNCTIONS
- 1. DIFFERENCES BETWEEN uPD78P4908 AND MASK ROM PRODUCTS
- 2. PIN CONFIGURATION (TOP VIEW)
- 3. BLOCK DIAGRAM
- 4. PIN FUNCTIONS
- 4.1 PINS FOR NORMAL OPERATING MODE
- 4.2 PINS FOR PROM PROGRAMMING MODE (VPP Greater or equal to +5 V or +12.5 V, RESET# = L)
- 4.2.1 Pin Functions
- 4.2.2 Pin Functions
- 4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS
- 5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
- 6. PROM PROGRAMMING
- 6.1 OPERATION MODE
- 6.2 PROM WRITE SEQUENCE
- 6.3 PROM READ SEQUENCE
- 7. SCREENING ONE-TIME PROM PRODUCTS
- 8. ELECTRICAL CHARACTERISTICS
- 9. PACKAGE DRAWING
- 10. RECOMMENDED SOLDERING CONDITIONS
- APPENDIX A DEVELOPMENT TOOLS
- APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING
- APPENDIX C RELATED DOCUMENTS
MOS INTEGRATED CIRCUIT
PD78P4908
Document No.
U11681EJ2V0DS00 (2nd edition)
Date Published February 1999 N CP(K)
Printed in Japan
DATA SHEET
16-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
The
PD78P4908, 78K/IV series' product, is a one-time PROM version of the
PD784907 and
PD784908 with
internal mask ROM.
Since user programs can be written to PROM, this microcomputer is best suited for evaluation in system
development, manufacture of small quantities of multiple products, and fast start-up of applications.
For specific functions and other detailed information, consult the following user's manuals.
These manuals are required reading for design work.
PD784908 Subseries User's Manual - Hardware : U11787E
78K/IV Series User's Manual - Instruction
: U10905E
FEATURES
78K/IV series
Internal PROM: 128 Kbytes
Internal RAM:
4,352 bytes
Supply voltage: V
DD
= 4.5 to 5.5 V
(At main clock: f
XX
= 12.58 MHz, internal system clock = f
XX
: f
CYK
= 79 ns)
V
DD
= 4.0 to 5.5 V
(Other than above: f
CYK
= 159 ns)
ORDERING INFORMATION
Part number
Package
Internal ROM
PD78P4908GF-3BA
100-pin plastic QFP (14
20 mm)
One-time PROM
The mark shows major revised points.
1996
The information in this document is subject to change without notice.
2
PD78P4908
Data Sheet U11681EJ2V0DS00
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
PD784026
PD784038Y
I
2
C bus supported
PD784038
Enhanced internal memory capacity,
pin compatible with the PD784026
PD784225Y
Multimaster I
2
C bus supported
PD784225
80 pins,
added ROM correction
PD784218Y
Multimaster I
2
C bus supported
Multimaster I
2
C bus supported
PD784218
Enhanced internal memory capacity,
added ROM correction
PD784928Y
Multimaster I
2
C bus supported
PD784928
Enhanced function of the PD784915
PD784216Y
PD784054
PD784216
PD784046
PD784908
Equipped with 10-bit A/D
100 pins,
enhanced I/O and
internal memory capacity
Enhanced A/D,
16-bit timer,
and power
management
PD784915
For software servo control,
equipped with analog circuit
for VCR,
enhanced timer
Equipped with IEBus
TM
controller
Standard models
ASSP models
: Under mass production
: Under development
PD784955
For DC inverter control
PD784938
Enhanced function of the PD784908,
enhanced internal memory capacity,
added ROM correction
3
PD78P4908
Data Sheet U11681EJ2V0DS00
FUNCTIONS
(1/2)
Function
113
8 bits
16 registers
8 banks, or 16 bits
8 registers
8 banks (memory mapping)
320 ns/636 ns/1.27
s/2.54
s (at 6.29 MHz)
160 ns/320 ns/636 ns/1.27
s (at 12.58 MHz)
128 Kbytes
4,352 bytes
Program and data: 1 Mbyte
80
8
72
24
8
4
4 bits
2, or 8 bits
1
Incorporated (simple version)
Timer/counter 0:
Timer register
1
Pulse output capability
(16 bits)
Capture register
1
Toggle output
Compare register
2
PWM/PPG output
One-shot pulse output
Timer/counter 1:
Timer register
1
Real-time output port
(16 bits)
Capture register
1
Capture/compare register
1
Compare register
1
Timer/counter 2:
Timer register
1
Pulse output capability
(16 bits)
Capture register
1
Toggle output
Capture/compare register
1
PWM/PPG output
Compare register
1
Timer 3:
Timer register
1
(16 bits)
Compare register
1
Interrupt requests are generated at 0.5-second intervals. (A clock timer oscillator is
incorporated.)
Either the main clock (6.29 MHz/12.58 MHz) or real-time clock (32.768 kHz) can be
selected as the input clock.
Selected from f
CLK
, f
CLK
/2, f
CLK
/4, f
CLK
/8, or f
CLK
/16 (can be used as a 1-bit output port)
12-bit resolution
2 channels
UART/IOE (3-wire serial I/O) : 2 channels (incorporating baud rate generator)
CSI (3-wire serial I/O)
: 2 channels
ROM
RAM
Total
Input
Input/output
LED direct
drive outputs
Transistor
direct drive
N-ch open
drain
Item
Number of basic instructions
(mnemonics)
General-purpose register
Minimum instruction execution
time
Internal
memory
Memory space
I/O ports
Additional
function
pins
Note
Real-time output ports
IEBus controller
Timer/counter
Clock timer
Clock output
PWM outputs
Serial interface
Note
Additional function pins are included in the I/O pins.
4
PD78P4908
Data Sheet U11681EJ2V0DS00
(2/2)
Function
8-bit resolution
8 channels
1 channel
HALT/STOP/IDLE mode
27 (20 internal, 7 external (sampling clock variable input: 1))
BRK or BRKCS instruction, operand error
1 internal, 1 external
19 internal, 6 external
4-level programmable priority
3 operation statuses: vectored interrupt, macro service, context switching
V
DD
= 4.5 to 5.5 V (At main clock: f
XX
= 12.58 MHz, internal system clock = f
XX
: f
CYK
=
79 ns)
V
DD
= 4.0 to 5.5 V (Other than above: f
CYK
= 159 ns)
100-pin plastic QFP (14
20 mm)
Item
A/D converter
Watchdog timer
Standby
Interrupt
Hardware source
Software source
Nonmaskable
Maskable
Power supply voltage
Package
5
PD78P4908
Data Sheet U11681EJ2V0DS00
CONTENTS
1.
DIFFERENCES BETWEEN
PD78P4908 AND MASK ROM PRODUCTS ............................
6
2.
PIN CONFIGURATION (TOP VIEW) .........................................................................................
7
3.
BLOCK DIAGRAM .....................................................................................................................
10
4.
PIN FUNCTIONS ........................................................................................................................
11
4.1
PINS FOR NORMAL OPERATING MODE ....................................................................................
11
4.2
PINS FOR PROM PROGRAMMING MODE (V
PP
+5 V or +12.5 V, RESET = L) ....................
14
4.2.1
Pin Functions .................................................................................................................
14
4.2.2
Pin Functions .................................................................................................................
15
4.3
I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS .................................................
16
5.
INTERNAL MEMORY SIZE SELECT REGISTER (IMS) ..........................................................
19
6.
PROM PROGRAMMING ............................................................................................................
20
6.1
OPERATION MODE ........................................................................................................................
20
6.2
PROM WRITE SEQUENCE ............................................................................................................
22
6.3
PROM READ SEQUENCE .............................................................................................................
26
7.
SCREENING ONE-TIME PROM PRODUCTS ..........................................................................
26
8.
ELECTRICAL CHARACTERISTICS .........................................................................................
27
9.
PACKAGE DRAWING ................................................................................................................
51
10. RECOMMENDED SOLDERING CONDITIONS ........................................................................
52
APPENDIX A DEVELOPMENT TOOLS ..........................................................................................
53
APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING .....................
56
APPENDIX C RELATED DOCUMENTS .........................................................................................
58
6
PD78P4908
Data Sheet U11681EJ2V0DS00
1. DIFFERENCES BETWEEN
PD78P4908 AND MASK ROM PRODUCTS
The
PD78P4908 is produced by replacing the mask ROM in the
PD784907 or
PD784908 with PROM to which
data can be written. The functions of the
PD78P4908 are the same as those of the
PD784907 or
PD784908 except
for the PROM specification such as writing and verification, except that the PROM size can be changed to 96 or 128
Kbytes, and except that the internal RAM size can be changed to 3,584 or 4,352 bytes.
Table 1-1 shows the differences between these products.
Table 1-1. Differences Between the
PD78P4908 and Mask ROM Products
Product name
Item
Internal program
memory
Internal RAM
Pin connection
Power supply voltage
Electrical
characteristics
PD78P4908
128-Kbyte PROM
Can be changed to 96
Kbytes by IMS
4,352-byte internal RAM
Can be changed to 3,584
bytes by IMS
Pin functions related to writing or reading of PROM have been added to the
PD78P4908.
V
DD
= 4.5 to 5.5 V
V
DD
= 4.0 to 5.5 V
(At main clock: f
XX
= 12.58
(At main clock: f
XX
= 12.58 MHz, internal system clock = f
XX
:
MHz, internal system clock =
f
CYK
= 79 ns)
f
XX
: f
CYK
= 79 ns
V
DD
= 3.5 to 5.5 V
V
DD
= 4.0 to 5.5 V
(Other than above: f
CYK
= 159 ns)
(Other than above: f
CYK
=
159 ns)
Partially differs between these products.
PD784907
96-Kbyte mask ROM
3,584-byte internal RAM
PD784908
128-Kbyte mask ROM
4,352-byte internal RAM
7
PD78P4908
Data Sheet U11681EJ2V0DS00
2. PIN CONFIGURATION (TOP VIEW)
(1) Normal operation mode
100-pin plastic QFP (14
20 mm)
PD78P4908GF-3BA
Notes 1. Connect the TEST pin to V
SS
directly.
2. Connect the REGOFF pin to V
SS
directly (select regulator operation)
3. Connect the REGC pin to V
SS
through a 1-
F capacitor.
P35/TO1
100
P34/TO0
99
P33/SO0
98
P32/SCK0
97
P31/TxD/SO1
96
P30/RxD/SI1
95
P27/SI0
94
P26/INTP5
93
P25/INTP4/ASCK/SCK1
92
P24/INTP3
91
P23/INTP2/CI
90
P22/INTP1
89
P21/INTP0
88
P20/NMI
87
TX
86
RX
85
AV
SS
84
AV
REF1
83
AV
DD
82
P77/ANI7
81
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
80
P76/ANI6
1
P36/TO2
2
3
P37/TO3
P100
4
P101
5
P102
6
P103
7
P104
8
P105/SCK3
9
P106/SI3
10
P107/SO3
11
RESET
12
XT2
13
XT1
14
V
SS
15
X2
16
X1
17
REGOFF
Note 2
18
REGC
Note 3
19
V
DD
20
P00
21
P01
22
P02
23
P03
24
P04
25
P05
26
P06
27
P07
28
P67/REFRQ/HLDAK
29
P66/WAIT/HLDRQ
30
P65/WR
79
P75/ANI5
78
P74/ANI4
77
P73/ANI3
76
P72/ANI2
75
P71/ANI1
74
P70/ANI0
73
TEST
Note 1
72
PWM1
71
PWM0
70
P17
69
P16
68
P15
67
P14/TxD2/SO2
66
P13/RxD2/SI2
65
P12/ASCK2/SCK2
64
P11
62
ASTB/CLKOUT
63
P10
61
P90
60
P91
59
P92
58
P93
57
P94
56
P95
55
P96
54
P97
53
P40/AD0
52
P41/AD1
51
P42/AD2
P64/RD
P63/A19
P62/A18
P61/A17
P60/A16
P57/A15
P56/A14
P55/A13
P54/A12
V
SS
V
DD
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
8
PD78P4908
Data Sheet U11681EJ2V0DS00
PWM0, PWM1 : Pulse width modulation output
RD
: Read strobe
REFRQ
: Refresh request
REGC
: Regulator capacitance
REGOFF
: Regulator off
RESET
: Reset
RX
: IEBus receive data
RxD, RxD2
: Receive data
SCK0-SCK3
: Serial clock
SI0-SI3
: Serial input
SO0-SO3
: Serial output
TEST
: Test
TO0-TO3
: Timer output
TX
: IEBus transmit data
TxD, TxD2
: Transmit data
V
DD
: Power supply
V
SS
: Ground
WAIT
: Wait
WR
: Write strobe
X1, X2
: Crystal (main system clock)
XT1, XT2
: Crystal (watch)
A8-A19
: Address bus
AD0-AD7
: Address/data bus
ANI0-ANI7
: Analog input
ASCK, ASCK2 : Asynchronous serial clock
ASTB
: Address strobe
AV
DD
: Analog power supply
AV
REF1
: Reference voltage
AV
SS
: Analog ground
CI
: Clock input
CLKOUT
: Clock output
HLDAK
: Hold acknowledge
HLDRQ
: Hold request
INTP0-INTP5
: Interrupt from peripherals
NMI
: Non-maskable interrupt
P00-P07
: Port 0
P10-P17
: Port 1
P20-P27
: Port 2
P30-P37
: Port 3
P40-P47
: Port 4
P50-P57
: Port 5
P60-P67
: Port 6
P70-P77
: Port 7
P90-P97
: Port 9
P100-P107
: Port 10
9
PD78P4908
Data Sheet U11681EJ2V0DS00
(2) PROM programming mode
100-pin plastic QFP (14
20 mm)
PD78P4908GF-3BA
Caution L
: Connect these pins separately to the V
SS
pins through 10-k
pull-down resistors.
V
SS
: To be connected to the ground.
Open : Nothing should be connected on these pins.
RESET: Set a low-level input.
A0-A16
: Address bus
RESET
: Reset
CE
: Chip enable
V
DD
: Power supply
D0-D7
: Data bus
V
PP
: Programming power supply
OE
: Output enable
V
SS
: Ground
PGM
: Program
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
OPEN
(L)
A9
V
SS
OPEN
OPEN
V
SS
V
SS
V
DD
OPEN
V
SS
OPEN
OPEN
V
PP
A0
A1
A2
OE
A15
A14
A13
A12
V
SS
V
DD
A11
A10
A16
A8
A7
A6
A5
A4
A3
(L)
OPEN
V
DD
RESET
OPEN
V
SS
V
SS
OPEN
V
SS
D0
D1
D2
D3
D4
D5
D6
D7
(L)
PGM
CE
10
PD78P4908
Data Sheet U11681EJ2V0DS00
3. BLOCK DIAGRAM
Note
In the PROM programming mode.
NMI
INTP3
TO0
TO1
INTP0
INTP1
INTP2/CI
TO2
TO3
P00-P03
P04-P07
PWM0
PWM1
INTP5
RESET
TEST
X1
X2
REGC
REGOFF
ANI0-ANI7
TxD/SO1
ASCK/SCK1
RxD/SI1
ASCK2/SCK2
SCK0
SO0
SI0
A8-A15
P00-P07
P20-P27
P10-P17
P30-P37
P40-P47
P50-P57
P60-P67
P70-P77
ASTB /CLKOUT
REFRQ/HLDAK
WR
WAIT/HLDRQ
AD0-AD7
A0-A16
Note
D0-D7
Note
RD
A16-A19
PGM
Note
CE
Note
OE
Note
AV
DD
V
DD
AV
REF1
AV
SS
V
SS
UART/IOE2
Baud-rate
generator
UART/IOE1
Clocked serial
interface
Clock output
Bus interface
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Programmable
interrupt controller
Timer/counter 0
Timer/counter 1
Timer/counter 2
Timer 3
Real-time output
port
PWM
A /D converter
INTP0-INTP5
(16 bits)
(16 bits)
(16 bits)
(16 bits)
ROM
(128 Kbytes)
78K /IV
CPU core
(RAM 512 bytes)
Watchdog timer
Baud-rate
generator
TxD2/SO2
RxD2/SI2
TX
RX
IEBus controller
XT1
XT2
Watch timer
SCK3
SO3
SI3
Clocked serial
interface 3
P90-P97
P100-P107
Port 9
Port 10
V
PP
Note
System control
(regulator)
RAM
(3,840 bytes)
11
PD78P4908
Data Sheet U11681EJ2V0DS00
Pin
P00-P07
P10
P11
P12
P13
P14
P15-P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34-P37
P40-P47
I/O
I/O
I/O
Input
I/O
I/O
Also used as
--
--
--
ASCK2/SCK2
RxD2/SI2
TxD2/SO2
--
NMI
INTP0
INTP1
INTP2/CI
INTP3
INTP4/ASCK/SCK1
INTP5
SI0
RxD/SI1
TxD/SO1
SCK0
SO0
TO0-TO3
AD0-AD7
Function
Port 0 (P0):
8-bit I/O port.
Functions as a real-time output port (4 bits
2).
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Can drive a transistor.
Port 1 (P1):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Can drive LED.
Port 2 (P2):
8-bit input-only port.
P20 does not function as a general-purpose port (nonmaskable
interrupt). However, the input level can be checked by an interrupt
service routine.
The use of built-in pull-up resistors can be specified by software for pins
P22 to P27 (in units of 6 bits).
The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 input/output pin
by CSIM1.
Port 3 (P3):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
P32 and P33 can be set as the N-ch open-drain pin.
Port 4 (P4):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Can drive LED.
4. PIN FUNCTIONS
4.1 PINS FOR NORMAL OPERATING MODE
(1) Port pins (1/2)
12
PD78P4908
Data Sheet U11681EJ2V0DS00
(1) Port pins (2/2)
Pin
P50-P57
P60-P63
P64
P65
P66
P67
P70-P77
P90-P97
P100-P104
P105
P106
P107
I/O
I/O
I/O
I/O
I/O
I/O
Function
Port 5 (P5):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Can drive LED.
Port 6 (P6):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Port 7 (P7):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
Port 9 (P9):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
Port 10 (P10):
8-bit I/O port.
Inputs and outputs can be specified bit by bit.
The use of built-in pull-up resistors can be simultaneously specified by
software for all pins in input mode.
P105 and P107 can be set as the N-ch open-drain pin.
Also used as
A8-A15
A16-A19
RD
WR
WAIT/HLDRQ
REFRQ/HLDAK
ANI0-ANI7
--
--
SCK3
SI3
SO3
13
PD78P4908
Data Sheet U11681EJ2V0DS00
(2) Non-port pins (1/2)
Pin
TO0-TO3
CI
RxD
RxD2
TxD
TxD2
ASCK
ASCK2
SI0
SI1
SI2
SI3
SO0
SO1
SO2
SO3
SCK0
SCK1
SCK2
SCK3
NMI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
AD0-AD7
A8-A15
A16-A19
RD
WR
WAIT
REFRQ
HLDRQ
HLDAK
ASTB
I/O
Output
Input
Input
Output
Input
Input
Output
I/O
Input
I/O
Output
Output
Output
Output
Input
Output
Input
Output
Output
Function
Timer output
Input of a count clock for timer/counter 2
Serial data input (UART0)
Serial data input (UART2)
Serial data output (UART0)
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data input (3-wire serial I/O 0)
Serial data input (3-wire serial I/O 1)
Serial data input (3-wire serial I/O 2)
Serial data input (3-wire serial I/O 3)
Serial data output (3-wire serial I/O 0)
Serial data output (3-wire serial I/O 1)
Serial data output (3-wire serial I/O 2)
Serial data output (3-wire serial I/O 3)
Serial clock I/O (3-wire serial I/O 0)
Serial clock I/O (3-wire serial I/O 1)
Serial clock I/O (3-wire serial I/O 2)
Serial clock I/O (3-wire serial I/O 3)
External interrupt request
--
Input of a count clock for timer/counter 1
Capture/trigger signal for CR11 or CR12
Input of a count clock for timer/counter 2
Capture/trigger signal for CR22
Input of a count clock for timer/counter 2
Capture/trigger signal for CR21
Input of a count clock for timer/counter 0
Capture/trigger signal for CR02
--
Input of a conversion start trigger for A/D converter
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for connecting
external memory)
Also used as
P34-P37
P23/INTP2
P30/SI1
P13/SI2
P31/SO1
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P27
P30/RxD
P13/RxD2
P106
P33
P31/TxD
P14/TxD2
P107
P32
P25/INTP4/ASCK
P12/ASCK2
P105
P20
P21
P22
P23/CI
P24
P25/ASCK/SCK1
P26
P40-P47
P50-P57
P60-P63
P64
P65
P66/HLDRQ
P67/HLDAK
P66/WAIT
P67/REFRQ
CLKOUT
14
PD78P4908
Data Sheet U11681EJ2V0DS00
(2) Non-port pins (2/2)
I/O
Output
Output
Output
Input
Output
--
--
Input
Input
--
Input
--
Input
--
Input
Function
Clock output
PWM output 0
PWM output 1
Data input (IEBus)
Data output (IEBus)
Capacitor connection for stabilizing the regulator output/Power supply
when the regulator is stopped. Connect to V
SS
via a 1-
F capacitor.
Signal for specifying regulator operation. Directly connect to V
SS
(regulator
selected).
Chip reset
Crystal input for system clock oscillation (A clock pulse can also be input
to the X1 pin.)
Real-time clock connection
Analog voltage inputs for the A/D converter
Application of A/D converter reference voltage
Positive power supply for the A/D converter
Ground for the A/D converter
Positive power supply
Ground
Directly connect to V
SS
. (The TEST pin is for the IC test.)
Also used as
ASTB
--
--
--
--
--
--
--
--
--
--
P70-P77
--
Pin
CLKOUT
PWM0
PWM1
RX
TX
REGC
REGOFF
RESET
X1
X2
XT1
XT2
ANI0-ANI7
AV
REF1
AV
DD
AV
SS
V
DD
V
SS
TEST
4.2 PINS FOR PROM PROGRAMMING MODE (V
PP
+5 V or +12.5 V, RESET = L)
4.2.1 Pin Functions
Pin name
V
PP
RESET
A0-A16
D0-D7
CE
OE
PGM
V
DD
V
SS
I/O
--
Input
I/O
Input
--
--
Function
PROM programming mode selection
High voltage input during program write or verification
PROM programming mode selection
Address bus
Data bus
PROM enable input/program pulse input
Read strobe input to PROM
Program/program inhibit input during PROM programming mode
Positive power supply
GND
15
PD78P4908
Data Sheet U11681EJ2V0DS00
4.2.2 Pin Functions
(1) V
PP
(Programming power supply): Input
Input pin for setting the
PD78P4908 to the PROM programming mode. When the input voltage on this pin is
+6.5 V or more and when RESET input goes low, the
PD78P4908 enters the PROM programming mode.
When CE is made low for V
PP
= +12.5 V and OE = high, program data on D0 to D7 can be written into the internal
PROM cell selected by A0 to A16.
(2) RESET (Reset): Input
Input pin for setting the
PD78P4908 to the PROM programming mode. When input on this pin is low, and when
the input voltage on the V
PP
pin goes +5 V or more, the
PD78P4908 enters the PROM programming mode.
(3) A0 to A16 (Address bus): Input
Address bus that selects an internal PROM address (0000H to 1FFFFH)
(4) D0 to D7 (Data bus): I/O
Data bus through which a program is written on or read from internal PROM
(5) CE (Chip enable): Input
This pin inputs the enable signal from internal PROM. When this signal is active, a program can be written or
read.
(6) OE (Output enable): Input
This pin inputs the read strobe signal to internal PROM. When this signal is made active for CE = low, a one-
byte program in the internal PROM cell selected by A0 to A16 can be read onto D0 to D7.
(7) PGM (Program): Input
The input pin for the operation mode control signal of the internal PROM.
Upon activation, writing to the internal PROM is enabled.
Upon inactivation, reading from the internal PROM is enabled.
(8) V
DD
Positive power supply pin
(9) V
SS
Ground potential pin
16
PD78P4908
Data Sheet U11681EJ2V0DS00
4.3 I/O CIRCUITS FOR PINS AND HANDLING OF UNUSED PINS
Table 4-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 4-1 shows the configuration of these various types of I/O circuits.
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin
P00-P07
P10, P11
P12/ASCK2/SCK2
P13/R
X
D2/SI2
P14/T
X
D2/SO2
P15-P17
P20/NMI
P21/INTP0
P22/INTP1
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1
P26/INTP5
P27/SI0
P30/R
X
D/SI1
P31/T
X
D/SO1
P32/SCK0
P33/SO0
P34/TO0-P37/TO3
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0-P77/ANI7
P90-P97
P100-P104
P105/SCK3
P106/SI3
P107/SO3
ASTB/CLKOUT
I/O circuit type
5-A
8-A
5-A
2
2-A
8-A
2-A
5-A
10-A
5-A
20
5-A
10-A
8-A
10-A
4
I/O
I/O
Input
I/O
Input
I/O
I/O
Output
Recommended connection method for unused pins
Input state:
To be connected to V
DD
Output state: To be left open
To be connected to V
DD
or V
SS
To be connected to V
DD
Input state:
To be connected to V
DD
Output state: To be left open
To be connected to V
DD
Input state:
To be connected to V
DD
Output state: To be left open
Input state:
To be connected to V
DD
or V
SS
Output state : To be left open
To be left open
17
PD78P4908
Data Sheet U11681EJ2V0DS00
Table 4-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to V
DD
through
a resistor of 10 to 100 k
(particularly when the voltage of the reset input pin becomes higher
than that of the low level input at power-on or when I/O is switched by software).
Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product.
(Some circuits are not included.)
Recommended connection method for unused pins
--
To be connected to V
SS
directly
To be left open
To be connected to V
SS
To be left open
To be connected to V
DD
or V
SS
To be left open
To be connected to V
SS
To be connected to V
DD
I/O
Input
--
Input
Output
Input
Output
--
Pin
RESET
TEST
XT2
XT1
PWM0, PWM1
RX
TX
AV
REF1
AV
SS
AV
DD
I/O circuit type
2
1
--
3
1
3
--
18
PD78P4908
Data Sheet U11681EJ2V0DS00
Figure 4-1. I/O Circuits for Pins
Type 1
Type 2
Type 3
Type 4
Type 10-A
Type 12
Type 5-A
Type 8-A
Type 20
Type 2-A
IN
V
DD
P
N
N
P
Analog output
voltage
OUT
IN
Schmitt trigger input with hysteresis characteristics
Schmitt trigger input with hysteresis characteristics
IN
V
DD
P
Pull-up
enable
Data
OUT
V
DD
P-ch
N-ch
Data
V
DD
P
N
OUT
Output
disable
Push-pull output which can output high impedance
(both the positive and negative channels are off.)
Data
V
DD
P
N
IN/OUT
Output
disable
V
DD
P
Pull-up
enable
Input
enable
Data
V
DD
P
N
IN/OUT
Output
disable
V
DD
P
Pull-up
enable
Data
V
DD
P
N
IN/OUT
Output
disable
V
DD
P
Pull-up
enable
Open
drain
Data
Comparator
V
DD
V
REF
P
(Threshold voltage)
P
N
N
IN/OUT
Output
disable
Input
enable
+
19
PD78P4908
Data Sheet U11681EJ2V0DS00
5. INTERNAL MEMORY SIZE SELECT REGISTER (IMS)
This register enables the software to avoid using part of the internal memory. The IMS can be set to establish
the same memory mapping as used in mask ROM products that have different internal memory (ROM and RAM)
configurations.
The IMS is set using 8-bit memory operation instructions.
A RESET input sets the IMS to FFH.
Figure 5-1. Internal Memory Size Select Register (IMS)
The IMS is not contained in a mask ROM product (
PD784907 or
PD784908). But the action is not affected if
the write command to the IMS is executed to the mask ROM product.
IMS
IMS7
IMS6
IMS5
IMS4
IMS3
IMS2
IMS1
IMS0
7
6
5
4
3
2
1
0
0FFFCH
Address
FFH
Reset value
W
R/W
IMS0-7
FFH
EEH
Other than
the above
Same as the PD784908
Memory size
Same as the PD784907
Not to be set
20
PD78P4908
Data Sheet U11681EJ2V0DS00
6. PROM PROGRAMMING
The
PD78P4908 has an on-chip 128-KB PROM device for use as program memory. When programming, set
the V
PP
and RESET pins for PROM programming mode. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM
programming mode with regard to handling of other, unused pins.
6.1 OPERATION MODE
PROM programming mode is selected when +6.5 V is added to the V
DD
pin, +12.5 V is added to the V
PP
pin, or
low-level input is added to the RESET pin. This mode can be set to operation mode by setting the CE pin, OE pin,
and PGM pin as shown in Table 6-1 below.
In addition, the PROM contents can be read by setting read mode.
Table 6-1. PROM Programming Operation Mode
Pin
RESET
V
PP
V
DD
CE
OE
PGM
D0-D7
Operation mode
Page data latch
L
+12.5 V
+6.5 V
H
L
H
Data input
Page write
H
H
L
High impedance
Byte write
L
H
L
Data input
Program verify
L
L
H
Data output
Program inhibit
H
H
High impedance
L
L
Read
+5 V
+5 V
L
L
H
Data output
Output disable
L
H
High impedance
Standby
H
High impedance
Remark
= L or H
21
PD78P4908
Data Sheet U11681EJ2V0DS00
(1) Read mode
Set CE to L and OE to L to set read mode.
(2) Output disable mode
Set OE to H to set high impedance for data output and output disable mode.
Consequently, if several
PD78P4908 devices are connected to a data bus, the OE pins can be controlled to
select data output from any of the devices.
(3) Standby mode
Set CE to H to set standby mode.
In this mode, data output is set to high impedance regardless of the OE setting.
(4) Page data latch mode
At the beginning of page write mode, set CE to H, PGM to H, and OE to L to set page data latch mode.
In this mode, 1 page (4 bytes) of data are latched to the internal address/data latch circuit.
(5) Page write mode
After latching the address and data for one page (4 bytes) using page data latch mode, adding a 0.1 ms program
pulse (active, low) to the PGM pin with both CE and OE set to H causes page write to be executed. Later, setting
both CE and OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X
10).
(6) Byte write mode
Adding a 0.1 ms program pulse (active, low) to the PGM pin with setting CE to L and OE to H causes byte write
to be executed. Later, setting OE to L causes program verification to be executed.
If programming is not completed after one program pulse, the write and verify operations may be repeated X times
(where X
10).
(7) Program verify mode
Set CE to L, PGM to H, and OE to L to set program verify mode. Use verify mode for verification following each
write operation.
(8) Program inhibit mode
Program inhibit mode is used to write to a single device when several
PD78P4908 devices are connected in
parallel to OE , V
PP
, and D0 to D7 pins.
Use the page write mode or byte write mode described above for each write operation. Write operations cannot
be done for devices in which the PGM pin has been set to H.
22
PD78P4908
Data Sheet U11681EJ2V0DS00
6.2 PROM WRITE SEQUENCE
Figure 6-1. Page Program Mode Flowchart
Remark G = Start address
N = Program end address
Start
Address = G
V
DD
= +6.5 V, V
PP
= +12.5 V
X = 0
Latch
Address = Address + 1
Latch
Address = Address + 1
Latch
Address = Address + 1
0.1 ms program pulse
X = X + 1
Latch
No
X = 10 ?
Yes
Verify 4 bytes
Pass
Address = N ?
Yes
V
DD
= 4.0 to 5.5 V, V
PP
= V
DD
Verify all bytes
Pass
No
All pass
Write end
Fail
Defective
Address = Address + 1
Fail
23
PD78P4908
Data Sheet U11681EJ2V0DS00
Figure 6-2. Page Program Mode Timing
Page data latch
Hi-Z
Hi-Z
Page program
Program verify
Data input
Data output
A2-A16
A0, A1
D0-D7
V
PP
V
DD
V
PP
V
DD
+ 1.5
V
DD
V
IH
V
IL
OE
V
IH
V
IL
PGM
V
IH
V
IL
CE
V
DD
24
PD78P4908
Data Sheet U11681EJ2V0DS00
Figure 6-3. Byte Program Mode Flowchart
Remark G = Start address
N = Program end address
Start
Address = G
V
DD
= +6.5 V, V
PP
= +12.5 V
X
= 0
X
= X + 1
0.1 ms program pulse
Verify
Address = N ?
Write end
Defective
Verify all bytes
V
DD
= 4.0 to 5.5 V, V
PP
= V
DD
Address = Address + 1
Fail
Pass
Fail
All pass
Yes
X
= 10 ?
No
Yes
Pass
No
25
PD78P4908
Data Sheet U11681EJ2V0DS00
Figure 6-4. Byte Program Mode Timing
Cautions 1. Add V
DD
before V
PP
, and turn off the V
DD
after V
PP
.
2. Do not allow V
PP
to exceed 13.5 V including overshoot.
3. Reliability problems may result if the device is inserted or pulled out while 12.5 V is applied
at V
PP
.
Program
Hi-Z
Hi-Z
Hi-Z
Program verify
Data input
Data output
A0-A16
D0-D7
V
PP
V
DD
V
PP
V
DD
+ 1.5
V
DD
V
DD
V
IH
V
IL
CE
V
IH
V
IL
PGM
V
IH
V
IL
OE
26
PD78P4908
Data Sheet U11681EJ2V0DS00
6.3 PROM READ SEQUENCE
Follow this sequence to read the PROM contents to an external data bus (D0 to D7).
(1) Set the RESET pin to low level and add 5 V to the V
PP
pin. See 2. PIN CONFIGURATION (TOP VIEW) (2) PROM
programming mode with regard to handling of other, unused pins.
(2) Add 5 V to the V
DD
and V
PP
pins.
(3) Input the data address to be read to pins A0 to A16.
(4) Set read mode.
(5) Output the data to pins D0 to D7.
Figure 6-5 shows the timing of steps (2) to (5) above.
Figure 6-5. PROM Read Timing
7. SCREENING ONE-TIME PROM PRODUCTS
NEC cannot execute a complete test of one-time PROM products (
PD78P4908GF-3BA) due to their structure
before shipment. It is recommended that you screen (verify) PROM products after writing necessary data into them
and storing them at 125
C for 24 hours.
Address input
Data output
CE (input)
A0-A16
OE (input)
D0-D7
Hi-Z
Hi-Z
27
PD78P4908
Data Sheet U11681EJ2V0DS00
8. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (T
A
= 25
C)
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to
the product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
Remark Unless otherwise stated, the characteristics of a dual-function pin are the same as those of a port pin.
Parameter
Symbol
Conditions
Rating
Unit
Supply voltage
V
DD
0.3 to +7.0
V
AV
DD
0.3 to V
DD
+ 0.3
V
AV
SS
0.3 to +0.3
V
Input voltage
V
I1
For pins other than V
PP
, A9
0.3 to V
DD
+ 0.3
V
V
I2
V
PP
, A9
0.3 to +13.5
V
Analog input voltage
V
AN
AV
SS
0.3 to AV
REF1
+ 0.3
V
Output voltage
V
O
0.3 to V
DD
+ 0.3
V
Output low current
I
OL
One pin
10
mA
Total for the P00-P07, P30-
50
mA
P37, P54-P57, P60-P67, and
P100-P107 pins
Total for the P10-P17, P40-
50
mA
P47, P50-P53, P70-P77,
P90-P97, PWM0, PWM1,
and TX pins
Output high current
I
OH
One pin
6
mA
Total for the P00-P07, P30-
30
mA
P37, P54-P57, P60-P67, and
P100-P107 pins
Total for the P10-P17, P40-
30
mA
P47, P50-P53, P70-P77,
P90-P97, PWM0, PWM1,
and TX pins
A/D converter reference input
AV
REF1
0.3 to V
DD
+ 0.3
V
voltage
Operating ambient temperature
T
A
40 to +85
C
Storage temperature
T
stg
65 to +150
C
28
PD78P4908
Data Sheet U11681EJ2V0DS00
OPERATING CONDITIONS
Operating ambient temperature (T
A
): 40
C to +85
C
Power supply voltage and clock cycle time: See Figure 8-1.
Internal regulator operation selected (REGOFF pin: low level)
Figure 8-1. Power Supply Voltage and Clock Cycle Time
CAPACITANCE (T
A
= 25
C, V
DD
= V
SS
= 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
C
I
C
O
C
IO
Conditions
f = 1 MHz
0 V on pins other than measured pins
MIN.
TYP.
MAX.
15
15
15
Unit
pF
pF
pF
10,000
4,000
1,000
159
100
79
10
0
1
2
3
4
5
6
7
Guaran-
teed
opera-
ting
range
Power supply voltage [V]
Clock cycle time t
CYK
[ns]
29
PD78P4908
Data Sheet U11681EJ2V0DS00
MAIN OSCILLATOR CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= 4.0 to 5.5 V, V
SS
= 0 V)
Caution When using the clock generator, run wires according to the following rules to avoid effects such
as stray capacitance:
Minimize the wiring length.
Never cause the wires to cross other signal lines.
Never cause the wires to run near a line carrying a large varying current.
The grounding point of the capacitor of the oscillator circuit must always be the same potential
as V
SS1
. Never connect the capacitor to a ground pattern carrying a large current.
Never extract a signal from the oscillator.
Remark Connect a 12.582912 or 6.291456 MHz oscillator to operate the internal clock timer with the main clock.
CLOCK OSCILLATOR CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= 4.0 to 5.5 V, V
SS
= 0 V)
Parameter
Oscillator frequency
MIN.
2
MAX.
12.58
Unit
MHz
Conditions
Ceramic or crystal resonator
Parameter
Oscillator frequency
Oscillation settling time
Oscillation hold voltage
Watch timer operating
voltage
Symbol
f
XT
t
SXT
V
DDXT
V
DDW
Conditions
Ceramic or crystal resonator
V
DD
= 4.5 to 5.5 V
MIN.
32
4.0
4.0
TYP.
32.768
1.2
MAX.
35
2
10
5.5
5.5
Unit
kHz
s
s
V
V
Symbol
f
XX
30
PD78P4908
Data Sheet U11681EJ2V0DS00
DC CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, V
SS
= AV
SS
= 0 V) (1/2)
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3,
P107/SO3, XT1, XT2
2. P40/AD0-P47/AD7, P50/A8-P57/A15, P60/A16-P67/REFRQ/HLDAK, P00-P07
3. P00-P07
4. P10-P17, P40/AD0-P47/AD7, P50/A8-P57/A15
5. Other than pull-up resistors
Parameter
Input low voltage
Note 5
Input high voltage
Output low voltage
Output high voltage
Symbol
V
IL1
V
IL2
V
IL3
V
IH1
V
IH2
V
IH3
V
OL1
V
OL2
V
OH1
V
OH2
Conditions
For pins other than those described in
Notes 1 and 2
For pins described in Note 1
V
DD
= 4.5 to 5.5 V
For pins described in Note 2
For pins other than those described in
Notes 1 and 2
For pins described in Note 1
V
DD
= 4.5 to 5.5 V
For pins described in Note 2
I
OL
= 20
A
I
OL
= 100
A
I
OL
= 2 mA
I
OL
= 8 mA
For pins described in Note 4
V
DD
= 4.5 to 5.5 V
I
OH
= -20
A
I
OH
= -100
A
I
OH
= -2 mA
V
DD
= 4.5 to 5.5 V
I
OH
= -5 mA
For pins described in Note 3
MIN.
0.3
0.3
0.3
0.7 V
DD
0.8 V
DD
2.2
V
DD
0.1
V
DD
0.2
V
DD
1.0
V
DD
2.4
TYP.
MAX.
0.3 V
DD
0.2 V
DD
+0.8
V
DD
+ 0.3
V
DD
+ 0.3
V
DD
+ 0.3
0.1
0.2
0.4
1.0
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
31
PD78P4908
Data Sheet U11681EJ2V0DS00
DC CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, V
SS
= AV
SS
= 0 V) (2/2)
Note
These values are valid when the internal regulator is ON (REGOFF pin = low level). They do not include
the AV
DD
and AV
REF1
currents.
Parameter
Input leakage current
Output leakage current
V
DD
supply current
Note
Pull-up resistor
Symbol
I
LI1
I
LI2
I
LO
I
DD1
I
DD2
I
DD3
R
L
Conditions
0 V
V
I
V
DD
For pins other than
X1 and XT1
X1, XT1
0 V
V
O
V
DD
Operation mode
f
XX
= 12.58 MHz
V
DD
= 4.5 to 5.5 V
f
XX
= 6.29 MHz
V
DD
= 4.0 to 5.5 V
HALT mode
f
XX
= 12.58 MHz
V
DD
= 4.5 to 5.5 V
f
CLK
= f
XX
/8
(STBC = B1H)
Peripheral operation
stops.
f
XX
= 6.29 MHz
V
DD
= 4.0 to 5.5 V
f
CLK
= f
XX
/8
(STBC = 31H)
Peripheral operation
stops.
IDLE mode
f
XX
= 12.58 MHz
V
DD
= 4.5 to 5.5 V
f
XX
= 6.29 MHz
V
DD
= 4.0 to 5.5 V
V
I
= 0 V
MIN.
15
TYP.
20
10
5.2
2.6
2.4
1.8
MAX.
10
20
10
40
20
10.4
5.2
4.8
3.6
80
Unit
A
A
A
mA
mA
mA
mA
mA
mA
k
32
PD78P4908
Data Sheet U11681EJ2V0DS00
AC CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
(1) Read/write operation
Remark T:
t
CYK
(system clock cycle time) V
DD
= 5.0 V T = 79 ns (MIN.)
a:
1 during address wait, otherwise, 0
n:
Number of wait states (n
0)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Address setup time
(to ASTB
)
ASTB high-level width
Address hold time (to ASTB
)
Address hold time (to RD
)
Delay from address to RD
Address float time (to RD
)
Delay from address to data
input
Delay from ASTB
to data input
Delay from RD
to data input
Delay from ASTB
to RD
Data hold time (to RD
)
Delay from RD
to address
active
Delay from RD
to ASTB
RD low-level width
Delay from address
to WR
Address hold time (to WR
)
Delay from ASTB
to data
output
Delay from WR
to data output
Delay from ASTB
to WR
Data setup time (to WR
)
Data hold time (to WR
)
Delay from WR
to ASTB
WR low-level width
Symbol
t
SAST
t
WSTH
t
HSTLA
t
HRA
t
DAR
t
FRA
t
DAID
t
DSTID
t
DRID
t
DSTR
t
HRID
t
DRA
t
DRST
t
WRL
t
DAW
t
HWA
t
DSTOD
t
DWOD
t
DSTW
t
SODWR
t
HWOD
t
DWST
t
WWL
MIN.
29
23
21
26
74
0
31
0
38
31
94
74
26
31
99
26
31
94
MAX.
400
283
238
55
15
Conditions
V
DD
= 5.0 V
(0.5 + a)T 11
V
DD
= 5.0 V
(0.5 + a)T 17
V
DD
= 5.0 V
0.5T 19
V
DD
= 5.0 V
0.5T 14
V
DD
= 5.0 V
(1 + a)T 5
V
DD
= 5.0 V
(2.5 + a + n)T 37
V
DD
= 5.0 V
(2 + n)T 35
V
DD
= 5.0 V
(1.5 + n)T 40
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
0.5T 2
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
(1.5 + n)T 25
V
DD
= 5.0 V
(1 + a)T 5
V
DD
= 5.0 V
0.5T 14
V
DD
= 5.0 V
0.5T + 15
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
(1.5 + n)T 20
V
DD
= 5.0 V
0.5T 14
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
(1.5 + n)T 25
33
PD78P4908
Data Sheet U11681EJ2V0DS00
(2) External wait timing
Remark T:
t
CYK
(system clock cycle time) V
DD
= 5.0 V T = 79 ns (MIN.)
a:
1 during address wait, otherwise, 0
n:
Number of wait states (n
0)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Delay from address to WAIT
input
Delay from ASTB
to WAIT
input
Hold time from ASTB
to WAIT
Delay from ASTB
to WAIT
Delay from RD
to WAIT
input
Hold time from RD
to WAIT
Delay from RD
to WAIT
Delay from WAIT
to data
input
Delay from WAIT
to RD
Delay from WAIT
to WR
Delay from WR
to WAIT
input
Hold time from WR
to WAIT
Delay from WR
to WAIT
Symbol
t
DAWT
t
DSTWT
t
HSTWT
t
DSTWTH
t
DRWTL
t
HRWT
t
DRWTH
t
DWTID
t
DWTR
t
DWTW
t
DWWTL
t
HWWT
t
DWWTH
MIN.
124
84
40
40
84
MAX.
198
79
238
39
198
35
39
198
Conditions
V
DD
= 5.0 V
(2 + a)T 40
V
DD
= 5.0 V
1.5T 40
V
DD
= 5.0 V
(0.5 + n)T + 5
V
DD
= 5.0 V
(1.5 + n)T 40
V
DD
= 5.0 V
T 40
V
DD
= 5.0 V
nT + 5
V
DD
= 5.0 V
(1 + n)T 40
V
DD
= 5.0 V
0.5T 5
V
DD
= 5.0 V
0.5T
V
DD
= 5.0 V
0.5T
V
DD
= 5.0 V
T 40
V
DD
= 5.0 V
nT + 5
V
DD
= 5.0 V
(1 + n)T 40
34
PD78P4908
Data Sheet U11681EJ2V0DS00
(3) Bus hold timing
Remark T:
t
CYK
(system clock cycle time) V
DD
= 5.0 V T = 79 ns (MIN.)
a:
1 during address wait, otherwise, 0
n:
Number of wait states (n
0)
(4) Refresh timing
Remark T: t
CYK
(system clock cycle time) V
DD
= 5.0 V T = 79 ns (MIN.)
Unit
ns
ns
ns
ns
ns
Parameter
Delay from HLDRQ
to float
Delay from HLDRQ
to HLDAK
Delay from float to HLDAK
Delay from HLDRQ
to HLDAK
Delay from HLDRQ
to active
Symbol
t
FHQC
t
DHQHHAH
t
DCFHA
t
DHQLHAL
t
DHAC
MIN.
59
MAX.
765
825
109
199
Conditions
V
DD
= 5.0 V
(2 + 4 + a + n)T + 50
V
DD
= 5.0 V
(3 + 4 + a + n)T + 30
V
DD
= 5.0 V
T + 30
V
DD
= 5.0 V
2T + 40
V
DD
= 5.0 V
T 20
Unit
ns
ns
ns
ns
ns
ns
ns
Parameter
Random read/write cycle time
REFRQ low-level pulse width
Delay from ASTB
to REFRQ
Delay from RD
to REFRQ
Delay from WR
to REFRQ
Delay from REFRQ
to ASTB
REFRQ high-level pulse width
Symbol
t
RC
t
WRFQL
t
DSTRFQ
t
DRRFQ
t
DWRFQ
t
DRFQST
t
WRFQH
MIN.
238
94
31
110
110
31
94
MAX.
Conditions
V
DD
= 5.0 V
3T
V
DD
= 5.0 V
1.5T 25
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
1.5T 9
V
DD
= 5.0 V
1.5T 9
V
DD
= 5.0 V
0.5T 9
V
DD
= 5.0 V
1.5T 25
35
PD78P4908
Data Sheet U11681EJ2V0DS00
SERIAL OPERATION (T
A
= 40
C to +85
C, V
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
(1) CSI, CSI3
Remarks 1. The values in this table are those when f
XX
= 12.58 MHz, C
L
is 100 pF.
2. f
CLK
:
System clock frequency (selectable from f
XX
, f
XX
/2, f
XX
/4, and f
XX
/8 by the standby control
register (STBC))
3. f
XX
:
Oscillation frequency (f
XX
= 12.58 MHz or f
XX
= 6.29 MHz)
Unit
ns
ns
ns
ns
ns
s
ns
s
ns
ns
ns
ns
ns
ns
ns
Symbol
t
CYSK0
t
WSKL0
t
WSKH0
t
SSSK0
t
HSSK0
t
DSBSK1
t
DSBSK2
t
HSBSK
MIN.
8/f
XX
4/f
CLK
8/f
XX
16/f
XX
4/f
XX
40
2/f
CLK
40
4/f
XX
40
8/f
XX
40
4/f
XX
40
2/f
CLK
40
4/f
XX
40
8/f
XX
40
80
1/f
CLK
+ 80
80
0
0
0
0
0.5t
CYSK0
40
MAX.
1/f
CLK
+ 150
150
1/f
CLK
+ 400
400
Conditions
Input
f
CLK
= f
XX
Other than f
CLK
= f
XX
Output
Other than f
CLK
= f
XX
/8
f
CLK
= f
XX
/8
Input
f
CLK
= f
XX
Other than f
CLK
= f
XX
Output
Other than f
CLK
= f
XX
/8
f
CLK
= f
XX
/8
Input
f
CLK
= f
XX
Other than f
CLK
= f
XX
Output
Other than f
CLK
= f
XX
/8
f
CLK
= f
XX
/8
External clock
Internal clock
CMOS push-pull output
External clock
Internal clock
Open-drain output
External clock
R
L
= 1 k
Internal clock
When data is transferred
Parameter
Serial clock cycle time
(SCK0, SCK3)
Serial clock low-level width
(SCK0, SCK3)
Serial clock high-level width
(SCK0, SCK3)
Setup time for SI0, SI3
(to SCK0, SCK3
)
Hold time for SI0, SI3
(to SCK0, SCK3
)
Output delay time for SO0,
SO3 (to SCK0, SCK3
)
Output hold time for SO0,
SO3 (to SCK0, SCK3
)
36
PD78P4908
Data Sheet U11681EJ2V0DS00
(2) IOE1, IOE2 (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Remarks 1. The values in this table are those when C
L
is 100 pF.
2. T: Serial clock cycle set by software. The minimum value is 8/f
XX
.
(3) UART, UART2 (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Parameter
Serial clock cycle time
(SCK1, SCK2)
Serial clock low-level width
(SCK1, SCK2)
Serial clock high-level width
(SCK1, SCK2)
Setup time for SI1 and SI2
(to SCK1, SCK2
)
Hold time for SI1 and SI2
(to SCK1, SCK2
)
Output delay time for SO1 and
SO2 (to SCK1, SCK2
)
Output hold time for SO1 and
SO2 (to SCK1, SCK2
)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MIN.
640
1,280
T
280
600
0.5T 40
280
600
0.5T 40
40
40
0
0.5t
CYSK1
40
MAX.
50
Symbol
t
CYSK1
t
WSKL1
t
WSKH1
t
SSSK1
t
HSSK1
t
DSOSK
t
HSOSK
Conditions
Input
V
DD
= 4.5 to 5.5 V
Output
Internal, divided by 8
Input
V
DD
= 4.5 to 5.5 V
Output
Internal, divided by 8
Input
V
DD
= 4.5 to 5.5 V
Output
Internal, divided by 8
When data is transferred
Unit
ns
ns
ns
ns
ns
ns
Parameter
ASCK clock input cycle time
ASCK clock low-level width
ASCK clock high-level width
Symbol
t
CYASK
t
WASKL
t
WASKH
MIN.
160
320
65
120
65
120
MAX.
Conditions
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
V
DD
= 4.5 to 5.5 V
37
PD78P4908
Data Sheet U11681EJ2V0DS00
CLOCK OUTPUT OPERATION (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Remark n:
Dividing ratio set by software in the CPU (n = 1, 2, 4, 8, and 16)
T:
t
CYK
(system clock cycle time)
OTHER OPERATIONS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Note
Use the RESET low-level width to ensure the lapse of the oscillation settling time when the power is applied.
Remark t
CYSMP
: Sampling clock set by software
t
CYCPU
: CPU operation clock set by software in the CPU
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
CLKOUT cycle time
CLKOUT low-level width
CLKOUT high-level width
CLKOUT rise time
CLKOUT fall time
Symbol
t
CYCL
t
CLL
t
CLH
t
CLR
t
CLF
MIN.
79
30
20
30
20
MAX.
32,000
10
20
10
20
Conditions
nT
V
DD
= 4.5 to 5.5 V, 0.5T 10
0.5T 20
V
DD
= 4.5 to 5.5 V, 0.5T 10
0.5T 20
4.5 V
V
DD
< 5.5 V
4.0 V
V
DD
< 4.5 V
4.5 V
V
DD
< 5.5 V
4.0 V
V
DD
< 4.5 V
Unit
s
s
ns
ns
ns
ns
s
s
s
s
Parameter
NMI low-level width
NMI high-level width
INTP0 low-level width
INTP0 high-level width
Low-level width for INTP1-
INTP3 and CI
High-level width for INTP1-
INTP3 and CI
Low-level width for INTP4 and
INTP5
High-level width for INTP4 and
INTP5
RESET low-level width
Note
RESET high-level width
Symbol
t
WNIL
t
WNIH
t
WIT0L
t
WIT0H
t
WIT1L
t
WIT1H
t
WIT2L
t
WIT2H
t
WRSL
t
WRSH
MIN.
10
10
4 t
CYSMP
4 t
CYSMP
4 t
CYCPU
4 t
CYCPU
10
10
10
10
MAX.
Conditions
38
PD78P4908
Data Sheet U11681EJ2V0DS00
A/D CONVERTER CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= AV
REF1
= 4.0 to 5.5 V, AV
SS
= V
SS
= 0 V)
Note
Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.
Caution To execute the conversion by the A/D converter set port 7, multiplexed with the A/D input lines,
to output mode to prevent data from being inverted.
Remark f
CLK
: System clock frequency (selectable from f
XX
, f
XX
/2, f
XX
/4, and f
XX
/8 by the standby control register
(STBC))
IEBus CONTROLLER CHARACTERISTICS (T
A
= 40
C to +85
C, V
DD
= AV
DD
= AV
REF1
= 4.5 to 5.5 V, AV
SS
= V
SS
= 0 V)
Notes 1. The value conforms to the IEBus standard. The IEBus controller is operable within the range of the
oscillator frequency of oscillator characteristics.
2. The value is measured when IEBus system clock: f
X
= 6.29 MHz.
3. C
L
is the load capacitance of TX output line.
Conditions
IEAD = 00H
FR = 0
FR = 1
IEAD = 01H
V
DD
= 4.5 to 5.5 V
FR = 1 120/f
CLK
FR = 0 240/f
CLK
FR = 1 18/f
CLK
FR = 0 36/f
CLK
CS = 1
CS = 0, STOP mode
MIN.
8
9.5
19.1
1.4
2.9
3
TYP.
1
1,000
10
2.0
1.0
MAX.
0.6
1.5
2.2
1/2
480
960
72
144
5.0
20
Symbol
t
CONV
t
SAMP
R
AN
R
REF1
AI
DD1
AI
DD2
Parameter
Resolution
Total error
Note
Quantization error
Conversion time
Sampling time
Analog input impedance
AV
REF1
impedance
AV
DD
power supply
voltage
Unit
bit
%
%
%
LSB
s
s
s
s
M
k
mA
A
Conditions
Transfer speed: mode 1
C
L
= 50 pF
Note 3
MIN.
6.20
TYP.
6.29
MAX.
6.39
1.5
0.7
0.85
Symbol
f
S
t
DTX
t
DRX
t
DBUS
Parameter
IEBus standard
frequency
Note 1
Driver delay time (delay from
TX output to bus line)
Note 2
Receiver delay time
(delay from bus line to
RX output)
Note 2
Transmission delay on
bus
Note 2
Unit
MHz
s
s
s
39
PD78P4908
Data Sheet U11681EJ2V0DS00
DATA RETENTION CHARACTERISTICS (T
A
= 40
C to +85
C)
Notes 1. Valid when input voltages to the pins described in Note 2 satisfy V
IL
or V
IH
in the above table.
2. RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0, P33/SO0, P105/SCK3, P106/SI3, and
P107/SO3 pins
AC TIMING TEST POINTS
Parameter
Data retention voltage
Data retention current
V
DD
rise time
V
DD
fall time
V
DD
hold time
(to STOP mode setting)
STOP clear signal input time
Oscillation settling time
Input low voltage
Input high voltage
Conditions
STOP mode
STOP mode
V
DDDR
= 2.5 V, AV
REF
=
0 V
Note 1
V
DDDR
= 4.0 to 5.5 V,
AV
REF1
= 0 V
Note 1
Crystal resonator
Ceramic resonator
Specific pins
Note 2
MIN.
2.5
200
200
0
0
30
5
0
0.9 V
DDDR
TYP.
2
10
MAX.
5.5
10
50
0.1 V
DDDR
V
DDDR
Unit
V
A
A
s
s
ms
ms
ms
ms
V
V
Symbol
V
DDDR
I
DDDR
t
RVD
t
FVD
t
HVD
t
DREL
t
WAIT
V
IL
V
IH
0.8 V
DD
or 2.2 V
0.8 V
0.8 V
DD
or 2.2 V
0.8 V
Test points
V
DD
1 V
0.45 V
40
PD78P4908
Data Sheet U11681EJ2V0DS00
TIMING WAVEFORM
(1) Read operation
(2) Write operation
ASTB
A8-A19
AD0-AD7
RD
t
WSTH
t
SAST
t
DSTID
t
HSTLA
t
DRST
t
FRA
t
DRID
t
DAR
t
WRL
t
DSTR
t
DAID
t
HRA
t
DRA
t
HRID
ASTB
A8-A19
AD0-AD7
WR
t
WSTH
t
SAST
t
HSTLA
t
DWST
t
DAW
t
DSTW
t
HWOD
t
DSTOD
t
DWOD
t
SODWR
t
WWL
t
HWA
41
PD78P4908
Data Sheet U11681EJ2V0DS00
HOLD TIMING
EXTERNAL WAIT SIGNAL INPUT TIMING
(1) Read operation
(2) Write operation
HLDRQ
HLDAK
t
DHQHHAH
t
FHQC
t
DCFHA
t
DHAC
t
DHQLHAL
ASTB, A8-A19,
AD0-AD7, RD, WR
ASTB
A8-A19
AD0-AD7
RD
WAIT
t
DSTWT
t
HSTWTH
t
DSTWTH
t
DAWT
t
DWTID
t
DWTR
t
DRWTL
t
HRWT
t
DRWTH
ASTB
A8-A19
AD0-AD7
WR
WAIT
t
DSTWT
t
HSTWTH
t
DSTWTH
t
DAWT
t
DWTW
t
DWWTL
t
HWWT
t
DWWTH
42
PD78P4908
Data Sheet U11681EJ2V0DS00
REFRESH TIMING WAVEFORM
(1) Random read/write cycle
(2) When refresh memory is accessed for a read and write at the same time
(3) Refresh after a read
(4) Refresh after a write
ASTB
WR
RD
t
RC
t
RC
t
RC
t
RC
t
RC
t
WRFQL
ASTB
RD, WR
REFRQ
t
DSTRFQ
t
DRFQST
t
WRFQH
ASTB
RD
REFRQ
t
DRFQST
t
DRRFQ
t
WRFQL
ASTB
WR
REFRQ
t
DRFQST
t
DWRFQ
t
WRFQL
43
PD78P4908
Data Sheet U11681EJ2V0DS00
SERIAL OPERATION (CSI, CSI3)
SERIAL OPERATION (IOE1, IOE2)
SERIAL OPERATION (UART, UART2)
CLOCK OUTPUT TIMING
SCK0, SCK3
SI0, SI3
SO0, SO3
Output data
Input data
t
SSSK0
t
HSSK0
t
DSBSK1
t
WSKL0
t
WSKH0
t
HSBSK1
t
CYSK0
SCK1, SCK2
SI1, SI2
SO1, SO2
Output data
Input data
t
SSSK1
t
HSSK1
t
DSOSK
t
HSOSK
t
WSKL1
t
WSKH1
t
CYSK1
ASCK,
ASCK2
t
WASKH
t
WASKL
t
CYASK
CLKOUT
t
CLH
t
CLL
t
CYCL
t
CLF
t
CLR
44
PD78P4908
Data Sheet U11681EJ2V0DS00
INTERRUPT REQUEST INPUT TIMING
RESET INPUT TIMING
NMI
INTP0
CI,
INTP1-INTP3
INTP4, INTP5
t
WNIH
t
WNIL
t
WIT0H
t
WIT0L
t
WIT1H
t
WIT1L
t
WIT2H
t
WIT2L
RESET
t
WRSH
t
WRSL
45
PD78P4908
Data Sheet U11681EJ2V0DS00
EXTERNAL CLOCK TIMING
DATA RETENTION CHARACTERISTICS
X1
t
WXH
t
WXL
t
CYX
t
XF
t
XR
V
DD
RESET
NMI
(Clearing by falling edge)
NMI
(Clearing by rising edge)
t
HVD
t
FVD
t
RVD
t
DREL
V
DDDR
STOP mode setting
t
WAIT
46
PD78P4908
Data Sheet U11681EJ2V0DS00
DC PROGRAMMING CHARACTERISTICS (T
A
= 25
C
5
C, V
SS
= 0 V)
Notes 1. Symbols for the corresponding
PD27C1001A
2. The V
DDP
represents the V
DD
pin as viewed in the programming mode.
Parameter
High-level input
voltage
Low-level input
voltage
Input leakage current
High-level output
voltage
Low-level output
voltage
Output leakage
current
V
DDP
supply voltage
V
PP
supply voltage
V
DDP
supply current
V
PP
supply current
Symbol
V
IH
V
IL
I
LIP
V
OH
V
OL
I
LO
V
DDP
V
PP
I
DD
I
PP
Symbol
Note 1
V
IH
V
IL
I
LI
V
OH
V
OL
V
CC
V
PP
I
DD
I
PP
MIN.
2.2
0.3
2.4
6.25
4.5
12.2
TYP.
6.5
5.0
12.5
10
10
5
1.0
MAX.
V
DDP
+ 0.3
+0.8
10
0.45
10
6.75
5.5
12.8
40
40
50
100
Unit
V
V
A
V
V
A
V
V
V
V
mA
mA
mA
A
Conditions
0
V
I
V
DDP
Note 2
I
OH
= 400
A
I
OL
= 2.1 mA
0
V
O
V
DDP
, OE = V
IH
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
Program memory write mode
Program memory read mode
V
PP
= V
DDP
47
PD78P4908
Data Sheet U11681EJ2V0DS00
AC PROGRAMMING CHARACTERISTICS (T
A
= 25
C
5
C, V
SS
= 0 V)
PROM Write Mode (Page Program Mode)
Notes 1. These symbols (except t
VDS
) correspond to those of the corresponding
PD27C1001A.
2. For
PD27C1001A, read t
VDS
as t
VCS
.
Parameter
Address setup time
CE set time
Input data setup time
Address hold time
Input data hold time
Output data hold time
V
PP
setup time
V
DDP
setup time
Initial program pulse width
OE set time
Valid data delay time from OE
OE pulse width in the data latch
PGM setup time
CE hold time
OE hold time
Symbol
Note 1
t
AS
t
CES
t
DS
t
AH
t
AHL
t
AHV
t
DH
t
DF
t
VPS
t
VDS
Note 2
t
PW
t
OES
t
OE
t
LW
t
PGMS
t
CEH
t
OEH
MIN.
2
2
2
2
2
0
2
0
2
2
0.095
2
1
2
2
2
TYP.
0.1
1
MAX.
130
0.105
2
s
s
s
s
s
s
s
ns
s
s
ms
s
ns
s
s
s
s
Conditions
Unit
48
PD78P4908
Data Sheet U11681EJ2V0DS00
PROM Write Mode (Byte Program Mode)
Notes 1. These symbols (except t
VDS
) correspond to those of the corresponding
PD27C1001A.
2. For
PD27C1001A, read t
VDS
as t
VCS
.
PROM Read Mode
Notes 1. These symbols correspond to those of the corresponding
PD27C1001A.
2. t
DF
is the time measured from when either OE or CE reaches V
IH
, whichever is faster.
Parameter
Address setup time
CE set time
Input data setup time
Address hold time
Input data hold time
Output data hold time
V
PP
setup time
V
DDP
setup time
Initial program pulse width
OE set time
Valid data delay time from OE
Symbol
Note 1
t
AS
t
CES
t
DS
t
AH
t
DH
t
DF
t
VPS
t
VDS
Note 2
t
PW
t
OES
t
OE
Symbol
Note 1
t
ACC
t
CE
t
OE
t
DF
t
OH
s
s
s
s
s
ns
s
s
ms
s
ns
Conditions
MAX.
130
0.105
2
TYP.
0.1
1
MIN.
2
2
2
2
2
0
2
2
0.095
2
TYP.
1
1
MIN.
0
0
CE = OE = V
IL
OE = V
IL
CE = V
IL
CE = V
IL
or OE = V
IL
CE = OE = V
IL
Conditions
Parameter
Data output time from address
Delay from CE
to data output
Delay from OE
to data output
Data hold time to OE
or CE
Note 2
Data hold time to address
Unit
ns
s
s
ns
ns
MAX.
200
2
2
60
Unit
49
PD78P4908
Data Sheet U11681EJ2V0DS00
PROM Write Mode Timing (Page Program Mode)
Page data latch
Page program
Program verify
Data
output
Hi-Z
Hi-Z
Hi-Z
A2-A16
A0, A1
D0-D7
V
PP
V
DDP
V
PP
V
DDP
+ 1.5
V
DDP
V
DDP
CE
PGM
OE
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
t
AS
t
AHL
t
DS
t
DH
t
VPS
Data input
t
PGMS
t
OE
t
VDS
t
AHV
t
DF
t
AH
t
OEH
t
CES
t
CEH
t
PW
t
OES
t
LW
50
PD78P4908
Data Sheet U11681EJ2V0DS00
PROM Write Mode Timing (Byte Program Mode)
Cautions 1. V
DDP
must be applied before V
PP
, and must be cut after V
PP
.
2. V
PP
including overshoot must not exceed 13.5 V.
3. Plugging in or out the board with the V
PP
pin supplied with 12.5 V may adversely affect its
reliability.
PROM Read Mode Timing
Notes 1. For reading within t
ACC
, the delay of the OE input from falling edge of CE must be within t
ACC
-t
OE
.
2. t
DF
is the time measured from when either OE or CE reaches V
IH
, whichever is faster.
Program
Program verify
A0-A16
V
PP
V
DDP
V
PP
V
DDP
+ 1.5
V
DDP
V
DDP
CE
PGM
V
IH
V
IL
V
IH
V
IL
t
DS
t
PW
Hi-Z
Hi-Z
Hi-Z
D0-D7
V
IH
V
IL
t
AS
t
DS
t
VPS
t
VDS
t
CES
t
DF
t
AH
t
DH
t
OES
t
OE
Data input
Data output
OE
A0-A16
CE
OE
Hi-Z
Hi-Z
D0-D7
Data output
t
CE
Valid address
t
ACC
Note 1
t
OH
t
OE
Note 1
t
DF
Note 2
51
PD78P4908
Data Sheet U11681EJ2V0DS00
9. PACKAGE DRAWING
Remark The shape and material of the ES version are the same
as those of the corresponding mass-produced product.
100PIN PLASTIC QFP (14x20)
ITEM
MILLIMETERS
INCHES
NOTE
Each lead centerline is located within 0.15 mm (0.006 inch) of
its true position (T.P.) at maximum material condition.
P100GF-65-3BA1-3
B
20.0
0.2
0.795+0.009
0.008
C
14.0
0.2
0.551+0.009
0.008
D
17.6
0.4
0.693
0.016
F
0.8
0.031
G
0.6
0.024
H
0.30
0.10
0.012
I
0.15
0.006
J
0.65 (T.P.)
0.026 (T.P.)
K
1.8
0.2
0.071+0.008
0.009
L
0.8
0.2
0.031
N
0.10
0.004
Q
0.1
0.1
0.004
0.004
S
3.0 MAX.
0.119 MAX.
detail of lead end
R
Q
J
K
M
L
N
P
G
F
H
I
M
P
2.7
0.1
0.106+0.005
0.004
80
81
50
100
1
31
30
51
B
A
C D
S
A
23.6
0.4
0.929
0.016
M
0.15
0.006
+0.10
0.05
R
5
5
5
5
+0.004
0.005
+0.009
0.008
+0.004
0.003
52
PD78P4908
Data Sheet U11681EJ2V0DS00
10. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the
PD78P4908.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 10-1. Soldering Conditions for Surface-Mount Devices
PD78P4908GF-3BA: 100-pin plastic QFP (14
20 mm)
Note
Maximum number of days during which the product can be stored at a temperature of 25
C and a relative
humidity of 65% or less after dry-pack package is opened.
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
Soldering process
Infrared ray reflow
VPS
Wave soldering
Partial heating method
Symbol
IR35-207-2
VP15-207-2
WS60-207-1
Soldering conditions
Peak package's surface temperature: 235
C
Reflow time: 30 seconds or less (210
C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
Note
(20 hours of pre-baking is required at 125
C
afterward)
Peak package's surface temperature: 215
C
Reflow time: 40 seconds or less (200
C or more)
Maximum allowable number of reflow processes: 2
Exposure limit: 7 days
Note
(20 hours of pre-baking is required at 125
C
afterward)
Solder temperature: 260
C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature: 120
C MAX. (measured on the package
surface)
Exposure limit: 7 days
Note
(20 hours of pre-baking is required at 125
C
afterward)
Terminal temperature: 300
C or less
Heat time: 3 seconds or less (for one side of a device)
53
PD78P4908
Data Sheet U11681EJ2V0DS00
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the
PD78P4908.
See also (5) Notes on using development tools.
(1) Language processing software
RA78K4
Assembler package for all 78K/IV series models
CC78K4
C compiler package for all 78K/IV series models
DF784908
Device file for
PD784908 subseries models
CC78K4-L
C compiler library source file for all 78K/IV series models
(2) PROM write tools
PG-1500
PROM programmer
PA-78P4908GF
Programmer adapter, connects to PG-1500
PG-1500 controller
Control program for PG-1500
(3) Debugging tools
When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS
In-circuit emulator for all 78K/IV series models
IE-70000-MC-PS-B
Power supply unit for IE-78K4-NS
IE-70000-98-IF-C
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine (C bus compatible)
IE-70000-CD-IF-A
PC card and interface cable when a notebook is used as the host machine
(PCMCIA socket compatible)
IE-70000-PC-IF-C
Interface adapter when the IBM PC/AT
TM
compatible is used as the host
machine (ISA compatible)
IE-7000-PCI-IF
Adapter when a computer with a PCI bus as the host machine
IE-784908-NS-EM1
Note
Emulation board for evaluating
PD784908 subseries models
NP-100GF
Note
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket for mounting on target system board made for 100-pin plastic QFP
(GF-3BA type). Used in LCC mode.
ID78K4-NS
Integrated debugger for IE-78K4-NS
SM78K4
System simulator for all 78K/IV series models
DF784908
Device file for
PD784908 subseries models
Note
Under development
54
PD78P4908
Data Sheet U11681EJ2V0DS00
When using the in-circuit emulator IE-784000-R
IE-784000-R
In-circuit emulator for all 78K/IV series models
IE-70000-98-IF-C
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine (C bus compatible)
IE-70000-PC-IF-C
Interface adapter when the IBM PC/AT compatible is used as the host
machine (ISA bus compatible)
IE-7000-PCI-IF
Adapter when a computer with a PCI bus as the host machine
IE-78000-R-SV3
Interface adapter and cable when the EWS is used as the host machine
IE-784908-NS-EM1
Emulation board for evaluating
PD784908 subseries models
IE-784908-R-EM1
IE-784000-R-EM
Emulation board for all 78K/IV series models
IE-78K4-R-EX2
Conversion board for emulation probes required to use the IE-784908-NS-
EM1 on the IE-784000-R. The board is not needed when the conventional
product IE-784908-R-EM1 is used.
EP-78064-GF-R
Emulation probe for 100-pin plastic QFP (GF-3BA type)
EV-9200GF-100
Socket for mounting on target system board made for 100-pin plastic QFP
(GF-3BA type)
ID78K4
Integrated debugger for IE-784000-R
SM78K4
System simulator for all 78K/IV series models
DF784908
Device file for
PD784908 subseries models
(4) Real-time OS
RX78K/IV
Real-time OS for 78K/IV series models
MX78K4
OS for 78K/IV series models
55
PD78P4908
Data Sheet U11681EJ2V0DS00
(5) Notes when using development tools
The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784908.
The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784908.
The NP-100GF is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales
representative for purchasing.
The host machines and operating systems corresponding to each software are shown below.
Host machine
PC
EWS
[OS]
PC-9800 series [Windows
TM
]
HP9000 series 700
TM
[HP-UX
TM
]
IBM PC/AT compatibles [Windows]
SPARCstation
TM
[SunOS
TM
,
Solaris
TM
]
Software
NEWS
TM
(RISC) [NEWS-OS
TM
]
RA78K4
Note
CC78K4
Note
PG-1500 controller
Note
ID78K4-NS
ID78K4
SM78K4
RX78K/IV
Note
MX78K4
Note
Note Software under MS-DOS
56
PD78P4908
Data Sheet U11681EJ2V0DS00
APPENDIX B CONVERSION SOCKET (EV-9200GF-100) PACKAGE DRAWING
Connect the
PD78P4908GF-3BA (100-pin plastic QFP (14
20 mm)) to the circuit board in combination with the
EV-9200GF-100.
Figure B-1. Package Drawings of EV-9200GF-100 (Reference)
EV-9200GF-100
A
D
E
B
F
1
No.1 pin index
M
N
O
L
K
S
R
Q
I
H
G
P
C
J
EV-9200GF-100-G0
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
L
M
N
O
P
Q
R
S
24.6
21
15
18.6
4-C 2
0.8
12.0
22.6
25.3
6.0
16.6
19.3
8.2
8.0
2.5
2.0
0.35
2.3
1.5
0.969
0.827
0.591
0.732
4-C 0.079
0.031
0.472
0.89
0.996
0.236
0.654
076
0.323
0.315
0.098
0.079
0.014
0.091
0.059
57
PD78P4908
Data Sheet U11681EJ2V0DS00
Figure B-2. Recommended Pattern to Mount EV-9200GF-100 on a Substrate (Reference)
F
H
E
D
A
B
C
I
J
K
L
0.026
1.142=0.742
0.026
0.748=0.486
EV-9200GF-100-P1E
ITEM
MILLIMETERS
INCHES
A
B
C
D
E
F
G
H
I
J
K
L
26.3
21.6
15.6
20.3
12
0.05
6
0.05
0.35
0.02
2.36
0.03
2.3
1.57
0.03
1.035
0.85
0.614
0.799
0.472
0.236
0.014
0.093
0.091
0.062
0.65
0.02
29=18.85
0.05
0.65
0.02
19=12.35
0.05
+0.001
0.002
+0.002
0.002
+0.001
0.002
+0.003
0.002
+0.003
0.002
+0.003
0.002
+0.001
0.001
+0.001
0.002
+0.001
0.002
G
Dimensions of mount pad for EV-9200 and that for target
device (QFP) may be different in some parts. For the
recommended mount pad dimensions for QFP, refer to
"SEMICONDUCTOR DEVICE MOUNTING
TECHNOLOGY MANUAL" (C10535E).
Caution
58
PD78P4908
Data Sheet U11681EJ2V0DS00
APPENDIX C RELATED DOCUMENTS
Documents Related to Devices
Document name
Document No.
Japanese
English
PD784907, 784908 Data Sheet
U11680J
U11680E
PD78P4908 Data Sheet
U11681J
This document
PD784908 Subseries User's Manual Hardware
U11787J
U11787E
PD784908 Subseries Special Function Registers
U11589J
--
78K/IV Series User's Manual Instruction
U10905J
U10905E
78K/IV Series Instruction Table
U10594J
--
78K/IV Series Instruction Set
U10595J
--
78K/IV Series Application Note Software Basic
U10095J
U10095E
Documents Related to Development Tools (User's Manual)
Document name
Document No.
Japanese
English
RA78K4 Assembler Package
Operation
U11334J
U11334E
Language
U11162J
U11162E
RA78K Series Structured Assembler Preprocessor
U11743J
U11743E
CC78K4 C Compiler
Operation
U11572J
U11572E
Language
U11571J
U11571E
PG-1500 PROM Programmer
U11940J
U11940E
PG-1500 Controller PC-9800 Series (MS-DOS
TM
) Base
EEU-704
EEU-1291
PG-1500 Controller IBM PC Series (PC DOS
TM
) Base
EEU-5008
U10540E
IE-78K4-NS
U13356J
U13356E
IE-784000-R
U12903J
U12903E
IE-784908-R-EM1
U11876J
--
IE-784908-NS-EM1
U13743J
On preparation
EP-78064
EEU-934
EEU-1469
SM78K4 System Simulator Windows Base
Reference
U10093J
U10093E
SM78K Series System Simulator
External Part User Open
U10092J
U10092E
Interface Specifications
ID78K4-NS Integrated Debugger PC Base
Reference
U12796J
U12796E
ID78K4 Integrated Debugger Windows Base
Reference
U10440J
U10440E
ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Base Reference
U11960J
U11960E
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
59
PD78P4908
Data Sheet U11681EJ2V0DS00
Documents Related to Software to Be Incorporated into the Product (User's Manual)
Document name
Document No.
Japanese
English
78K/IV Series Real-Time OS
Fundamental
U10603J
U10603E
Installation
U10604J
U10604E
Debugger
U10364J
--
OS for 78K/IV Series MX78K4
Fundamental
U11779J
--
Other Documents
Document name
Document No.
Japanese
English
NEC IC Package Manual (CD-ROM)
C13388E
Semiconductor Device Mounting Technology Manual
C10535J
C10535E
Quality Grades on NEC Semiconductor Device
C11531J
C11531E
NEC Semiconductor Device Reliability/Quality Control System
C10983J
C10983E
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
C11892J
C11892E
Guide to Quality Assurance for Semiconductor Devices
--
MEI-1202
Guide for Products Related to Microcomputer: Other Companies
U11416J
--
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
60
PD78P4908
Data Sheet U11681EJ2V0DS00
[MEMO]
61
PD78P4908
Data Sheet U11681EJ2V0DS00
[MEMO]
62
PD78P4908
Data Sheet U11681EJ2V0DS00
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconduc-
tor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
63
PD78P4908
Data Sheet U11681EJ2V0DS00
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
Fax: 408-588-6130
800-729-9288
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
Fax: 65-250-3583
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
Tel: 91-504-2787
Fax: 91-504-2860
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
J99.1
PD78P4908
Some related documents may be preliminary versions. Note that, however, what documents are preliminary is not indicated
in this document.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
Solaris and SunOS are trademarks of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
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