1996

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75P4308

The

PD75P4308 replaces the

PD754304's internal mask ROM with a one-time PROM and features expanded

ROM capacity.

Because the

PD75P4308 supports programming by users, it is suitable for use in prototype testing for system

development using the

PD754302 and 754304 products, and for use in small-lot production.

Detailed descriptions of functions are provided in the following document. Be sure to read the document

before designing.

PD754304 User's Manual: U10123E

FEATURES

Compatible with

PD754304

Memory capacity:

· PROM : 8192

8 bits

· RAM

: 256

4 bits

Can operate in the same power supply voltage as the mask version

PD754304

· V

= 1.8 to 5.5 V

Adopts a compact shrink SOP package

ORDERING INFORMATION

Part Number

Package

PD75P4308GS

36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)

Caution On-chip pull-up resistors by mask option are not provided.

4-BIT SINGLE-CHIP MICROCONTROLLER

The information in this document is subject to change without notice.

Document No. U10909EJ2V0DS00 (2nd edition)
Date Published January 1997 N
Printed in Japan

The mark

shows major revised points.

PD75P4308

OVERVIEW OF FUNCTIONS

Item Function

Instruction execution time · 0.95, 1.91, 3.81, or 15.3

s (system clock: @ 4.19 MHz)

· 0.67, 1.33, 2.67, or 10.7

s (system clock: @ 6.0 MHz)

Internal memory PROM 8192

8 bits

RAM 256

4 bits

General-purpose register · 4-bit manipulation: 8 registers

4 banks

· 8-bit manipulation: 4 registers

8 banks

I/O ports CMOS input 8 Connection of on-chip pull-up resistors can be specified by software: 7

CMOS I/O 18 Connection of on-chip pull-up resistors can be specified by software: 18

N-ch open-drain I/O 4 13-V withstand voltage

Total 30

Timers 3 channels

· 8-bit timer/event counter: 2 channels

(Can be used as a 16-bit timer/event counter)

· 8-bit basic interval timer/watchdog timer: 1 channel

Serial interface · 3-wire serial I/O mode ... MSB/LSB-first switchable

· 2-wire serial I/O mode

Bit sequential buffer 16 bits

Clock output (PCL) ·

, 524, 262, 65.5 kHz (system clock: @ 4.19 MHz)

, 750, 375, 93.8 kHz (system clock: @ 6.0 MHz)

Vectored interrupts External: 3, Internal: 4

Test input External: 1

System clock oscillator Ceramic/crystal oscillator

Standby functions STOP mode/HALT mode

Operating ambient temperature T

= 40 to +85°C

Power supply voltage V

= 1.8 to 5.5 V

Package 36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)

PD75P4308

CONTENTS

PIN CONFIGURATION (Top View) ................................................................................................... 4

BLOCK DIAGRAM ............................................................................................................................. 5

PIN FUNCTIONS ................................................................................................................................ 6

3.1

Port Pins ........................................................................................................................................................ 6

3.2

Non-port Pins ................................................................................................................................................ 8

3.3

Pin I/O Circuits .............................................................................................................................................. 9

3.4

Recommended Connection of Unused Pins ............................................................................................. 11

SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ........................................ 12

4.1

Differences between Mk I Mode and Mk II Mode ..................................................................................... 12

4.2

Setting of Stack Bank Selection (SBS) Register ..................................................................................... 13

DIFFERENCES BETWEEN

PD75P4308 AND

PD754302, 754304 ......................................... 14

MEMORY CONFIGURATION ........................................................................................................... 15

INSTRUCTION SET ......................................................................................................................... 17

ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY .............................................. 28

8.1

Operation Modes for Program Memory Write/Verify ............................................................................... 28

8.2

Program Memory Write Procedure ........................................................................................................... 29

8.3

Program Memory Read Procedure ........................................................................................................... 30

8.4

One-Time PROM Screening ....................................................................................................................... 31

ELECTRICAL SPECIFICATIONS .................................................................................................... 32

10. CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ........................................................... 45

11. PACKAGE DRAWINGS .................................................................................................................... 47

12. RECOMMENDED SOLDERING CONDITIONS .............................................................................. 48

APPENDIX A. COMPARISON OF

PD750004, 754304, AND 75P4308 FUNCTIONS ..................... 49

APPENDIX B. DEVELOPMENT TOOLS ............................................................................................... 51

APPENDIX C. RELATED DOCUMENTS ............................................................................................... 55

PD75P4308

1. PIN CONFIGURATION (Top View)

36-pin plastic shrink SOP (300 mil, 0.8 mm pitch)

PD75P4308GS

Vss

P51/D5

RESET

P52/D6

P53/D7

P60/KR0/D0

P33/MD3

P32/MD2

P31/MD1

P30/MD0

P81

P80

P61/KR1/D1

P22/PCL

P62/KR2/D2

P21/PTO1

P63/KR3/D3

P20/PTO0

P70/KR4

P03/SI

P71/KR5

P02/SO/SB0

P72/KR6

P01/SCK

P73/KR7

P00/INT4

P13/TI0/TI1

P23

P50/D4

P12/INT2

P11/INT1

P10/INT0

Note

Note Connect V

directly to V

during normal operations.

PIN IDENTIFICATIONS

P00 to P03

: Port0

: Serial Input

P10 to P13

: Port1

: Serial Output

P20 to P23

: Port2

SB0

: Serial Bus 0

P30 to P33

: Port3

RESET

: Reset

P50 to P53

: Port5

TI0, 1

: Timer Input 0, 1

P60 to P63

: Port6

PTO0, 1

: Programmable Timer Output 0, 1

P70 to P73

: Port7

PCL

: Programmable Clock

P80, P81

: Port8

INT0, 1, 4

: External Vectored Interrupt 0, 1, 4

KR0 to KR7

: Key Return 0 to 7

INT2

: External Test Input 2

: Positive Power Supply

X1, 2

: System Clock Oscillation 1, 2

: GND

MD0 to 3

: Mode Selection 0 to 3

: Programming Power Supply

D0 to D7

: Data Bus 0 to 7

SCK

: Serial Clock

PD75P4308

2. BLOCK DIAGRAM

BIT SEQ.
BUFFER (16)

PORT0

P00-P03

PORT1

PORT2

PORT3

P30/MD0-
P33/MD3

PORT5

P50/D4-
P53/D7

PORT6

P60/KR0/D0-
P63/KR3/D3

Vss

RESET

CPU CLOCK

STAND BY

CONTROL

CLOCK
GENERATOR

CLOCK
DIVIDER

CLOCK
OUTPUT
CONTROL

fx/2

PCL/P22

GENERAL
REG.

RAM
DATA
MEMORY
256

4 BITS

BANK

SP (8)

ALU

PROGRAM
COUNTER

PROM

PROGRAM

MEMORY

8192

8 BITS

DECODE

AND

CONTROL

BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER

TI0/TI1/P13

INTBT

PTO0/P20

INTT1

CLOCKED
SERIAL
INTERFACE

SI/P03

INTERRUPT
CONTROL

INT0/P10

SO/SB0/P02

SCK/P01

INT1/P11
INT2/P12

INT4/P00

KR0/P60/D0-

KR3/P63/D3

KR4/P70-

KR7/P73

PORT7

P70-P73

PORT8

P80, P81

P10-P13

P20-P23

INTCSI

CASCADED
16-BIT
TIMER/
EVENT
COUNTER

8-BIT
TIMER/EVENT
COUNTER#0

8-BIT
TIMER/EVENT
COUNTER#1

INTT0

TOUT0

SBS

PTO1/P21

PD75P4308

3. PIN FUNCTIONS

3.1 Port Pins (1/2)

Pin name

I/O

Alternate

Function

8-bit

After

I/O Circuit

function

I/O

reset

type

Note 1

P00

Input

INT4

Input

P01

I/O

SCK

<F>-A

P02

I/O

SO/SB0

<F>-B

P03

Input

-C

P10

Input

INT0

Input

-C

P11

INT1

P12

INT2

P13

TI0/TI1

P20

I/O

PTO0

Input

E-B

P21

PTO1

P22

PCL

P23

P30

I/O

MD0

Input

E-B

P31

MD1

P32

MD2

P33

MD3

P50

Note 2

I/O

High-

M-E

P51

Note 2

impedance

P52

Note 2

P53

Note 2

Notes 1. Circuit types in brackets indicate Schmitt trigger input.

2. Low-level input leakage current increases when input instructions or bit manipulation instructions are

executed.

4-bit I/O port (PORT2).

Connections of on-chip pull-up resistors are

software-specifiable in 4-bit units.

4-bit input port (PORT1).

Connections of on-chip pull-up resistors are

software-specifiable in 4-bit units.

Noise elimination circuit can be selected

only for P10/INT0.

N-ch open-drain 4-bit input/output port

(PORT5).

13-V withstand during open-drain.

Data input/output pin for program memory

(PROM) write/verify (upper 4 bits).

Programmable 4-bit I/O port (PORT3).

Input and output can be specified in single-

bit units.

Connections of on-chip pull-up resistors are

software-specifiable in 4-bit units.

4-bit input port (PORT0).

For P01 to P03, connections of on-chip pull-

up resistors are software-specificable in 3-

bit units.

PD75P4308

3.1 Port Pins (2/2)

Pin name

I/O

Alternate

Function

8-bit

After

I/O Circuit

function

I/O

reset

type

Note

P60

I/O

KR0/D0

Yes

Input

<F>-A

P61

KR1/D1

P62

KR2/D2

P63

KR3/D3

P70

I/O

KR4

Input

<F>-A

P71

KR5

P72

KR6

P73

KR7

P80

I/O

Input

E-B

P81

Note Circuit types in brackets indicate the Schmitt trigger input.

4-bit I/O port (PORT7).
Connections of on-chip pull-up resistors are
software-specifiable in 4-bit units.

2-bit I/O port (PORT8).
Connections of on-chip pull-up resistors are
software-specifiable in 2-bit units.

Programmable 4-bit I/O port (PORT6).
Input and output can be specified in single-bit
units. Connections of on-chip pull-up resistors
are software-specifiable in 4-bit units.
Data input/output pin for program memory
(PROM) write/verify (lower 4 bits).

PD75P4308

External event pulse input to timer/event counter

Timer/event counter output

Clock output

Serial clock I/O

Serial data output

Serial data bus I/O

Serial data input

Edge-triggered vectored interrupt input

(triggered by both rising and falling edges).

3.2 Non-port Pins

Pin name

I/O

Alternate

Function

After

I/O Circuit

function

reset

type

Note 1

TI0/TI1

Input

P13

Input

-C

PTO0

Output

P20

Input

E-B

PTO1

P21

PCL

P22

SCK

I/O

P01

Input

<F>-A

SO/SB0

P02

<F>-B

Input

P03

-C

INT4

P00

INT0

Input

P10

-C

INT1

P11

INT2

P12

KR0 to KR3

Input

P60/D0 to

Input

<F>-A

P63/D3

KR4 to KR7

P70 to P73

Input

RESET

Input

MD0 to MD3

Input

P30 to P33

Input

E-B

D0 to D3

I/O

P60/KR0 to

Input

<F>-A

P63/KR3

D4 to D7

P50 to P53

M-E

Note 2

Notes 1. Circuit types in brackets indicate Schmitt trigger input.

2. During normal operation, the V

pin will not operate normally unless connected to V

pin.

Noise elimination

circuit appended/

asynchronous

selectable

Edge-triggered vectored interrupt

input (detected edge is selectable).

Noise elimination circuit selectable

in INT0/P10.

Asynchronous

Rising edge-triggered test input

Falling edge-triggered testable input

Ceramic/crystal connection for system clock oscillation.

If using an external clock, input it to X1 and input the

inverted clock to X2.

System reset input

Mode selection for program memory (PROM) write/

verify.

Data bus pin for program memory (PROM) write/verify.

Program supply voltage in program memory (PROM)

write/verify mode.

In normal operation mode, connect directly to V

Apply +12.5 V in PROM write/verify mode.

Positive power supply

Ground

PD75P4308

3.3 Pin I/O Circuits

The equivalent circuits for the

PD75P4308's pin are shown in simplified schematic diagrams below.

(1/2)

P-ch

N-ch

P-ch

N-ch

OUT

Data

Output

disable

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R.: Pull-Up Resistor

Type A

P-ch

P.U.R.
enable

P.U.R.

P.U.R. : Pull-Up Resistor

P-ch

IN/OUT

P.U.R.

enable

Data

P.U.R.

Type D

Output

disable

P.U.R.: Pull-Up Resistor

Type B

CMOS standard input buffer

Push-pull output that can be set to high impedance output
(with both P-ch and N-ch OFF).

Schmitt trigger input with hysteresis characteristics.

TYPE A

TYPE D

TYPE E-B

TYPE B

TYPE B-C

TYPE F-A

Schmitt trigger input with hysteresis characteristics.

PD75P4308

1 2

4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

Setting a stack bank selection (SBS) register for the

PD75P4308 enables the program memory to be switched

between the Mk I mode and the Mk II mode. This capability enables the evaluation of the

PD754302 or 754304 using

the

PD75P4308.

When the SBS bit 3 is set to 1: sets Mk I mode (corresponds to Mk I mode of

PD754302 and 754304)

When the SBS bit 3 is set to 0: sets Mk II mode (corresponds to Mk II mode of

PD754302 and 754304)

4.1 Differences between Mk I Mode and Mk II Mode

Table 4-1 lists the differences between the Mk I mode and the Mk II mode of the

PD75P4308.

Table 4-1. Differences between Mk I Mode and Mk II Mode

Item

Mk I Mode

Mk II Mode

Program counter

12-0

Program memory (bytes)

8192

Data memory (bits)

256

Stack

Stack bank

Memory bank 0

Stack bytes

2 bytes

3 bytes

Instruction

BRA !addr1

Not provided

Provided

CALLA !addr1

Instruction

CALL !addr

3 machine cycles

4 machine cycles

execution time CALLF !faddr

2 machine cycles

3 machine cycles

Supported mask ROM versions

Mk I mode of

PD754302 and 754304

Mk II mode of

PD754302 and 754304

Caution The Mk II mode supports 16 Kbytes or more of program area in the 75X and 75XL Series. This

mode allows the software compatibility with 16-Kbyte or more versions to be improved.

Compared with the Mk I mode, selecting the Mk II mode increases the stack bytes by one during

execution of the subroutine call instruction. When a CALL !addr or CALLF !faddr instruction is

used, the instruction execution time increases by one machine cycle. Therefore, if RAM efficiency

or throughput is more important than software compatibility, use the Mk I mode.

PD75P4308

1 3

4.2 Setting of Stack Bank Selection (SBS) Register

Use the stack bank selection register to switch between the Mk I mode and the Mk II mode. Figure 4-1 shows the

format for doing this.

The stack bank selection register is set using a 4-bit memory manipulation instruction. When using the Mk I mode,

be sure to initialize the stack bank selection register to 1000B at the beginning of the program. When using the Mk

II mode, be sure to initialize it to 0000B.

Figure 4-1. Format of Stack Bank Selection Register

SBS3 SBS2 SBS1 SBS0

F84H

Address

SBS

Symbol

Stack area specification

Memory bank 0

Be sure to enter "0" for bit 2.

Mk II mode

Mk I mode

Mode selection specification

Setting prohibited other than above

Cautions 1. SBS3 is set to "1" after RESET input, and consequently the CPU operates in the Mk I mode.

When using instructions for the Mk II mode, set SBS3 to "0" to enter the Mk II mode before

using the instructions.

2. When using the Mk II mode, execute a subroutine call instruction and an interrupt instruction

after RESET input and after setting the stack bank selection register.

PD75P4308

1 4

5. DIFFERENCES BETWEEN

PD75P4308 AND

PD754302, 754304

The

PD75P4308 replaces the internal mask ROM in the

PD754302 and 754304 with a one-time PROM and

features expanded ROM capacity. The

PD75P4308's Mk I mode supports the Mk I mode in the

PD754302 and

754304 and the

PD75P4308's Mk II mode supports the Mk II mode in the

PD754302 and 754304.

Table 5-1 lists differences among the

PD75P4308 and the

PD754302 and 754304. Be sure to check the

differences between corresponding versions beforehand, especially when a PROM version is used for debugging or

prototype testing of application systems and later the corresponding mask ROM version is used for full-scale

production.

For details of CPU functions and incorporated hardware, refer to

PD754304 User's Manual (U10123E).

Table 5-1. Differences between

PD75P4308 and

PD754302, 754304

Item

PD754302

PD754304

PD75P4308

Program counter

11-bit

12-bit

13-bit

Program memory (bytes)

Mask ROM

One-time PROM

2048

4096

8192

Data memory (

4 bits)

256

Mask options

Pull-up resistor for

Yes (On-chip/not on-chip specifiable)

No (On-chip not possible)

PORT5

Wait time in

Yes (Selectable from 2

and 2

)

Note

No (fixed at 2

)

Note

RESET state

Pin configuration

Pins 5 to 8

P33-P30

P33/MD3-P30/MD0

Pin 19

Pins 29 to 32

P63/KR3-P60/KR0

P63/KR3/D3-

P60/KR0/D0

Pins 33 to 36

P53-P50

P53/D7-P50/D4

Other

Noise resistance and noise radiation may differ due to the different circuit

complexities and mask layouts.

Note 2

: 21.8 ms @6.0-MHz operation, 31.3 ms @4.19-MHz operation.

: 5.46 ms @6.0-MHz operation, 7.81 ms @4.19-MHz operation.

Caution Noise resistance and noise radiation are different in PROM version and mask ROM versions. If

using a mask ROM version instead of the PROM version for processes between prototype

development and full production, be sure to fully evaluate the CS (not ES) of the mask ROM

version.

PD75P4308

1 5

6. MEMORY CONFIGURATION

Figure 6-1. Program Memory Map

MBE

RBE

Internal reset start address (upper 5 bits)

Internal reset start address (lower 8 bits)

INTBT/INT4 start address (upper 5 bits)

INTBT/INT4 start address (lower 8 bits)

INT0 start address (upper 5 bits)

INT0 start address (lower 8 bits)

INT1 start address (upper 5 bits)

INT1 start address (lower 8 bits)

INTCSI start address (upper 5 bits)

INTCSI start address (lower 8 bits)

INTT0 start address (upper 5 bits)

INTT0 start address (lower 8 bits)

INTT1 start address (upper 5 bits)

INTT1 start address (lower 8 bits)

Reference table for GETI instruction

0000H

0002H

0004H

0006H

0008H

000AH

000CH

007FH

0080H

07FFH

0800H

0FFFH

1000H

1FFFH

CALLF

!faddr instruction

entry address

Branch address for

the following instructions

Branch/call

address

by GETI

BR $addr instruction

relative branch address

(15 to 1,

+2 to +16)

BRCB

!caddr instruction

branch address

BRCB

!caddr instruction

branch address

· BR BCDE
· BR BCXA
· BR !addr
· CALL !addr
· BRA !addr1
· CALLA !addr1

Note

0020H

Note Can be used only in the Mk II mode.

Remark For instructions other than those noted above, the "BR PCDE" and "BR PCXA" instructions can be used

to branch to addresses with changes in the PC's lower 8 bits only.

PD75P4308

1 7

7. INSTRUCTION SET

(1) Representation and coding formats for operands

In the instruction's operand area, use the following coding format to describe operands corresponding to the

instruction's operand representations (for further description, refer to RA75X Assembler Package User's

Manual Language (EEU-1363)). When there are several codes, select and use just one. Uppercase letters,

and + and symbols are key words that should be entered as they are.

For immediate data, enter an appropriate numerical value or label.

Instead of mem, fmem, pmem, bit, etc., a register flag symbol can be described as a label descriptor (for details,

refer to

PD754304 User's Manual (U10123E)). Labels that can be entered for fmem and pmem are restricted.

Representation

Coding format

reg

X, A, B, C, D, E, H, L

reg1

X, B, C, D, E, H, L

XA, BC, DE, HL

rp1

BC, DE, HL

rp2

BC, DE

rp'

XA, BC, DE, HL, XA', BC', DE', HL'

rp'1

BC, DE, HL, XA', BC', DE', HL'

rpa

HL, HL+, HL, DE, DL

rpa1

DE, DL

4-bit immediate data or label

8-bit immediate data or label

mem

8-bit immediate data or label

Note

bit

2-bit immediate data or label

fmem

FB0H-FBFH, FF0H-FFFH immediate data or label

pmem

FC0H-FFFH immediate data or label

addr

0000H-1FFFH immediate data or label

addr1

0000H-1FFFH immediate data or label (in Mk II mode only)

caddr

12-bit immediate data or label

faddr

11-bit immediate data or label

taddr

20H-7FH immediate data (however, bit0 = 0) or label

PORTn

PORT0-PORT3, PORT5-PORT8

¥¥¥

IEBT, IECSI, IET0, IET1, IE0-IE2, IE4

RBn

RB0-RB3

MBn

MB0, MB15

Note When processing 8-bit data, only even addresses can be specified.

PD75P4308

1 8

(2) Operation legend

: A register; 4-bit accumulator

: B register

: C register

: D register

: E register

: H register

: L register

: X register

: Register pair (XA); 8-bit accumulator

: Register pair (BC)

: Register pair (DE)

: Register pair (HL)

XA'

: Expansion register pair (XA')

BC'

: Expansion register pair (BC')

DE'

: Expansion register pair (DE')

HL'

: Expansion register pair (HL')

: Program counter

: Stack pointer

: Carry flag; bit accumulator

PSW

: Program status word

MBE

: Memory bank enable flag

RBE

: Register bank enable flag

PORTn : Port n (n = 0 to 3, 5 to 8)

IME

: Interrupt master enable flag

IPS

: Interrupt priority select register

¥¥¥

: Interrupt enable flag

RBS

: Register bank select register

MBS

: Memory bank select register

PCC

: Processor clock control register

: Delimiter for address and bit

(

¥¥

)

: Contents of address

¥¥

: Hexadecimal data

PD75P4308

1 9

(3) Description of symbols used in addressing area

MB = 0 (000H-07FH)

MB = 15 (F80H-FFFH)

MB = MBS

(MBS = 0, 15)

MB = MBE·MBS

(MBS = 0, 15)

MB = 0

MBE = 1 :

MBE = 0 :

MB = 15, fmem = FB0H-FBFH, FF0H-FFFH

MB = 15, pmem = FC0H-FFFH

addr, addr1 = 0000H-1FFFH

addr, addr1 =

(Current PC) 15 to (Current PC) 1

(Current PC) +2 to (Current PC) +16

caddr = 0000H-0FFFH (PC

= 0) or

1000H-1FFFH (PC

= 1)

faddr = 0000H-07FFH

taddr = 0020H-007FH

addr1 = 0000H-1FFFH (Mk II mode only)

*10

*11

Program memory

addressing

Data memory

addressing

Remarks 1. MB indicates access-enabled memory banks.

2. In area *2, MB = 0 for both MBE and MBS.

3. In areas *4 and *5, MB = 15 for both MBE and MBS.

4. Areas *6 to *11 indicate corresponding address-enabled areas.

PD75P4308

2 0

(4) Description of machine cycles

S indicates the number of machine cycles required for skipping of skip-specified instructions. The value of S varies

as shown below.

No skip áááááááááááááááááááááááááááááááááááááááá S = 0

Skipped instruction is 1-byte or 2-byte instruction áááááá S = 1

Skipped instruction is 3-byte instruction

Note

ááááááááááá S = 2

Note 3-byte instructions: BR !addr, BRA !addr1, CALL !addr, CALLA !addr1

Caution The GETI instruction is skipped for one machine cycle.

One machine cycle equals one cycle (= t

) of the CPU clock

. Use the PCC setting to select among four cycle

times.

PD75P4308

2 1

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Transfer

MOV

A, #n4

String-effect A

reg1, #n4

reg1

XA, #n8

String-effect A

HL, #n8

String-effect B

rp2, #n8

rp2

A, @HL

(HL)

A, @HL+

2 + S

(HL), then L

L + 1

L = 0

A, @HL

2 + S

(HL), then L

L 1

L = FH

A, @rpa1

(rpa1)

XA, @HL

(HL)

@HL, A

(HL)

@HL, XA

(HL)

A, mem

(mem)

XA, mem

(mem)

mem, A

(mem)

mem, XA

(mem)

A, reg1

reg1

XA, rp'

rp'

reg1, A

reg1

rp'1, XA

rp'1

XCH

A, @HL

¨Æ

(HL)

A, @HL+

2 + S

¨Æ

(HL), then L

L + 1

L = 0

A, @HL

2 + S

¨Æ

(HL), then L

L 1

L = FH

A, @rpa1

¨Æ

(rpa1)

XA, @HL

¨Æ

(HL)

A, mem

¨Æ

(mem)

XA, mem

¨Æ

(mem)

A, reg1

¨Æ

reg1

XA, rp'

¨Æ

rp'

Table

MOVT

XA, @PCDE

(PC

12 - 8

+ DE)

ROM

reference

XA, @PCXA

(PC

12 - 8

+ XA)

ROM

XA, @BCDE

(BCDE)

ROM

Note

XA, @BCXA

(BCXA)

ROM

Note

Note As for the B register, only the lower 1 bit is valid.

PD75P4308

2 2

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Bit transfer

MOV1

CY, fmem.bit

(fmem.bit)

CY, pmem.@L

(pmem

7 - 2

+ L

3 - 2

.bit (L

1 - 0

))

CY, @H + mem.bit

(H + mem

3 - 0

.bit)

fmem.bit, CY

(fmem.bit)

pmem.@L, CY

(pmem

7 - 2

+ L

3 - 2

.bit (L

1 - 0

))

@H + mem.bit, CY

(H + mem

3 - 0

.bit)

Operation

ADDS

A, #n4

1 + S

A + n4

carry

XA, #n8

2 + S

XA + n8

carry

A, @HL

1 + S

A + (HL)

carry

XA, rp'

2 + S

XA + rp'

carry

rp'1, XA

2 + S

rp'1

rp'1 + XA

carry

ADDC

A, @HL

A, CY

A + (HL) + CY

XA, rp'

XA, CY

XA + rp' + CY

rp'1, XA

rp'1, CY

rp'1 + XA + CY

SUBS

A, @HL

1 + S

A (HL)

borrow

XA, rp'

2 + S

XA rp'

borrow

rp'1, XA

2 + S

rp'1

rp'1 XA

borrow

SUBC

A, @HL

A, CY

A (HL) CY

XA, rp'

XA, CY

XA rp' CY

rp'1, XA

rp'1, CY

rp'1 XA CY

AND

A, #n4

A ^ n4

A, @HL

A ^ (HL)

XA, rp'

XA ^ rp'

rp'1, XA

rp'1

rp'1 ^ XA

A, #n4

A v n4

A, @HL

A v (HL)

XA, rp'

XA v rp'

rp'1, XA

rp'1

rp'1 v XA

XOR

A, #n4

A v n4

A, @HL

A v (HL)

XA, rp'

XA v rp'

rp'1, XA

rp'1

rp'1 v XA

PD75P4308

2 3

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Accumulator

RORC

, A

CY, A

n - 1

manipulate

NOT

Increment/

INCS

reg

1 + S

reg

reg + 1

reg = 0

decrement

rp1

1 + S

rp1

rp1 + 1

rp1 = 00H

@HL

2 + S

(HL)

(HL) + 1

(HL) = 0

mem

2 + S

(mem)

(mem) + 1

(mem) = 0

DECS

reg

1 + S

reg

reg 1

reg = FH

rp'

2 + S

rp'

rp' 1

rp' = FFH

Compare

SKE

reg, #n4

2 + S

Skip if reg =n4

reg = n4

@HL, #n4

2 + S

Skip if (HL) = n4

(HL) = n4

A, @HL

1 + S

Skip if A = (HL)

A = (HL)

XA, @HL

2 + S

Skip if XA = (HL)

XA = (HL)

A, reg

2 + S

Skip if A = reg

A = reg

XA, rp'

2 + S

Skip if XA = rp'

XA = rp'

Carry flag

SET1

manipulate

CLR1

SKT

1 + S

Skip if CY = 1

CY = 1

NOT1

PD75P4308

2 4

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Memory bit

SET1

mem.bit

(mem.bit)

manipulate

fmem.bit

(fmem.bit)

pmem.@L

(pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0)

)

@H + mem.bit

(H+mem

3 - 0

.bit)

CLR1

mem.bit

(mem.bit)

fmem.bit

(fmem.bit)

pmem.@L

(pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

))

@H + mem.bit

(H+mem

3 - 0

.bit)

SKT

mem.bit

2 + S

Skip if (mem.bit) = 1

(mem.bit)=1

fmem.bit

2 + S

Skip if (fmem.bit) = 1

(fmem.bit)=1

pmem.@L

2 + S

Skip if (pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

)) = 1

(pmem.@L) = 1

@H + mem.bit

2 + S

Skip if (H + mem

3 - 0

.bit) = 1

(@H + mem.bit) = 1

SKF

mem.bit

2 + S

Skip if (mem.bit) = 0

(mem.bit) = 0

fmem.bit

2 + S

Skip if (fmem.bit) = 0

(fmem.bit) = 0

pmem.@L

2 + S

Skip if (pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

)) = 0

(pmem.@L) = 0

@H + mem.bit

2 + S

Skip if (H + mem

3 - 0

.bit) = 0

(@H + mem.bit) = 0

SKTCLR

fmem.bit

2 + S

Skip if (fmem.bit) = 1 and clear

(fmem.bit) = 1

pmem.@L

2 + S

Skip if (pmem

+ L

3 - 2

.bit (L

1 - 0

)) = 1 and clear

(pmem.@L) = 1

@H + mem.bit

2 + S

Skip if (H + mem

3 - 0

.bit) = 1 and clear

(@H + mem.bit) = 1

AND1

CY, fmem.bit

CY ^ (fmem.bit)

CY, pmem.@L

CY ^ (pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

))

CY, @H + mem.bit

CY ^ (H + mem

3 - 0

.bit)

OR1

CY, fmem.bit

CY v (fmem.bit)

CY, pmem.@L

CY v (pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

))

CY, @H + mem.bit

CY v (H + mem

3 - 0

.bit)

XOR1

CY, fmem.bit

CY v (fmem.bit)

CY, pmem.@L

CY v (pmem

7 - 2

+ L

3 - 2

.bit(L

1 - 0

))

CY, @H + mem.bit

CY v (H + mem

3 - 0

.bit)

PD75P4308

2 5

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Branch

Note1

addr

12 - 0

addr

Assembler selects the most

appropriate instruction among

the following:

· BR !addr

· BRCB !caddr

· BR $addr

addr1

12 - 0

addr1

*11

Assembler selects the most

appropriate instruction among

the following:

· BRA !addr1

· BR !addr

· BRCB !caddr

· BR $addr1

!addr

12 - 0

addr

$addr

12 - 0

addr

$addr1

12 - 0

addr1

PCDE

12 - 0

12 - 8

+ DE

PCXA

12 - 0

12 - 8

+ XA

BCDE

12 - 0

BCDE

Note 2

BCXA

12 - 0

BCXA

Note 2

BRA

Note 1

!addr1

12 - 0

addr1

*11

BRCB

!caddr

12 - 0

+ caddr

11 - 0

Notes 1. Shaded areas indicate support for the Mk II mode only.

2. Only the lower 2 bit in the B register is valid.

PD75P4308

2 6

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Subroutine

CALLA

Note

!addr1

(SP 5)

0, 0, 0, PC

*11

stack control

(SP 6) (SP 3) (SP 4)

11 - 0

(SP 2)

, MBE, RBE

12 - 0

addr1, SP

SP 6

CALL

Note

!addr

(SP 4) (SP 1) (SP 2)

11 - 0

(SP 3)

MBE, RBE, 0, PC

12 - 0

addr, SP

SP 4

(SP 5)

0, 0, 0, PC

(SP 6) (SP 3) (SP 4)

11 - 0

(SP 2)

, MBE, RBE

12 - 0

addr, SP

SP 6

CALLF

Note

!faddr

(SP 4) (SP 1) (SP 2)

11 - 0

(SP 3)

MBE, RBE, 0, PC

12 - 0

00 + faddr, SP

SP 4

(SP 5)

0, 0, 0, PC

(SP 6) (SP 3) (SP 4)

11 - 0

(SP 2)

, MBE, RBE

12 - 0

00 + faddr, SP

SP 6

RET

Note

MBE, RBE, 0, PC

(SP + 1)

11 - 0

(SP) (SP + 3) (SP + 2)

SP + 4

, MBE, RBE

(SP + 4)

0, 0, 0, PC

(SP + 1)

11 - 0

(SP) (SP + 3) (SP + 2)

SP + 6

RETS

Note

3 + S

MBE, RBE, 0, PC

(SP + 1)

Unconditional

11 - 0

(SP) (SP + 3) (SP + 2)

SP + 4

then skip unconditionally

, MBE, RBE

(SP + 4)

0, 0, 0, PC

(SP + 1)

11, 0

(SP) (SP + 3) (SP + 2)

SP + 6

then skip unconditionally

RETI

MBE, RBE, 0, PC

(SP + 1)

11 - 0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

0, 0, 0, PC

(SP + 1)

11 - 0

(SP) (SP + 3) (SP + 2)

PSW

(SP + 4) (SP + 5), SP

SP + 6

Note Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode only.

PD75P4308

2 7

Group

Mnemonic

Operand

No. of Machine

Operation

Addressing

Skip condition

bytes cycle

area

Subroutine

PUSH

(SP 1) (SP 2)

rp, SP

SP 2

stack control

(SP 1)

MBS, (SP 2)

RBS, SP

SP 2

POP

(SP + 1) (SP), SP

SP + 2

MBS

(SP + 1), RBS

(SP), SP

SP + 2

Interrupt

IME (IPS.3)

control

¥¥¥

IME (IPS.3)

¥¥¥

I/O

Note 1

A, PORTn

PORTn

(n = 0 - 3, 5 - 8)

XA, PORTn

PORTn +

, PORTn

(n = 6)

OUT

Note 1

PORTn, A

PORTn

(n = 2 - 3, 5 - 8)

PORTn, XA

PORTn +

, PORTn

(n = 6)

CPU control

HALT

Set HALT Mode(PCC.2

STOP

Set STOP Mode(PCC.3

NOP

No Operation

Special

SEL

RBn

RBS

(n = 0 - 3)

MBn

MBS

(n = 0, 15)

GETI

Note 2, 3

taddr

· When using TBR instruction

*10

12 - 0

(taddr)

4 - 0

+ (taddr + 1)

· When using TCALL instruction

(SP 4) (SP 1) (SP 2)

11 - 0

(SP 3)

MBE, RBE, 0, PC

12 - 0

(taddr)

4 - 0

+ (taddr + 1)

SP 4

· When using instruction other than

Determined by

TBR or TCALL

referenced

Execute (taddr) (taddr + 1) instructions

instruction

· When using TBR instruction

*10

12 - 0

(taddr)

4 - 0

+ (taddr + 1)

· When using TCALL instruction

(SP 5)

0, 0, 0, PC

(SP 6) (SP 3) (SP 4)

11 - 0

(SP 2)

, MBE, RBE

12 - 0

(taddr)

4 - 0

+ (taddr + 1)

SP 6

· When using instruction other than

Determined by

TBR or TCALL

referenced

Execute (taddr) (taddr + 1) instructions

instruction

Notes 1. Before executing the IN or OUT instruction, set MBE to 0 or 1 and set MBS to 15.

2. TBR and TCALL are assembler pseudo-instructions for the GETI instruction's table definitions.

3. Shaded areas indicate support for the Mk II mode only. Other areas indicate support for the Mk I mode

only.

PD75P4308

2 8

8. ONE-TIME PROM (PROGRAM MEMORY) WRITE AND VERIFY

The program memory in the

PD75P4308 is a 8192

8-bit electrically write-enabled one-time PROM. The pins

listed in the table below are used for this one-time PROM's write/verify operations. Clock input from the X1 pin is

used instead of address input as a method for updating addresses.

Pin name

Function

Pin (usually V

) where programming voltage is applied during

program memory write/verify

X1, X2

Clock input pin for address updating during program memory write/

verify. Input the X1 pin's inverted signal to the X2 pin.

MD0-MD3

Operation mode selection pin for program memory write/verify

D0/P60/KR0-D3/P63/KR3 (lower 4) 8-bit data I/O pin for program memory write/verify

D4/P50-D7/P53 (upper 4)

Pin where power supply voltage is applied. Power voltage range

for normal operation is 1.8 to 5.5 V. Apply 6.0 V for program

memory write/verify.

Caution Pins not used for program memory write/verify connect to Vss via a pull-down resistor.

8.1 Operation Modes for Program Memory Write/Verify

When +6 V is applied to the

PD75P4308's V

pin and +12.5 V is applied to its V

pin, program write/verify modes

are in effect. Furthermore, the following detailed operation modes can be specified by setting pins MD0 to MD3 as

shown below.

Operation mode specification

Operation mode

MD0

MD1

MD2

MD3

+12.5 V

+6 V

Zero-clear program memory address

Write mode

Verify mode

Program inhibit mode

: L or H

PD75P4308

2 9

8.2 Program Memory Write Procedure

High-speed program memory write can be executed via the following steps.

(1)

Pull down unused pins to V

via resistors. Set the X1 pin to low.

(2)

Apply +5 V to the V

and V

pins.

(3)

Wait 10

(4)

Zero-clear mode for program memory addresses.

(5)

Apply +6 V to V

and +12.5 V to V

(6)

Write data using 1-ms write mode.

(7)

Verify mode. If write is verified, go to step (8) and if write is not verified, go back to steps (6) and (7).

(8)

X [= number of write operations from steps (6) and (7)]

1 ms additional write

(9)

4 pulse inputs to the X1 pin updates (increments +1) the program memory address.

(10) Repeat steps (6) to (9) until the last address is completed.

(11) Zero-clear mode for program memory addresses.

(12) Apply +5 V to the V

and V

pins.

(13) Power supply OFF

The following diagram illustrates steps (2) to (9).

+ 1

D0/P60/KR0-

D3/P63/KR3

D4/P50-

D7/P53

MD0/P30

MD1/P31

MD2/P32

MD3/P33

Write

Verify

Additional write

Address

increment

X repetitions

Data input

Data output

Data input

PD75P4308

3 0

8.3 Program Memory Read Procedure

The

PD75P4308 can read out the program memory contents via the following steps.

(1)

Pull down unused pins to V

via resistors. Set the X1 pin to low.

(2)

Apply +5 V to the V

and V

pins.

(3)

Wait 10

(4)

Zero-clear mode for program memory addresses.

(5)

Apply +6 V to V

and +12.5 V to V

(6)

Verify mode. When a clock pulse is input to the X1 pin, data is output sequentially to one address at a

time based on a cycle of four pulse inputs.

(7)

Zero-clear mode for program memory addresses.

(8)

Apply +5 V to the V

and V

pins.

(9)

Power supply OFF

The following diagram illustrates steps (2) to (7).

+ 1

D0/P60/KR0-

D3/P63/KR3

D4/P50-

D7/P53

Data output

MD0/P30

MD2/P32

MD3/P33

MD1/P31

"L"

PD75P4308

3 2

9. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (T

= 25 °C)

Parameter Symbol Conditions Ratings Unit

Supply voltage V

0.3 to +7.0 V

PROM supply voltage V

0.3 to +13.5 V

Input voltage V

Other than port 5 0.3 to V

+0.3 V

Port 5 (N-ch open-drain) 0.3 to +14 V

Output voltage V

0.3 to V

+0.3 V

High-level output current I

Per pin 10 mA

Total for all pins 30 mA

Low-level output current I

Per pin 30 mA

Total for all pins 220 mA

Operating ambient T

40 to +85 °C

temperature

Storage temperature T

stg

65 to +150 °C

Caution If the absolute maximum ratings of even one of the parameters is exceeded even momentarily,

the quality of the product may be degraded. The absolute maximum ratings are therefore values

which, when exceeded, can cause the product to be damaged. Be sure that these values are never

exceeded when using the product.

Capacitance (T

= 25°C, V

= 0 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Input capacitance C

f = 1 MHz 15 pF

Output capacitance C

OUT

Unmeasured pins returned to 0 V

15 pF

I/O capacitance C

15 pF

PD75P4308

3 3

System Clock Oscillation Circuit Characteristics (T

= 40 to +85°C, V

= 1.8 to 5.5. V)

Resonator

Recommended

Parameter Conditions MIN. TYP. MAX. Unit

constants

Ceramic Oscillation frequency 1.0 6.0

Note 3

MHz

resonator (f

)

Note 1

Oscillation After V

has 4 ms

stabilization time

Note 2

reached MIN. value of

oscillation voltage

range

Crystal Oscillation frequency 1.0 6.0

Note 3

MHz

resonator (f

)

Note 1

Oscillation V

= 5.0 V ± 10 % 10 ms

stabilization time

Note 2

30 ms

External X1 input frequency 1.0 6.0

Note 3

MHz

clock (f

)

Note 1

X1 input high-, 83.3 500 ns

low-level widths

, t

)

Notes 1. The oscillation frequency and X1 input frequency shown above indicate characteristics of the oscillation

circuit only. For the instruction execution time, refer to AC Characteristics.

2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V

or releasing

the STOP mode.

3. When the oscillation frequency f

satisfies 4.19 MHz < f

- 6.0 MHz at 1.8 V - V

< 2.7 V, do not set

PCC = 0011 as an instruction execution time. If PCC = 0011 is selected, one machine cycle takes less

than 0.95

s, and the MIN. value rating of 0.95

s is not satisfied.

Caution When using the system clock oscillation circuit, wire the portion enclosed in the dotted line in

the above figure as follows to prevent adverse influence due to wiring capacitance:

Keep the wiring length as short as possible.

Do not cross the wiring with other signal lines.

Do not route the wiring in the vicinity of a line through which a high alternating current flows.

Always keep the ground point of the capacitor of the oscillation circuit at the same potential

as V

. Do not ground to a ground pattern through which a high current flows.

Do not extract signals from the oscillation circuit.

PD75P4308

3 4

Recommended Oscillation Circuit Constant

Ceramic Resonator (T

= 40 to +85°C)

Frequency

Recommended Oscillation voltage

Manufacturer Product name

circuit constant (pF) range (V

)

Remark

(MHz)

C1 C2 MIN. MAX.

Murata CSB1000J

Note

Rd = 5.6 k

Manufacturing

CSA2.00MG

Co., Ltd.

CST2.00MG On-chip capacitor

CSA3.58MG

CST3.58MGW On-chip capacitor

CSA3.58MGU

CST3.58MGWU On-chip capacitor

CSA4.00MG

CST4.00MGW On-chip capacitor

CSA4.00MGU

CST4.00MGWU On-chip capacitor

CSA4.19MG

CST4.19MGW On-chip capacitor

CSA4.19MGU

CST4.19MGWU On-chip capacitor

CSA6.00MG

CST6.00MGW On-chip capacitor

CSA6.00MGU

CST6.00MGWU On-chip capacitor

Kyocera Corp. KBR-1000F/Y T

= 20 to +80°C

KBR-2.0MS

KBR-4.0MSA

KBR-4.0MKS On-chip capacitor, T

= 20 to +80°C

PBRC4.00A T

= 20 to +80°C

PBRC4.00B On-chip capacitor, T

= 20 to +80°C

KBR-4.19MSA T

= 20 to +80°C

KBR-4.19MSB

KBR-4.19MKS On-chip capacitor, T

= 20 to +80°C

PBRC4.19A T

= 20 to +80°C

PBRC4.19B On-chip capacitor, T

= 20 to +80°C

KBR-6.0MSA T

= 20 to +80°C

KBR-6.0MSB

KBR-6.0MKS On-chip capacitor, T

= 20 to +80°C

PBRC6.00A T

= 20 to +80°C

PBRC6.00B On-chip capacitor, T

= 20 to +80°C

Caution The oscillation circuit constants and oscillation voltage range indicate conditions for stable

oscillation but do not guarantee accuracy of the oscillation frequency. If the application circuit
requires accuracy of the oscillation frequency, it is necessary to set the oscillation frequency of
the resonator in the application circuit. For this, it is necessary to directly contact the manufacturer
of the resonator being used.

1.0 100 100 2.6 5.5

2.0 30 30 1.8 5.5

3.58 30 30 1.8 5.5

30 30 1.8

4.0 30 30 2.0 5.5

30 30 1.8

4.19 30 30 1.9 5.5

30 30 1.8

6.0 30 30 2.9 5.5

30 30 2.0

1.0 100 100 1.8 5.5

2.0 47 47 2.4 5.5

4.0 33 33 1.8 5.5

33 33

4.19 33 33 1.8 5.5

33 33

6.0 33 33 1.8 5.5

33 33

PD75P4308

3 6

DC Characteristics (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Low-level I

Per pin 15 mA

output current

Total for all pins 150 mA

High-level input V

IH1

Ports 2, 3, 8 2.7 V - V

- 5.5 V 0.7 V

voltage

1.8 V - V

< 2.7 V 0.9 V

IH2

Ports 0, 1, 6, 7, RESET 2.7 V - V

- 5.5 V 0.8 V

1.8 V - V

< 2.7 V 0.9 V

IH3

Port 5 2.7 V - V

- 5.5 V 0.7 V

13 V

(N-ch open-drain) 1.8 V - V

< 2.7 V 0.9 V

13 V

IH4

X1 V

0.1 V

Low-level input V

IL1

Ports 2, 3, 5, 8 2.7 V - V

- 5.5 V 0 0.3 V

voltage

1.8 V - V

< 2.7 V 0 0.1 V

IL2

Ports 0, 1, 6, 7, RESET 2.7 V - V

- 5.5 V 0 0.2 V

1.8 V - V

< 2.7 V 0 0.1 V

IL3

X1 0 0.1 V

High-level output V

SCK, SO, Ports 2, 3, 6 to 8 I

= 1 mA V

0.5 V

voltage

Low-level output V

OL1

SCK, SO, Ports 2, 3, 5 to 8 I

= 15 mA, 0.2 2.0 V

voltage V

= 5.0 V ± 10 %

= 1.6 mA 0.4 V

OL2

SB0 N-ch open-drain 0.2 V

Pull-up resistor · 1 k

High-level input I

LIH1

= V

Pins other than port 5 and X1 3

leakage current

LIH2

X1 20

LIH3

= 13 V Port 5 (N-ch open-drain) 20

Low-level input I

LIL1

= 0 V Pins other than port 5 and X1 3

leakage current

LIL2

X1 20

LIL3

Port 5 (N-ch open-drain) 3

Other than the input instruction
execution time

= 5.0 V 10 27

= 3.0 V 3 8

Port 5
(N-ch open-drain)
At the input
instruction
execution time

PD75P4308

3 7

High-level output I

LOH1

= V

SCK, SO/SB0, Ports 2, 3, 6 to 8 3

leakage current

LOH2

= 13 V Port 5 (N-ch open-drain) 20

Low-level output I

LOL

= 0 V 3

leakage current

On-chip pull-up R

= 0 V Ports 0 to 3, 6 to 8 (except P00 pin) 50 100 200 k

resistor

Supply current

Note 1

DD1

= 5.0 V ± 10 %

Note 2

2.20 7.00 mA

= 3.0 V ± 10 %

Note 3

0.43 1.30 mA

DD2

HALT V

= 5.0 V ± 10 % 0.53 1.60 mA

mode

= 3.0 V ± 10 % 0.21 0.70 mA

DD1

= 5.0 V ± 10 %

Note 2

1.70 5.10 mA

= 3.0 V ± 10 %

Note 3

0.35 1.10 mA

DD2

HALT V

= 5.0 V ± 10 % 0.51 1.60 mA

mode V

= 3.0 V ± 10 % 0.19 0.60 mA

DD5

STOP V

= 5.0 V ± 10 % 0.05 10.0

mode

= 3.0 V ± 10 % 0.02 5.00

= 25°C 0.02 3.00

Notes 1. The current flowing through the on-chip pull-up resistor is not included.

2. When the device operates in high-speed mode with the processor clock control register (PCC) set to

0011.

3. When the device operates in low-speed mode with PCC set to 0000.

6.0 MHz

crystal

oscillation

C1 = C2

= 22 pF

4.19 MHz

crystal

oscillation

C1 = C2

= 22 pF

DC Characteristics (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

PD75P4308

3 8

AC Characteristics (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Operates with V

= 2.7 to 5.5 V 0.67 64

system clock

0.95 64

TI0, TI1 input frequency f

= 2.7 to 5.5 V 0 1 MHz

0 275 kHz

TI0, TI1 input high-, t

TIH

, t

TIL

= 2.7 to 5.5 V 0.48

low-level widths

1.8

Interrupt input high-, t

INTH

, t

INTL

INT0 IM02 = 0 Note 2

low-level widths

IM02 = 1 10

INT1, 2, 4 10

KR0-7 10

RESET low-level width t

RSL

Notes 1. The cycle time (minimum instruction

execution time) of the CPU clock (

) is

determined by the oscillation frequency

of the connected resonator and proces-

sor clock control register (PCC).

The figure on the right shows the supply

voltage V

vs. cycle time t

character-

istics when the device operates with the

system clock.

2. 2t

or 128/f

depending on the setting

of the interrupt mode register (IM0).

CPU clock cycle time

Note 1

(minimum instruction execution
time = 1 machine cycle)

0.5

(with system clock)

vs V

Operation guaranteed range

Cycle time t

[ s]

Supply voltage V

[V]

PD75P4308

3 9

Serial transfer operation

2-wire and 3-wire serial I/O modes (SCK ··· internal clock output): (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY1

= 2.7 to 5.5 V 1300 ns

3800 ns

SCK high-, low-level t

KL1

, t

KH1

= 2.7 to 5.5 V t

KCY1

/250 ns

widths

KCY1

/2150 ns

Note 1

setup time (to SCK

)

SIK1

= 2.7 to 5.5 V 150 ns

500 ns

Note 1

hold time (from SCK

) t

KSI1

= 2.7 to 5.5 V 400 ns

600 ns

SCK

Note 1

output t

KSO1

= 1 k

= 2.7 to 5.5 V 0 250 ns

delay time C

= 100 pF

Note 2

0 1000 ns

Notes 1. In the 2-wire serial I/O mode, read SB0 instead.

2. R

and C

are the load resistance and load capacitance of the SO output line.

2-wire and 3-wire serial I/O modes (SCK ··· external clock input): (T

= 40 to +85°C, V

= 1.8 to 5.5 V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

SCK cycle time t

KCY2

= 2.7 to 5.5 V 800 ns

3200 ns

SCK high-, low-level t

KL2

, t

KH2

= 2.7 to 5.5 V 400 ns

widths

1600 ns

Note 1

setup time (to SCK

)

SIK2

= 2.7 to 5.5 V 100 ns

150 ns

Note 1

hold time (from SCK

) t

KSI2

= 2.7 to 5.5 V 400 ns

600 ns

SCK

Note 1

output t

KSO2

= 1 k

= 2.7 to 5.5 V 0 300 ns

delay time C

= 100 pF

Note 2

0 1000 ns

Notes 1. In the 2-wire serial I/O mode, read SB0 instead.

2. R

and C

are the load resistance and load capacitance of the SO output line.

PD75P4308

4 2

Interrupt input timing

INT0, 1, 2, 4
KR0-7

INTL

INTH

RESET input timing

RESET

RSL

Data retention characteristics of data memory in STOP mode and at low supply voltage

= 40 to +85°C)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

Release signal set time t

SREL

Oscillation stabilization t

WAIT

Released by RESET 2

wait time

Note 1

Released by interrupt request Note 2 ms

Notes 1. The oscillation stabilization wait time is the time during which the CPU stops operating to prevent

unstable operation when oscillation is started.

2. Set by the basic interval timer mode register (BTM). (Refer to the table below.)

BTM3 BTM2 BTM1 BTM0

Wait time

= 4.19 MHz f

= 6.0 MHz

(approx. 250 ms) 2

(approx. 175 ms)

(approx. 31.3 ms) 2

(approx. 21.8 ms)

(approx. 7.81 ms) 2

(approx. 5.46 ms)

(approx. 1.95 ms) 2

(approx. 1.37 ms)

PD75P4308

4 4

DC Programming Characteristics (T

= 25 ± 5°C, V

= 6.0 ± 0.25 V, V

= 12.5 ± 0.3 V, V

= 0V)

Parameter Symbol Conditions MIN. TYP. MAX. Unit

High-level input voltage V

IH1

Other than X1, X2 0.7 V

IH2

X1, X2 V

0.5 V

Low-level input voltage V

IL1

Other than X1, X2 0 0.3 V

IL2

X1, X2 0 0.4 V

Input leakage current I

= V

or V

High-level output voltage V

= 1 mA V

1.0 V

Low-level output voltage V

= 1.6 mA 0.4 V

supply current I

30 mA

supply current I

MD0 = V

, MD1 = V

30 mA

Cautions 1. Keep V

to within +13.5 V, including overshoot.

2. Apply V

before V

and turn it off after V

AC Programming Characteristics (T

= 25 ± 5°C, V

= 6.0 ± 0.25 V, V

= 12.5 ± 0.3 V, V

= 0 V)

Parameter Symbol Note 1 Conditions MIN. TYP. MAX. Unit

Address setup time

Note 2

(to MD0

)

MD1 setup time (to MD0

)

M1S

OES

Data setup time (to MD0

)

Address hold time

Note 2

(from MD0

)

Data hold time (from MD0

)

MD0

· Æ

data output float t

0 130 ns

delay time

setup time (to MD3

)

VPS

setup time (to MD3

)

VDS

VCS

Initial program pulse width t

0.95 1.0 1.05 ms

Additional program pulse width t

OPW

0.95 21.0 ms

MD0 setup time (to MD1

)

M0S

CES

MD0

Ø Æ

data output delay time t

MD0 = MD1 = V

MD1 hold time (from MD0

)

M1H

OEH

M1H

+ t

M1R

· 50

MD1 recovery time (from MD0

) t

M1R

Program counter reset time t

PCR

X1 input high-, low-level widths t

, t

-- 0.125

X1 input frequency f

-- 4.19 MHz

Initial mode set time t

MD3 setup time (to MD1

)

M3S

MD3 hold time (from MD1

)

M3H

MD3 setup time (to MD0

)

M3SR

-- When program memory is read 2

Address

Note 2

data output t

DAD

ACC

When program memory is read 2

delay time

Address

Note 2

data output t

HAD

When program memory is read 0 130 ns

hold time

MD3 hold time (from MD0

)

M3HR

-- When program memory is read 2

MD3

Ø Æ

data output float t

DFR

-- When program memory is read 2

delay time

Notes 1. Symbol of corresponding

PD27C256A

2. The internal address signal is incremented by one at the rising edge of the fourth X1 input and is not

connected to a pin.

PD75P4308

4 8

11. PACKAGE DRAWINGS

36 PIN PLASTIC SHRINK SOP (300 mil)

detail of lead end

5°±

5°

P36GM-80-300B-3

ITEM

MILLIMETERS

INCHES

15.54 MAX.

0.8 (T.P.)

1.8 MAX.

1.55

7.7±0.3

0.97 MAX.

0.612 MAX.

0.005±0.003

0.071 MAX.

0.303±0.012

0.220

0.039 MAX.

NOTE

0.10

0.6±0.2

1.1

5.6

0.004

0.024

+0.008
0.009

Each lead centerline is located within 0.10
mm (0.004 inch) of its true position (T.P.) at
maximum material condition.

0.043

0.061

0.031 (T.P.)

0.20

+0.10
0.05

0.008

+0.004
0.002

0.10

0.004

0.014

+0.004
0.003

0.35

0.125±0.075

+0.10
0.05

PD75P4308

4 9

12. RECOMMENDED SOLDERING CONDITIONS

Solder the

PD75P4308 under the following recommended conditions.

For the details on the recommended soldering conditions, refer to Information Document Semiconductor

Device Mounting Technology Manual (C10535E).

For the soldering methods and conditions other than those recommended, consult NEC.

Table 12-1. Soldering Conditions of Surface Mount Type

PD75P4308GS: 36-pin plastic shrink SOP (300 mil, 0.8-mm pitch)

Soldering method Soldering conditions Symbol

Infrared reflow Package peak temperature: 235°C, Reflow time: 30 seconds or below IR35-107-2

(210°C or higher), Number of reflow processes: 2 max., Exposure limit: 7 days

Note

(after that, prebaking is necessary at 125°C for 10 hours)

VPS Package peak temperature: 215°C, Reflow time: 40 seconds or below VP15-107-2

(200°C or higher), Number of reflow processes: 2 max., Exposure limit: 7 days

Note

(after that, prebaking is necessary at 125°C for 10 hours)

Wave soldering Solder temperature: 260°C or below, Flow time: 10 seconds or below, WS60-107-1

Number of flow processes: 1

Preheating temperature: 120°C or below (package surface temperature)

Exposure limit: 7 days

Note

(after that, prebaking is necessary at 125°C for

10 hours)

Pin partial heating Pin temperature: 300°C or below, Time: 3 seconds or below (per side of device)

Note The number of days for storage after the dry pack has been opened. Storage conditions are 25°C and 65%

RH max.

Caution Do not use two or more soldering methods in combination (except the pin partial heating method).

PD75P4308

5 0

APPENDIX A. COMPARISON OF

PD750004, 754304, AND 75P4308 FUNCTIONS

(1/2)

Item

PD750004

PD754304

PD75P4308

Program memory

Mask ROM

One-time PROM

0000H-0FFFH

0000H-1FFFH

(4096

8 bits)

(4096

8 bits)

(8192

8 bits)

Data memory

000H-1FFH

000H-0FFH

(512

4 bits)

(256

4 bits)

CPU

75XL CPU

Instruction

When main system

· 0.95, 1.91, 3.81, 15.3

s (@ 4.19 MHz)

execution time

clock is selected

· 0.67, 1.33, 2.67, 10.7

s (@ 6.0 MHz)

When subsystem

122

No subsystem clock

clock is selected

(@ 32.768 kHz)

I/O ports

CMOS input

8 (connections of on-chip pull-up resistors are software-specifiable: 7)

CMOS I/O

18 (connections of on-chip pull-up resistors are software-specifiable)

N-ch open-drain I/O

8 (on-chip pull-up resistors

4 (on-chip pull-up resistors

4 (No mask option)

(13-V withstand)

are specified by mask option) are specified by mask option)

Total

30 (No port 4 pin)

Timers

4 channels

3 channels

· Basic interval timer/

· Basic interval timer/watchdog timer

watchdog timer

· 8-bit timer/event counter 0 (fx/2

added)

· 8-bit timer/event counter

· 8-bit timer/event counter 1 (TI1, fx/2

added)

· 8-bit timer

(Can be used as a 16-bit timer/event counter)

· Watch timer

Clock output (PCL)

, 524, 262, 65.5 kHz

(main system clock: @ 4.19 MHz)

, 750, 375, 93.8 kHz

(main system clock: @ 6.0 MHz)

BUZ output

Yes

Serial interface

Can support three modes

Can support two modes

· 3-wire serial I/O mode

· 3-wire serial I/O mode...MSB/LSB-first switchable

...MSB/LSB-first switchable

· 2-wire serial I/O mode

· SBI mode

Watch mode register (WM)

Yes

System clock control register (SCC)

Sub-oscillator control register (SOS)

PD75P4308

5 2

APPENDIX B. DEVELOPMENT TOOLS

The following development tools are provided for system development using the

PD75P4308. In the 75XL series,

the common relocatable assembler is used together with the device file of each model.

RA75X relocatable assembler

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

S5A13RA75X

Ver.3.30 to

5" 2HD

S5A10RA75X

Ver.6.2

Note

IBM PC/AT

Refer to OS for

3.5" 2HC

S7B13RA75X

or compatible

IBM PCs

5" 2HC

S7B10RA75X

Device file

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

S5A13DF754304

Ver.3.30 to

5" 2HD

S5A10DF754304

Ver.6.2

Note

IBM PC/AT

Refer to OS for

3.5" 2HC

S7B13DF754304

or compatible

IBM PCs

5" 2HC

S7B10DF754304

Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function.

Remark Operations of the assembler and the device file are guaranteed only when using the host machine and

OS described above.

PD75P4308

5 3

PROM Write Tools

Hardware

PG-1500

A stand-alone system can be configured of a single-chip microcontroller with on-chip PROM

when connected to an auxiliary board (attached) and a programmer adapter (separately sold).

Alternatively, a PROM programmer can be operated on a host machine for programming.

In addition, typical PROMs in capacities ranging from 256 K to 4 Mbits can be programmed.

PA-75P4308GS

This is a PROM programmer adapter for the

PD75P4308GS. It can be used when connected

to a PG-1500.

Software

PG-1500 controller

Establishes serial and parallel connections between the PG-1500 and a host machine for host-

machine control of the PG-1500.

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

S5A13PG1500

Ver.3.30 to

5" 2HD

S5A10PG1500

Ver.6.2

Note

IBM PC/AT

Refer to OS for

3.5" 2HD

S7B13PG1500

or compatible

IBM PCs

5" 2HC

S7B10PG1500

Note Ver. 5.00 and above include a task swapping function, but this software is not able to use that function.

Remark Operation of the PG-1500 controller is guaranteed only when using the host machine and OS described

above.

PD75P4308

5 4

Debugging Tools

In-circuit emulators (IE-75000-R and IE-75001-R) are provided as program debugging tools for the

PD75P4308.

Various system configurations using these in-circuit emulators are listed below.

Hardware

IE-75000-R

Note 1

The IE-75000-R is an in-circuit emulator to be used for hardware and software debugging

during development of application systems that use 75X or 75XL Series products. For

development of the

PD754304 subseries, the IE-75000-R is used with a separately sold

emulation board (IE-75300-R-EM) and emulation probe (EP-754304GS-R).

These products can be applied for highly efficient debugging when connected to a host

machine and PROM programmer.

The IE-75000-R can include a connected emulation board (IE-75000-R-EM).

IE-75001-R

The IE-75001-R is an in-circuit emulator to be used for hardware and software debugging

during development of application systems that use 75X or 75XL Series products.

The IE-75001-R is used with a separately sold emulation board (IE-75300-R-EM) and

emulation probe (EP-754304GS-R).

These products can be applied for highly efficient debugging when connected to a host

machine and PROM programmer.

IE-75300-R-EM

This is an emulation board for evaluating application systems that use the

PD754304

subseries. It is used in combination with the IE-75000-R or IE-75001-R in-circuit emulator.

EP-754304GS-R

This is an emulation probe for the

PD75P4308.

EV-9500GS-36

When being used, it is connected with the IE-75000-R or IE-75001-R and the IE-75300-R-EM.

It includes a flexible board (EV-9500GS-36) to facilitate connections with various target

systems.

Software

IE control program

This program can control the IE-75000-R or IE-75001-R on a host machine when connected

to the IE-75000-R or IE-75001-R via an RS-232-C or Centronics interface.

Host machine

Part No. (name)

Supply medium

PC-9800 Series

MS-DOS

3.5" 2HD

S5A13IE75X

Ver.3.30 to

5" 2HD

S5A10IE75X

Ver.6.2

Note 2

IBM PC/AT

Refer to OS for

3.5" 2HC

S7B13IE75X

or compatible

IBM PCs

5" 2HC

S7B10IE75X

Notes 1. This is a service part provided for maintenance purpose only.

2. Ver. 5.00 and above include a task swapping function, but this software is not able to use that function.

Remarks 1. Operation of the IE control program is guaranteed only when using the host machine and OS

described above.

2. The

PD754302, 754304, and 75P4308 are commonly referred to as the

PD754304 subseries.

PD75P4308

5 6

APPENDIX C. RELATED DOCUMENTS

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Documents Related to Device

Document Name

Document Number

Japanese

English

PD754302, 754304 Data Sheet

U10797J

U10797E

PD75P4308 Data Sheet

U10909J

U10909E

(this document)

PD754304 User's Manual

U10123J

U10123E

PD754304 Instruction Table

IEM-5605

75XL Series Selection Guide

U10453J

U10453E

Documents Related to Development Tools

Document Name

Document Number

Japanese

English

Hardware

IE-75000-R/IE-75001-R User's Manual

EEU-846

EEU-1416

IE-75300-R-EM User's Manual

U11354J

U11354E

EP-754304GS-R User's Manual

U10677J

U10677E

PG-1500 User's Manual

EEU-651

EEU-1335

Software

RA75X Assembler Package

Operation

EEU-731

EEU-1346

User's Manual

Language

EEU-730

EEU-1363

PG-1500 Controller User's Manual

PC9800 Series (MS-DOS) base

EEU-704

EEU-1291

IBM PC/AT Series (PC DOS) base

EEU-5008

U10540E

Other Related Documents

Document Name

Document Number

Japanese

English

IC Package Manual

C10943X

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

Quality Grades on NEC Semiconductor Devices

C11531J

C11531E

NEC Semiconductor Device Reliability/Quality Control System

C10983J

C10983E

Electrostatic Discharge (ESD) Test

MEM-539

Guide to Quality Assurance for Semiconductor Devices

MEI-603

MEI-1202

Microcomputer-Related Product Guide Third Party Products

U11416J

Caution The related documents listed above are subject to change without notice. Be sure to use the latest

documents for designing, etc.

PD75P4308

5 8

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction

of the gate oxide and ultimately degrade the device operation. Steps must

be taken to stop generation of static electricity as much as possible, and

quickly dissipate it once, when it has occurred. Environmental control must

be adequate. When it is dry, humidifier should be used. It is recommended

to avoid using insulators that easily build static electricity. Semiconductor

devices must be stored and transported in an anti-static container, static

shielding bag or conductive material. All test and measurement tools

including work bench and floor should be grounded. The operator should

be grounded using wrist strap. Semiconductor devices must not be touched

with bare hands. Similar precautions need to be taken for PW boards with

semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no

connection is provided to the input pins, it is possible that an internal input

level may be generated due to noise, etc., hence causing malfunction. CMOS

devices behave differently than Bipolar or NMOS devices. Input levels of

CMOS devices must be fixed high or low by using a pull-up or pull-down

circuitry. Each unused pin should be connected to V

or GND with a

resistor, if it is considered to have a possibility of being an output pin. All

handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Produc-

tion process of MOS does not define the initial operation status of the device.

Immediately after the power source is turned ON, the devices with reset

function have not yet been initialized. Hence, power-on does not guarantee

out-pin levels, I/O settings or contents of registers. Device is not initialized

until the reset signal is received. Reset operation must be executed imme-

diately after power-on for devices having reset function.

PD75P4308

5 9

NEC Electronics Inc. (U.S.)

Santa Clara, California
Tel: 800-366-9782
Fax: 800-729-9288

NEC Electronics (Germany) GmbH

Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 0211-65 03 490

NEC Electronics (UK) Ltd.

Milton Keynes, UK
Tel: 01908-691-133
Fax: 01908-670-290

NEC Electronics Italiana s.r.1.

Milano, Italy
Tel: 02-66 75 41
Fax: 02-66 75 42 99

NEC Electronics Hong Kong Ltd.

Hong Kong
Tel: 2886-9318
Fax: 2886-9022/9044

NEC Electronics Hong Kong Ltd.

Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130
Tel: 253-8311
Fax: 250-3583

NEC Electronics Taiwan Ltd.

Taipei, Taiwan
Tel: 02-719-2377
Fax: 02-719-5951

NEC do Brasil S.A.

Sao Paulo-SP, Brasil
Tel: 011-889-1680
Fax: 011-889-1689

NEC Electronics (Germany) GmbH

Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 040-2444580

NEC Electronics (France) S.A.

Velizy-Villacoublay, France
Tel: 01-30-67 58 00
Fax: 01-30-67 58 99

NEC Electronics (France) S.A.

Spain Office
Madrid, Spain
Tel: 01-504-2787
Fax: 01-504-2860

NEC Electronics (Germany) GmbH

Scandinavia Office
Taeby, Sweden
Tel: 08-63 80 820
Fax: 08-63 80 388

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:

· Device availability

· Ordering information

· Product release schedule

· Availability of related technical literature

· Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

· Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.

J96. 8

5 8

PD75P4308

No part of this document may be copied or reproduced in any form or by any means without the prior written consent
of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use of
such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property
arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in
its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment and
industrial robots

Special:

Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for
life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support

systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they
should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.

M4 96.5

The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.

MS-DOS is a trademark of Microsoft Corporation.

IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.

Document Outline

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD78P9014

Document Outline

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: UPD78P9014