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Электронный компонент: UPD8670A

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2004
MOS INTEGRATED CIRCUIT
PD8670A
7400 PIXELS CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S17147EJ1V0DS00 (1st edition)
Date Published August 2004 NS CP (K)
Printed in Japan
The
PD8670A is a high sensitive and high-speed CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The
PD8670A is a 2-output type CCD sensor with 2 rows of high-speed charge transfer register, which transfers the
photo signal electrons of 7400 pixels separately in odd and even pixels. And it has reset feed-through level clamp circuits
and voltage amplifiers. Therefore, it is suitable for 600 dpi/A3 high-speed digital copiers, multi-function products and so on.
FEATURES
Valid photocell : 7400 pixels
Photocell pitch : 4.7
m
Photocell size
: 4.7
4.7
m
2
Resolution
: 24 dot/mm (600 dpi) A3 (297
420 mm) size (shorter side)
Data rate
: 44 MHz MAX. (22 MHz/1 output)
Output type
: 2 outputs in-phase operation, and out of phase also supported
High sensitivity : 17.0 V/lxs TYP. (Light source: Daylight color fluorescent lamp)
Peak response wavelength : 550 nm (green)
Low image lag : 1 % MAX.
Drive clock level : CMOS output under +5 V operation
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
:
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8670ACY
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Data Sheet S17147EJ1V0DS
2
PD8670A
DIFFERENCE BETWEEN
PD8670ACY AND
PD3747D
Part Item
PD8670ACY
PD3747D
Referential
Page
Features
Output type
2 outputs out of phase or in phase
2 outputs in phase only
1
Sensitivity (Daylight
color fluorescent lamp)
TYP. 17 V/lx
s
TYP. 19 V/lx
s
Ordering information
Package
32-pin plastic DIP
22-pin ceramic DIP (CERDIP)
Pin configuration
Input clock
4
Block diagram
3
Application circuit
CP1,
CP2 separated,
R1,
R2 separated,
2L1,
2L2 separated
(Output: in/out of phase)
CP common,
R common,
2L common
(Output: in phase)
21
example
Equivalent circuit Tr.
2SA1206, 2SC1842
2SA1005, 2SC945
Absolute maximum
ratings
Operating ambient
temperature
0 to +60C
25 to +55C
5
Storage temperature
40 to +70C
40 to +100C
Recommended
operating condition
Each clock amplitude
Addition of specifications
(from 4.5 V to 5.8 V)
Electrical
characteristics
ADS, DSNU, DR1,
DR2
Change of specifications
6
R
F
TYP. 17 V/lx
s
TYP. 19 V/lx
s
RFTN
Addition of PRFTN, RFTN1,
RFTN2
Only RFTN
t
d
TYP. 13 ns
Addition of min. max.
TYP. 14 ns
bit,
line,
shot
Addition of condition (t6)
Input pin capacitance Capacitance
Change of specification
Addition of note
7
Timing chart
Operation
Addition of out-of-phase
timing chart
8,
9
t6
MIN. 5 ns
MIN. 0 ns
12, 14
t10
MIN. 0 ns
MIN. t3
t13, t16, t17
MAX. 10000 ns
14
Close point
Change of specifications
15
Definitions V
OS
, RFTN
Additional item
19
Recommended
soldering condition
Partial heating method
350C or blow, 3 seconds or less
300C or blow, 3 seconds or less
24
Package drawing
Package
32-pin plastic DIP
22-pin ceramic DIP (CERDIP)
23
Cap
Plastic cap 0.7t
Glass cap 0.7t
From CCD to bottom
of package
2.45
0.3 mm
2.38
0.3 mm
From CCD to top of
cap
(2.0) mm
(1.95) mm
Remark T
A
= +25C, V
OD
= 12 V
Data Sheet S17147EJ1V0DS
3
PD8670A
BLOCK DIAGRAM
Transfer gate
Transfer gate
CCD analog shift register
CCD analog shift register
D1
D6
S2
S1
S7399
S7400
D7
D12
OB1
OB96
22
23
24
28
29
30
32
1
31
10
11
9
5
4
TG
12
22
21
11
2L1
V
OUT
2
(Even)
V
OUT
1
(Odd)
GND
GND
2L2
R2
CP2
R1
3
CP1
2
V
OD
Data Sheet S17147EJ1V0DS
4
PD8670A
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
PD8670ACY
1
2
3
4
5
6
7
8
9
10
11
NC
IC
V
OUT
2
GND
IC
22
2L2
R2
2L1
CP1
CP2
12
Internal connection
Reset feed-through level clamp clock 2
No connection
Output signal 2 (Even)
Ground
Reset gate clock 2
Internal connection
Shift register clock 2-2
Transfer gate clock
V
OUT
1
V
OD
Output signal 1 (Odd)
Output drain voltage
Reset feed-through level clamp clock 1
Shift register clock 1-1
IC
Internal connection
IC
Internal connection
Last stage shift register clock 2
Shift register clock 1-2
Shift register clock 2-1
11
21
R1
GND
Ground
Reset gate clock 1
Last stage shift register clock 1
No connection
NC
12
13
14
IC
Internal connection
IC
Internal connection
No connection
NC
15
16
NC
No connection
NC
No connection
TG
32
31
30
29
28
27
26
25
24
23
22
IC
IC
Internal connection
Internal connection
21
20
NC
No connection
19
NC
No connection
18
NC
No connection
17
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
PHOTOCELL STRUCTURE DIAGRAM
4.7
3.2
m
1.5
Channel stopper
Aluminum
shield
m
m
Data Sheet S17147EJ1V0DS
5
PD8670A
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
C)
Parameter Symbol
Ratings
Unit
Output drain voltage
V
OD
-0.3 to +14.0
V
Shift register clock voltage
V
1
, V
2
-0.3 to +8.0
V
Last stage shift register clock voltage
V
2L
-0.3 to +8.0
V
Reset gate clock voltage
V
R
-0.3 to +8.0
V
Transfer gate clock voltage
V
TG
-0.3 to +8.0
V
Reset feed-through level clamp clock voltage
V
CP
-0.3 to +8.0
V
Operating ambient temperature
Note
T
A
0 to +60
C
Storage temperature
T
stg
-40 to +70
C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
= +25
C)
Parameter Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Output drain voltage
V
OD
11.4 12.0 12.6 V
Shift register clock high level
V
1H
, V
2H
4.5 5.0 5.5 V
Shift register clock low level
V
1L
, V
2L
-0.3 0 +0.5 V
Last stage shift register clock high level
V
2LH
4.5 5.0 5.5 V
Last stage shift register clock low level
V
2LL
-0.3 0 +0.5 V
Reset gate clock high level
V
RH
4.5 5.0 5.5 V
Reset gate clock low level
V
RL
-0.3 0 +0.5 V
Reset feed-through level clamp clock high level
V
CPH
4.5 5.0 5.5 V
Reset feed-through level clamp clock low level
V
CPL
-0.3 0 +0.5 V
Transfer gate clock high level
V
TGH
4.5 5.0 5.5 V
Transfer gate clock low level
V
TGL
-0.3 0 +0.5 V
Shift register clock amplitude
V
1_pp
,
f < 10 MHz/ch
4.0
5.0
5.8
V
V
2_pp
f
10 MHz/ch
4.5
5.0
5.8
V
Last stage shift register clock amplitude
V
2L_pp
4.5 5.0 5.8 V
Reset gate clock amplitude
V
R_pp
4.5 5.0 5.8 V
Reset feed-through level clamp clock amplitude
V
CP_pp
4.5 5.0 5.8 V
Transfer gate clock amplitude
V
TG_pp
4.5 5.0 5.8 V
Data rate
2f
R
1
2
44 MHz
Data Sheet S17147EJ1V0DS
6
PD8670A
ELECTRICAL CHARACTERISTICS
T
A
= +25
C, V
OD
= 12 V, f
R
= 1 MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp + C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol Test
Conditions
MIN.
TYP.
MAX.
Unit
Saturation voltage
V
sat
1.5 2.0
-
V
Saturation exposure
SE
Daylight color fluorescent lamp
-
0.10
-
lx
s
Photo response non-uniformity
PRNU
V
OUT
= 500 mV
-
5.0 10.0 %
Average dark signal
ADS
Light shielding
-
1.0 6.0 mV
Dark signal non-uniformity DSNU
Light
shielding
-
16.0 28.0 mV
Power consumption
P
W
-
350 420 mW
Output impedance
Z
O
-
0.2 0.3 k
Response R
F
Daylight color fluorescent lamp
13.6
17.0
20.4
V/lx
s
Image lag
IL
V
OUT
= 500 mV
-
0.5 1.0 %
Offset level
Note 1
V
OS
3.7 4.7 5.7
V
Output fall delay time
Note 2
t
d
V
OUT
= 500 mV
11.0
13.0
15.0
ns
Total transfer efficiency
TTE
V
OUT
= 1 V, data rate = 44 MHz
94
98
-
%
Register imbalance
RI
V
OUT
= 500 mV
0
1.0
4.0
%
Response peak
-
550
-
nm
DR1 V
sat
/DSNU
-
125
-
times
Dynamic range
DR2 V
sat
/
bit, t6
20 ns
-
1000
-
times
Reset feed-through noise
Note 1
PRFTN
Light shielding, t4 = 5 ns
- +0.4
-
V
RFTN1
-1.0
-0.4
+0.2 V
RFTN2
-0.3
+0.2
+0.7 V
Random noise
bit
Light shielding,
t6 = 5 ns
-
2.6
-
mV
bit clamp mode
t6
20 ns
-
2.0
-
mV
line
Light shielding,
t6
5 ns
-
8.0
-
mV
line clamp mode
Shot noise
shot
V
OUT
= 500 mV,
t6
5 ns
-
10.0
-
mV
bit clamp mode
Notes 1. Refer to 13 and 14 of DEFINITION OF CHARACTERISTIC ITEMS.
2. When the fall time of
2L (t2') is the TYP. value (refer to TIMING CHART 5, 6). Note that V
OUT
1 and V
OUT
2 are
the outputs of the two steps of emitter-follower shown in APPLICATION CIRCUIT EXAMPLE.
Data Sheet S17147EJ1V0DS
7
PD8670A
INPUT PIN CAPACITANCE (T
A
= +25
C, V
OD
= 12 V)
Parameter
Symbol
Pin name
Pin No.
MIN.
TYP.
MAX.
Unit
Shift register clock pin capacitance 1
C
1
Note
11
9
225 250 275 pF
12
23 200 220 240 pF
Shift register clock pin capacitance 2
C
2
Note
21
10 200 220 240 pF
22
24 225 250 275 pF
Last stage shift register clock pin capacitance
C
L
2L1
5 4 5 6 pF
2L2 28 4 5 6 pF
Reset gate clock pin capacitance
C
R
R1
4 4 5 6 pF
R2
29 4 5 6 pF
Reset feed-through level clamp clock pin capacitance
C
CP
CP1 3 7 8 9 pF
CP2 30 7 8 9 pF
Transfer gate clock pin capacitance
C
TG
TG
22 240 270 300 pF
Note C
1
, C
2
are equivalent capacitance with driving device, including the co-capacitance between
1 and
2.
Remark Pins 9 and 23 (
11 and
12), Pins 10 and 24 (
21 and
22) aren't each connected inside of the device.
Data S
heet
S1714
7EJ1V0DS
8
PD8670A
TG
11
21
R1
CP1
CP2
2L1
12
22
R2
2L2
35
125
127
129
131
133
1
3
5
29
31
33
137
135
7531
7541
7533
7537
7539
7535
36
126
128
130
132
134
2
4
6
30
32
34
138
136
7532
7542
7534
7538
7540
7536
V
OUT
1
V
OUT
2
Note
Optical black
(96 pixels)
Dummy cell
(32 pixels)
Valid photocells
(7400 pixels)
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the R1,
CP2 to low level during this period.
CP1 and
R2,
TIMING CHART 1 (Bit clamp mode, Out of phase operation)
Data S
heet
S1714
7EJ1V0DS
9
PD8670A
TG
11
21
R1
CP1
CP2
2L1
12
22
R2
2L2
35
125
127
129
131
133
1
3
5
29
31
33
137
135
7531
7541
7533
7537
7539
7535
36
126
128
130
132
134
2
4
6
30
32
34
138
136
7532
7542
7534
7538
7540
7536
V
OUT
1
V
OUT
2
Note Set the R1,
CP2 to low level during this period.
CP1 and
R2,
Note
Optical black
(96 pixels)
Dummy cell
(32 pixels)
Valid photocells
(7400 pixels)
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
TIMING CHART 2 (Line clamp mode, Out of phase operation)
Data S
heet
S1714
7EJ1V0DS
10
PD8670A
TG
12
11,
22
21,
R2
R1,
CP2
CP1,
2L2
2L1,
35
125
127
129
131
133
1
3
5
29
31
33
137
135
7531
7541
7533
7537
7539
7535
36
126
128
130
132
134
2
4
6
30
32
34
138
136
7532
7542
7534
7538
7540
7536
V
OUT
1
V
OUT
2
Note
Optical black
(96 pixels)
Dummy cell
(32 pixels)
Valid photocells
(7400 pixels)
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
Note Set the R1,
CP2 to low level during this period.
CP1 and
R2,
TIMING CHART 3 (Bit clamp mode, In phase operation)
Data S
heet
S1714
7EJ1V0DS
11
PD8670A
TG
12
11,
22
21,
R2
R1,
CP2
CP1,
2L2
2L1,
35
125
127
129
131
133
1
3
5
29
31
33
137
135
7531
7541
7533
7537
7539
7535
36
126
128
130
132
134
2
4
6
30
32
34
138
136
7532
7542
7534
7538
7540
7536
V
OUT
1
V
OUT
2
Note Set the R1,
CP2 to low level during this period.
CP1 and
R2,
Note
Optical black
(96 pixels)
Dummy cell
(32 pixels)
Valid photocells
(7400 pixels)
Invalid photocell
(6 pixels)
Invalid photocell
(6 pixels)
TIMING CHART 4 (Line clamp mode, In phase operation)
Data Sheet S17147EJ1V0DS
12
PD8670A
TIMING CHART 5 (Bit clamp mode)
V
OS
t1
t1'
t2
t2'
t3 t5 t6
t4
t
d
11
21
R1
CP1
V
OUT
1
2L1
10%
10%
90%
t7
t9
t11
t8
t10
10%
90%
10%
90%
10%
10%
90%
90%
Symbol MIN. TYP. MAX. Unit
t1, t2
0
50
-
ns
t1', t2'
0
5
-
ns
t3 10
125
-
ns
t4, t5
0
5
-
ns
t6 5
125
-
ns
t7 5
125
-
ns
t8, t9
0
5
-
ns
t10 0
125
-
ns
t11 0
250
-
ns
Caution This shows timing chart of V
OUT
1 side (
11,
21,
2L1,
R1,
CP1, V
OUT
1). The timing chart of V
OUT
2
side (
12,
22,
2L2,
R2,
CP2, V
OUT
2) is equal.
Data Sheet S17147EJ1V0DS
13
PD8670A
TIMING CHART 6 (Line clamp mode)
V
OS
t1
t1'
t2
t2'
t3 t5
t12
t4
t
d
11
21
R1
CP1
V
OUT
1
2L1
10%
10%
90%
10%
90%
10%
10%
90%
90%
"L"
Symbol MIN. TYP. MAX. Unit
t1, t2
0
50
-
ns
t1', t2'
0
5
-
ns
t3 10
125
-
ns
t4, t5
0
5
-
ns
t12 5
250
-
ns
Caution This shows timing chart of V
OUT
1 side (
11,
21,
2L1,
R1,
CP1, V
OUT
1). The timing chart of V
OUT
2
side (
12,
22,
2L2,
R2,
CP2, V
OUT
2) is equal.
Data Sheet S17147EJ1V0DS
14
PD8670A
TIMING CHART 7 (Bit clamp mode, Line clamp mode)
t16
t14
t13
t15
t3 t5
t6
t17
t4
TG
R1
CP1
11
2L1
21,
10%
90%
t7 t9
t11
t10
t8
10%
90%
90%
90%
10%
90%
Note
Note Set the
R and
CP to low level during this period.
Symbol MIN. TYP. MAX. Unit
t3 10
125
-
ns
t4, t5
0
5
-
ns
t6 5
125
-
ns
t7 5
125
-
ns
t8, t9
0
5
-
ns
t10 0
125
-
ns
t11 0
250
-
ns
t13 1000
1500
10000
ns
t14, t15
0
50
-
ns
t16, t17
200
300
10000
ns
Caution This shows timing chart of V
OUT
1 side (
11,
21,
2L1,
R1,
CP1, V
OUT
1). The timing chart of V
OUT
2
side (
12,
22,
2L2,
R2,
CP2, V
OUT
2) is equal.
Data Sheet S17147EJ1V0DS
15
PD8670A
11, 21 cross points
11, 2L1 cross points
11
21
1.5 V or more
1.5 V or more
11
2L1
1.5 V or more
0 V or more

 12, 22 cross points
12, 2L2 cross points
12
22
1.5 V or more
1.5 V or more
12
2L2
1.5 V or more
0 V or more
Remark Adjust cross points of (
11,
21), (
11,
2L1), (
12,
22) and (
12,
2L2) with input resistance of each pin.
11, 12, 21, 22, 2L1, 2L2 clock width
0 ns or more
0 ns or more
11,
12,
21,
22,
2L1,
2L2
0.5 V
4.5 V
Data Sheet S17147EJ1V0DS
16
PD8670A
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light of
uniform illumination. This is calculated by the following formula.
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x: maximum of x
j
- x
x
7400
j = 1
7400
x
j
100
x
Register dark
DC level
V
OUT
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
7400
j = 1
7400
d
j
Data Sheet S17147EJ1V0DS
17
PD8670A
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid
pixels at light shielding. This is calculated by the following formula.
d
j
: Dark signal of valid pixel number j
DSNU (mV): maximum of
d
j
- ADS
j = 1 to 7400
ADS
DSNU
Register dark
DC level
V
OUT
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx
s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
9. Total transfer efficiency : TTE
The total transfer rate of CCD analog shift register. This is calculated by the following formula, it is difined by each
output.
TTE (%) = (1
- V
b
/ average output of all the valid pixels)
100
V
a
-1
: The last pixel output
- 1 (Odd pixel: 7537th pixel)
V
a
: The last pixel output (Odd pixel: 7539th pixel)
V
b
: The spilt pixel output (Odd pixel: 7541st pixel)
V
a
-1
V
a
V
b
Data Sheet S17147EJ1V0DS
18
PD8670A
10. Register imbalance : RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average
output voltage of all the valid pixels.
RI (%) =
2
n
j = 1
n
2
(V
2j 1
V
2j
)
1
n
j = 1
n
V
j
100
: Number of valid pixels
: Output voltage of each pixel
n
V
j
11. Random noise :
Random
noise
is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines)
data sampling at dark (light shielding).
(mV) =
, V =
i = 1
100
(V
i
V)
2
i = 1
100
V
i
100
100
1
V
i
: A valid pixel output signal among all of the valid pixels
V
1
V
100
V
2
...
...
line 2
line 100
line 1
V
OUT
This is measured by the DC level sampling of only the signal level, not by CDS (Correlated Double Sampling).
12. Shot noise :
shot
Shot noise is defined as the standard deviation of a valid pixel output signal with 100 times (= 100 lines) data
sampling in the light. This includes the random noise.
The formula is the same with that of random noise.
Data Sheet S17147EJ1V0DS
19
PD8670A
13. Offset level : V
OS
DC level of output signal is defined as follows.
14. Reset feed-through noise and peak reset feed-through noise : RFTN and PRFTN
RTFN is switching noise of
R and
CP. Reset feed-through noise (RFTN) and peak of RFTN (PRFTN) are
defined as follows.
<1> Bit clamp operation
V
OS
PRFTN
RFTN1
RFTN2
CP1
V
OUT
1
R1
2L1
Caution This shows timing of V
OUT
1 side (
2L1,
R1,
CP1, V
OUT
1). The definition of V
OUT
2 side (
2L2,
R2,
CP2, V
OUT
2) is equal.
<2> Line clamp operation
V
OS
PRFTN
CP1
"L"
V
OUT
1
R1
2L1
RFTN1
Caution This shows timing of V
OUT
1 side (
2L1,
R1,
CP1, V
OUT
1). The definition of V
OUT
2 side (
2L2,
R2,
CP2, V
OUT
2) is equal.
Data Sheet S17147EJ1V0DS
20
PD8670A
STANDARD CHARACTERISTIC CURVES (Reference Value)
0
10
20
30
40
50
0.1
0.25
1
2
0.5
4
8
5
10
1
0.1
0.2
1
2
1200
600
400
1000
800
0
20
40
60
80
100
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
=
+25C)
Operating Ambient Temperature T
A
(
C)
Relative Output Voltage
Relative Output Voltage
Storage Time (ms)
Wavelength (nm)
Response Ratio (%)
TOTAL SPECTRAL RESPONSE CHARACTERISTIC
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
Data Sheet S17147EJ1V0DS
21
PD8670A
APPLICATION CIRCUIT EXAMPLE
V
OUT
1
PD8670A
GND
GND
V
OD
22
12
11
21
TG
1
32
31
30
29
28
27
26
25
2
V
OUT
2
IC
IC
IC
IC
NC
IC
IC
NC
NC
NC
NC
IC
IC
NC
NC
NC
CP2
B2
B1
+5 V
CP2
R2
2L2
CP1
CP1
R1
R1
2L1
2L1
R2
2L2
+12 V
0.1 F
10 F/16 V
47
47
47
47
47
47
24
2
23
2
2
2
22
21
10
20
19
18
17
3
4
5
6
7
8
9
10
11
12
13
14
15
16
+5 V
0.1 F
10 F/16 V
0.1 F
47 F/25 V
22
12
TG
11
21
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26 and 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remark The inverters shown in the above application circuit example are the 74AC04.
Data Sheet S17147EJ1V0DS
22
PD8670A
+12 V
110
4.7 k
47 F/25 V
2SA1206
2SC1842
1 k
47
+
CCD
V
OUT
B1, B2 EQUIVALENT CIRCUIT
Output
Data Sheet S17147EJ1V0DS
23
PD8670A
PACKAGE DRAWING
55.2
0.5
54.8
0.5
12.6
0.5
9.05
0.3
9.25
0.3
4.1
0.5
1st valid pixel
3.2
0.3
1
4
4
32
17
16
1
2.0
46.7
2.54
0.25
0.46
0.1
1.02
0.15
(5.42)
4.21
0.5
4.55
0.5
(2.0)
2.45
0.3
0.25
0.05
10.16
0.20
3
5
2
10.16
+0.70
-0.20
Name
Dimensions
Refractive index
Plastic cap
52.2
6.40.8 (0.7 )
1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
4 Mirror finishied surface
5 Thickness of mirror finished surface
32C-1CCD-PKG10-2
(Unit : mm)
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
PD8670CY, PD8670ACY
Data Sheet S17147EJ1V0DS
24
PD8670A
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to
consult with our sales offices.
Type of Through-hole Device
PD8670ACY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method
Pin temperature : 350
C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S17147EJ1V0DS
25
PD8670A
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 M
.
4
3
RECOMMENDED SOLVENTS
Solvents
Symbol
Data Sheet S17147EJ1V0DS
26
PD8670A
[ NOTE ]
Data Sheet S17147EJ1V0DS
27
PD8670A
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
PD8670A
The information in this document is current as of August, 2004. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not
all products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
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Descriptions of circuits, software and other related information in this document are provided for illustrative
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The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
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(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
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"Standard":
"Special":
"Specific":