Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- INPUT PIN CAPACITANCE
- TIMING CHART 1 (for each color)
- TIMING CHART 2 (Bit clamp mode, for each color)
- TIMING CHART 3 (Line clamp mode, for each color)
- TIMING CHART 4
-
-
- DEFINITIONS OF CHARACTERISTIC ITEMS
- STANDARD CHARACTERISTIC CURVES (Nominal)
- APPLICATION CIRCUIT EXAMPLE
- PACKAGE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
2000
MOS INTEGRATED CIRCUIT
PD8861
5400 PIXELS
3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
The mark shows major revised points.
Document No. S15167EJ2V0DS00 (2nd edition)
Date Published June 2001 NS CP (K)
Printed in Japan
DESCRIPTION
The
PD8861 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD8861 has 3 rows of 5400 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 600 dpi/A4 color
image scanners, color facsimiles and so on.
FEATURES
Valid photocell
: 5400 pixels
3
Photocell pitch
: 5.25
m
Photocell size
: 5.25
5.25
m
2
Line spacing
: 42
m (8 lines) Red line - Green line, Green line - Blue line
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 24 dot/mm A4 (210
297 mm) size (shorter side)
:
600 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 6 MHz Max.
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
::
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8861CY
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Data Sheet S15167EJ2V0DS
2
PD8861
BLOCK DIAGRAM
21
22
1
20
2
11
15
14
13
12
10
9
8
5
D14
D64
D65
D66
S5399
S5400
S1
S2
Photocell
(Red)
Transfer gate
CCD analog shift register
D67
TG1
(Blue)
TG2
(Green)
TG3
(Red)
1L
3
RB
2
1
2
1
GND
GND
V
OD
V
OUT
3
(Red)
V
OUT
2
(Green)
V
OUT
1
(Blue)
4
CLB
D14
D64
D65
D66
S5399
S5400
S1
S2
Photocell
(Green)
Transfer gate
CCD analog shift register
D67
D14
D64
D65
D66
S5399
S5400
S1
S2
Photocell
(Blue)
Transfer gate
CCD analog shift register
D67
Data Sheet S15167EJ2V0DS
3
PD8861
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD8861CY
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
Blue photocell array
5.25 m
Green photocell array
5.25 m
Red photocell array
5.25 m
8 lines
(42 m)
8 lines
(42 m)
5.25 m
2.75 m
m
2.5
Channel stopper
Aluminum
shield
1
2
3
4
5
6
7
8
9
10
11
NC
V
OUT
2
V
OUT
1
NC
1
2
TG1
No connection
NC
No connection
NC
No connection
Output signal 2 (Green)
Output signal 1 (Blue)
No connection
Shift register clock 1
Shift register clock 2
Transfer gate clock 2
(for Green)
V
OUT
3
GND
TG3
Output signal 3 (Red)
Ground
Reset gate clock
Shift register clock 1
Shift register clock 2
NC
No connection
NC
No connection
5400
5400
5400
Red
Green
Blue
1
1
1
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
Output drain voltage
V
OD
1
2
GND
Ground
RB
Reset feed-through level clamp clock
CLB
1L
Last stage shift register clock 1
TG2
22
21
20
19
18
17
16
15
14
13
12
Data Sheet S15167EJ2V0DS
4
PD8861
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
+
+
+25C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
-0.3 to +15
V
Shift register clock voltage
V
1
, V
2
, V
1L
-0.3 to +8
V
Reset gate clock voltage
V
RB
-0.3 to +8
V
Reset feed-through level clamp clock
voltage
V
CLB
-0.3 to +8
V
Transfer gate clock voltage
V
TG1
to V
TG3
-0.3 to +8
V
Operating ambient temperature
T
A
0 to
+60
C
Storage temperature
T
stg
-40 to +70
C
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
+
+
+25C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
1H
, V
2H
, V
1LH
4.5
5.0
5.5
V
Shift register clock low level
V
1L
, V
2L
, V
1LL
-0.3
0
+0.5
V
Reset gate clock high level
V
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
RBL
-0.3
0
+0.5
V
Reset feed-through level clamp clock
high level
V
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock
low level
V
CLBL
-0.3
0
+0.5
V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.5
V
1H
Note
V
1H
Note
V
Transfer gate clock low level
V
TG1L
to V
TG3L
-0.3
0
+0.3
V
Data rate
f
RB
-
1.0
6.0
MHz
Note
When Transfer gate clock high level (V
TG1H
to V
TG3H
) is higher than Shift register clock high level (V
1H
),
Image lag can increase.
Data Sheet S15167EJ2V0DS
5
PD8861
ELECTRICAL CHARACTERISTICS
T
A
=
+25C, V
OD
= 12 V, data rate (f
RB
) = 1 MHz, storage time = 5.5 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp
+ C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Saturation voltage
V
sat
2.0
2.5
-
V
Red
SER
-
0.420
-
lxs
Green
SEG
-
0.429
-
lxs
Saturation exposure
Blue
SEB
-
0.739
-
lxs
Photo response non-uniformity
PRNU
V
OUT
= 1.0 V
-
6
20
%
Average dark signal
ADS
Light shielding
-
0.2
2.0
mV
Dark signal non-uniformity
DSNU
Light shielding
-
1.5
5.0
mV
Power consumption
P
W
-
360
540
mW
Output impedance
Z
O
-
0.35
1
k
Red
R
R
4.15
5.94
7.72
V/lxs
Green
R
G
4.07
5.82
7.57
V/lxs
Response
Blue
R
B
2.36
3.38
4.39
V/lxs
Image lag
IL
V
OUT
= 1.0 V
-
1.5
7.0
%
Offset level
Note 1
V
OS
4.0
5.5
7.0
V
Output fall delay time
Note 2
t
d
V
OUT
= 1.0 V
-
25
-
ns
Total transfer efficiency
TTE
V
OUT
= 1.0 V, data rate = 6 MHz
92
98
-
%
Red
-
630
-
nm
Green
-
540
-
nm
Response peak
Blue
-
460
-
nm
DR1
V
sat
/DSNU
-
1666
-
times
Dynamic range
DR2
V
sat
/
CDS
-
2777
-
times
Reset feed-through noise
Note 1
RFTN
Light shielding
0
750
1500
mV
Random noise (CDS)
CDS
Light shielding, bit clamp mode
-
0.9
-
mV
Notes 1. Refer to TIMING CHART 2, 3.
2. When the fall time of
1L (t1') is the Typ. value (refer to TIMING CHART 2, 3).
Data Sheet S15167EJ2V0DS
6
PD8861
INPUT PIN CAPACITANCE (T
A
=
+
+
+
+25C, V
OD
= 12 V)
Parameter
Symbol
Pin name
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
C
1
1
9
-
300
-
pF
14
-
300
-
pF
Shift register clock pin capacitance 2
C
2
2
8
-
300
-
pF
15
-
300
-
pF
Last stage shift register clock pin capacitance
C
L
1L
5
-
10
-
pF
Reset gate clock pin capacitance
C
RB
RB
3
-
10
-
pF
Reset feed-through level clamp clock pin capacitance
C
CLB
CLB
4
-
10
-
pF
Transfer gate clock pin capacitance
TG1
13
-
100
-
pF
TG2
12
-
100
-
pF
C
TG
TG3
10
-
100
-
pF
Remark Pin 9 and 14 (
1), 8 and 15 (
2) are each connected inside of the device.
Data S
h
e
e
t S
151
67E
J
2
V
0
DS
7
PD8861
TIMING CHART 1 (for each color)
Note Set the
RB and
CLB (Bit clamp mode) to high level during this period.
And stop the
RB pulse while the
CLB pulse is low level at line clamp mode.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB at line clamp mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
5463
5464
5465
5466
5467
5468
5469
V
OUT
1 to V
OUT
3
RB
CLB
(Bit clamp mode)
CLB
(Line clamp mode)
1L
Note
Invalid photocell
(3 pixels)
Invalid photocell
(2 pixels)
Valid photocell
(5400 pixels)
Optical black
(49 pixels)
2
1
TG1 to
TG3
Note
Data Sheet S15167EJ2V0DS
8
PD8861
TIMING CHART 2 (Bit clamp mode, for each color)
Symbol
Min.
Typ.
Max.
Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3
20
200
-
ns
t4
40
300
-
ns
t5, t6
0
5
-
ns
t7
-5
Note
50
-
ns
t8
35
200
-
ns
t9, t10
0
5
-
ns
t11
10
50
-
ns
Note Min. of t7 shows that the
RB and
CLB overlap each other.
V
OUT
CLB
RB
2
1
90%
10%
1L
90%
10%
90%
10%
90%
10%
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
90%
10%
t10
t8
t11
t7
t9
t2'
t1'
10%
CLB
RB
90%
90%
t7
Data Sheet S15167EJ2V0DS
9
PD8861
TIMING CHART 3 (Line clamp mode, for each color)
Symbol
Min.
Typ.
Max.
Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3
20
200
-
ns
t4
40
300
-
ns
t5, t6
0
5
-
ns
V
OUT
CLB
RB
2
1
90%
10%
1L
90%
10%
90%
10%
90%
10%
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
t2'
t1'
10%
"H"
Data Sheet S15167EJ2V0DS
10
PD8861
TIMING CHART 4
Symbol
Min.
Typ.
Max.
Unit
t7
-5
Note 3
50
-
ns
t9, t10
0
5
-
ns
t11
10
50
-
ns
t12
3000
10000
50000
ns
t13, t14
0
50
-
ns
t15, t16
900
1000
-
ns
t17, t18
200
400
-
ns
t19
t12
t12
50000
ns
t20, t21
0
50
-
ns
t22, t23
0
350
-
ns
Notes 1. Set the
RB and
CLB (Bit clamp mode) to high level during this period.
2. Stop the
RB pulse during this period.
3. Min. of t7 shows that the
RB and
CLB overlap each other.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
RB
CLB
(Bit clamp mode)
1L
2
TG1 to
TG3
CLB
(Line clamp mode)
1
10%
90%
90%
90%
90%
90%
90%
10%
t12
t13
t17
t7
t19
t9
t20
t10
t23
t21
t22
t11
Note 1
Note 2
t18
t16
t15
t14
Data Sheet S15167EJ2V0DS
11
PD8861
1,
2 cross points
1L,
2 cross points
Remark Adjust cross points (
1,
2) and (
1L,
2) with input resistance of each pin.
2
1L
2.0 V or more
0.5 V or more
1
2
1.0 V to 4.0 V
1.0 V to 4.0 V
Data Sheet S15167EJ2V0DS
12
PD8861
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x : maximum of
x
j
- x
x
5400
j = 1
5400
x
j
100
x
Register Dark
DC level
V
OUT
x
ADS (mV) =
d
j
: Dark signal of valid pixel number j
5400
j = 1
5400
d
j
Data Sheet S15167EJ2V0DS
13
PD8861
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lxs).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
ADS
DSNU
Register Dark
DC level
V
OUT
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of
d
j
- ADS
j = 1 to 5400
Data Sheet S15167EJ2V0DS
14
PD8861
9. Random noise (CDS) :
CDS
Random noise
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
"VD
i
".
3. The output level is measured during the video output time averaged over 100 ns to get "VO
i
".
4.
The correlated double sampling output is defined by the following formula.
VCDS
i
= VD
i
VO
i
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
CDS using the following formula equation.
CDS (mV) =
, V =
i
=
1
100
(VCDS
i
V)
2
i
=
1
100
VCDS
i
100
100
1
Reset feed-through
Video output
Data Sheet S15167EJ2V0DS
15
PD8861
STANDARD CHARACTERISTIC CURVES (Nominal)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25
C)
Operating Ambient Temperature T
A
(
C)
Storage Time (ms)
8
4
2
1
0.5
0.25
0.1
10
0
20
30
40
50
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.1
1
5
10
400
500
600
700
800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
Data Sheet S15167EJ2V0DS
16
PD8861
APPLICATION CIRCUIT EXAMPLE
Remark The inverters shown in the above application circuit example are the 74HC04 (data rate
< 2 MHz) or the
74AC04 (2 MHz
data rate < 6 MHz).
V
OUT
3
PD8861
V
OUT
1
GND
NC
NC
NC
NC
GND
NC
1
2
2
TG3
CLB
1L
TG1
1
TG2
47
4.7
4.7
4.7
10
10
4.7
47
150
10
1
22
21
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
9
8
10
11
B3
V
OUT
2
NC
V
OD
RB
B2
+12 V
0.1 F
10 F/16 V
0.1 F
10 F/16 V
TG
1
RB
2
CLB
B1
+5 V
+5 V
+
0.1 F
10 F/16 V
+
+
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
12 V
100
100
CCD
V
OUT
2SC945
2 k
Data Sheet S15167EJ2V0DS
17
PD8861
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
1bit
10.16
2.54
(5.42)
25.4
0.50.3
37.5
44.00.3
2.0
9.250.3
1.020.15
0.460.1
4.210.5
4.390.4
0.250.05
Name
Dimensions
Refractive index
Plastic cap
1.5
22C-1CCD-PKG6-1
(Unit : mm)
42.9
8.35 0.7
2
1 The bottom of the package The surface of the chip
0
10
2 The thickness of the cap over the chip
2.550.2 1
(1.79)
Data Sheet S15167EJ2V0DS
18
PD8861
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For more details, refer to our document "Semiconductor Device Mounting Technology Manual" (C10535E).
Type of Through-hole Device
PD8861CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300
C or below, Heat time : 3 seconds or less (per pin)
Caution During assembly care should be taken to prevent solder or flux from contacting the plastic cap.
The optical characteristics could be degraded by such contact.
Data Sheet S15167EJ2V0DS
19
PD8861
NOTES ON CLEANING THE PLASTIC CAP
1
CLEANING THE PLASTIC CAP
Care should be taken when cleaning the surface to prevent scratches.
The optical characteristics of the CCD will be degraded if the cap is scratched during
cleaning.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended
solvents below. Excessive pressure should not be applied to the cap during cleaning. If the
cap requires multiple cleanings it is recommended that a clean surface or cloth be used.
2
RECOMMENDED SOLVENTS
The following are the recommended solvents for cleaning the CCD plastic cap. Use of
solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
Solvents
Symbol
Ethyl Alcohol
EtOH
Methyl Alcohol
MeOH
Isopropyl Alcohol
IPA
N-methyl Pyrrolidone
NMP
Data Sheet S15167EJ2V0DS
20
PD8861
[MEMO]
Data Sheet S15167EJ2V0DS
21
PD8861
[MEMO]
Data Sheet S15167EJ2V0DS
22
PD8861
[MEMO]
Data Sheet S15167EJ2V0DS
23
PD8861
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD8861
M8E 00. 4
The information in this document is current as of June, 2001. The information is subject to change
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