Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- PHOTOCELL STRUCTURE DIAGRAM
- PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
- ABSOLUTE MAXIMUM RATINGS (TA = +25 degrees)
- RECOMMENDED OPERATING CONDITIONS (TA = +25 degrees)
- ELECTRICAL CHARACTERISTICS
- INPUT PIN CAPACITANCE (TA = +25 degrees, VOD = 12 V)
-
- TIMING CHART 2 (Bit clamp mode, for each color)
- TIMING CHART 3 (Line clamp mode, for each color)
- PHY TG1 to PHY TG3, PHY 1, PHY 2 TIMING CHART
-
-
- DEFINITIONS OF CHARACTERISTIC ITEMS
- STANDARD CHARACTERISTICS CURVES (Reference Value)
- APPLICATION CIRCUIT EXAMPLE
- PACKAGE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
MOS INTEGRATED CIRCUIT
PD8871
10680 PIXELS
3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S15329EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
2001
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
DESCRIPTION
The
PD8871 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD8871 has 3 rows of 10680 pixels, and each row has a single-sided readout type of charge transfer register.
And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for 1200 dpi/A4 color
image scanners, color facsimiles and so on.
FEATURES
Valid photocell
: 10680 pixels
3
Photocell pitch
: 4
m
Photocell size
: 4
4
m
2
Line spacing
: 32
m (8 lines) Red line - Green line, Green line - Blue line
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 48 dot/mm A4 (210
297 mm) size (shorter side)
:
1200 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 10 MHz Max.
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
::
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8871CY
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
The mark
shows major revised points.
Data Sheet S15329EJ2V0DS
2
PD8871
BLOCK DIAGRAM
30
31
32
29
1
16
22
19
18
17
15
14
11
3
D14
D64
D65
D66
S10679
S10680
S1
S2
Photocell
(Red)
Transfer gate
CCD analog shift register
D67
D14
D64
D65
D66
S10679
S10680
S1
S2
Photocell
(Green)
Transfer gate
D67
D14
D64
D65
D66
S10679
S10680
S1
S2
Photocell
(Blue)
Transfer gate
D67
TG1
(Blue)
TG2
(Green)
TG3
(Red)
1L
4
RB
2
1
2
1
GND
GND
V
OD
V
OUT
3
(Red)
V
OUT
2
(Green)
V
OUT
1
(Blue)
2
CLB
CCD analog shift register
CCD analog shift register
Data Sheet S15329EJ2V0DS
3
PD8871
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
PD8871CY
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
1
2
3
4
5
6
7
8
9
10
11
NC
NC
V
OUT
2
V
OUT
1
IC
1
TG1
No connection
No connection
NC
No connection
NC
No connection
Output signal 2 (Green)
Output signal 1 (Blue)
Output drain voltage
Internal connection
Shift register clock 1
Transfer gate clock 2
(for Green)
V
OUT
3
GND
2
TG3
Output signal 3 (Red)
Ground
Reset gate clock
Shift register clock 1
IC
Internal connection
IC
Internal connection
IC
Internal connection
IC
Internal connection
Shift register clock 2
10680
10680
10680
Red
Green
Blue
1
1
1
Internal connection
Transfer gate clock 1
(for Blue)
Transfer gate clock 3
(for Red)
V
OD
IC
1
2
Shift register clock 2
GND
Ground
RB
Last stage shift register clock 1
1L
Reset feed-through level
clamp clock
CLB
No connection
NC
No connection
NC
No connection
NC
No connection
NC
TG2
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
IC
Internal connection
IC
Internal connection
Data Sheet S15329EJ2V0DS
4
PD8871
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM
(Line spacing)
4 m
m
2
m
2
Channel stopper
Aluminum
shield
Blue photocell array
4 m
Green photocell array
4 m
Red photocell array
4 m
8 lines
(32 m)
8 lines
(32 m)
Data Sheet S15329EJ2V0DS
5
PD8871
ABSOLUTE MAXIMUM RATINGS (T
A
=
+
+
+
+25C)
Parameter
Symbol
Ratings
Unit
Output drain voltage
V
OD
-0.3 to +15
V
Shift register clock voltage
V
1
, V
2
, V
1L
-0.3 to +8
V
Reset gate clock voltage
V
RB
-0.3 to +8
V
Reset feed-through level clamp
clock voltage
V
CLB
-0.3 to +8
V
Transfer gate clock voltage
V
TG1
to V
TG3
-0.3 to +8
V
Operating ambient temperature
Note
T
A
0 to
+60
C
Storage temperature
T
stg
-40 to +70
C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+
+
+
+25C)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
1H
, V
2H
, V
1LH
4.75
5.0
5.5
V
Shift register clock low level
V
1L
, V
2L
, V
1LL
-0.3
0
+0.25
V
Reset gate clock high level
V
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
RBL
-0.3
0
+0.5
V
Reset feed-through level clamp clock
high level
V
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock
low level
V
CLBL
-0.3
0
+0.5
V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.75
V
1H
Note
V
1H
Note
V
Transfer gate clock low level
V
TG1L
to V
TG3L
-0.3
0
+0.15
V
Data rate
f
RB
-
2.0
10.0
MHz
Note
When Transfer gate clock high level (V
TG1H
to V
TG3H
) is higher than Shift register clock high level (V
1H
),
Image lag can increase.
Data Sheet S15329EJ2V0DS
6
PD8871
ELECTRICAL CHARACTERISTICS
T
A
=
+25C, V
OD
= 12 V, data rate (f
RB
) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp
+ C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Saturation voltage
V
sat
2.5
3.2
-
V
Red
SER
-
0.889
-
lxs
Green
SEG
-
0.970
-
lxs
Saturation exposure
Blue
SEB
-
1.455
-
lxs
Photo response non-uniformity
PRNU
V
OUT
= 1.0 V
-
6
20
%
Average dark signal
ADS
Light shielding
-
0.2
4.0
mV
Dark signal non-uniformity
DSNU
Light shielding
-
1.0
4.0
mV
Power consumption
P
W
-
360
540
mW
Output impedance
Z
O
-
0.30
1.00
k
Red
R
R
2.52
3.60
4.68
V/lxs
Green
R
G
2.31
3.30
4.29
V/lxs
Response
Blue
R
B
1.54
2.20
2.86
V/lxs
Image lag
IL
V
OUT
= 1.0 V
-
1.0
7.0
%
Offset level
Note 1
V
OS
4.5
6.0
7.5
V
Output fall delay time
Note 2
t
d
V
OUT
= 1.0 V, (t1') = 5 ns
-
25
-
ns
Total transfer efficiency
TTE
V
OUT
= 1.0 V, data rate = 10 MHz
92
98
-
%
Red
-
630
-
nm
Green
-
540
-
nm
Response peak
Blue
-
460
-
nm
DR1
V
sat
/DSNU
-
3200
-
times
Dynamic range
DR2
V
sat
/
CDS
-
3200
-
times
Reset feed-through noise
Note 1
RFTN
Light shielding
-2000
+100
+1000
mV
Random noise (CDS)
CDS
Light shielding
-
1.0
-
mV
Notes 1. Refer to TIMING CHART 2, 3.
2. When the fall time of
1L (t1') is the Typ. value (refer to TIMING CHART 2, 3).
Data Sheet S15329EJ2V0DS
7
PD8871
INPUT PIN CAPACITANCE (T
A
=
+
+
+
+25C, V
OD
= 12 V)
Parameter
Symbol
Pin
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
C
1
1
14
-
450
-
pF
19
-
450
-
pF
Shift register clock pin capacitance 2
C
2
2
11
-
450
-
pF
22
-
450
-
pF
Last stage shift register clock pin capacitance
C
L
1L
3
-
10
-
pF
Reset gate clock pin capacitance
C
RB
RB
4
-
10
-
pF
Reset feed-through level clamp clock pin capacitance
C
CLB
CLB
2
-
10
-
pF
Transfer gate clock pin capacitance
TG1
18
-
100
-
pF
TG2
17
-
100
-
pF
C
TG
TG3
15
-
100
-
pF
Remark Pin 14 and 19 (
1), 11 and 22 (
2) are each connected inside of the device.
Data S
h
e
e
t S
153
29E
J
2
V
0
DS
8
PD8871
TIMING CHART 1 (for each color)
Note Set the
RB pulse to high level during the
TG1 to
TG3 pulse.
And stop the
RB pulse while the
CLB pulse is low level at line clamp mode.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB at line clamp mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
10743
10744
10745
10746
10747
10748
10749
V
OUT
1 to V
OUT
3
RB
CLB
(Bit clamp mode)
CLB
(Line clamp mode)
1L
Note
Invalid photocell
(3 pixels)
Invalid photocell
(3 pixels)
Valid photocell
(10680 pixels)
Optical black
(48 pixels)
2
1,
TG1 to
TG3
Note
Data Sheet S15329EJ2V0DS
9
PD8871
TIMING CHART 2 (Bit clamp mode, for each color)
Symbol
Min.
Typ.
Max.
Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3
20
100
-
ns
t4
40
150
-
ns
t5, t6
0
25
-
ns
t7
-5
Note
25
-
ns
t8
20
100
-
ns
t9, t10
0
25
-
ns
t11
10
25
-
ns
Note Min. of t7 shows that the
RB and
CLB overlap each other.
CLB
RB
90%
90%
t7
V
OUT
CLB
RB
2
1
90%
10%
1L
90%
10%
90%
10%
90%
10%
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
90%
10%
t10
t8
t11
t7
t9
t2'
t1'
10%
Data Sheet S15329EJ2V0DS
10
PD8871
TIMING CHART 3 (Line clamp mode, for each color)
Symbol
Min.
Typ.
Max.
Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3
20
100
-
ns
t4
40
150
-
ns
t5, t6
0
25
-
ns
V
OUT
CLB
RB
2
1
90%
10%
1L
90%
10%
90%
10%
90%
10%
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
t2'
t1'
10%
"H"
Data Sheet S15329EJ2V0DS
11
PD8871
TG1 to
TG3,
1,
2 TIMING CHART
Symbol
Min.
Typ.
Max.
Unit
t7
-5
Note 3
25
-
ns
t9, t10
0
25
-
ns
t11
10
25
-
ns
t12
5000
10000
50000
ns
t13, t14
0
50
-
ns
t15, t16
900
1000
-
ns
t17, t18
200
400
-
ns
t19
t12
t12
50000
ns
t20, t21
0
50
-
ns
t22, t23
0
350
-
ns
Notes 1. Set the
RB pulse to high level during this period.
2. Stop the
RB pulse during this period.
3. Min. of t7 shows that the
RB and
CLB overlap each other.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
1,
2 cross points
1L,
2 cross points
Remark Adjust cross points (
1,
2) and (
1L,
2) with input resistance of each pin.
2
1
2 V or more
2 V or more
2
1L
2 V or more
0.5 V or more
RB
CLB
(Bit clamp mode)
1L
1,
2
TG1 to
TG3
CLB
(Line clamp mode)
1L
1,
10%
90%
90%
90%
90%
90%
90%
10%
t12
t13
t17
t7
t19
t9
t20
t10
t23
t21
t22
t11
Note 1
Note 2
t18
t16
t15
t14
Data Sheet S15329EJ2V0DS
12
PD8871
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
10680
j = 1
10680
d
j
x
Register Dark
DC level
V
OUT
x
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x : maximum of
x
j
- x
x
10680
j = 1
10680
x
j
100
Data Sheet S15329EJ2V0DS
13
PD8871
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lxs).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of
d
j
- ADS
j = 1 to 10680
ADS
DSNU
Register Dark
DC level
V
OUT
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
Data Sheet S15329EJ2V0DS
14
PD8871
9. Random noise (CDS) :
CDS
Random noise
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
"VD
i
".
3. The output level is measured during the video output time averaged over 100 ns to get "VO
i
".
4. The correlated double sampling output is defined by the following formula.
VCDS
i
= VD
i
VO
i
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
CDS using the following formula equation.
Reset feed-through
Video output
CDS (mV) =
, V =
i
=
1
100
(VCDS
i
V)
2
i
=
1
100
VCDS
i
100
100
1
Data Sheet S15329EJ2V0DS
15
PD8871
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25
C)
Operating Ambient Temperature T
A
(
C)
Storage Time (ms)
8
4
2
1
0.5
0.25
0.1
10
0
20
30
40
50
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.1
1
5
10
400
500
600
700
800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
Data Sheet S15329EJ2V0DS
16
PD8871
APPLICATION CIRCUIT EXAMPLE
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
PD8871
4.7
4.7
4.7
B3
+12 V
0.1 F
47 F/25 V
+
B2
+5 V
0.1 F
10 F/16 V
+
4.7
B1
47
150
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
4.7
4.7
4.7
NC
NC
V
OUT
2
V
OUT
1
IC
1
TG1
NC
NC
V
OUT
3
GND
2
1L
2
TG3
IC
IC
IC
IC
V
OD
IC
1
2
GND
RB
CLB
TG
1
RB
1L
NC
NC
NC
NC
TG2
IC
IC
47
CLB
0.1 F
10 F/16 V
+5 V
+
Data Sheet S15329EJ2V0DS
17
PD8871
Remarks 1. B1 to B3 in the application circuit example are shown in the figure below.
2. Number and type of inverters in the application circuit example are different by data rate.
The following table shows the recommended number and type of inverters for data rate.
Pin Name
Pin No.
Data Rate (MHz)
Inverter
Type
Number (each pin)
CLB
2
(data rate)
< 10
74HC04
1
1L
3
(data rate)
< 2
74HC04
1
2
(data rate) < 10
74AC04
1
RB
4
(data rate)
< 10
74HC04
1
1,
2
14, 19, 11, 22
(data rate)
< 2
74HC04
1
2
(data rate) < 6
74AC04
1
6
(data rate) < 10
74AC04
3
TG1 to
TG3
18, 17, 15
(data rate)
< 10
74HC04
1
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
12 V
100
100
CCD
V
OUT
2SC945
2 k
Data Sheet S15329EJ2V0DS
18
PD8871
PACKAGE DRAWING
55.2
0.5
54.8
0.5
9.05
0.3
9.25
0.3
12.6
0.5
1.02
0.15
2.54
0.25
(5.42)
(1.80)
0.46
0.1
4.21
0.5
2.58
0.3
0.25
0.05
4.1
0.5
4.55
0.5
10.16
0.20
46.7
1st valid pixel
6.15
0.3
1
32
17
1
16
2.0
2
3
10.16
+0.7
-0.2
(Unit : mm)
Name
Dimensions
Refractive index
Plastic cap
52.2
6.40.7
1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
32C-1CCD-PKG5-1
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
PD8871CY
Data Sheet S15329EJ2V0DS
19
PD8871
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
PD8871CY : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process
Conditions
Partial heating method
Pin temperature : 300
C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of plastic cap
soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S15329EJ2V0DS
20
PD8871
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 M
.
4
3
RECOMMENDED SOLVENTS
Solvents
Symbol
Data Sheet S15329EJ2V0DS
21
PD8871
[MEMO]
Data Sheet S15329EJ2V0DS
22
PD8871
[MEMO]
Data Sheet S15329EJ2V0DS
23
PD8871
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD8871
M8E 00. 4
The information in this document is current as of September, 2002. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special":
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
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