Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- PHOTOCELL STRUCTURE DIAGRAM
- PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
- ABSOLUTE MAXIMUM RATINGS
- RECOMMENDED OPERATING CONDITIONS
- ELECTRICAL CHARACTERISTICS
- INPUT PIN CAPACITANCE
- TIMING CHART 1-1 (Bit clamp mode, for each color)
- TIMING CHART 1-2 (Line clamp mode, for each color)
- TIMING CHART 2 (Bit clamp mode, for each color)
- TIMING CHART 3 (Line clamp mode, for each color)
- PHI TG1 to PHI TG3, PHI 1, PHI 2 TIMING CHART
- PHI 1, PHI 2 cross points
- PHI 1, PHI 2L cross points
- PHI 2, PHI 1L cross points
- DEFINITIONS OF CHARACTERISTIC ITEMS
- STANDARD CHARACTERISTIC CURVES (Reference Value)
- APPLICATION CIRCUIT EXAMPLE
- PACKAGE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
MOS INTEGRATED CIRCUIT
PD8872
(5400 + 5400) PIXELS
3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S15330EJ3V0DS00 (3rd edition)
Date Published July 2003 NS CP (K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
The mark shows major revised points.
DESCRIPTION
The
PD8872 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD8872 has 3 rows of (5400 + 5400) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
1200 dpi/A4 color image scanners, color facsimiles and so on.
FEATURES
Valid photocell : (5400 + 5400) staggered pixels 3
Photocell pitch : 5.25
m
Line spacing
: 63
m (12 lines) Red line - Green line, Green line - Blue line
10.5
m (2 lines) Odd line - Even line (for each color)
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 48 dot/mm A4 (210
297 mm) size (shorter side)
1200 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: 10 MHz Max.
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8872CY
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Data Sheet S15330EJ3V0DS
2
PD8872
BLOCK DIAGRAM
17
20
1
11
15
14
8
9
19
3
2
4
TG1
(Blue)
TG2
(Green)
TG3
(Red)
1L
RB
2
2L
1
2
1
GND GND
V
OD
V
OUT
1
(Blue)
21
V
OUT
2
(Green)
22
13
12
10
V
OUT
3
(Red)
CLB
D14
D66
D67
D68
S10799
S10800
S1
S2
Photocell
(Blue)
D69
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D14
S10799
S10800
S1
S2
Photocell
(Green)
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D66
D14
S10799
S10800
S1
S2
Photocell
(Red)
CCD analog shift register
CCD analog shift register
Transfer gate
Transfer gate
D67
D68
D69
D66
D67
D68
D69
D70
D70
D70
Data Sheet S15330EJ3V0DS
3
PD8872
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD8872CY
Caution Connect the No connection pins (NC) to GND.
1
2
3
4
5
6
7
8
9
10
11
NC
No connection
Last stage shift register clock 2
V
OUT
2
Output signal 2 (Green)
V
OUT
1
Output signal 1 (Blue)
NC
No connection
1
Shift register clock 1
2
2L
Shift register clock 2
V
OUT
3
Output signal 3 (Red)
GND
Ground
NC
No connection
NC
No connection
NC
No connection
10800
10800
10800
Red
Green
Blue
1
1
1
TG1
Transfer gate clock 1
(for Blue)
TG3
Transfer gate clock 3
(for Red)
Output drain voltage
V
OD
Shift register clock 1
1
Shift register clock 2
2
GND
Ground
Reset gate clock
RB
Reset feed-through level clamp clock
CLB
1L
Last stage shift register clock 1
Transfer gate clock 2
(for Green)
TG2
22
21
20
19
18
17
16
15
14
13
12
Data Sheet S15330EJ3V0DS
4
PD8872
PHOTOCELL STRUCTURE DIAGRAM
PHOTOCELL ARRAY STRUCTURE DIAGRAM (Line spacing)
5.25 m
2.75 m
m
2.5
Channel stopper
Aluminum
shield
Blue photocell array
Blue photocell array
Green photocell array
Green photocell array
5.25
m
2 lines
(10.5
m)
10 lines
(52.5
m)
2 lines
(10.5
m)
5.25
m
5.25
m
5.25
m
5.25
m
5.25
m
Red photocell array
Red photocell array
10 lines
(52.5
m)
12 lines
(63
m)
12 lines
(63
m)
2 lines
(10.5
m)
5.25
m
5.25
m
5.25
m
Data Sheet S15330EJ3V0DS
5
PD8872
ABSOLUTE MAXIMUM RATINGS (T
A
=
+25C)
Parameter Symbol
Ratings Unit
Output drain voltage
V
OD
-0.3 to +15 V
Shift register clock voltage
V
1
, V
2
, V
1L
, V
2L
-0.3 to +8 V
Reset gate clock voltage
V
RB
-0.3 to +8 V
Reset feed-through level clamp clock
voltage
V
CLB
-0.3 to +8 V
Transfer gate clock voltage
V
TG1
to V
TG3
-0.3 to +8 V
Operating ambient temperature
Note
T
A
0
to
+60
C
Storage temperature
T
stg
-40 to +70
C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+25C)
Parameter Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4 12.0 12.6
V
Shift register clock high level
V
1_H
, V
2_H
, V
1LH
, V
2LH
4.75
5.0
5.5
V
Shift register clock low level
V
1_L
, V
2_L
, V
1LL
, V
2LL
-0.3 0 +0.25 V
Reset gate clock high level
V
RBH
4.5 5.0 5.5
V
Reset gate clock low level
V
RBL
-0.3 0 +0.5 V
Reset feed-through level clamp clock
high level
V
CLBH
4.5 5.0 5.5
V
Reset feed-through level clamp clock
low level
V
CLBL
-0.3 0 +0.5 V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.75
V
1_ H
Note
V
1_H
Note
V
Transfer gate clock low level
V
TG1L
to V
TG3L
-0.3 0 +0.15 V
Data rate
f
RB
-
2.0 10.0
MHz
Note When Transfer gate clock high level (V
TG1H
to V
TG3H
) is higher than Shift register clock high level (V
1_H
),
Image lag can increase.
Data Sheet S15330EJ3V0DS
6
PD8872
ELECTRICAL CHARACTERISTICS
T
A
=
+25C, V
OD
= 12 V, data rate (f
RB
) = 2 MHz, storage time = 5.5 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp
+ C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol
Test
Conditions Min.
Typ.
Max.
Unit
Saturation voltage
V
sat
2.7
3.0
-
V
Red SER
-
0.505
-
lxs
Green SEG
-
0.573
-
lxs
Saturation exposure
Blue SEB
-
0.888
-
lxs
Photo response non-uniformity
PRNU
V
OUT
= 1.0 V
-
6 20
%
Average dark signal
ADS
Light shielding
-
0.2 2.0
mV
Dark signal non-uniformity DSNU
Light
shielding
-
1.5 5.0
mV
Power consumption
P
W
-
360 540
mW
Output impedance
Z
O
-
0.35 1.00 k
Red R
R
4.15 5.94 7.73
V/lxs
Green R
G
3.66 5.24 6.82
V/lxs
Response
Blue R
B
2.36 3.38 4.39
V/lxs
Image lag
IL
V
OUT
= 1.0 V
-
3.0 7.0 %
Offset level
Note 1
V
OS
4.5
6.0
7.5 V
Output fall delay time
Note 2
t
d
V
OUT
= 1.0 V, t1', t2' = 5 ns
-
25
-
ns
Total transfer efficiency
TTE
V
OUT
= 1.0 V, data rate = 10 MHz
92
98
-
%
Register imbalance
RI
V
OUT
= 1.0 V
-
1.0 4.0 %
Red
-
630
-
nm
Green
-
540
-
nm
Response peak
Blue
-
460
-
nm
DR1 V
sat
/DSNU
-
2000
-
times
Dynamic range
DR2 V
sat
/
CDS
-
3000
-
times
Reset feed-through noise
Notes 1, 3
RFTN
Light
shielding
-2000
+300
+1000 mV
Random noise (CDS)
CDS Light
shielding
-
1.0
-
mV
Notes 1. Refer to TIMING CHART 2, 3.
2. When the fall time of
1L and
2L (t1', t2') is the Typ. value (refer to TIMING CHART 2, 3).
3. The reset feed-through noise changes by peripheral circuit of register, the driver circuit for
RB and so on.
Data Sheet S15330EJ3V0DS
7
PD8872
INPUT PIN CAPACITANCE (T
A
=
+25C, V
OD
= 12 V)
Parameter
Symbol
Pin name
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
C
1
1 9
-
500
-
pF
14
-
500
-
pF
1 total capacitance
-
1000
-
pF
Shift register clock pin capacitance 2
C
2
2 8
-
500
-
pF
15
-
500
-
pF
2 total capacitance
-
1000
-
pF
Last stage shift register clock pin capacitance
C
L
1L 4
-
10
-
pF
2L 19
-
10
-
pF
Reset gate clock pin capacitance
C
RB
RB 2
-
10
-
pF
Reset feed-through level clamp clock pin capacitance
C
CLB
CLB
3
-
10
-
pF
Transfer gate clock pin capacitance
TG1 13
-
200
-
pF
TG2 12
-
200
-
pF
C
TG
TG3 10
-
200
-
pF
Remarks 1. Pins 9 and 14 (
1), 8 and 15 (
2) are each connected inside of the device.
2. C
1
and C
2
show the equivalent capacity of the real drive including the capacity of between
1 and
2.
Data S
heet
S1533
0EJ3V0DS
8
PD8872
TIMING CHART 1-1 (Bit clamp mode, for each color)
Note Set the
RB and
CLB to high level during this period.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
10866
10867
10868
10869
10870
10871
V
OUT
1 to V
OUT
3
RB
CLB
1L
Note
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
Valid photocell
(10800 pixels)
Optical black
(49 pixels)
1,
2L
2,
TG1 to
TG3
Note
Data S
heet
S1533
0EJ3V0DS
9
PD8872
TIMING CHART 1-2 (Line clamp mode, for each color)
Note Set the
RB to high level during this period.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
61
62
63
64
65
66
10866
10867
10868
10869
10870
10871
V
OUT
1 to V
OUT
3
RB
CLB
1L
Note
Invalid photocell
(4 pixels)
Invalid photocell
(4 pixels)
Valid photocell
(10800 pixels)
Optical black
(49 pixels)
1,
2L
2,
TG1 to
TG3
TG1 to
TG3)
(
Note
Data Sheet S15330EJ3V0DS
10
PD8872
TIMING CHART 2 (Bit clamp mode, for each color)
Symbol Min. Typ. Max. Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3 20
100
-
ns
t4 30
150
-
ns
t5, t6
0
25
-
ns
t7
-5
Note
25
-
ns
t8 20
100
-
ns
t9, t10
0
25
-
ns
t11 5
25
-
ns
Note Min. of t7 shows that the
RB and
CLB overlap each other.
V
OUT
CLB
RB
2
1
90%
10%
1L
2L
90%
10%
90%
10%
RFTN
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
t1'
10%
90%
10%
t10
t11
t8
t9
t7
t2'
90%
10%
90%
10%
t4
t6
t3
t5
t
d
t10
t11
t8
t9
t7
CLB
RB
90%
90%
t7
Data Sheet S15330EJ3V0DS
11
PD8872
TIMING CHART 3 (Line clamp mode, for each color)
Symbol Min. Typ. Max. Unit
t1, t2
0
25
-
ns
t1', t2'
0
5
-
ns
t3 20
100
-
ns
t4 30
150
-
ns
t5, t6
0
25
-
ns
V
OUT
CLB
RB
2
1
90%
10%
1L
2L
90%
10%
90%
10%
"H"
RFTN
RFTN
V
OS
t2
t1
t4
t6
t3
t5
t
d
t1'
10%
t2'
90%
10%
90%
10%
t4
t6
t3
t5
t
d
Data Sheet S15330EJ3V0DS
12
PD8872
TG1 to TG3, 1, 2 TIMING CHART
Symbol Min. Typ. Max. Unit
t7
-5
Note 3
25
-
ns
t9, t10
0
25
-
ns
t12 5000
10000
50000
ns
t13, t14
0
50
-
ns
t15, t16
900
1000
-
ns
t17, t18
200
400
-
ns
t19 t12
t12
50000
ns
t20, t21
0
50
-
ns
t22, t23
0
350
-
ns
Notes 1. Set the
RB and
CLB to high level during this period.
2. Set the
RB to high level during this period.
3.
Min. of t7 shows that the
RB and
CLB overlap each other.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
CLB
RB
90%
90%
t7
RB
CLB
(Bit clamp mode)
2
TG1 to
TG3
CLB
(Line clamp mode)
1
10%
90%
90%
90%
90%
90%
10%
t12
t13
t17
t7
t19
t9
t20
t10
t23
t21
t22
Note 1
Note 2
t18
t16
t15
t14
Data Sheet S15330EJ3V0DS
13
PD8872
1, 2 cross points
1, 2L cross points
2, 1L cross points
Remark Adjust cross points (
1,
2), (
1,
2L) and (
2,
1L) with input resistance of each pin.
1
2
1.0 V to 4.0 V
1.0 V to 4.0 V
1
2L
2.0 V or more
0.5 V or more
2
1L
2.0 V or more
0.5 V or more
Data Sheet S15330EJ3V0DS
14
PD8872
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x : maximum of
x
j
- x
x
10800
j = 1
10800
x
j
100
ADS (mV) =
d
j
: Dark signal of valid pixel number j
10800
j = 1
10800
d
j
x
Register Dark
DC level
V
OUT
x
Data Sheet S15330EJ3V0DS
15
PD8872
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lxs).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of
d
j
- ADS
j = 1 to 10800
ADS
DSNU
Register Dark
DC level
V
OUT
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
Data Sheet S15330EJ3V0DS
16
PD8872
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
10. Random noise (CDS) :
CDS
Random
noise
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
"VD
i
".
3. The output level is measured during the video output time averaged over 100 ns to get "VO
i
".
4. The correlated double sampling output is defined by the following formula.
VCDS
i
= VD
i
VO
i
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
CDS using the following formula equation.
RI (%) =
2
n
j = 1
j = 1
n
2
(V
2j 1
V
2j
)
1
n
n
V
j
100
n
V
j
: Number of valid pixels
: Output voltage of each pixel
CDS (mV) =
, V =
i
=
1
100
(VCDS
i
V)
2
i
=
1
100
VCDS
i
100
100
1
Reset feed-through
Video output
Data Sheet S15330EJ3V0DS
17
PD8872
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25
C)
Operating Ambient Temperature T
A
(
C)
Storage Time (ms)
8
4
2
1
0.5
0.25
0.1
10
0
20
30
40
50
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.1
1
5
10
400
500
600
700
800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
Data Sheet S15330EJ3V0DS
18
PD8872
APPLICATION CIRCUIT EXAMPLE
Caution Connect the No connection pins (NC) to GND.
Remarks 1. The inverters shown in the above application circuit example are the 74HC04 (data rate
< 2 MHz) or
the 74AC04 (2
data rate < 10 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
12 V
100
100
CCD
V
OUT
2SC945
2 k
V
OUT
3
PD8872
V
OUT
1
GND
NC
NC
NC
NC
GND
NC
1
2
2
2L
TG3
CLB
1L
TG1
1
TG2
47
4.7
150
4.7
4.7
10
10
4.7
47
150
10
1
22
21
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
9
8
10
11
V
OUT
2
V
OD
RB
B3
+12 V
0.1 F
47 F/25 V
0.1 F
10 F/16 V
TG
1
RB
2
CLB
B2
+5 V
+5 V
+
0.1 F
10 F/16 V
1L
+
+
B1
2L
Data Sheet S15330EJ3V0DS
19
PD8872
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400) )
PD8872CY
44.0
0.3
37.5
1st valid pixel
0.5
0.3
1
9.25
0.3
2.0
0.25
0.05
10.16
0.2
0.46
0.1
2.54
0.25
1.02
0.15
(5.42)
4.21
0.5
4.39
0.4
12
11
2.55
0.2
3
(1.79)
2
Name
Dimensions
Refractive index
Plastic cap
42.9
8.350.7
1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
22C-1CCD-PKG14-2
(Unit : mm)
1
22
10.16
+0.7
-0.2
Data Sheet S15330EJ3V0DS
20
PD8872
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
PD8872CY : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method
Pin temperature : 300
C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S15330EJ3V0DS
21
PD8872
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 M
.
4
3
RECOMMENDED SOLVENTS
Solvents
Symbol
Data Sheet S15330EJ3V0DS
22
PD8872
[MEMO]
Data Sheet S15330EJ3V0DS
23
PD8872
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to V
DD
or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
PD8872
The information in this document is current as of July, 2003. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
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M8E 02. 11-1
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