Document Outline
- COVER
- DESCRIPTION
- FEATURES
- ORDERING INFORMATION
- BLOCK DIAGRAM
- PIN CONFIGURATION (Top View)
- PHOTOCELL STRUCTURE DIAGRAM
- PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
- PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Odd-even pixel)
- PHOTOCELL ARRAY STRUCTURE DIAGRAM-3 (Dummy, OB, for each color)
- ABSOLUTE MAXIMUM RATINGS (TA = +25 degrees)
- RECOMMENDED OPERATING CONDITIONS (TA = +25 degrees)
- ELECTRICAL CHARACTERISTICS
- INPUT PIN CAPACITANCE (TA = +25 degrees, VOD = 12 V)
- TIMING CHART 1-1 (2400 dpi, bit clamp mode, for each color)
- TIMING CHART 1-2 (2400 dpi, line clamp mode, for each color)
- TIMING CHART 1-3 (1200 dpi, bit clamp mode, for each color)
- TIMING CHART 1-4 (1200 dpi, line clamp mode, for each color)
- TIMING CHART 1-5 (600 dpi, bit clamp mode, for each color)
- TIMING CHART 1-6 (600 dpi, line clamp mode, for each color)
- TIMING CHART 1-7 (300 dpi, bit clamp mode, for each color)
- TIMING CHART 1-8 (300 dpi, line clamp mode, for each color)
- TIMING CHART 2-1 (2400 dpi, for each color)
- TIMING CHART 2-2 (1200 dpi, for each color)
- TIMING CHART 2-3 (600 dpi, for each color)
- TIMING CHART 2-4 (300 dpi, for each color)
- TIMING CHART 3
- PHI 1, PHI 2, PHI 3, PHI 4 cross points
- SELECTION OF RESOLUTION MODE
- PHI SEL TIMING CHART
- DEFINITIONS OF CHARACTERISTIC ITEMS
- STANDARD CHARACTERISTIC CURVES (Reference Value)
- APPLICATION CIRCUIT EXAMPLE
- PACKAGE DRAWING
- RECOMMENDED SOLDERING CONDITIONS
MOS INTEGRATED CIRCUIT
PD8882
(10680 + 10680) PIXELS
3 COLOR CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S17085EJ2V0DS00 (2nd edition)
Date Published May 2005 NS CP (K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
2004
The mark
shows major revised points.
DESCRIPTION
The
PD8882 is a color CCD (Charge Coupled Device) linear image sensor which changes optical images to
electrical signal and has the function of color separation.
The
PD8882 has 3 rows of (10680 + 10680) staggered pixels, and each row has a dual-sided readout-type charge
transfer register. And it has reset feed-through level clamp circuits and voltage amplifiers. Therefore, it is suitable for
2400 dpi/A4 color image scanners.
FEATURES
Valid photocell : (10680 + 10680) staggered pixels 3
Photocell's size : 2.7
m
5.4
m
Line spacing
: 86.4
m (16 lines) Red line - Green line, Green line - Blue line
43.2
m (8 lines) Odd line - Even line (for each color)
Color filter
: Primary colors (red, green and blue), pigment filter (with light resistance 10
7
lxhour)
Resolution
: 96 dot/mm A4 (210
297 mm) size (shorter side)
2400 dpi US letter (8.5"
11") size (shorter side)
Drive clock level : CMOS output under 5 V operation
Data rate
: Built-in amplifiers : 10.0 MHz Max. CCD transfer : 4.5 MHz Max./each CCD
Power supply
: +12 V
On-chip circuits : Reset feed-through level clamp circuits
Voltage amplifiers
ORDERING INFORMATION
Part Number
Package
PD8882CY-A
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Remark The
PD8882CY-A is a lead-free product.
Data Sheet S17085EJ2V0DS
2
PD8882
BLOCK DIAGRAM
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Blue-odd)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Blue-even)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Green-odd)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Green-even)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Red-odd)
Transfer gate
CCD analog shift register
CCD analog shift register
Transfer gate
Photocell (Red-even)
Transfer gate
14
15
9
8
13
TG1
12
TG2
10
TG3
4
3
4
19
CLB
SEL
2
3
RB
11
2
20
21
V
OUT
1
V
OUT
2
V
OUT
3
GND
GND
V
OD
7
V
OD
1
22
1
Data Sheet S17085EJ2V0DS
3
PD8882
PIN CONFIGURATION (Top View)
CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
PD8882CY-A
1
2
3
4
5
6
7
8
9
10
11
NC
No connection
Dpi selector
V
OUT
2
Output signal 2 (Green)
V
OUT
1
Output signal 1 (Blue)
NC
No connection
NC
No connection
2
Shift register clock 2
1
SEL
Shift register clock 1
V
OUT
3
Output signal 3 (Red)
GND
Ground
NC
No connection
V
OD
Output drain voltage
NC
No connection
21360
21360
21360
Red
Green
Blue
1
1
1
TG1
Transfer gate clock 1
(for Blue)
TG3
Transfer gate clock 3
(for Red)
Output drain voltage
V
OD
Shift register clock 4
4
Shift register clock 3
3
GND
Ground
Reset gate clock
RB
Reset feed-through level clamp clock
CLB
Transfer gate clock 2
(for Green)
TG2
22
21
20
19
18
17
16
15
14
13
12
Caution Connect the No connection pins (NC) to GND.
Data Sheet S17085EJ2V0DS
4
PD8882
PHOTOCELL STRUCTURE DIAGRAM
5.4 m
2.0 m
m
0.7
Channel stopper
Aluminum
shield
PHOTOCELL ARRAY STRUCTURE DIAGRAM-1 (Line spacing)
Blue odd photocell array
Blue even photocell array
Green odd photocell array
Green even photocell array
5.4
m
8 lines
(43.2
m)
8 lines
(43.2
m)
8 lines
(43.2
m)
8 lines
(43.2
m)
8 lines
(43.2
m)
5.4
m
5.4
m
5.4
m
Red odd photocell array
Red even photocell array
16 lines
(86.4
m)
16 lines
(86.4
m)
5.4
m
5.4
m
Data Sheet S17085EJ2V0DS
5
PD8882
PHOTOCELL ARRAY STRUCTURE DIAGRAM-2 (Odd-even pixel)
1
(8 lines)
43.2
m
1.35
m
37.8
m
5.4
m
5.4
m
2.0
m
0.7
m
3
5
7
2
4
6
8
PHOTOCELL ARRAY STRUCTURE DIAGRAM-3 (Dummy, OB, for each color)
1
55
57
151 153
157 159
163
21517 21519
161
155
2
56
58
152 154
158 160
164
21518 21520
162
156
Optical black
(96 pixels)
Invalid photocell
(8 pixels)
Invalid photocell
(4 pixels)
Dummy
(56 pixels)
Valid photocell
(21360 pixels)
Data Sheet S17085EJ2V0DS
6
PD8882
ABSOLUTE MAXIMUM RATINGS (T
A
=
+25C)
Parameter Symbol
Ratings
Unit
Output drain voltage
V
OD
-0.3 to +15 V
Shift register clock voltage
V
1
, V
2
, V
3
, V
4
-0.3 to +8 V
Reset gate clock voltage
V
RB
-0.3 to +8 V
Reset feed-through level clamp clock voltage
V
CLB
-0.3 to +8 V
Dpi select signal voltage
V
SEL
-0.3 to +8 V
Transfer gate clock voltage
V
TG1
to V
TG3
-0.3 to +8 V
Operating ambient temperature
Note
T
A
0
to
+60
C
Storage temperature
T
stg
-40 to +70
C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (T
A
=
+25C)
Parameter Symbol
Min.
Typ.
Max.
Unit
Output drain voltage
V
OD
11.4
12.0
12.6
V
Shift register clock high level
V
1H
, V
2H
, V
3H
, V
4H
4.7
5.0
5.5
V
Shift register clock low level
V
1L
, V
2L
, V
3L
, V
4L
-0.3 0 +0.3 V
Reset gate clock high level
V
RBH
4.5
5.0
5.5
V
Reset gate clock low level
V
RBL
-0.3 0 +0.5 V
Reset feed-through level clamp clock high level
V
CLBH
4.5
5.0
5.5
V
Reset feed-through level clamp clock low level
V
CLBL
-0.3 0 +0.5 V
Dpi select signal high level
V
SELH
4.5
5.0
5.5
V
Dpi select signal low level
V
SELL
-0.3 0 +0.5 V
Transfer gate clock high level
V
TG1H
to V
TG3H
4.5 5.0 5.5
V
Transfer gate clock low level
V
TG1L
to V
TG3L
-0.3 0 +0.5 V
Data rate (amplifier)
f
RB
-
2.0 10.0
MHz
Clock pulse frequency
f
1
, f
2
, f
3
, f
4
-
0.5 4.5
MHz
Data Sheet S17085EJ2V0DS
7
PD8882
ELECTRICAL CHARACTERISTICS
T
A
=
+25C, V
OD
= 12 V, data rate (f
RB
) = 2 MHz, storage time = 11.0 ms, input signal clock = 5 V
p-p
,
light source : 3200 K halogen lamp
+ C-500S (infrared cut filter, t = 1 mm) + HA-50 (heat absorbing filter, t = 3 mm)
Parameter Symbol
Test
Conditions Min.
Typ.
Max.
Unit
Saturation voltage
V
sat
2.0 2.5
-
V
Red SER
-
0.877
-
lxs
Green SEG
-
0.926
-
lxs
Saturation exposure
Blue SEB
-
1.445
-
lxs
Photo response non-uniformity
PRNU
V
OUT
= 1.0 V
-
6 20 %
Average dark signal
ADS
Light shielding
-
0.1 4.0 mV
Dark signal non-uniformity DSNU
Light
shielding
-
2.0 8.0 mV
Power consumption
P
W
-
280 450 mW
Output impedance
Z
O
-
0.4 1.0 k
Red R
R
2.00 2.85 3.70 V/lxs
Green R
G
1.89 2.70 3.51 V/lxs
Response
Blue R
B
1.21 1.73 2.25 V/lxs
Offset level
Note 1
V
OS
5.0 6.0 7.0 V
Output fall delay time
Note 2
t
d
V
OUT
= 1.0 V
-
25
-
ns
Total transfer efficiency
TTE
V
OUT
= 1.0 V
Clock pulse frequency = 4.5 MHz
92 98
-
%
Image lag
IL
V
OUT
= 1.0 V
-
0.5 3.0 %
Photo diode response imbalance
PDRI
V
OUT
= 1.0 V
-
1.0 4.0 %
Red
-
630
-
nm
Green
-
540
-
nm
Response peak
Blue
-
460
-
nm
Reset feed-through noise
Note 1
RFTN
74HC04,
R
S
= 47
Note 3
-2.0
-0.8
+1.0 mV
Random noise (CDS)
CDS Light
shielding
-
1.2
-
mV
Notes 1. Refer
to
TIMING CHART 2-1 to 2-4.
2. When the fall time
1-600,
1-2400 (t1) is the Typ. value (refer to TIMING CHART 2-1 to 2-4).
3. Using application circuit example.
Data Sheet S17085EJ2V0DS
8
PD8882
INPUT PIN CAPACITANCE (T
A
=
+25C, V
OD
= 12 V)
Parameter
Symbol
Pin name
Pin No.
Min.
Typ.
Max.
Unit
Shift register clock pin capacitance 1
C
1
1 15
-
600
-
pF
Shift register clock pin capacitance 2
C
2
2 14
-
600
-
pF
Shift register clock pin capacitance 3
C
3
3 8
-
600
-
pF
Shift register clock pin capacitance 4
C
4
4 9
-
600
-
pF
Reset gate clock pin capacitance
C
RB
RB 3
-
20
-
pF
Reset feed-through level clamp clock pin capacitance
C
CLB
CLB
4
-
20
-
pF
Select signal and gain pin capacitance
C
SEL
SEL
19
-
20
-
pF
Transfer gate clock pin capacitance
TG1 13
-
20
-
pF
TG2 12
-
20
-
pF
C
TG
TG3 10
-
20
-
pF
Remark C
1
to C
4
show the equivalent capacity of the real drive including the capacity of between each clock pin
(
1 and
4).
Data S
heet
S1708
5EJ2V0DS
9
PD8882
TIMING CHART 1-1 (2400 dpi, bit clamp mode, for each color)
1
2
3
4
5
151
152
160
161
162
154
153
159
6
55
58
56
57
21520
21519
21521
21524
21525
21522
21523
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"H"
Optical black
(96 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(8 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
Note
Note
Note Set the
RB and the
CLB to high during this period.
Data S
heet
S1708
5EJ2V0DS
10
PD8882
TIMING CHART 1-2 (2400 dpi, line clamp mode, for each color)
1
2
3
4
5
151
152
160
161
162
154
153
159
6
55
58
56
57
21520
21519
21521
21524
21525
21522
21523
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"H"
Optical black
(96 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(8 pixels)
Valid photocell
(21360 pixels)
Invalid photocell
(4 pixels)
Note
Note
Note Set the
RB to high level and the
CLB to low level during this period.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
Data S
heet
S1708
5EJ2V0DS
11
PD8882
TIMING CHART 1-3 (1200 dpi, bit clamp mode, for each color)
1
3
5
151
161
153
155
157
159
55
57
21519
21521
21525
21523
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(48 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(4 pixels)
Valid photocell
(10680 pixels)
Invalid photocell
(2 pixels)
Note
Note
Note Set the
RB and the
CLB to high level during this period.
Data S
heet
S1708
5EJ2V0DS
12
PD8882
TIMING CHART 1-4 (1200 dpi, line clamp mode, for each color)
1
3
5
151
161
153
155
157
159
55
57
21519
21521
21525
21523
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(48 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(4 pixels)
Valid photocell
(10680 pixels)
Invalid photocell
(2 pixels)
Note
Note
Note Set the
RB to high level and the
CLB to low level during this period.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
Data S
heet
S1708
5EJ2V0DS
13
PD8882
TIMING CHART 1-5 (600 dpi, bit clamp mode, for each color)
1+3
5+7
149+
151
161+
163
153+
155
157+
159
53+55
57+59
21517+
21519
21521+
21523
21525+
21527
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(24 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(2 pixels)
Valid photocell
(5340 pixels)
Invalid photocell
(1 pixels)
Note
Note
Note Set the
RB and the
CLB to high level during this period.
Data S
heet
S1708
5EJ2V0DS
14
PD8882
TIMING CHART 1-6 (600 dpi, line clamp mode, for each color)
1+3
5+7
149+
151
161+
163
153+
155
157+
159
53+55
57+59
21517+
21519
21521+
21523
21525+
21527
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(24 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(2 pixels)
Valid photocell
(5340 pixels)
Invalid photocell
(1 pixels)
Note
Note
Note Set the
RB to high level and the
CLB to low level during this period.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
Data S
heet
S1708
5EJ2V0DS
15
PD8882
TIMING CHART 1-7 (300 dpi, bit clamp mode, for each color)
1+3+
5+7
153+
155+
157+
159
145+
147+
149+
151
161+
163+
165+
167
49+51+
53+55
57+59+
61+63
21513+
21515+
21517+
21519
21521+
21523+
21525+
21527
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(12 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(1 pixels)
Valid photocell
(2670 pixels)
Invalid photocell
(1 pixels)
Note
Note
Note Set the
RB and the
CLB to high level during this period.
Data S
heet
S1708
5EJ2V0DS
16
PD8882
TIMING CHART 1-8 (300 dpi, line clamp mode, for each color)
1+3+
5+7
153+
155+
157+
159
145+
147+
149+
151
161+
163+
165+
167
49+51+
53+55
57+59+
61+63
21513+
21515+
21517+
21519
21521+
21523+
21525+
21527
V
OUT
1 to V
OUT
3
RB
CLB
SEL
"L"
Optical black
(12 pixels)
1
2
3
4
TG1 to
TG3
Invalid photocell
(1 pixels)
Valid photocell
(2670 pixels)
Invalid photocell
(1 pixels)
Note
Note
Note Set the
RB to high level and
CLB to low level during this period.
Remark Inverse pulse of the
TG1 to
TG3 can be used as
CLB.
Data Sheet S17085EJ2V0DS
17
PD8882
TIMING CHART 2-1 (2400 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
90%
10%
10%
90%
10%
90%
t9
t10
t11
t1
t1
t2
t2
t7
t8
t6
t4
t19
t19
t11
t7
t4
t11
t7
t11
t
d
V
OS
t7
t4
V
OUT
CLB
CLB "H"
RB
2
1
4
3
(Bit clamp mode)
(Line clamp mode)
SEL "H"
RFTN
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
160
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-5
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t19 110
500
-
ns
t
d
- 25 -
ns
Data Sheet S17085EJ2V0DS
18
PD8882
TIMING CHART 2-2 (1200 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
90%
10%
10%
90%
t9
t10
t11
t1
t2
t7
t8
t6
t5
t3
t4
t9
t10
t11
t7
t8
t6
t19
t19
t
d
t
d
V
OS
10%
V
OUT
CLB
CLB "H"
SEL "L"
RB
2
1
4
3
(Bit clamp mode)
(Line clamp mode)
RFTN
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
160
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-5
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t19 110
500
-
ns
t
d
- 25 -
ns
Data Sheet S17085EJ2V0DS
19
PD8882
TIMING CHART 2-3 (600 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
10%
90%
t9 t10
t11
t1
t2
t7
t8
t6
90%
10%
10%
90%
t1
t2
t19
t19
V
OUT
CLB
CLB "H"
RB
2
1
4
3
(Bit clamp mode)
(Line clamp mode)
RFTN
t
d
SEL "L"
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
160
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-5
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t19 110
500
-
ns
t
d
- 25 -
ns
Data Sheet S17085EJ2V0DS
20
PD8882
TIMING CHART 2-4 (300 dpi, for each color)
t5
t3
t4
90%
10%
90%
10%
90%
10%
10%
10%
90%
t9 t10
t11
t1
t2
t7
t8
t6
90%
10%
10%
90%
t1
t2
t19
t19
V
OUT
CLB
CLB "H"
RB
2
1
4
3
(Bit clamp mode)
(Line clamp mode)
RFTN
t
d
SEL "L"
Symbol Min. Typ. Max. Unit
t1, t2
0
30
-
ns
t3 20
160
-
ns
t4
40
150
-
ns
t5, t6
0
10
-
ns
t7
-5
+25
-
ns
t8
20
100
-
ns
t9, t10
0
10
-
ns
t11 10
25
-
ns
t19 110
500
-
ns
t
d
- 25 -
ns
Data Sheet S17085EJ2V0DS
21
PD8882
TIMING CHART 3
90%
90%
90%
90%
90%
90%
t13
t15
t17
t18
t16
t12
t14
10%
90%
90%
10%
CLB
RB
1
TG1 to TG3
3
(Line clamp mode)
Remark
Inverse pulse of the
TG1 to
TG3 can be used as
CLB (when line clamp mode).
Symbol Min. Typ. Max. Unit
t12 5000
10000
50000
ns
t13, t14
0
50
-
ns
t15, t16
900
1000
-
ns
t17, t18
200
400
-
ns
1, 2, 3, 4 cross points
2, 4
1, 3
2.0 V or more
2.0 V or more
Remark
Adjust cross points of (
1,
2) and (
3,
4) with input resistance of each pin.
Data Sheet S17085EJ2V0DS
22
PD8882
SELECTION OF RESOLUTION MODE
The
PD8882 has function of two readout modes, High Resolution Mode and Low Resolution Mode. These two
modes can be selected by
SEL switch.
Read Mode
Description
SEL
High Resolution Mode
2400 dpi (Max.)
High level
Low Resolution Mode
1200 dpi (Max.) (odd line readout mode)
Low level
(1) High Resolution Mode
In this mode, both signals in even lines and odd lines can be read out. This mode enables 2400 dpi (Max.)
resolution with A4 size (210
297 mm, shorter side).
Please refer to TIMING CHART 1-1, 1-2 and 2-1.
(2) Low Resolution Mode
In this mode, only signal in odd photocell arrays can be read out.
This mode enables 1200 dpi (Max.) resolution with A4 size.
To use intermittent reset drive enable signal charges of adjacent pixels in odd line to add at the charge to voltage
conversion area. Then it can achieve low resolution with A4 size such as 600, 300 or 150 dpi.
Please refer to TIMING CHART 1-3 to 1-8, 2-2 to 2-4.
SEL TIMING CHART
After changing the dpi selector signal (
SEL), subsequent data of one line cannot be guaranteed (refer the follow
figure).
Invalid date 1 line
Valid date
V
OUT
1 to V
OUT
3
SEL
TG1 to
TG3
Data Sheet S17085EJ2V0DS
23
PD8882
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : V
sat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The output signal non-uniformity of all the valid pixels when the photosensitive surface is applied with the light
of uniform illumination. This is calculated by the following formula.
PRNU (%) =
x =
x
j
: Output voltage of valid pixel number j
x
x : maximum of
x
j
- x
x
21360
j = 1
21360
x
j
100
x
Register Dark
DC level
V
OUT
x
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
21360
j = 1
21360
d
j
Data Sheet S17085EJ2V0DS
24
PD8882
5. Dark signal non-uniformity : DSNU
Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the
valid pixels at light shielding. This is calculated by the following formula.
d
j
: Dark signal of valid pixel number j
DSNU (mV) : maximum of
d
j
- ADS
j = 1 to 21360
ADS
DSNU
Register Dark
DC level
V
OUT
6. Output impedance : Z
O
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lxs).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
V
OUT
TG
Light
V
OUT
ON
OFF
V
1
IL (%) =
V
1
V
OUT
100
Data Sheet S17085EJ2V0DS
25
PD8882
9. Photo diode response imbalance: PDRI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
PDRI (%) =
2
n
j = 1
j = 1
n
2
(V
2j 1
V
2j
)
1
n
n
V
j
100
n
V
j
: Number of valid pixels
: Output voltage of each pixel
10. Offset level : V
OS
DC level of output signal is defined as follows.
11. Reset feed-through noise : RFTN
Reset feed-through noise (RFTN) are defined as follows.
V
OUT
+
V
OS
RFTN
Data Sheet S17085EJ2V0DS
26
PD8882
12. Random noise (CDS) :
CDS
Random
noise
CDS is defined as the standard deviation of a valid pixel output signal with 100 times (=100
lines) data sampling at dark (light shielding).
CDS is calculated by the following procedure.
1. One valid photocell in one reading is fixed as measurement point.
2. The output level is measured during the reset feed-through period which is averaged over 100 ns to get
"VD
i
".
3. The output level is measured during the video output time averaged over 100 ns to get "VO
i
".
4. The correlated double sampling output is defined by the following formula.
VCDS
i
= VD
i
VO
i
5. Repeat the above procedure (1 to 4) for 100 times (= 100 lines).
6. Calculate the standard deviation
CDS using the following formula equation.
CDS (mV) =
, V =
i
=
1
100
(VCDS
i
V)
2
i
=
1
100
VCDS
i
100
100
1
Reset feed-through
Video output
Data Sheet S17085EJ2V0DS
27
PD8882
STANDARD CHARACTERISTIC CURVES (Reference Value)
400
500
600
700
800
100
80
60
40
20
0
B
B
G
R
G
Response Ratio (%)
Wavelength (nm)
TOTAL SPECTRAL RESPONSE CHARACTERISTICS
(without infrared cut filter and heat absorbing filter) (T
A
= +25
C)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC
STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25
C)
Operating Ambient Temperature T
A
(
C)
Storage Time (ms)
8
4
2
1
0.5
0.25
0.1
10
0
20
30
40
50
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.1
1
5
10
Data Sheet S17085EJ2V0DS
28
PD8882
APPLICATION CIRCUIT EXAMPLE
V
OUT
2
V
OUT
3
PD8882
V
OD
GND
NC
NC
NC
NC
V
OD
GND
NC
4
3
1
SEL
TG3
CLB
TG1
2
TG2
47
R
S
4.7
47
4.7
4.7
10
10
4.7
47
10
1
22
21
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
9
8
10
11
V
OUT
1
RB
B2
+12 V
0.1 F
47 F/25 V
0.1 F
10 F/16 V
TG
2
RB
4
CLB
B1
+5 V
+5 V
+
0.1 F
10 F/16 V
+
+
SEL
B3
3
1
Caution Connect the No connection pins (NC) to GND.
Remarks 1.
RB,
CLB,
TG1 to
TG3 and
SEL driving inverters shown in the above application circuit
example are the 74HC04.
1 to
4 driving inverters shown in the above application circuit example are the 74HC04 (
2.0
MHz) or the 74AC04 (
> 2.0 MHz).
2. Inverters B1 to B3 in the above application circuit example are shown in the figure below.
47 F/25 V
B1 to B3 EQUIVALENT CIRCUIT
+
12 V
100
100
CCD
V
OUT
2SC1842
2 k
Data Sheet S17085EJ2V0DS
29
PD8882
PACKAGE DRAWING
CCD LINEAR IMAGE SENSOR 22-PIN PLASTIC DIP (10.16 mm (400))
PD8882CY
44.0
0.3
37.5
1st valid pixel
1.52
0.3
1
9.25
0.3
2.0
0.25
0.05
10.16
0.2
0.46
0.1
2.54
0.25
1.02
0.15
(5.42)
4.21
0.5
4.39
0.4
12
11
2.62
0.2
3
(1.72)
2
Name
Dimensions
Refractive index
Plastic cap
42.7
8.350.8(0.7 )
1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
22C-1CCD-PKG18
(Unit : mm)
1
22
10.16
+0.7
-0.2
4
4
5
4 Mirror finished surface
5 Thickness of mirror finished surface
Data Sheet S17085EJ2V0DS
30
PD8882
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
For technical information, see the following website.
Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
Type of Through-hole Device
PD8882CY-A : CCD linear image sensor 22-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method
Pin temperature : 300
C or below, Heat time : 3 seconds or less (per pin)
Cautions 1.
During assembly care should be taken to prevent solder or flux from contacting the plastic
cap. The optical characteristics could be degraded by such contact.
2.
Soldering by the solder flow method may have deleterious effects on prevention of plastic
cap soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S17085EJ2V0DS
31
PD8882
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don't either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 M
.
4
3
RECOMMENDED SOLVENTS
Solvents
Symbol
Data Sheet S17085EJ2V0DS
32
PD8882
[MEMO]
Data Sheet S17085EJ2V0DS
33
PD8882
[MEMO]
Data Sheet S17085EJ2V0DS
34
PD8882
[MEMO]
Data Sheet S17085EJ2V0DS
35
PD8882
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
PD8882
The information in this document is current as of May, 2005. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or
data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all
products and/or types are available in every country. Please check with an NEC Electronics sales
representative for availability and additional information.
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may
appear in this document.
NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from the use of NEC Electronics products listed in this document
or any other liability arising from the use of such products. No license, express, implied or otherwise, is
granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others.
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of a customer's equipment shall be done under the full
responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by
customers or third parties arising from the use of these circuits, software and information.
While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products,
customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To
minimize risks of damage to property or injury (including death) to persons arising from defects in NEC
Electronics products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment and anti-failure features.
NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and
"Specific".
The "Specific" quality grade applies only to NEC Electronics products developed based on a customer-
designated "quality assurance program" for a specific application. The recommended applications of an NEC
Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of
each NEC Electronics product before using it in a particular application.
The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC
Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications
not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to
determine NEC Electronics' willingness to support a given application.
(Note)
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
defined above).
Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots.
Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support).
Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
"Standard":
"Special":
"Specific":
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