QB-8 Series Features
QB-8 Series Benefits
0.44-micron (drawn), 3-level metal process
Delivers Bipolar speed at CMOS turn-time and cost
BiCMOS process does not use epitaxial layer
Shortens turnaround time and reduces cost of production
11 base arrays with raw gates from 33K to 382K gates
Satisfies user requirements with many base arrays
Optimized pad pitch
Reduces assembly cost for BGA and QFP wirebond
Optimized I/O cell size
Enables high-speed I/O buffers in only one I/O slot
"PUZZLE" cell architecture with mixed transistor sizes
Achieves high speed; keeps driveability and low power
PCI, GTL, HSTL, pECL interface blocks
Delivers I/O for up to 250-MHz data transfer
90- to 160-MHz PLL and clock tree synthesis
Eliminates clock insertion delay; reduces clock skew
Clock tree synthesis tool
Automatic insertion of low-skew clock tree
Low power dissipation of 1.0 W/MHz/gate
Delivers support for ultra-high-speed communications
Asynchronous 1- and 2-port RAM blocks
Allows high-speed, low-power BiCMOS operation
BGA, PQFP, PGA packaging
Provides support for high-speed RAM
622-MHz I/O and 622MHz PLL in QB-8E (release FY/96)
Supports popular packaging solutions
QB-8
3.3-Volt, 0.44-Micron
Gate Arrays
Figure 1. 672-pin BGA
April 1996
OpenCAD is a registered trademark of NEC Electronics Inc.
NEC Electronics Inc.
Description
NEC's 3.3-volt QB-8 family consists of ultra-high-
performance, submicron gate arrays targeted for
applications requiring high speeds and low power
dissipation. The QB-8 family offers not only high speed
but also low power dissipation and high density at a
reasonable price. This combination of features is made
possible through the use of a unique epi-less process
that delivers the low cost and short manufacturing time
of CMOS with the high speed of bipolar technology.
QB-8 is targeted for designs in advanced networks and
data communications, industrial applications, telecom-
munications, and computing applications such as
engineering workstations, high-end personal computers,
mainframes, and high-speed peripherals.
The device processing includes a 0.44-micron silicon-
gate technology and three-layer metalization. This
t e c h n o l o g y f e a t u r e s c h a n n e l e s s ( s e a - o f - g a t e )
architecture with an internal gate delay of 107 ps (F/O =
1, L = 0) and power dissipation of 1.0 W/MHz/gate.
The high-performance I/O macros include LVTTL, GTL,
HSTL, and pECL. PCI signaling standards are also
supported, including those for a 3.3-volt, 66 MHz PCI.
This technology is enhanced by a set of advanced
features that include phase-locked loops, clock tree
synthesis, and high-speed memories.
A11111EU1V0DS00
Table 1. QB-8 Series Features and Benefits
The QB-8 family consists of 11 masters offered in
densities of 33K to 382K raw gates. The gate array
family is supported by NEC's OpenCAD design
system, a mixture of popular third-party CAE tools, and
proprietary NEC tools. NEC's proprietary tools include
the GALET floorplanner, which helps reduce design
cycle time and improve design performance, clock tree
synthesis for clock skew minimization, and a table look-
up delay calculator for accurate delay calculation.
Preliminary
QB-8
2
Array Architecture
The QB-8 family is built with NEC's 0.44-micron
channeless array architecture. The array is divided into
I/O and core regions (see Figure 2). The I/O regions
contain input and output buffers. The core region
contains the sea-of-gates array. The QB-8 gate arrays
architecture provides extra flexibility for high-performance
system designs. The arrays contain several power rails,
a 3.3-volt rail, and power rails for special I/O types such
as 5-volt PCI, HSTL, GTL, and pECL.
Core Architecture
QB-8 uses a proprietary architecture called PUZZLE.
It combines three transistors of different sizes into a
single, highly dense architecture tightly interlocked as
in a puzzle. The result is an ASIC that uses small
CMOS transistors for low input capacitance and
signaling within a macro, and bipolar transistors for
high drive-ability and signaling between macros.
The core region consists of an array of gates. Each
cell contains four n-channel and two p-channel
transistors and one bipolar transistor. One cell is
equivalent to one 2-input NAND gate (L302). The logic
transistors are sized to offer a superior ratio of speed
to silicon area.
Figure 2. Chip Layout and Internal Cell Configuration
Test
The QB-8 family supports automatic test generation
through a scan-test methodology, which allows higher
fault coverage, easier testing, and quicker development
time. NEC also offers optional BIST test architecture for
RAM testing.
Packaging
NEC offers an extensive variety of more than 60 package
types. The QB-8 family can be packaged in NEC's most
popular surface-mount and through-hole packages.
These include plastic quad-flat packs (PQFPs). Pin grid
arrays (PGAs) and BGA packages are also supported.
The 672-pin BGA package is shown in Figure 1.
Publications
This data sheet contains specifications, package
information, and operational data for the QB-8 gate
array families. Additional design information is avail-
able in NEC's QB-8 Block Library and QB-8 Design
Manual. Call your local NEC design center or call the
NEC toll-free literature line for additional ASIC design
information; see the back of this data sheet for
locations and telephone numbers.
Gate Array Sizes
Available
Usable
I/O
Metal
Device
Gates
Gates
Pads
Layers
PD67821
32832
22982
156
3
PD67822
44352
31046
180
3
PD67823
56800
39760
204
3
PD67824
69520
48664
224
3
PD67825
93184
65229
260
3
PD67826
123808
86666
300
3
PD67827
136752
95726
316
3
PD67828
167280
117096
348
3
PD67829
234320
164024
412
3
PD67830
292896
205027
460
3
PD67831
381840
267288
524
3
Actual gate utilitization varies depending on circuit implementation. Utiliza-
tion is 70% for three-layer metal. Depending on package and circuit
specifications, some pads are used for V
DD
and GND and are not
available as signal pads.
Universal
power
lines
3.3V
3
QB-8
Input/Output Capacitance
V
DD
= V
I
= 0 V; f = 1 MHz
Terminal
Symbol
Typ
Max
Unit
Input
C
IN
10
20
pF
Output
C
OUT
10
20
pF
I/O
C
I/ O
10
20
pF
Note:
(1) Values do not include package pin capacitance.
Power Consumption
Description
Limits
Unit
Internal cell
1.09
W/MHz
Input block (FI01)
6.92
W/MHz
Output block (F002 @ 15 pF)
260
W/MHz
Absolute Maximum Ratings
Power supply voltage, V
DD
0.5 to 4.6 V
Input voltage, V
I
3 V input buffer (at V
I
< V
DD
+ 0.5 V)
0.5 to 4.6 V
3 V fail-safe input buffer (at V
I
< V
DD
+ 0.5 V)
0.5 to 4.6 V
5 V-tolerant buffer (at V
I
< V
DD
+ 3.0 V)
0.5 to 6.6 V
Output voltage, V
O
3 V buffer (at V
O
< V
DD
+ 0.5 V)
0.5 to 4.6 V
5 V-tolerant buffer (at V
O
< V
DD
+ 3.0 V)
0.5 to 6.6 V
Latch-up current, I
LATCH
>1 A (typ)
Operating temperature, T
OPT
40 to +85C
Storage temperature, T
STG
65 to +150C
Recommended Operating Conditions
3 V Buffer
5 V-Tolerant
3.3 V PCI
5 V PCI
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Power supply voltage
V
DD
3.0
3.6
3.0
3.6
3.0
3.6
3.0
3.6
V
Junction temperature
T
J
40
+125
40
+125
40
+125
40
+125
C
Low-level input voltage
V
IL
0
0.8
0
0.8
0.5
0.3 V
DD
0.5
0.8
V
High-level input voltage
V
IH
2.0
V
DD
2.0
V
DD
0.5 V
DD
V
DD
+0.5
2.0
V
DD
+0.5
V
Input rise or fall time
t
R
, t
F
0
200
0
200
0
200
0
200
ns
Input rise or fall time, Schmitt
t
R
, t
F
0
10
0
10
0
200 ns
--
--
ms
AC Characteristics
V
DD
= 3.3 V 0.3 V; T
j
= -40 to +125C
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Toggle frequency
f
TOG
670
MHz
D-F/F; F/O = 1
Delay time
2-input NAND (F322)
t
PD
90
ps
F/O = 1; L = 0 mm
t
PD
106
ps
F/O = 2; L = typ
Flip-flop (F611)
t
PD
463
ps
F/O = 1; L = 0 mm
t
PD
492
ps
F/O = 2; L = typ
t
SETUP
540
ps
--
t
HOLD
10
ps
--
Input buffer (FI01)
t
PD
211
ps
F/O = 1; L = 0 mm
t
PD
220
ps
F/O = 2; L = typ
Output buffer (12 mA) 3.3 V
t
PD
925
ps
C
L
= 0 pF
Output buffer (12 mA) 3.3 V
t
PD
2136
ps
C
L
= 50 pF
Output buffer (12 mA) 5 V-tolerant
t
PD
TBD
ps
C
L
= 0 pF, 50 pF
Output buffer (6 mA) 5 V-tolerant
t
PD
1004
ps
C
L
= 0 pF
Output buffer (6 mA) 5 V-tolerant
t
PD
2158
ps
C
L
= 50 pF
Output rise time (9 mA)
t
R
920
ps
C
L
= 15 pF
Output fall time (9 mA)
t
F
680
ps
C
L
= 15 pF
QB-8
4
DC Characteristics
V
DD
= 3.3 V 0.3 V; T
J
= -40 to +125C
Parameter
Symbol
Min
Typ
Max
Unit
Conditions
Quiescent current
PD67831, 67830
I
DDS
15
4800
A
V
I
= V
DD
or GND
PD67829, 67828, 67827
I
DDS
9
3000
A
V
I
= V
DD
or GND
PD67826, 67825, 67824
I
DDS
5
1500
A
V
I
= V
DD
or GND
PD67823, 67822, 67821
I
DDS
2
700
A
V
I
= V
DD
or GND
Off-state output leakage current
3 V output
I
OZ
10
A
V
O
= V
DD
or GND
5 V-tolerant output
I
OZ
14
A
V
O
= V
DD
or GND
Output sink current with pull-up (V
O
= 3 V)
I
R
14
A
V
PU
= 5.5 V, R
PU
= 2k
Output sink short circuit current
I
OS
250
mA
V
O
= GND
Input leakage current
Regular
I
I
10
A
V
I
= V
DD
or GND
50 k
pull-up
I
I
30
66
144
A
V
I
= GND
5 k
pull-up
I
I
300
660
1440
mA
V
I
= GND
50 k
pull-down
I
I
30
66
144
A
V
I
= V
DD
Pull-up resistor
50 k
pull-up
R
PU
25.0
50.0
100.0
k
5 k
pull-up
R
PU
2.5
5.0
10.0
k
50 k
pull-down
R
PD
25.0
50.0
100.0
k
Low-level output current
3 V buffers
3 mA (F009)
I
OL
3
mA
V
OL
= 0.4 V
6 mA (F004)
I
OL
6
mA
V
OL
= 0.4 V
9 mA (F001)
I
OL
9
mA
V
OL
= 0.4 V
12 mA (F002)
I
OL
12
mA
V
OL
= 0.4 V
18 mA (F003)
I
OL
18
mA
V
OL
=0.4 V
24 mA (F006)
I
OL
24
mA
V
OL
= 0.4 V
5 V-tolerant buffers
1 mA (FV0A)
I
OL
1
mA
V
OL
= 0.4 V
2 mA (FV0B)
I
OL
2
mA
V
OL
= 0.4 V
3 mA (FV09)
I
OL
3
mA
V
OL
= 0.4 V
6 mA (F002)
I
OL
6
mA
V
OL
= 0.4 V
Low-level output voltage
3 V buffers
V
OL
0.1
V
I
OL
= 0 mA
5 V-tolerant buffers
V
OL
0.1
V
I
OL
= 0 mA
High-level output voltage
3 V buffers
V
OH
V
DD
0.1
V
I
OH
= 0 mA
5 V-tolerant buffers
V
OH
V
DD
0.2
V
I
OH
= 0 mA
5
QB-8
QB-8
6
For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782
or FAX your request to: 1-800-729-9288
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc.
(NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE
PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY, WAR-
RANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding information set forth
herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that
may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The
devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems, aerospace
equipment, submarine cables, nuclear reactor control systems and life support systems. "Standard" quality grade devices are recom-
mended for computers, office equipment, communication equipment, test and measurement equipment, machine tools, industrial robots,
audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-
disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the
reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in
life support devices or systems or in any application where failure could result in injury or death. If customers wish to use NECEL devices
in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL's willingness
to support a given application.
1996 NEC Electronics Inc./Printed in U.S.A.
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