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Электронный компонент: UPD98411

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ATM QUAD SONET FRAMER
Document No. S12953EJ4V0DS00 (4th edition)
Date Published January 1999 NS CP(K)
Printed in Japan
NEC Corporation 1997,1999
MOS INTEGRATED CIRCUIT



PD98411
DATA SHEET
The
PD98411 NEASCOT-P40 is one of ATM-LAN LSIs and provides the functions of the TC sublayer of the
SONET/SDH-base physical layer of the ATM protocol specified by the ATM Forum. Its main functions include a
transmission function to map an ATM cell passed from an ATM layer to the payload of 155M-bps SONET STS-
3c/SDH STM-1 frame and transmit the cell to the PMD (Physical Media Dependent) sublayer of the physical layer,
and a reception function to separate the overhead and ATM cell from the data string received from the PMD device
and transmit the ATM cell to the ATM layer. The
PD98411 NEASCOT-P40 combines these transmission
/reception functions into a port function that is realized as a single 4-port LSI chip. This LSI is ideally suited for
use in the ATM hubs, ATM switches, and other equipment used to configure an ATM network.
In addition, the
PD98411 also has a clock recovery function for each port to extract synchronous clock for
reception of receive data from the bit stream, and a clock synthesis function to generate a clock for transmission.
For the details of functional description, refer to the following user's manual.



PD98411 User's Manual : S12736E
FEATURES
Incorporates an ATM user network interface TC sublayer function for four channels.
Conforms to ATM FORUM UNI v3.1.
Incorporates four clock recovery PLLs and one clock synthesizer PLL.
Conforms to ATM FORUM UTOPIA Level 2 v1.0.
ATM layers can be selected from the multi-PHY interface (up to 800 Mbps) in several different modes.
Single 16-bit
1TCLAV/1RCLAV (Cell Available signal mode)
Single 8-bit
Direct Status Indication mode
Dual 8-bit
Multiplexed Status Polling mode
A management interface can be set to either of two modes.
RD-WR-RDY style (Intel-compatible mode)
DS-R/W-ACK style (Motorola-compatible mode)
The line-side PMD interface accepts a P-ECL level input.
Supports a loopback function.
Supports a pseudo error generation frame transmission function.
Incorporates one general input port per channel and three output ports (each able to drive an LED) per
channel.
Supports JTAG boundary scan test (IEEE 1149.1).
Data Sheet S12953EJ4V0DS00
2



PD98411
Incorporates a wide range of operation, administration, and maintenance (OAM) functions.
Transmission
Alarm Condition and Failure Detection
Line Quality Monitoring
APS
Insertion of B1-byte computation
Line AIS/Path AIS
Insertion of B2-byte computation
Line RDI/Path RDI
Insertion of B3-byte computation
Automatic transmission of a Line REI
Automatic transmission of a Path REI
Reception
Alarm Condition and Failure Detection
Notification of Degraded Line Quality
Line Quality Monitor Counter
External input signal change
B1 error
B1 error counter
LOS
B2 error
B2 error counter
OOF
B3 error
B3 error counter
LOF
Line REI
Line REI counter
LOP
Path REI
Path REI counter
OCD
Frequency justification
Frequency justification counter
LCD
FIFO overflow
HEC processing dropped cell counter
Line AIS/Path AIS
FIFO overflow dropped cell counter
Line RDI/Path RDI
Received idle cell counter
APS
Valid cell counter
0.35-
m CMOS process
Low power consumption; +3.3 V single-voltage power supply
ORDERING INFORMATION
Part Number
Package
PD98411GN-MMU
240-pin plastic QFP (fine pitch) (32
32 mm)
Data Sheet S12953EJ4V0DS00
3



PD98411
APPLICATIONS
The following are examples of the application using the
PD98411.



ATM Switches
NIC
NIC
NIC
PD98411
UTOPIA Level2
CPU
SWITCH
155 ATM Interface
Backbone
Network
OC-12
SONET Framer
PD98411
PD98411
PD98411
Data Sheet S12953EJ4V0DS00
4



PD98411
SYSTEM CONFIGURATION
1)



PD98411 System Application



PD98411
(NEASCOT-P40)
Processor
ATM Layer Device
Optical
Module
Optical
Module
Equalizer
Components
Equalizer
Components
Magnetics
RJ-45
Connector
Magnetics
RJ-45
Connector
OSC
(19.44M)
Shielded Twist Pair
Management I/F
Rx UTOPIA I/F
Multimode Fiber
Tx UTOPIA I/F
Status
PMD I/F
(PECL)
2) Connection to 5-V transceiver/receiver
The following show an example of connecting the
PD98411 to a 5-V optical transceiver. Since the
PD98411 operates on 3.3 V, a coupling circuit should be added if it is to be connected to a 5-V device.
820
110
110
510
820
91
91
Port0
RDIT0
RDIC0
TDOT0
TDOC0
SD0
RSDT
RSDC
TXDT
TXDC
VCCR
VCCT
VEER
VEET
SD
PECL->TTL
translator
MC10H350 by
Motorola, etc.
5V optical transceiver
5V
0.1
F
0.1
F
3.3V
GND
5V
510
GND
GND
0.1
F
4
430
430
82
130
1.1k
1.1k
82
GND
PD98411
130
Data Sheet S12953EJ4V0DS00
5



PD98411
3) UTOPIA Interface
The UTOPIA interface transfers transmit/receive cell data to a device in the upper ATM layer. The interface
between the
PD98411 and the ATM layer conforms to "MPHY Data Path Operation" of the "UTOPIA Level 2
version 1.0 June '95" standard.
Bus Mode
The way to indicate Cell Available state
Dual eight-bit bus.
In this mode, an 8-bit data bus is used for two ports. Ports 0
and 1 transfer signals using one eight-bit bus, while ports 2
and 3 transfer signals using another eight-bit bus. The ports
operate independently.
PD98411
8-bit
ATM layer
device
8-bit
ATM layer
device
Port1
Port2
Port3
Port0
PMD
UTOPIA
One TCLAV & one RCLAV signal mode
The one TCLAV & one RCLAV signal mode outputs the TCLAV
and RCLAV signal status information for four ports of the
PD98411 by multiplexing them into a single signal.
RADD
TADD
RDO
TCLAV
RCLAV
ATM layer
Device
PD98411
Port0
Port1
Port2
Port3
TDI
8 or 16-bit
Single eight-bit bus.
In this mode, cell data for all four ports is transferred through
an eight-bit bus. The maximum transfer rate is 400 Mbps
(8 bits x 50 MHz).
PD98411
8-bit
ATM layer
device
Port0
Port1
Port2
Port3
PMD
UTOPIA
Direct Status Indication Mode
PD98411 has four TXCLAV and RXCLAV status signals, one
pair of TXCLAV and RXCLAV for each port. Status signals and
cell transfers are independent of each other. No address
information is needed to obtain status information.
8 or 16-bit
TDI
RCLAV3-RCLAV0
TCLAV3-TCLAV0
ATM layer
Device
PD98411
Port0
Port1
Port2
Port3
RDO
RADD
TADD
Single sixteen-bit bus.
In this mode, cell data for all four ports is transferred through
a sixteen-bit bus. The maximum transfer rate is 800 Mbps
(16 bits x 50 MHz).
PD98411
16-bit
ATM layer
device
Port0
Port1
Port2
Port3
PMD
UTOPIA
Multiplexed Status Polling Mode
When six or more
PD98411s are connected to one ATM layer,
ATM layer obtain the status information of all the connected
ports in the 53 clock cycles in which it transmits or receives a
single data cell. Because a minimum of two clock cycles are
required to obtain the TCLAV/RCLAV signal status of a port by
ATM layer polling. Therefore every port address is allocated in a
fixed manner to one of the four status signals and to one of eight
port groups.