NJU6356
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SERIAL I/O REAL TIME CLOCK
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GENERAL DESCRIPTION
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PACKAGE OUTLINE
The NJU6356 series is a serial I/O real time clock suitable
for 4 bits microprocessor.
It contains quartz crystal oscillator, counter, shift register,
voltage regulator, voltage detector and interface controller.
The NJU6356 series required only 4-port of microprocessor
for data transfer, and the microprocessor can receive the data
at any time when the microprocessor requires.
The operating voltage is as wide as 2.0V to 5.5V,
consequently, the NJU6356 series can count accurate time
data even if the back up period.
Furthermore, the long time back up is available as the
operating current during the back up period is less than
3uA(TYP).
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FEATURES
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PIN CONFIGURATION
q
Low Operating Voltage
2.0 to 3.6V
q
Low Operating Current
3.0uA (TYP) @2.0V
3.0uA
(TYP)
@3.0V
4.0uA
(TYP)
@5.0V
q
BCD Counts of Seconds, Minutes, Hours, Days of Week
Day, Month and Year
q
Required only 4-port
DATA, CLK, CE and I/O
q
Low Battery Detector
Low Voltage Alarm Signal Output
q
Automatic Leap Year Compensation
Up to AD 2099
q
Package Outline
DIP8 / DMP8
q
C-MOS Technology
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LINE-UP TABLE
Type No.
Output Data
Oscillation Capacitor
NJU6356 E Seconds, Minutes, Hours, Days of Week, Day, Month, Year Cd=21pF / Cg=21pF on Chip
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BLOCK DIAGRAM
DATA
Timer Counter
Sec. Min.
Hr.
Days of
Week
Day
Month Year
Shift Register
Controller
&
Clock Counter
Voltage Detector
CLK
CE
XT
XT
V
SS
V
DD
Oscillator
Divider
I/O
Sec. Min.
Hr.
Day
Month Year
Days of
Week
XT
V
SS
V
DD
DATA
CLK
CE
XT
I/O
NJU6356ED
NJU6356EM
NJU6356
- 2 -
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TREMINAL DESCRIPTION
No. SYMBOL
FUNCTION
1
I/O
Input/Output Select Terminal for DATA Terminal
"H" : Input, "L" : Output
During the CE terminal is "L", the DATA terminal is high impedance.
2 XT
3
XT
Quartz Crystal Connecting Terminal (f=32.768kHz)
Refer to the line-up table for internal Cg, Cd value.
5 CE
Chip Enable Input Terminal (with Pull-down Resistance)
"H" : DATA input/output is available.
"L" : DATA terminal is high impedance.
When the CE signal is which rising edge or falling edge,
the CLK signal should be fixed to "L".
6 CLK
Clock Input Terminal
The DATA input/output is synchronized this clock.
When the CE terminal is "L" the DATA terminal is high impedance.
I/O
CE DATA
H H
Input
L H
Output
H L
High
Impedance
L L
High
Impedance
7 DATA
Serial Timer Data Input/Output Terminal
8 V
DD
Power Supply
4 V
SS
GND
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FUNCTIONAL DESCRIPTION
1. Timer Data Structure
The NJU6356 using BCD code which consisting of 4 bits per 1 digit. The calender function including the last
date of each month and the leap year calculation is executed automatically. The unused bit for the timer data is
"0".
Timer Data Bit Map
MSB
LSB
Range
Second
0 S6 S5 S4 S3 S2 S1 S0 0
to
59
Minute
0 m6 m5 m4 m3 m2 m1 m0 0
to 59
Hour
0 0 H5 H4 H3 H2 H1 H0 0
to
23
Days
of
Week
0
W2
W1
W0
1
to
7
Day
0 0 D5 D4 D3 D2 D1 D0 1
to
31
Month
0 0 0 M4 M3 M2 M1 M0
1
to
12
Year
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0
to
99
NJU6356
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2. Timer Data Reading
When the I/O termianl is "L" and the CE tarminal is "H", timer data can read out. The output is LSB first and the
output data strings is shown below.
The timer data is transferred from timer counter to shift register at rising edge of the chip enable on the CE
terminal, and output the LSB of the timer data from the DATA terminal.
Afterward the timer data in the shift register shift by synchronized at the falling edge of clock signal on the CLK
terminal and output from the DATA terminal.
If the timer data is updated in the data output, there are one second difference between timer data and output
data.
Type E
Year Month Day
Days of
Week
Hour Minute
Second
The data is read out from LSB of Year, and first 52-bit is effective.
If the low voltage detector detect the low battery, (EE)
H
is written into each digit of timer data and read out. The
code of (EE)
H
is a warning for the broken.
< Read Out Timing >
Year
Second
CLK
CE
I/O
Data
Output
Shift
Register
(1) (2)
The timer data is transferred to the shift register at rising edge of the CE (1)
and LSB of the timer data is output to the DATA terminal. Afterward the
timer data in the shift register shift by synchronized at falling edge of the
CLK(2) then output to the DATA terminal time-to-time.
1
2
3
4
5
6
7
3
4
5
6
7
0
1
2
3
4
5
6
7
3
4
5
6
7
0
Note) When the CE signal is which rising edge or falling edge,
the CLK signal should be fixed to "L". And so, before the
CE signal is raised, the I/O signal should be fixed to "L".
NJU6356
- 4 -
3. Timer Data Writing
When both of the I/O terminal and the CE terminal are "H", update is stopped, the oscillator divider is cleared,
and the timer data can be written to the NJU6356.
The timer data is written into the shift register from the DATA terminal by synchronized with rising edge of the
clock signal input from the CLK terminal, and the data is transferred from the shift register to the timer counter by
synchronized with falling edge of the CE signal. In this time the second-counter is cleared to "0", and the oscillator
divider start the operation.
The input data strings are LSB first of each digit as shown below.
Type E
Year Month Day
Days of
Week
Hour Minute
Second
The data is read out from LSB of Year, and last 44-bit is effective.
< Write Down Timing >
4. Low Voltage Detector
The NJU6356 series incorporate the low battery detector. If the supply voltage reduce to the detection level,
(EE)
H
is written into each digit of the shift register as warning code for the CPU.
5. Data Access
The NJU6356 series can operate from 2.0V to 5.5V. However, it is not allow the data access out of the range of
5V10%. It may be broken the data unless 5V10%.
Thus, when the data access, the CE terminal should be "H" after the power supply rise to 5V10%, then start the
operation.
CLK
CE
I/O
The data is input into the shift
register at rising edge of the
CLK.
The data in the shift register is
transferred to the timer counter at this
falling edge of the CE, then the
oscillator divider start the operation.
Year
1
2
3
4
5
6
7
3
4
5
6
7
0
1
2
3
4
5
6
7
0
3
4
5
6
7
Minute
Data
Input
Shift
Register
Note) When the CE signal is which rising edge or falling edge,
the CLK signal should be fixed to "L". And so, before the
CE signal is raised, the I/O signal should be fixed to "H".
NJU6356
- 5 -
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ABSOLUTE MAXIMUM RATINGS
(Ta=25
C)
PARAMETER SYMBOL RATING
UNIT
Supply Voltage
V
DD
-0.3
to
+6.0 V
Input Voltage
V
IN
V
SS
-0.3 to V
DD
+0.3 V
Power Dissipation
P
D
250(DIP8) 200(DMP8)
mW
Operating Temperature Range
Topr
-30 to +80
C
Storage Temperature Range
Tstg
-55 to +150
C
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ELECTRICAL CHARACTERISTICS
DC Characteristics (V
DD
=2.0V, Ta=25
C)
PARAMETER SYMBOL
CONDITIONS MIN
TYP
MAX
UNIT
Operating Current
I
DD
XT=32.768kHz,
CE=0V
3.0
4.0
uA
Low Battery Detect Voltage
V
DET
1.1
1.7
V
(V
DD
=5.0V10%, Ta=25
C)
PARAMETER SYMBOL
CONDITIONS MIN
TYP
MAX
UNIT
Operating Voltage
V
DD
4.5
5.5
V
Operating Current
I
DD
XT=32.768kHz,
CE=0V
4
15
uA
3-st. Leakage Current
I
TSL
DATA (CE=0V)
-2.0
2.0
uA
Input Leakage Current
I
IL
I/O,
CLK
-1.0
1.0 uA
Input Current
I
CE
CE (CE=V
DD
)
20
uA
V
IH
I/O, CE, CLK, DATA
0.8V
DD
V
DD
Input Voltage
V
IL
I/O, CE, CLK, DATA
V
SS
0.2V
DD
V
V
OH
DATA (I
OH
=-0.4mA) 4.1
Output Voltage
V
OL
DATA (I
OL
=1.0mA)
0.4
V
AC Characteristics (V
DD
=5.0V10%, Ta=25
C, C
L
=50pF)
PARAMETER SYMBOL
CONDITIONS MIN
TYP
MAX
UNIT
CLK Pulse "H" Period
t
CWH
0.47 5000
us
CLK Pulse "L" Period
t
CWL
0.47 5000
us
CE Set-up Time Before
CLK Rising
t
CS
470 ns
CE Hold Time After CLK Falling
t
CH
20
ns
I/O Set-up Time
Before CLK Rising
t
DS
60 ns
I/O Hold Time After CLK Falling
t
DH
20
ns
Write Down Data Set-Up Time
t
WDS
100
ns
Write Down Data Hold Time
t
WDH
20
ns
Data Delay Time
After CLK Falling
t
RDD
200
ns
Rise/Fall Time
t
RF
50 ns
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