NJU6624A/B

12-character 1-line Dot Matrix LCD Controller Driver

Maximum 60 Icon Display

Serial Direct Interface with Microprocessor

Display Data RAM

- 14 x 8 bits

- 14 x 8 bits : Maximum 12-character 1-line Display

: Maximum 12-character 1-line Display

Character Generator ROM

- 7,840 bits

- 7,840 bits : 224 Characters for 5 x 7 Dots

: 224 Characters for 5 x 7 Dots

Character Generator RAM

- 1,120 bits

- 1,120 bits : 32 Patterns( 5 x 7 Dots )

: 32 Patterns( 5 x 7 Dots )

Icon Display RAM

- Maximum 60 Icons

High Voltage LCD Driver

: 8-common / 71-segment

Duty and Bias Ratio

: 1/8 duty, 1/4 bias

Master/Slave Function

:NJU6624A : Master, NJU6624B : Slave

Useful Instruction Set

: Clear Display, Address Home, Display ON/OFF Cont., Display Blink,

Address Shift, Character Shift, Dot shift, Keyscan ON/OFF Cont. e.t.c.

32Key Input (4x8 keyscan)

General output port (4 ports)

eneral output port (4 ports)

Power On Initialization / Hardware Reset

Bleeder Resistance on-chip

Software contrast control(16 step)

Oscillation Circuit on-chip

Low Power Consumption

Operating Voltage --- 2.4 to 5.5 V

Package Outline --- QFP 100

C-MOS Technology

PACKAGE OUTLINE

GENERAL DESCRIPTION

Mar.2000

Mar.2000
Ver.1

Ver.1

FEATURES

The NJU6624A/B is a Dot Matrix LCD controller driver for 12-character

The NJU6624A/B is a Dot Matrix LCD controller driver for 12-character
1-line with icon display in single chip.

1-line with icon display in single chip.
It contains bleeder resistance, general output port, keyscan circuit,

It contains bleeder resistance, general output port, keyscan circuit,
CR oscillator, microprocessor interface circuit, instruction decoder con-

CR oscillator, microprocessor interface circuit, instruction decoder con-
troller, character generator ROM/RAM, high voltage operation com-

troller, character generator ROM/RAM, high voltage operation com-
mon and segment drivers, and others.

mon and segment drivers, and others.
The character generator ROM consisting of 7,840 bits stores 224 kinds

The character generator ROM consisting of 7,840 bits stores 224 kinds
of character Font. Each 1,120 bits CG RAM and Icon display RAM

of character Font. Each 1,120 bits CG RAM and Icon display RAM
can store 32 kinds of special character displayed on the dot matrix

can store 32 kinds of special character displayed on the dot matrix
display area or 60 kinds of Icon on the Icon display area.

display area or 60 kinds of Icon on the Icon display area.
The 8-common (7 for character, 1 for icon) and 71-segment drivers

The 8-common (7 for character, 1 for icon) and 71-segment drivers
operate 12-character 1-line with 60 Icon LCD display and LED driver

operate 12-character 1-line with 60 Icon LCD display and LED driver
drives 4 LED which can use like as indicator.

drives 4 LED which can use like as indicator.
The 16th display contrast control function is incorporated. Therefore,

The 16th display contrast control function is incorporated. Therefore,
the contrast adjustment is operated easily by only simple power sup-

the contrast adjustment is operated easily by only simple power sup-
ply circuit on-chip.

ply circuit on-chip.
The complete CR oscillator requires no external components.

The complete CR oscillator requires no external components.
The serial interface which operates by 1MHz, communicates with ex-

The serial interface which operates by 1MHz, communicates with ex-
ternal MCU.

ternal MCU.
As an outstanding feature, NJU6624A/B realizes the horizontal smooth

As an outstanding feature, NJU6624A/B realizes the horizontal smooth
scroll of characters by combination of instructions.

scroll of characters by combination of instructions.
The combination of NJU6624A as the Master and NJU6624B as the

The combination of NJU6624A as the Master and NJU6624B as the
slave drive the 12-character and 2-line LCD panel or 24-character 1-

slave drive the 12-character and 2-line LCD panel or 24-character 1-
line in 1/8 duty.

line in 1/8 duty.

12-CHARACTER 1-LINE DOT MATRIX LCD

CONTROLLER DRIVER with SMOOTH SCROLL FUNCTION

NJU6624A/BFG1

PRELIMINARY

NJU6624A/B

BLOCK DIAGRAM

PIN CONFIGURATION

CR OSC Circuit

Instruction

Decoder(ID)

t
c

i
f
t

r
i
v

e
r

r
i
v

b
i
t

i
t

14x8bits

Character

Generator

RAM

(CG RAM)

Character

Generator

ROM

(CG ROM)

Icon Display

RAM

(MK RAM)

Timing

Gen.

12x5bits

5x7x32bits

840bits

r
i
a
l

t
o

r
a

l
l
e

e
r
t
o
r

I
/
O

f
f
e

Power On Reset

Reset

Display

Data RAM

(DD RAM)

Output

Buffer

LED port

I
n

t
r
u

t
i
o

i
s
t
e

r
(
I
R

)

Address

Counter

t
a

g
i
s

t
e

r
(
I
R

)

REQ

SCL

COM1

SEG

to COM7

to SEG

DATA

/COMMK

RESET

VLCD

)

P0 to P3

0SC1

VLCD2

VLCD1

Key scan Circuit

K0 to K3

VLCD1

NJU6624A/BFG1

SEG52

SEG51

SEG50

SEG49

SEG48

SEG47

SEG46

SEG45

SEG44

SEG42

SEG43

SEG41

SEG40

SEG38

SEG39

SEG37

SEG36

SEG35

SEG34

VDD

OSC1

SCL

DATA

RESET

VSS

SEG1/S0

REQ

SEG2/S1

SEG3/S2

SEG4/S3

SEG5/S4

SEG6/S5

SEG7/S6

SEG8/S7

SEG58

SEG57

SEG56

SEG55

SEG54

SEG53

NJU6624A/B

No.

SYMBOL

I/O

F U N C T I O N

2,13

VDD,VSS

Power Source:VDD=+5V,GND:VSS=0V

VLCD1

LCD driving voltage input terminal

100

99
98
97

VLCD2

V2
V4

LCD driving voltage stabilization capacitor terminals.

Connect the capacitor between VLCD2 and VSS, V1 and VSS, V2 and
VSS, V4 and VSS.

typ. : 0.1uF

OSC1

System clock input terminal

This terminal should be open for internal clock operation.

Chip select signal input of serial I/F.

SCL

Sift clock input of serial I/F.

DATA

Serial Data Input of serial I/F.

RESET

Reset Terminal.

When the "L" level is input over than 1.2ms to this terminal,
the system will be reset ( at f

OSC

145KHz ).

4-7

P0-P3

General output port
LED driver drives LED as indicator on athers.

REQ

Key request signal output terminal.

14-17

K0-K3

Key scanning input terminals.

18-25

SEG

LCD segment driving signal output / Key scanning output terminals.

26-88

SEG

LCD segment driving signal output terminals

89-95

COM

LCD common driving signal output terminals

COMMK

Icon common driving signal output terminals

TERMINAL DESCRIPTION

NJU6624A/B

FUNCTIONAL DESCRIPTION

(1-1)Register

The NJU6624A/B incorporates two 8-bit registers, an Instruction Register(IR) and a Data Register(DR). The

The NJU6624A/B incorporates two 8-bit registers, an Instruction Register(IR) and a Data Register(DR). The
Register (IR) stores instruction codes such as "Clear Display" and "Cursor Shift" or address data for Display Data

RAM(DD RAM), Character Generator RAM(CG RAM) and Icon Display RAM (MK RAM).

RAM(DD RAM), Character Generator RAM(CG RAM) and Icon Display RAM (MK RAM).
The Register(DR) is a temporary register, the data in the Register(DR) is written into the DD RAM, CG RAM or

The Register(DR) is a temporary register, the data in the Register(DR) is written into the DD RAM, CG RAM or
MK RAM.

MK RAM.

The data in the Register(DR) written by the MPU is transferred automatically to the DD RAM, CG RAM or MK

The data in the Register(DR) written by the MPU is transferred automatically to the DD RAM, CG RAM or MK
RAM by internal operation.

RAM by internal operation.
These two registers are selected by the selection signal RS as shown below.

These two registers are selected by the selection signal RS as shown below.

(1-2)Address Counter (AC)

The address counter(AC) addresses the DD RAM, CG RAM or MK RAM.

The address counter(AC) addresses the DD RAM, CG RAM or MK RAM.
When the address setting instruction is written into the Register(IR), the address information is transferred from

When the address setting instruction is written into the Register(IR), the address information is transferred from

Register(IR) to the Counter(AC). The selection of either the DD RAM, CG RAM or MK RAM is also determined by
this instruction.

this instruction.
After writing (or reading) the display data to (or from) the DD RAM, CG RAM or MK RAM, the Counter(AC) incre-

After writing (or reading) the display data to (or from) the DD RAM, CG RAM or MK RAM, the Counter(AC) incre-

ments (or decrements) automatically.

(1-3)Display Data RAM (DD RAM)

The display data RAM (DD RAM) consist of 14x 8 bits stores up to 14-character display data represented in 8-bit

code. (2 out of the 14characters are used for scroll RAM.)

code. (2 out of the 14characters are used for scroll RAM.)
The DD RAM address data set in the address counter(AC) is represented in Hexadecimal.

The DD RAM address data set in the address counter(AC) is represented in Hexadecimal.

(Example) DD RAM address " 08 "

Higher L o w e r

A C

HEX.

8
8

0
0

When the display shift is performed,the DD RAM address changes as follows:

( Left Shift Display )

0D 00

01 02

0A 0B 0C =>(0E)

( Right Shift Display )

The Character Generator ROM (CG ROM) generates 5 x 7 dots character pattern represented in 8-bit character

The Character Generator ROM (CG ROM) generates 5 x 7 dots character pattern represented in 8-bit character
code.

code.
The storage capacity is up to 224 kinds of 5 x 7 dots character pattern(available address is (20)

The storage capacity is up to 224 kinds of 5 x 7 dots character pattern(available address is (20)

through (FF)

The correspondence between character code and standard character pattern of NJU6624A/B is shown in Table 2.

The correspondence between character code and standard character pattern of NJU6624A/B is shown in Table 2.
User-defined character patterns (Custom Font) are also available by mask option.

User-defined character patterns (Custom Font) are also available by mask option.

(
(1-4)Character Generator ROM (CG ROM)

1-4)Character Generator ROM (CG ROM)

The relation between DD RAM address and display position on the LCD is shown below.

14 -Display Position

09 0A

0B 0C 0D -DD RAM Address (Hex.)

(00)<= 01

09 0A

0B 0C 0D 00

| | Scroll RAM

Электронный компонент: NJU6624AFG1