100341
Low Power 8-Bit Shift Register
General Description
The 100341 contains eight edge-triggered, D-type flip-flops
with individual inputs (P
n
) and outputs (Q
n
) for parallel op-
eration, and with serial inputs (D
n
) and steering logic for bidi-
rectional shifting. The flip-flops accept input data a setup
time before the positive-going transition of the clock pulse
and their outputs respond a propagation delay after this ris-
ing clock edge.
The circuit operating mode is determined by the Select in-
puts S
0
and S
1
, which are internally decoded to select either
"parallel entry", "hold", "shift left" or "shift right" as described
in the Truth Table. All inputs have 50 k
pull-down resistors.
Features
n
35% power reduction of the 100141
n
2000V ESD protection
n
Pin/function compatible with 100141
n
Voltage compensated operating range = -4.2V to -5.7V
n
Standard Microcircuit
Drawing (SMD) 5962-9459101
Logic Symbol
Pin Names
Description
CP
Clock Input
S
0
, S
1
Select Inputs
D
0
, D
7
Serial Inputs
P
0
P
7
Parallel Inputs
Q
0
Q
7
Data Outputs
DS100315-1
August 1998
100341
Low
Power
8-Bit
Shift
Register
1998 National Semiconductor Corporation
DS100315
www.national.com
Connection Diagrams
24-Pin DIP
DS100315-2
24-Pin Quad Cerpak
DS100315-3
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2
Logic Diagram
Truth Table
Function
Inputs
Outputs
D
7
D
0
S
1
S
0
CP
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
Load Register
X
X
L
L
N
P
7
P
6
P
5
P
4
P
3
P
2
P
1
P
0
Shift Left
X
L
L
H
N
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
L
Shift Left
X
H
L
H
N
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Q
0
H
Shift Right
L
X
H
L
N
L
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Shift Right
H
X
H
L
N
H
Q
7
Q
6
Q
5
Q
4
Q
3
Q
2
Q
1
Hold
X
X
H
H
X
Hold
X
X
X
X
H
No Change
Hold
X
X
X
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
N
= LOW-to-HIGH Transition
DS100315-5
3
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Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
V
EE
Pin Potential to Ground Pin
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output Current (DC Output HIGH)
-50 mA
ESD (Note 2)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to +125C
(Notes 3, 4,
5)
-1085
-870
mV
-55C
V
IN
= V
IH
(Max)
Loading with
V
OL
Output LOW Voltage
-1830 -1620
mV
0C to +125C
or V
IL
(Min)
50
to -2.0V
-1830 -1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to +125C
(Notes 3, 4,
5)
-1085
mV
-55C
V
IN
= V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-1610
mV
0C to +125C
or V
IL
(Max)
50
to -2.0V
-1555
mV
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to +125C
Guaranteed HIGH Signal
(Notes 3, 4,
5, 6)
for All Inputs
V
IL
Input LOW Current
-1830 -1475
mV
-55C to +125C
Guaranteed LOW Signal
(Notes 3, 4,
5, 6)
for All Inputs
I
IL
Input LOW Current
0.50
A
-55C to +125C
V
EE
= -4.2V
(Notes 3, 4,
5, 6)
V
IN
= V
IL
(Min)
I
IH
Input High Current
240
A
0C to +125C
V
EE
= -5.7V
(Notes 3, 4,
5)
340
A
-55C
V
IN
= V
IH
(Max)
I
EE
Power Supply Current
Inputs Open
(Notes 3, 4,
5)
-168
-55
mA
-55C to +125C
V
EE
= -4.2V to -4.8V
-178
-55
mA
V
EE
= -4.2V to -5.7V
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specifications which can be considered a
worst case condition at cold temperatures.
Note 4: Screen tested 100% on each device at -55C, +25C and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
f
max
Max Clock Frequency
400
400
300
MHz
Figures 2, 3
4
t
PLH
Propagation Delay
0.50
2.50
0.50
2.30
0.50
2.80
ns
(Notes 7, 8,
9, 11)
t
PHL
CP to Output
Figures 1, 3
t
TLH
Transition Time
0.30
1.30
0.30
1.30
0.30
1.30
ns
t
THL
20% to 80%, 80% to 20%
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4
AC Electrical Characteristics
(Continued)
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
t
s
Setup Time
D
n
, P
n
0.60
0.60
0.60
ns
S
n
1.70
1.60
2.40
Figure 4
(Note 10)
t
h
Hold Time
D
n
, P
n
0.90
0.90
0.90
ns
S
n
0.50
0.50
0.50
t
pw
(H)
Pulse Width HIGH
2.00
2.00
2.00
ns
Figure 3
CP
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
after power-up. This provides "cold start" specifications which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each manufactured lot at +25C, Subgroup A9, and at +125C and -55C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25C, +125C and -55C temperature (design characterization data).
Note 11: The propagation delay specified is for the switching of a single output. Delays may vary up to 0.40 ns if multiple outputs are switching simultaneously.
Test Circuitry
DS100315-6
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1, L2 and L3 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Fixture and stray capacitance
3 pF
Pin numbers shown are for Flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
5
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