100351
Low Power Hex D Flip-Flop
General Description
The 100351 contains six D-type edge-triggered, master/
slave flip-flops with true and complement outputs, a pair of
common Clock inputs (CP
a
and CP
b
) and common Master
Reset (MR) input. Data enters a master when both CP
a
and
CP
b
are LOW and transfers to the slave when CP
a
and CP
b
(or both) go HIGH. The MR input overrides all other inputs
and makes the Q outputs LOW. All inputs have 50 k
pull-down resistors.
Features
n
40% power reduction of the 100151
n
2000V ESD protection
n
Pin/function compatible with 100151
n
Voltage compensated operating range:
-4.2V to -5.7V
n
Standard Microcircuit Drawing
(SMD) 5962-9457901
Logic Symbol
Pin Names
Description
D
0
D
5
Data Inputs
CP
a
, CP
b
Common Clock Inputs
MR
Asynchronous Master Reset Input
Q
0
Q
5
Data Outputs
Q
0
Q
5
Complementary Data Outputs
DS100318-11
August 1998
100351
Low
Power
Hex
D
Flip-Flop
1998 National Semiconductor Corporation
DS100318
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Connection Diagrams
Logic Diagram
Truth Tables
(Each Flip-flop)
Synchronous Operation
Inputs
Outputs
D
n
CP
a
CP
b
MR
Q
n
(t+1)
L
N
L
L
L
H
N
L
L
H
L
L
N
L
L
H
L
N
L
H
X
H
N
L
Q
n
(t)
X
N
H
L
Q
n
(t)
X
L
L
L
Q
n
(t)
Asynchronous Operation
Inputs
Outputs
D
n
CP
a
CP
b
MR
Q
n
(t+1)
X
X
X
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
t = Time before CP positive transition
t+1 = Time after CP positive transition
N
= LOW-to-HIGH transition
24-Pin DIP
DS100318-1
24-Pin Quad Cerpak
DS100318-2
DS100318-4
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Above which the useful life may be impaired
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
V
EE
Pin Potential to Ground Pin
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output Current (DC Output HIGH)
-50 mA
ESD (Note 2)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to
V
IN
= V
IH
(Max)
or V
IL
(Min)
Loading with
50
to -2.0V
(Notes 3, 4, 5)
+125C
-1085
-870
mV
-55C
V
OL
Output LOW Voltage
-1830
-1620
mV
0C to
+125C
-1830
-1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to
V
IN
= V
IH
(Min)
or V
IL
(Max)
Loading with
50
to -2.0V
(Notes 3, 4, 5)
+125C
-1085
mV
-55C
V
OLC
Output LOW Voltage
-1610
mV
0C to
+125C
-1555
mV
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to
Guaranteed HIGH Signal
(Notes 3, 4, 5, 6)
+125C
for All Inputs
V
IL
Input LOW Voltage
-1830
-1475
mV
-55C to
Guaranteed LOW Signal
(Notes 3, 4, 5, 6)
+125C
for All Inputs
I
IL
Input LOW Current
0.50
A
-55C to
V
EE
= -4.2V
(Notes 3, 4, 5)
+125C
V
IN
= V
IL
(Min)
I
IH
Input HIGH Current
V
EE
= -5.7V
V
IN
= V
IH
(Max)
(Notes 3, 4, 5)
CP, MR
350
A
0C to
D
0
D
5
240
+125C
CP, MR
500
A
-55C
D
0
D
5
340
I
EE
Power Supply Current
-135
-50
mA
-55C to
Inputs Open
(Notes 3, 4, 5)
+125C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups A1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
3
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AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
f
max
Toggle Frequency
375
375
375
MHz
Figures 2, 3
(Note 10)
t
PLH
Propagation Delay
0.40
2.40
0.50
2.20
0.50
2.60
ns
Figures 1, 3
t
PHL
CP
a
, CP
b
to Output
(Notes 7, 8, 9)
t
PLH
Propagation Delay
0.60
2.70
0.70
2.60
0.80
2.90
ns
Figures 1, 4
t
PHL
MR to Output
t
TLH
Transition Time
0.20
1.60
0.20
1.60
0.20
1.60
ns
Figures 1, 3
(Note 10)
t
THL
20% to 80%, 80% to 20%
t
s
Setup Time
D
0
D
5
0.90
0.80
0.90
ns
Figure 5
MR (Release Time)
1.60
1.80
2.60
Figure 4
t
h
Hold Time
1.50
1.40
1.60
ns
Figure 5
D
0
D
5
t
pw
(H)
Pulse Width HIGH
2.00
2.00
2.00
ns
Figures 3, 4
CP
a
, CP
b
, MR
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissipation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25C, Temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each Mfg. lot at +25C, Subgroup A9, and at +125C, and -55C Temperature, Subgroups A10 and A11.
Note 10: Not tested at +25C, +125C and -55C Temperature (design characterization data).
Test Circuitry
DS100318-5
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1 and L2 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Fixture and stray capacitance
3 pF
FIGURE 1. AC Test Circuit
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4
Test Circuitry
(Continued)
Switching Waveforms
DS100318-6
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1 and L2 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Jig and stray capacitance
3 pF
FIGURE 2. Toggle Frequency Test Circuit
DS100318-7
FIGURE 3. Propagation Delay (Clock) and Transition Times
5
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