100371
Low Power Triple 4-Input Multiplexer with Enable
General Description
The 100371 contains three 4-input multiplexers which share
a common decoder (inputs S
0
and S
1
). Output buffer gates
provide true and complement outputs. A HIGH on the Enable
input (E) forces all true outputs LOW (see Truth Table). All in-
puts have 50 k
pull-down resistors.
Features
n
35% power reduction of the 100171
n
2000V ESD protection
n
Pin/function compatible with 100171
n
Voltage compensated operating range = -4.2V to -5.7V
n
Available to MIL-STD-883
Logic Symbol
Pin Names
Description
I
0x
I
3x
Data Inputs
S
0
, S
1
Select Inputs
E
Enable Input (Active LOW)
Z
a
Z
c
Data Outputs
Z
a
Z
c
Complementary Data Outputs
DS100975-1
September 1998
100371
Low
Power
T
riple
4-Input
Multiplexer
with
Enable
1998 National Semiconductor Corporation
DS100975
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Connection Diagrams
Logic Diagram
24-Pin DIP
DS100975-2
24-Pin Quad Cerpak
DS100975-3
DS100975-5
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2
Truth Table
Inputs
Outputs
E
S
0
S
1
Z
n
L
L
L
I
0x
L
H
L
I
1x
L
L
H
I
2x
L
H
H
I
3x
H
X
X
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
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3
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature (T
STG
)
-65C to +150C
Maximum Junction Temperature (T
J
)
Ceramic
+175C
V
EE
Pin Potential to Ground Pin
-7.0V to +0.5V
Input Voltage (DC)
V
EE
to +0.5V
Output current (DC Output HIGH)
-50 mA
ESD (Note 2)
2000V
Recommended Operating
Conditions
Case Temperature (T
C
)
Military
-55C to +125C
Supply Voltage (V
EE
)
-5.7V to -4.2V
Note 1: Absolute maximum ratings are those values beyond which the de-
vice may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Note 2: ESD testing conforms to MIL-STD-883, Method 3015.
Military Version
DC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND, T
C
= -55C to +125C
Symbol
Parameter
Min
Max
Units
T
C
Conditions
Notes
V
OH
Output HIGH Voltage
-1025
-870
mV
0C to
(Notes 3, 4,
5)
+125C
-1085
-870
mV
-55C
V
IN
= V (Max)
Loading with
V
OL
Output LOW Voltage
-1830
-1620
mV
0C to
or V
IL (Min)
50
to -2.0V
+125C
-1830
-1555
mV
-55C
V
OHC
Output HIGH Voltage
-1035
mV
0C to
(Notes 3, 4,
5)
+125C
-1085
mV
-55C
V
IN
= V
IH
(Min)
Loading with
V
OLC
Output LOW Voltage
-1610
mV
0C to
or V
IL
(Max)
50
to -2.0V
+125C
-1555
mV
-55C
V
IH
Input HIGH Voltage
-1165
-870
mV
-55C to
Guaranteed HIGH Signal
(Notes 3, 4,
5, 6)
+125C
for All Inputs
V
IL
Input LOW Voltage
-1830
-1475
mV
-55C to
Guaranteed LOW Signal
(Notes 3, 4,
5, 6)
+125C
for All Inputs
I
IL
Input LOW Current
0.50
A
-55C to
V
EE
= -4.2V
(Notes 3, 4,
5)
+125C
V
IN
= V
IL
(Min)
I
IH
Input HIGH Current
(Notes 3, 4,
5)
I
0X
I
3X
340
A
0C to
S
0
, S
1
, E
300
+125C
V
EE
= -5.7V
I
0X
I
3X
490
A
-55C
V
IN
= V
IH
(Max)
S
0
, S
1
, E
450
I
EE
Power Supply Current
-80
-30
mA
-55C to
Inputs Open
(Notes 3, 4,
5)
+125C
Note 3: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
without allowing for the junction temperature to stabilize due to heat dissapation after power-up. This provides "cold start" specs which can be considered a worst case
condition at cold temperatures.
Note 4: Screen tested 100% on each device at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 5: Sample tested (Method 5005, Table I) on each manufactured lot at -55C, +25C, and +125C, Subgroups 1, 2, 3, 7, and 8.
Note 6: Guaranteed by applying specified input condition and testing V
OH
/V
OL
.
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Military Version
AC Electrical Characteristics
V
EE
= -4.2V to -5.7V, V
CC
= V
CCA
= GND
Symbol
Parameter
T
C
= -55C
T
C
= +25C
T
C
= +125C
Units
Conditions
Notes
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
0.10
1.90
0.20
1.70
0.20
2.00
ns
(Notes 7,
8, 9, 11)
t
PHL
I
0x
I
3x
to Output
t
PLH
Propagation Delay
0.40
2.70
0.60
2.40
0.50
2.90
ns
t
PHL
S
0
, S
1
to Output
Figures 1, 2
t
PLH
Propagation Delay
0.50
2.70
0.60
2.40
0.50
2.90
ns
t
PHL
E to Output
t
TLH
Transition Time
0.20
1.60
0.30
1.50
0.20
1.60
ns
(Note 10)
t
THL
20% to 80%, 80% to 20%
Note 7: F100K 300 Series cold temperature testing is performed by temperature soaking (to guarantee junction temperature equals -55C), then testing immediately
after power-up. This provides "cold start" specs which can be considered a worst case condition at cold temperatures.
Note 8: Screen tested 100% on each device at +25C temperature only, Subgroup A9.
Note 9: Sample tested (Method 5005, Table I) on each mfg. lot at +25C, Subgroup A9, and at +125C and -55C temperatures, Subgroups A10 and A11.
Note 10: Not tested at +25C, +125C and -55C temperature (design characterization data).
Note 11: The propagation delay specified is for single output switching. Delays may vary up to 300 ps with multiple outputs switching.
Test Circuitry
DS100975-6
Notes:
V
CC
, V
CCA
= +2V, V
EE
= -2.5V
L1 and L2 = equal length 50
impedance lines
R
T
= 50
terminator internal to scope
Decoupling 0.1 F from GND to V
CC
and V
EE
All unused outputs are loaded with 50
to GND
C
L
= Fixture and stray capacitance
3 pF
Pin numbers shown are for flatpak; for DIP see logic symbol
FIGURE 1. AC Test Circuit
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