TL F 9892
11C9011C91
650
MHz
Prescalers
Not Intended For New Designs
August 1992
11C90 11C91
650 MHz Prescalers
General Description
The 11C90 and 11C91 are high-speed prescalers designed
specifically for communication and instrumentation applica-
tions All discussions and examples in this data sheet are
applicable to the 11C91 as well as the 11C90
The 11C90 will divide by 10 or 11 and the 11C91 by 5 or 6
both over a frequency range from DC to typically 650 MHz
The division ratio is controlled by the Mode Control The
divide-by-10 or -11 capability allows the use of pulse swal-
lowing techniques to control high-speed counting modulos
by lower-speed circuits The 11C90 may be used with either
ECL or TTL power supplies
In addition to the ECL outputs Q and Q the 11C90 contains
an ECL-to-TTL converter and a TTL output The TTL output
operates from the same V
CC
and V
EE
levels as the counter
but a separate pin is used for the TTL circuit V
EE
This mini-
mizes noise coupling when the TTL output switches and
also allows power consumption to be reduced by leaving
the separate V
EE
pin open if the TTL output is not used
To facilitate capacitive coupling of the clock signal a 400X
resistor (V
REF
) is connected internally to the V
BB
reference
Connecting this resistor to the Clock Pulse input (CP) auto-
matically centers the input about the switching threshold
Maximum frequency operation is achieved with a 50% duty
cycle
Each of the Mode Control inputs is connected to an internal
2 kX resistor with the other end uncommitted (RM
1
and
RM
2
) An M input can be driven from a TTL circuit operating
from the same V
CC
by connecting the free end of the asso-
ciated 2 kX resistor to V
CCA
When an M input is driven
from the ECL circuit the 2 kX resistor can be left open or if
required can be connected to V
EE
to act as a pull-down
resistor
Logic Symbol
TL F 9892 2
Pin Names
Description
CE
Count Enable Input (Active LOW)
CP
Clock Pulse Input
M
n
Count Modulus Control Input
MS
Asynchronous Master Set Input
Q Q
ECL Outputs
QTTL
TTL Output
RM
n
2 kX Resistor to M
n
V
REF
400X Resistor to V
BB
Connection Diagram
16-Pin DIP
TL F 9892 1
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Absolute Maximum Ratings
Above which the useful life may be impaired
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Maximum Junction Temperature (T
J
)
a
150 C
Supply Voltage Range
b
7 0V to GND
Input Voltage (DC)
V
EE
to GND
Output Current (DC Output HIGH)
b
50 mA
Operating Range
b
5 7V to
b
4 7V
Lead Temperature
(Soldering 10 sec )
300 C
Recommended Operating
Conditions
Min
Typ
Max
Ambient Temperature (T
A
)
Commercial
0 C
a
75 C
Military
b
55 C
a
125 C
Supply Voltage (V
EE
)
Commercial
b
5 7V
b
5 2V
b
4 7V
Military
b
5 7V
b
5 2V
b
4 7V
TTL Input Output Operation
DC Electrical Characteristics
Over Operating Temperature and Voltage Range unless otherwise noted Pins 12 and 13
e
GND
Symbol
Parameter
Min
Typ
Max
Units
Conditions
(Note 3)
V
IH
Input HIGH Voltage
4 1
V
Guaranteed Input HIGH Threshold
M
1
and M
2
Inputs
Voltage (Note 4) V
CC
e
V
CCA
e
5 0V
V
IL
Input LOW Voltage
3 3
V
Guaranteed Input LOW Threshold
M
1
and M
2
Inputs
Voltage (Note 4) V
CC
e
V
CCA
e
5 0V
V
OH
Output HIGH Voltage
2 3
3 3
V
V
CC
e
V
CCA
e
Min
QTTL Output
I
OH
e b
640 mA
V
OL
Output LOW Voltage
0 2
0 5
V
V
CC
e
V
CCA
e
Min
QTTL Output
I
OL
e
20 0 mA
I
IL
Input LOW Current
b
2 3
b
5 0
mA
V
CC
e
V
CCA
e
Max
M
1
and M
2
Inputs
V
IN
e
0 4V Pins 6 7
e
V
CC
I
SC
Output Short Circuit
b
20
b
35
b
80
mA
V
CC
e
V
CCA
e
Max
Current
V
OUT
e
0 0V Pin 14
e
V
CC
AC Electrical Characteristics
V
CC
e
V
CCA
e
5 0V Nominal V
EE
e
GND T
A
e a
25 C
Symbol
Parameter
Min
Typ
Max
Units
Conditions
t
PLH
Propagation Delay (50% to 50%)
6
10
14
ns
See
Figure 1
t
PHL
CP to QTTL
t
PLH
Propagation Delay (50% to 50%)
12
17
ns
MS to QTTL
t
s
Mode Control Setup Time
4
2
ns
t
h
Mode Control Hold Time
0
b
2
ns
t
TLH
Output Rise Time
10
ns
(20% to 80%)
t
THL
Output Fall Time
2
ns
(80% to 20%)
f
MAX
Count Frequency
550
650
MHz
b
55 C to
a
125 C
600
650
0 C to
a
75 C
Clock Input AC Coupled
350 mV Peak-to-Peak
Sinewave (Note 5)
2
ECL Operation
Commercial Version
DC Electrical Characteristics
V
CC
e
V
CCA
e
GND V
EE
e b
5 2V
Symbol
Parameter
Min
Typ
Max
Units
T
A
Conditions
V
OH
Output HIGH Voltage
b
1060
b
995
b
905
0 C
Load
e
50X to
b
2V
Q and Q
b
1025
b
960
b
880
mV
a
25 C
b
980
b
910
b
805
a
75 C
V
OL
Output LOW Voltage
b
1820
b
1705
b
1620
mV
0 C to
Q and Q
a
75 C
V
IH
Input HIGH Voltage
b
1135
b
840
0 C
Guaranteed Input HIGH
b
1095
b
810
mV
a
25 C
Signal (Note 6)
b
1035
b
720
a
75 C
V
IL
Input LOW Voltage
b
1870
b
1500
0 C
Guaranteed Input LOW
b
1850
b
1485
mV
a
25 C
Signal
b
1830
b
1460
a
75 C
I
IH
Input HIGH Current
V
IN
e
V
IHA
CP Input (Note 1)
400
a
25 C
MS Input
400
m
A
a
25 C
M
1
and M
2
Input
250
a
25 C
I
IL
Input LOW Current
0 5
m
A
a
25 C
V
IN
e
V
ILB
I
EE
Power Supply Current
b
110
b
75
mA
0 C to
Pins 6 7 13 not connected
b
119
a
75 C
V
EE
Operating Supply
b
5 7
b
5 2
b
4 7
V
0 C to
Voltage Range
a
75 C
V
REF
Reference Voltage
b
1550
b
1150
mV
a
25 C
V
RM1
e
V
RM2
e b
5 2V
I
N
e b
10 0 mA
AC Electrical Characteristics
T
A
e
0 C to
a
75 C V
CC
e
V
CCA
e
GND V
EE
e b
5 2V
Symbol
Parameter
0 C
a
25 C
a
75 C
Units
Conditions
Typ
Min
Typ
Max
Typ
t
PLH
Propagation Delay
1 8
1 3
2 0
3 0
2 5
ns
Output
t
PHL
(50% to 50%) CP to Q
R
L
e
50X to
b
2 0V
t
PLH
Propagation Delay
3 7
4 0
6 0
4 5
ns
Input
(50% to 50%) MS to Q
t
ri
e
t
fi
e
2 0
g
0 1 ns
t
s
Setup Time M to CP
2 0
4 0
2 0
2 0
ns
(20% to 80%)
t
h
Hold Time M to CP
b
2 0
0 0
b
2 0
b
2 0
ns
See
Figure 1
t
TLH
Output Rise Time
1 0
1 0
2 0
1 0
ns
(20% to 80%)
t
THL
Output Fall Time
1 0
1 0
2 0
1 0
ns
(80% to 20%)
f
MAX
Maximum Clock Frequency
AC Coupled Input 350 mV
650
600
650
625
MHz
Peak-to-Peak f
MAX
is
Guaranteed to be 575 MHz
Min at 0 C to
a
75 C
3
ECL Operation
Military Version
DC Electrical Characteristics
V
CC
e
V
CCA
e
GND V
EE
e b
5 2V
Symbol
Parameter
Min
Typ
Max
Units
T
A
Conditions
V
OH
Output HIGH Voltage
b
1100
b
1030
b
900
b
55 C
Load
e
100X to
b
2V
Q and Q
b
980
b
910
b
820
mV
a
25 C
b
910
b
820
b
670
a
125 C
V
OL
Output LOW Voltage
b
1820
b
1705
b
1620
mV
b
55 C to
Q and Q
a
125 C
V
IH
Input HIGH Voltage
b
1190
b
905
b
55 C
Guaranteed Input HIGH
b
1095
b
810
mV
a
25 C
Signal (Note 6)
b
975
b
690
a
125 C
V
IL
Input LOW Voltage
b
1890
b
1525
b
55 C
Guaranteed Input LOW
b
1850
b
1485
mV
a
25 C
Signal
b
1800
b
1435
a
125 C
I
IH
Input HIGH Current
V
IN
e
V
IHA
CP Input (Note 1)
400
a
25 C
MS Input
400
m
A
a
25 C
M
1
and M
2
Input
250
a
25 C
I
IL
Input LOW Current
0 5
m
A
a
25 C
V
IN
e
V
ILB
I
EE
Power Supply Current
b
110
b
75
mA
a
25 C
Pins 6 7 13 not connected
b
119
mA
b
55 C to
a
125 C
V
EE
Operating Supply
b
5 7
b
5 2
b
4 7
V
b
55 C to
Voltage Range
a
125 C
V
REF
Reference Voltage
b
1550
b
1150
mV
a
25 C
V
RM1
e
V
RM2
e b
5 2V
I
N
e b
10 0 mA
AC Electrical Characteristics
T
A
e b
55 C to
a
125 C V
CC
e
V
CCA
e
GND V
EE
e b
5 2V
Symbol
Parameter
b
55 C
a
25 C
a
125 C
Units
Conditions
Typ
Min
Typ
Max
Typ
t
PLH
Propagation Delay
1 5
1 3
2 0
3 0
3 0
ns
Output
t
PHL
(50% to 50%) CP to Q
R
L
e
50X to
b
2 0V
t
PLH
Propagation Delay
3 5
4 0
6 0
5 0
ns
(50% to 50%) MS to Q
Input
t
s
Setup Time M to CP
2 0
4 0
2 0
2 0
ns
t
ri
e
t
fi
e
2 0
g
0 1 ns
t
h
Hold Time M to CP
b
2 0
0 0
b
2 0
b
2 0
ns
(20% to 80%)
t
TLH
Output Rise Time
1 0
1 0
2 0
1 0
ns
See
Figure 1
(20% to 80%)
t
THL
Output Fall Time
1 0
1 0
2 0
1 0
ns
(80% to 20%)
f
MAX
Maximum Clock Frequency
AC Coupled Input 350 mV
700
600
650
600
MHz
Peak-to-Peak f
MAX
is
Guaranteed to be 550 MHz
Min at
b
55 C to
a
125 C
Note 1
Conditions for testing not shown in the Table are chosen to guarantee operation under ``worst case'' conditions
Note 2
The specified limits represent the ``worst case'' value for the parameter Since these ``worst case'' values normally occur at the temperature and supply
voltage extremes additional noise immunity and guard banding can be achieved by decreasing the allowable system operating ranges
Note 3
Typical limits are at V
CC
e
5 0V and T
A
e a
25 C
Note 4
The M
1
and M
2
threshold specifications are normally referenced to the V
CC
potential as shown in the ECL operation tables Using V
EE
(GND) as the
reference as in normal TTL practice effectively makes the threshold vary directly with V
CC
Threshold is typically 1 3V below V
CC
(e g
a
3 7V at V
CC
e a
5V) A
signal swing about threshold of
g
0 4V is adequate which gives the state V
IH
and V
IL
values The internal 2 kX resistors are intended to pull TTL outputs up to the
required V
IH
range as discussed in the Functional Description and shown in
Figure 5
Note 5
TTL Output Signal swing is guaranteed at f
MAX
over temperature range
Note 6
M
1
or M
2
can be tied to V
CC
for fixed divide-by-ten operation
4
TL F 9892 3
TL F 9892 4
Conditions
V
CC
e a
2 0V
V
EE
e b
3 2V
R
T
e
50X (scope input impedance)
C
L
e
Jig and stray capacitance
k
5 0 pF
I
1
e
L
2
e
equal 50X impedance lines
C
e
0 1 pF
Note 7
Use high impedance to test QTTL
Connect pin 13 to V
EE
Note 8
For High frequency test use AC coupled input as in
Figure 3
Adjust input amplitude to 350 mV peak-to-peak
FIGURE 1 AC Test Circuit
5
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