54ABT16500
18-Bit Universal Bus Transceivers with TRI-STATE
Outputs
General Description
These 18-bit universal bus transceivers combine D-type
latches and D-type flip-flops to allow data flow in transparent,
latched, and clocked modes.
Data flow in each direction is controlled by output-enable
(OEAB and OEBA), latch-enable (LEAB and LEBA), and
clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the
device operates in the transparent mode when LEAB is high.
When LEAB is low, the A data is latched if CLKAB is held at
a high or low logic level. If LEAB is low, the A bus data is
stored in the latch/flip-flop on the high-to-low transition of
CLKAB. Output-enable OEAB is active-high. When OEAB is
high, the outputs are active. When OEAB is low, the outputs
are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA,
LEBA, and CLKBA. The output enables are complementary
(OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or
power down, OE should be tied to GND through a pulldown
resistor; the minimum value of the resistor is determined by
the current-sourcing capability of the driver.
Features
n
Combines D-Type latches and D-Type flip-flops for
operation in transparent, latched, or clocked mode
n
Flow-through architecture optimizes PCB layout
n
Guaranteed latch-up protection
n
High impedance glitch free bus loading during entire
power up and power down cycle
n
Non-destructive hot insertion capability
n
Standard Microcircuit Drawing (SMD) 5962-9687001
Ordering Code
Military
Package
Package Description
Number
54ABT16500W-QML
WA56A
56-Lead Cerpack
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
July 1998
54ABT16500
18-Bit
Universal
Bus
T
ransceivers
with
TRI-ST
A
T
E
Outputs
54ABT16500
1998 National Semiconductor Corporation
DS100225
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1
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1
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Proof
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Connection Diagram
Function Table
(Note 1)
Inputs
Output
B
OEAB
LEAB
CLKAB
A
L
X
X
X
Z
H
H
X
L
L
H
H
X
H
H
H
L
L
L
H
L
H
H
H
L
H
X
B
0
(Note 2)
H
L
L
X
B
0
(Note 3)
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA.
Note 2: Output level before the indicated steady-state input conditions were established.
Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was low before LEAB went low.
Pin Assignment for Cerpack
DS100225-1
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1
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Logic Diagram
DS100225-2
3
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Absolute Maximum Ratings
(Note 4)
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 4)
-0.5V to +7.0V
Input Current (Note 4)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-off State
-0.5V to 5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
-500 mA
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 4: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT16500
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54ABT
2.5
V
Min
I
OH
= -3 mA
54ABT
2.0
V
Min
I
OH
= -24 mA
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Note 6)
5
V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
= 7.0V
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Note 6)
-5
V
IN
= 0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A
All Other Pins Grounded
I
IH
+
Output Leakage Current
50
A
0 - 5.5V
V
OUT
= 2.7V; OE, OE = 2.0V
I
OZH
I
IL
+
Output Leakage Current
-50
A
0 - 5.5V
V
OUT
= 0.5V; OE, OE = 2.0V
I
OZL
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
= V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current
1.0
mA
Max
All Outputs HIGH
I
CCL
Power Supply Current
68
A
Max
An or Bn Outputs Low
I
CCZ
Power Supply Current
1.0
mA
Max
OE
n
= V
CC
,
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
2.5
mA
Max
V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open
(Note 6)
0.23
MHz
Transparent Mode
One Bit Toggling, 50% Duty Cycle
Note 6: Guaranteed, but not tested.
PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1
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DC Electrical Characteristics
Symbol
Parameter
Min
Max
Units
V
CC
Conditions
C
L
= 50 pF; R
L
=
500
V
OLP
Quiet Output Maximum Dynamic V
OL
1.1
V
5.0
T
A
= 25C (Note 7)
V
OLV
Quiet Output Minimum Dynamic V
OL
-1.7
V
5.0
T
A
= 25C (Note 7)
Note 7: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V5.5V
C
L
= 50 pF
Min
Max
f
max
Maximum Clock Frequency
150
MHz
t
PLH
Propagation Delay
1.0
6.5
ns
Figure 4
t
PHL
A or B to B or A
1.0
7.0
t
PLH
Propagation Delay
1.0
7.0
ns
Figure 4
t
PHL
LEAB or LEBA to B or A
1.0
7.8
t
PLH
Propagation Delay
1.0
7.5
ns
Figure 4
t
PHL
CLKAB or CLKBA to B or A
1.0
8.0
t
PZH
Propagation Delay
1.0
6.3
ns
Figure 6
t
PZL
OEAB or OEBA to B or A
1.0
6.5
t
PHZ
Propagation Delay
1.0
7.2
ns
Figure 6
t
PLZ
OEAB or OEBA to B or A
1.0
6.8
AC Operating Requirements
Symbol
Parameter
54ABT
Units
Fig.
No.
T
A
= -55C to +125C
V
CC
= 4.5V5.5V
C
L
= 50 pF
Min
Max
t
s
(H)
Setup Time,
4.5
ns
Figure 7
t
s
(L)
A to CLKAB
4.5
t
h
(H)
Hold Time,
0
ns
Figure 7
t
h
(L)
A to CLKAB
0
t
s
(H)
Setup Time,
4.0
ns
Figure 7
t
s
(L)
B to CLKBA
4.0
t
h
(H)
Hold Time,
0
ns
Figure 7
t
h
(L)
B to CLKBA
0
t
s
(H)
Setup Time, A to LEAB
1.5
ns
Figure 7
t
s
(L)
or B to LEBA, CLK High
1.5
t
h
(H)
Hold Time, A to LEAB
1.5
ns
Figure 7
t
h
(L)
or B to LEBA, CLK High
1.5
t
s
(H)
Setup Time, A to LEAB
4.5
ns
Figure 7
t
s
(L)
or B to LEBA, CLK Low
4.5
t
h
(H)
Hold Time, A to LEAB
1.5
ns
Figure 7
t
h
(L)
or B to LEBA, CLK Low
1.5
t
w
(H)
Pulse Width,
3.3
ns
Figure 5
t
w
(L)
LEAB or LEBA, High
3.3
5
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PrintDate=1998/07/14 PrintTime=11:08:55 43605 ds100225 Rev. No. 1
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Proof
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