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Электронный компонент: 54ABT373CPCQB

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TL F 11547
54ABT74ABT373
Octal
Transparent
Latch
with
TRI-STATE
Outputs
September 1995
54ABT 74ABT373
Octal Transparent Latch with TRI-STATE
Outputs
General Description
The 'ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications The flip-flops
appear transparent to the data when Latch Enable (LE) is
HIGH When LE is LOW the data that meets the setup
times is latched Data appears on the bus when the Output
Enable (OE) is LOW When OE is HIGH the bus output is in
the high impedance state
Features
Y
TRI-STATE outputs for bus interfacing
Y
Output sink capability of 64 mA source capability of
32 mA
Y
Guaranteed output skew
Y
Guaranteed multiple output switching specifications
Y
Output switching specified for both 50 pF and 250 pF
loads
Y
Guaranteed simultaneous switching noise level and
dynamic threshold performance
Y
Guaranteed latchup protection
Y
High impedance glitch free bus loading during entire
power up and power down
Y
Nondestructive hot insertion capability
Y
Standard Military Drawing (SMD) 5962-9321801
Commercial
Military
Package
Package Description
Number
74ABT373CSC (Note 1)
M20B
20-Lead (0 300 Wide) Molded Small Outline JEDEC
74ABT373CSJ (Note 1)
M20D
20-Lead (0 300 Wide) Molded Small Outline EIAJ
74ABT373CPC
N20B
20-Lead (0 300 Wide) Molded Dual-In-Line
54ABT373J 883
J20A
20-Lead Ceramic Dual-In-Line
74ABT373CMSA (Note 1)
MSA20
20-Lead Molded Shrink Small Outline EIAJ Type II
54ABT373W 883
W20A
20-Lead Cerpack
54ABT373E 883
E20A
20-Lead Ceramic Leadless Chip Carrier Type C
74ABT373CMTC (Notes 1 2)
MTC20
20-Lead Molded Thin Shrink Small Outline JEDEC
Note 1
Devices also available in 13
reel Use suffix
e
SCX SJX MSAX and MTCX
Note 2
Contact factory for package availability
Connection Diagrams
Pin Assignment
for DIP SOIC SSOP and Flatpak
TL F 11547 1
Pin Assignment
for LCC
TL F 11547 2
Pin Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
(Active HIGH)
OE
Output Enable Input
(Active LOW)
O
0
O
7
TRI-STATE Latch
Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation
RRD-B30M115 Printed in U S A
Functional Description
The
'ABT373
contains
eight
D-type
latches
with
TRI-STATE output buffers When the Latch Enable (LE) in-
put is HIGH data on the D
n
inputs enters the latches In this
condition the latches are transparent i e a latch output will
change state each time its D input changes When LE is
LOW the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE The TRI-STATE buffers are controlled by the
Output Enable (OE) input When OE is LOW the buffers are
in the bi-state mode When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches
Truth Table
Inputs
Output
LE
OE
D
n
O
n
H
L
H
H
H
L
L
L
L
L
X
O
n
(no change)
X
H
X
Z
H
e
HIGH Voltage Level
L
e
LOW Voltage Level
X
e
Immaterial
Z
e
High Impedance State
Logic Diagram
TL F 11547 3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2
Absolute Maximum Ratings
(Note 1)
If Military Aerospace specified devices are required
please contact the National Semiconductor Sales
Office Distributors for availability and specifications
Storage Temperature
b
65 C to
a
150 C
Ambient Temperature under Bias
b
55 C to
a
125 C
Junction Temperature under Bias
Ceramic
b
55 C to
a
175 C
Plastic
b
55 C to
a
150 C
V
CC
Pin Potential to
Ground Pin
b
0 5V to
a
7 0V
Input Voltage (Note 2)
b
0 5V to
a
7 0V
Input Current (Note 2)
b
30 mA to
a
5 0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
b
0 5V to
a
5 5V
in the HIGH State
b
0 5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
DC Latchup Source Current
OE Pin
b
150 mA
(Across Comm Operating Range) Other Pins
b
500 mA
Over Voltage Latchup (I O)
10V
Note 1
Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired Functional operation under
these conditions is not implied
Note 2
Either voltage limit or current limit is sufficient to protect inputs
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
b
55 C to
a
125 C
Commercial
b
40 C to
a
85 C
Supply Voltage
Military
a
4 5V to
a
5 5V
Commercial
a
4 5V to
a
5 5V
Minimum Input Edge Rate
(DV Dt)
Data Input
50 mV ns
Enable Input
20 mV ns
DC Electrical Characteristics
Symbol
Parameter
ABT373
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2 0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0 8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
b
1 2
V
Min
I
IN
e b
18 mA
V
OH
Output HIGH Voltage
54ABT 74ABT
2 5
I
OH
e b
3 mA
54ABT
2 0
V
Min
I
OH
e b
24 mA
74ABT
2 0
I
OH
e b
32 mA
V
OL
Output LOW Voltage
54ABT
0 55
V
Min
I
OL
e
48 mA
74ABT
0 55
I
OL
e
64 mA
I
IH
Input HIGH Current
5
m
A
Max
V
IN
e
2 7V (Note 2)
5
V
IN
e
V
CC
I
BVI
Input HIGH Current Breakdown Test
7
m
A
Max
V
IN
e
7 0V
I
IL
Input LOW Current
b
5
m
A
Max
V
IN
e
0 5V (Note 2)
b
5
V
IN
e
0 0V
V
ID
Input Leakage Test
4 75
V
0 0
I
ID
e
1 9 mA
All Other Pins Grounded
I
OZH
Output Leakage Current
50
m
A
0
b
5 5V V
OUT
e
2 7V OE
e
2 0V
I
OZL
Output Leakage Current
b
50
m
A
0
b
5 5V V
OUT
e
0 5V OE
e
2 0V
I
OS
Output Short-Circuit Current
b
100
b
275
mA
Max
V
OUT
e
0 0V
I
CEX
Output High Leakage Current
50
m
A
Max
V
OUT
e
V
CC
I
ZZ
Bus Drainage Test
100
m
A
0 0
V
OUT
e
5 5V All Others GND
I
CCH
Power Supply Current
50
m
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
m
A
Max
OE
e
V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
Input
Outputs Enabled
2 5
mA
V
I
e
V
CC
b
2 1V
Outputs TRI-STATE
2 5
mA
Max
Enable Input V
I
e
V
CC
b
2 1V
Outputs TRI-STATE
2 5
mA
Data Input V
I
e
V
CC
b
2 1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA
Max
Outputs Open LE
e
V
CC
(Note 2)
0 12
MHz
OE
e
GND (Note 1)
One Bit Toggling 50% Duty Cycle
Note 1
For 8 bits toggling I
CCD
k
0 8 mA MHz
Note 2
Guaranteed but not tested
3
DC Electrical Characteristics
(SOIC Package) (Continued)
Symbol
Parameter
Min
Typ
Max
Units
V
CC
Conditions
C
L
e
50 pF R
L
e
500X
V
OLP
Quiet Output Maximum Dynamic V
OL
0 4
0 8
V
5 0
T
A
e
25 C (Note 1)
V
OLV
Quiet Output Minimum Dynamic V
OL
b
1 2
b
0 8
V
5 0
T
A
e
25 C (Note 1)
V
OHV
Minimum High Level Dynamic Output Voltage
2 5
3 0
V
5 0
T
A
e
25 C (Note 3)
V
IHD
Minimum High Level Dynamic Input Voltage
2 0
1 7
V
5 0
T
A
e
25 C (Note 2)
V
ILD
Maximum Low Level Dynamic Input Voltage
0 9
0 6
V
5 0
T
A
e
25 C (Note 2)
Note 1
Max number of outputs defined as (n) n
b
1 data inputs are driven 0V to 3V One output at Low Guaranteed but not tested
Note 2
Max number of data inputs (n) switching n
b
1 inputs switching 0V to 3V Input-under-test switching 3V to theshold (V
ILD
) 0V to threshold (V
IHD
)
Guaranteed but not tested
Note 3
Max number of outputs defined as (n) n
b
1 data inputs are driven 0V to 3V One output HIGH Guaranteed but not tested
AC Electrical Characteristics
Symbol
Parameter
74ABT
54ABT
74ABT
Units
T
A
e a
25 C
T
A
e b
55 C to
a
125 C
T
A
e b
40 C to
a
85 C
V
CC
e a
5 0V
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
C
L
e
50 pF
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1 9
2 7
4 5
1 0
6 8
1 9
4 5
ns
t
PHL
D
n
to O
n
1 9
2 8
4 5
1 0
7 0
1 9
4 5
t
PLH
Propagation Delay
2 0
3 1
5 0
1 0
7 7
2 0
5 0
ns
t
PHL
LE to O
n
2 0
3 0
5 0
1 5
7 7
2 0
5 0
t
PZH
Output Enable Time
1 5
3 1
5 3
1 0
6 7
1 5
5 3
ns
t
PZL
1 5
3 1
5 3
1 5
7 2
1 5
5 3
t
PHZ
Output Disable Time
2 0
3 6
5 4
1 7
8 0
2 0
5 4
ns
t
PLZ
2 0
3 4
5 4
1 0
7 0
2 0
5 4
AC Operating Requirements
Symbol
Parameter
74ABT
54ABT
74ABT
Units
T
A
e a
25 C
T
A
e b
55 C to
a
125 C
T
A
e b
40 C to
a
85 C
V
CC
e a
5 0V
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
C
L
e
50 pF
C
L
e
50 pF
C
L
e
50 pF
Min
Typ
Max
Min
Max
Min
Max
f
toggle
Max Toggle
100
100
MHz
Frequency
t
s
(H)
Setup Time HIGH
1 5
2 5
1 5
ns
t
s
(L)
or LOW D
n
to LE
1 5
2 5
1 5
t
h
(H)
Hold Time HIGH
1 0
2 5
1 0
ns
t
h
(L)
or LOW D
n
to LE
1 0
2 5
1 0
t
w
(H)
Pulse Width
3 0
3 3
3 0
ns
LE HIGH
4
Extended AC Electrical Characteristics
(SOIC package)
74ABT
74ABT
74ABT
T
A
e b
40 C to
a
85 C
T
A
e b
40 C to
a
85 C
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
V
CC
e
4 5V to 5 5V
Symbol
Parameter
C
L
e
50 pF
C
L
e
250 pF
C
L
e
250 pF
Units
8 Outputs Switching
(Note 5)
8 Outputs Switching
(Note 4)
(Note 6)
Min
Max
Min
Max
Min
Max
t
PLH
Propagation Delay
1 5
5 2
2 0
6 8
2 0
9 0
ns
t
PHL
D
n
to O
n
1 5
5 2
2 0
6 8
2 0
9 0
t
PLH
Propagation Delay
1 5
5 5
2 0
7 5
2 0
9 5
ns
t
PHL
LE to O
n
1 5
5 5
2 0
7 5
2 0
9 5
t
PZH
Output Enable Time
1 5
6 2
2 0
8 0
2 0
10 5
ns
t
PZL
1 5
6 2
2 0
8 0
2 0
10 5
t
PHZ
Output Disable Time
1 0
5 5
(Note 7)
(Note 7)
ns
t
PZL
1 0
5 5
Note 4
This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc )
Note 5
This specification is guaranteed but not tested The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in
the standard AC load This specificaiton pertains to single output switching only
Note 6
This specification is guaranteed but not tested The limits represent propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc ) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load
Note 7
The TRI-STATE delay times are dominated by the RC network (500X 250 pF) on the output and has been excluded from the datasheet
Skew
Symbol
Parameter
74ABT
74ABT
Units
T
A
e b
40 C to
a
85 C
T
A
e b
40 C to
a
85 C
V
CC
e
4 5V5 5V
V
CC
e
4 5V5 5V
C
L
e
50 pF
C
L
e
250 pF
8 Outputs Switching
8 Outputs Switching
(Note 3)
(Note 4)
Max
Max
t
OSHL
Pin to Pin Skew
1 0
1 5
ns
(Note 1)
HL Transitions
t
OSLH
Pin to Pin Skew
1 0
1 5
ns
(Note 1)
LH Transitions
t
PS
Duty Cycle
1 4
3 5
ns
(Note 5)
LHHL Skew
t
OST
Pin to Pin Skew
1 5
3 9
ns
(Note 1)
LH HL Transitions
t
PV
Device to Device Skew
2 0
4 0
ns
(Note 2)
LH HL Transitions
Note 1
Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device The
specification applies to any outputs switching HIGH to LOW (t
OSHL
) LOW to HIGH (t
OSLH
) or any combination switching LOW to HIGH and or HIGH to LOW
(t
OST
) This specification is guaranteed but not tested
Note 2
Propagation delay variation for a given set of conditions (i e temperature and V
CC
) from device to device This specification is guaranteed but not tested
Note 3
This specification is guaranteed but not tested The limits apply to propagation delays for all paths described switching in phase (i e all LOW-to-HIGH
HIGH-to-LOW etc )
Note 4
This specification is guaranteed but not tested The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load
Note 5
This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin It is measured across all the
outputs (drivers) on the same chip the worst (largest delta) number is the guaranteed specification This specification is guaranteed but not tested
5