54ABT373
Octal Transparent Latch with TRI-STATE
Outputs
General Description
The 'ABT373 consists of eight latches with TRI-STATE out-
puts for bus organized system applications. The flip-flops ap-
pear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup times
is latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH the bus output is in the high
impedance state.
Features
n
TRI-STATE outputs for bus interfacing
n
Output sink capability of 48 mA, source capability of
24 mA
n
Guaranteed multiple output switching specifications
n
Output switching specified for both 50 pF and 250 pF
loads
n
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n
Guaranteed latchup protection
n
High impedance glitch free bus loading during entire
power up and power down
n
Nondestructive hot insertion capability
n
Standard Microcircuit Drawing (SMD) 5962-9321801
Ordering Code
Military
Package Number
Package Description
54ABT373J-QML
J20A
20-Lead Ceramic Dual-In-Line
54ABT373W-QML
W20A
20-Lead Cerpack
54ABT373E-QML
E20A
20-Lead Ceramic Leadless Chip Carrier, Type C
Connection Diagrams
Pin Names
Description
D
0
D
7
Data Inputs
LE
Latch Enable Input
(Active HIGH)
OE
Output Enable Input
(Active LOW)
O
0
O
7
TRI-STATE Latch
Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
Pin Assignment
for DIP and Flatpak
DS100206-1
Pin Assignment
for LCC
DS100206-2
July 1998
54ABT373
Octal
T
ransparent
Latch
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100206
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Functional Description
The 'ABT373 contains eight D-type latches with TRI-STATE
output buffers. When the Latch Enable (LE) input is HIGH,
data on the D
n
inputs enters the latches. In this condition the
latches are transparent, i.e., a latch output will change state
each time its D input changes. When LE is LOW, the latches
store the information that was present on the D inputs a
setup time preceding the HIGH-to-LOW transition of LE. The
TRI-STATE buffers are controlled by the Output Enable (OE)
input. When OE is LOW, the buffers are in the bi-state mode.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data into
the latches.
Truth Table
Inputs
Output
LE
OE
D
n
O
n
H
L
H
H
H
L
L
L
L
L
X
O
n
(no change)
X
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance State
Logic Diagram
DS100206-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
-65C to +150C
Ambient Temperature under Bias
-55C to +125C
Junction Temperature under Bias
Ceramic
-55C to +175C
V
CC
Pin Potential to
Ground Pin
-0.5V to +7.0V
Input Voltage (Note 2)
-0.5V to +7.0V
Input Current (Note 2)
-30 mA to +5.0 mA
Voltage Applied to Any Output
in the Disabled or
Power-Off State
-0.5V to +5.5V
in the HIGH State
-0.5V to V
CC
Current Applied to Output
in LOW State (Max)
twice the rated I
OL
(mA)
Over Voltage Latchup (I/O)
10V
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
-55C to +125C
Supply Voltage
Military
+4.5V to +5.5V
Minimum Input Edge Rate
(
V/
t)
Data Input
50 mV/ns
Enable Input
20 mV/ns
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under these
conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
ABT373
Units
V
CC
Conditions
Min
Typ
Max
V
IH
Input HIGH Voltage
2.0
V
Recognized HIGH Signal
V
IL
Input LOW Voltage
0.8
V
Recognized LOW Signal
V
CD
Input Clamp Diode Voltage
-1.2
V
Min
I
IN
= -18 mA
V
OH
Output HIGH Voltage
54ABT
2.5
I
OH
= -3 mA
54ABT
2.0
V
Min
I
OH
= -24 mA
V
OL
Output LOW Voltage
54ABT
0.55
V
Min
I
OL
= 48 mA
I
IH
Input HIGH Current
5
A
Max
V
IN
= 2.7V (Note 4)
5
V
IN
= V
CC
I
BVI
Input HIGH Current Breakdown Test
7
A
Max
V
IN
= 7.0V
I
IL
Input LOW Current
-5
A
Max
V
IN
= 0.5V (Note 4)
-5
V
IN
= 0.0V
V
ID
Input Leakage Test
4.75
V
0.0
I
ID
= 1.9 A
All Other Pins Grounded
I
OZH
Output Leakage Current
50
A
0 - 5.5V
V
OUT
= 2.7V; OE = 2.0V
I
OZL
Output Leakage Current
-50
A
0 - 5.5V
V
OUT
= 0.5V; OE = 2.0V
I
OS
Output Short-Circuit Current
-100
-275
mA
Max
V
OUT
= 0.0V
I
CEX
Output High Leakage Current
50
A
Max
V
OUT
= V
CC
I
ZZ
Bus Drainage Test
100
A
0.0
V
OUT
= 5.5V; All Others GND
I
CCH
Power Supply Current
50
A
Max
All Outputs HIGH
I
CCL
Power Supply Current
30
mA
Max
All Outputs LOW
I
CCZ
Power Supply Current
50
A
Max
OE = V
CC
All Others at V
CC
or GND
I
CCT
Additional I
CC
/Input
Outputs Enabled
2.5
mA
V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Max
Enable Input V
I
= V
CC
- 2.1V
Outputs TRI-STATE
2.5
mA
Data Input V
I
= V
CC
- 2.1V
All Others at V
CC
or GND
I
CCD
Dynamic I
CC
No Load
mA/
Max
Outputs Open, LE = V
CC
(Note 4)
0.12
MHz
OE = GND, (Note 3)
One Bit Toggling, 50% Duty Cycle
Note 3: For 8 bits toggling, I
CCD
<
0.8 mA/MHz.
Note 4: Guaranteed, but not tested.
3
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AC Electrical Characteristics
Symbol
Parameter
54ABT
Units
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
PLH
Propagation Delay
1.0
6.8
ns
t
PHL
D
n
to O
n
1.0
7.0
t
PLH
Propagation Delay
1.0
7.7
ns
t
PHL
LE to O
n
1.5
7.7
t
PZH
Output Enable Time
1.0
6.7
ns
t
PZL
1.5
7.2
t
PHZ
Output Disable Time
1.7
8.0
ns
t
PLZ
1.0
7.0
AC Operating Requirements
Symbol
Parameter
54ABT
Units
T
A
= -55C to +125C
V
CC
= 4.5V to 5.5V
C
L
= 50 pF
Min
Max
t
s
(H)
Setup Time, HIGH
2.5
ns
t
s
(L)
or LOW D
n
to LE
2.5
t
h
(H)
Hold Time, HIGH
2.5
ns
t
h
(L)
or LOW D
n
to LE
2.5
t
w
(H)
Pulse Width,
3.3
ns
LE HIGH
Capacitance
Symbol
Parameter
Typ
Units
Conditions
(T
A
= 25C)
C
IN
Input Capacitance
5
pF
V
CC
= 0V
C
OUT
(Note 5)
Output Capacitance
9
pF
V
CC
= 5.0V
Note 5: C
OUT
is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012.
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
t
PLH
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
Data to Output
DS100206-11
t
PHL
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
Data to Output
DS100206-12
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4
Capacitance
(Continued)
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
t
PZH
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
OE to Output
DS100206-13
t
PZL
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
OE to Output
DS100206-14
t
PHZ
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
OE to Output
DS100206-15
t
PLZ
vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
OE to Output
DS100206-16
t
SET
LOW vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
Data to LE
DS100206-17
t
SET
HIGH vs Temperature (T
A
)
C
L
= 50 pF, 1 Output Switching
Data to LE
DS100206-18
5
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