54ACT534
Octal D Flip-Flop with TRI-STATE
Outputs
General Description
The 'ACT534 is a high-speed, low-power octal D-type
flip-flop featuring separate D-type inputs for each flip-flop
and TRI-STATE outputs for bus-oriented applications. A buff-
ered Clock (CP) and Output Enable (OE) are common to all
flip-flops. The 'ACT534 is the same as the 'ACT374 except
that the outputs are inverted.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Edge-triggered D-type inputs
n
Buffered positive edge-triggered clock
n
TRI-STATE outputs for bus-oriented applications
n
Outputs source/sink 24 mA
n
'ACT534 has TTL-compatible inputs
n
Inverted output version of 'ACT374
n
Standard Microcircuit Drawing (SMD) 5962-8965801
Logic Symbols
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
TRI-STATE Output Enable Input
O
0
O
7
Complementary TRI-STATE Outputs
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100292-1
IEEE/IEC
DS100292-2
July 1998
54ACT534
Octal
D
Flip-Flop
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100292
www.national.com
Connection Diagrams
Functional Description
The 'ACT534 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE complementary out-
puts. The buffered clock and buffered Output Enable are
common to all flip-flops. The eight flip-flops will store the
state of their individual D inputs that meet the setup and hold
times requirements on the LOW-to-HIGH Clock (CP) transi-
tion. With the Output Enable (OE) LOW, the contents of the
eight flip-flops are available at the outputs. When the OE is
HIGH, the outputs go to the high impedance state. Operation
of the OE input does not affect the state of the flip-flops.
Logic Diagram
Function Table
Inputs
Output
CP
OE
D
O
N
L
H
L
N
L
L
H
L
L
X
O
0
X
H
X
Z
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N
= LOW-to-HIGH Clock Transition
Z = High Impedance
O
0
= Value stored from previous clock cycle
Pin Assignment
for DIP and Flatpak
DS100292-3
Pin Assignment
for LCC
DS100292-4
DS100292-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACT
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACT
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'ACT Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Characteristics for 'ACT Family Devices
54ACT
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input Leakage
Current
5.5
1.0
A
V
I
= V
CC
, GND
I
OZ
Maximum TRI-STATE
5.5
5.0
A
V
I
= V
IL
, V
IH
Current
V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
OLD
Minimum Dynamic
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Output Current (Note 3)
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: I
CC
for 54ACT
@
25C is identical to 74ACT
@
25C.
3
www.national.com
AC Electrical Characteristics
54ACT
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 5)
C
L
= 50 pF
Min
Max
f
max
Maximum Clock
5.0
85
MHz
Frequency
t
PLH
Propagation Delay
5.0
1.5
14.0
ns
CP to Q
n
t
PHL
Propagation Delay
5.0
1.5
13.0
ns
CP to Q
n
t
PZH
Output Enable Time
5.0
1.5
14.0
ns
t
PZL
Output Enable Time
5.0
1.5
13.0
ns
t
PHZ
Output Disable Time
5.0
1.5
14.5
ns
t
PLZ
Output Disable Time
5.0
1.5
11.5
ns
Note 5: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
54ACT
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 6)
C
L
= 50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
5.0
ns
D
n
to CP
t
h
Hold Time, HIGH or LOW
5.0
3.0
ns
D
n
to CP
t
w
CP Pulse Width
5.0
5.0
ns
HIGH or LOW
Note 6: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation
40.0
pF
V
CC
= 5.0V
Capacitance
www.national.com
4
Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
16 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J16A
5
www.national.com
PDF 
ZIP