54ACTQ377
Octal D Flip-Flop with Clock Enable
General Description
The ACTQ377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D in-
put, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop's Q output.
The CE input must be stable only one setup time prior to the
LOW-to-HIGH clock transition for predictable operation.
The ACTQ377 utilizes FACT Quiet Series
technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series features GTO
output control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
n
Ideal for addressable register applications
n
Clock enable for address and data synchronization
applications
n
Eight edge-triggered D flip-flops
n
Buffered common clock
n
Outputs source/sink 24 mA
n
See '273 for master reset version
n
See '373 for transparent latch version
n
See '374 for TRI-STATE
version
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
TTL-compatible inputs and outputs
n
Standard Microcircuit Drawing (SMD) 5962-9219001
Logic Symbols
Pin
Names
Description
D
0
D
7
Data Inputs
CE
Clock Enable (Active LOW)
Q
0
Q
7
Data Outputs
CP
Clock Pulse Input
GTO
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
and FACT Quiet Series
are registered trademarks of Fairchild Semiconductor Corporation.
DS100357-1
IEEE/IEC
DS100357-2
September 1998
54ACTQ377
Octal
D
Flip-Flop
with
Clock
Enable
1998 National Semiconductor Corporation
DS100357
www.national.com
Connection Diagrams
Mode Select-Function Table
Operating Mode
Inputs
Outputs
CP
CE
D
n
Q
n
Load `1'
N
L
H
H
Load `0'
N
L
L
L
Hold (Do Nothing)
N
H
X
No Change
X
H
X
No Change
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
N = LOW-to-HIGH Clock Transition
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100357-3
Pin Assignment
for LCC
DS100357-4
DS100357-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACTQ
-55C to +125C
Minimum Input Edge Rate (
V/
t)
'ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
circuits outside databook specifications.
DC Characteristics for 'ACTQ Family Devices
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 2)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 2)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
CCT
Maximum
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
CC
/Input
I
OLD
(Note 3)
5.5
50
mA
V
OLD
= 1.65V Max
Minimum Dynamic
I
OHD
Output Current
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
160.0
A
V
IN
= V
CC
Supply Current
or GND
V
OLP
Quiet Output Maximum
Dynamic V
OL
5.0
1.5
V
(Note 4)
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3
DC Characteristics for 'ACTQ Family Devices
(Continued)
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
OLV
Quiet Output Minimum
Dynamic V
OL
5.0
-1.2
V
(Note 4)
Note 2:
*
All outputs loaded; thresholds on input associated with output under test.
Note 3:
Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. one output GND.
AC Electrical Characteristics
54ACTQ
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note 5)
C
L
= 50 pF
Min
Max
f
max
Maximum Clock
5.0
85
MHz
Frequency
t
PLH
Propagation Delay
5.0
1.5
10.0
ns
CP to Q
n
t
PHL
Propagation Delay
5.0
1.5
10.0
ns
CP to Q
n
Note 5: Voltage Range 5.0 is 5.0V
0.5V
AC Operating Requirements
54ACTQ
V
CC
T
A
= -55C
Fig.
Symbol
Parameter
(V)
to +125C
Units
No.
(Note
6)
C
L
= 50 pF
Guaranteed Minimum
t
s
Setup Time, HIGH or LOW
5.0
4.0
ns
D
n
to CP
t
h
Hold Time, HIGH or LOW
5.0
1.5
ns
D
n
to CP
t
s
Setup Time, HIGH or LOW
5.0
5.0
ns
CE to CP
t
h
Hold Time, HIGH or LOW
5.0
1.5
ns
CE to CP
t
w
CP Pulse Width
5.0
5.0
ns
HIGH or LOW
Note 6: Voltage Range 5.0 is 5.0V
0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
10.0
pF
V
CC
= OPEN
C
PD
Power Dissipation
80.0
pF
V
CC
= 5.0V
Capacitance
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Physical Dimensions
inches (millimeters) unless otherwise noted
20 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E20A
20 Lead Ceramic Dual-In-Line Package (D)
NS Package Number J20A
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5
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
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20 Lead Ceramic Flatpak (F)
NS Package Number W20A
54ACTQ377
Octal
D
Flip-Flop
with
Clock
Enable
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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