54ACTQ574
Quiet Series Octal D Flip-Flop with TRI-STATE
Outputs
General Description
The ACTQ574 is a high-speed, low-power octal D-type
flip-flop with a buffered Common Clock (CP) and a buffered
common Output Enable (OE). The information presented to
the D inputs is stored in the flip-flops on the LOW-to-HIGH
clock (CP) transition.
ACTQ574 utilizes Quiet Series technology to guarantee
quiet output switching and improve dynamic threshold per-
formance. FACT Quiet Series
TM
features GTO
TM
output con-
trol and undershoot corrector in addition to a split ground bus
for superior performance.
The ACTQ574 is functionally identical to the 'ACTQ374 but
with different pin-out.
Features
n
I
CC
and I
OZ
reduced by 50%
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Inputs and outputs on opposite sides of the package
allowing easy interface with microprocessors
n
Functionally identical to the ACTQ374
n
TRI-STATE outputs drive bus lines or buffer memory
address registers
n
Outputs source/sink 24 mA
n
Faster prop delays than the standard ACT574
n
4 kV minimum ESD immunity
Logic Diagrams
Pin Names
Description
D
0
D
7
Data Inputs
CP
Clock Pulse Input
OE
TRI-STATE Output Enable Input
O
0
O
7
TRI-STATE Outputs
GTO
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100243-1
IEEE/IEC
DS100243-2
August 1998
54ACTQ574
Quiet
Series
Octal
D
Flip-Flop
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100243
www.national.com
Connection Diagrams
Functional Description
The ACTQ574 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
go to the high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs
Internal
Outputs
Function
OE
CP
D
Q
O
N
H
H
L
NC
Z
Hold
H
H
H
NC
Z
Hold
H
N
L
L
Z
Load
H
N
H
H
Z
Load
L
N
L
L
L
Data Available
L
N
H
H
H
Data Available
L
H
L
NC
NC
No Change in
Data
L
H
H
NC
NC
No Change in
Data
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N
= LOW-to-HIGH Transition
NC = No Change
Logic Diagram
Pin Assignment
for DIP and Flatpak
DS100243-3
Pin Assignment for LCC
DS100243-4
DS100243-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2
Absolute Maximum Ratings
(Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source or
Sink Current
300 mA
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACTQ
-55C to +125C
Minimum Input Edge Rate
V/
t
'ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from -40C to +125C.
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
TM
circuits outside databook specifications.
DC Electrical Characteristics for 'ACTQ Family Devices
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 3)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 3)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input Leakage Current
5.5
1.0
A
V
I
= V
CC
, GND
I
OZ
Maximum TRI-STATE
5.5
5.0
A
V
I
= V
IL
, V
IH
Leakage Current
V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
OLD
(Note 4)
5.5
50
mA
V
OLD
= 1.65V Max
Minimum Dynamic
I
OHD
Output Current
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
80.0
A
V
IN
= V
CC
Supply Current
or GND (Note 5)
3
www.national.com
DC Electrical Characteristics for 'ACTQ Family Devices
(Continued)
54ACTQ
Symbol
Parameter
V
CC
T
A
=
Units
Conditions
(V)
-55C to +125C
Guaranteed Limits
V
OLP
Quiet Output
5.0
1.5
V
(Notes 6, 7)
Maximum Dynamic V
OL
V
OLV
Quiet Output
5.0
-1.2
V
(Notes 6, 7)
Minimum Dynamic V
OL
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
CC
for 54ACTQ
@
25C is identical to 74ACTQ
@
25C.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
@
GND.
Note 8: Max number of data inputs (n) switching. (n-1) inputs switching 0V to 3V ('ACTQ). Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold (V
IHD
),
f = 1 MHz.
AC Electrical Characteristics
54ACTQ
V
CC
T
A
= -55C
Symbol
Parameter
(V)
to +125C
Units
(Note 9)
C
L
= 50 pF
Min
Max
f
max
Maximum Clock
Frequency
5.0
95
MHz
t
PLH
,
Propagation Delay
5.0
1.0
11.0
ns
t
PHL
CP to O
n
t
PZH
,
Output Enable Time
5.0
1.0
11.0
ns
t
PZL
t
PHZ
,
Output Disable Time
5.0
1.0
10.0
ns
t
PLZ
Note 9: Voltage Range 5.0 is 5.0V
0.5V.
Note 10: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The speci-
fication applies to any outputs switching in the same direction, either HIGH to LOW (t
OSHL
) or LOW to HIGH (t
OSLH
). Parameter guaranteed by design.
AC Operating Requirements
54ACTQ
V
CC
T
A
= -55C
Symbol
Parameter
(V)
to +125C
Units
(Note 11)
C
L
= 50 pF
Guaranteed Minimum
t
S
Setup Time, HIGH or LOW
5.0
3.5
ns
D
n
to CP
t
H
Hold Time, HIGH or LOW
5.0
2.0
ns
D
n
to CP
t
W
CP Pulse Width,
5.0
5.0
ns
HIGH or LOW
Note 11: Voltage Range 5.0 is 5.0V
0.5V
www.national.com
4
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation Capacitance
40.0
pF
V
CC
= 5.0V
5
www.national.com
PDF 
ZIP