54ACTQ827
Quiet Series 10-Bit Buffer/Line Driver with TRI-STATE
Outputs
General Description
The 'ACTQ827 10-bit bus buffer provides high performance
bus interface buffering for wide data/address paths or buses
carrying parity. The 10-bit buffers have NOR output enables
for maximum control flexibility. The 'ACTQ827 utilizes NSC
Quiet Series technology to guarantee quiet output switching
and improved dynamic threshold performance. FACT Quiet
Series
TM
feature GTO
TM
output control and undershoot cor-
rector in addition to a split ground bus for superior perfor-
mance.
Features
n
Guaranteed simultaneous switching noise level and
dynamic threshold performance
n
Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
n
Improved latch-up immunity
n
Outputs source/sink 24 mA
n
Functionally and pin-compatible to AMD's AM29827
n
'ACTQ827 has TTL-compatible inputs
n
4 kV minimum ESD immunity
n
Standard Microcircuit Drawing (SMD) 5962-92199
Logic Symbols
Pin Names
Description
OE
1
, OE
2
Output Enable
D
0
D
9
Data Inputs
O
0
O
9
Data Outputs
Connection Diagrams
GTO
TM
is a trademark of National Semiconductor Corporation.
TRI-STATE
is a registered trademark of National Semiconductor Corporation.
FACT
is a registered trademark of Fairchild Semiconductor Corporation.
FACT Quiet Series
TM
is a trademark of Fairchild Semiconductor Corporation.
DS100249-1
IEEE/IEC
DS100249-2
Pin Assignment
for DIP and Flatpak
DS100249-3
Pin Assignment for LCC
DS100249-4
August 1998
54ACTQ827
Quiet
Series
10-Bit
Buffer/Line
Driver
with
TRI-ST
A
T
E
Outputs
1998 National Semiconductor Corporation
DS100249
www.national.com
Functional Description
The 'ACTQ827 line driver is designed to be employed as
memory address driver, clock driver and bus-oriented
transmitter/receiver. The devices have TRI-STATE outputs
controlled by the Output Enable (OE) pins. When the OE is
LOW, the device is transparent. When OE is HIGH, the de-
vice is in TRI-STATE mode.
Function Table
Inputs
Outputs
Function
OE
D
n
O
n
L
H
H
Transparent
L
L
L
Transparent
H
X
Z
High Z
H = HIGH Voltage Level
L = LOW Voltage Level
Z = HIGH Impedance
X = Immaterial
Logic Diagram
DS100249-5
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings
(Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
CC
)
-0.5V to +7.0V
DC Input Diode Current (I
IK
)
V
I
= -0.5V
-20 mA
V
I
= V
CC
+ 0.5V
+20 mA
DC Input Voltage (V
I
)
-0.5V to V
CC
+ 0.5V
DC Output Diode Current (I
OK
)
V
O
= -0.5V
-20 mA
V
O
= V
CC
+ 0.5V
+20 mA
DC Output Voltage (V
O
)
-0.5V to V
CC
+ 0.5V
DC Output Source
or Sink Current (I
O
)
50 mA
DC V
CC
or Ground Current
per Output Pin (I
CC
or I
GND
)
50 mA
Storage Temperature (T
STG
)
-65C to +150C
DC Latch-Up Source
or Sink Current
300 mA
Junction Temperature (T
J
)
CDIP
175C
Recommended Operating
Conditions
Supply Voltage (V
CC
)
'ACTQ
4.5V to 5.5V
Input Voltage (V
I
)
0V to V
CC
Output Voltage (V
O
)
0V to V
CC
Operating Temperature (T
A
)
54ACTQ
-55C to +125C
Minimum Input Edge Rate
V/
t
'ACTQ Devices
V
IN
from 0.8V to 2.0V
V
CC
@
4.5V, 5.5V
125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of FACT
circuits outside databook specifications.
Note 2: All commercial packaging is not recommended for applications re-
quiring greater than 2000 temperature cycles from -40C to +125C.
DC Electrical Characteristics for 'ACTQ Family Devices
Symbol
Parameter
V
CC
(V)
54ACTQ
Units
Conditions
T
A
= -55C to +125C
Guaranteed Limits
V
IH
Minimum High Level
4.5
2.0
V
V
OUT
= 0.1V
Input Voltage
5.5
2.0
or V
CC
- 0.1V
V
IL
Maximum Low Level
4.5
0.8
V
V
OUT
= 0.1V
Input Voltage
5.5
0.8
or V
CC
- 0.1V
V
OH
Minimum High Level
4.5
4.4
V
I
OUT
= -50 A
Output Voltage
5.5
5.4
(Note 3)
V
IN
= V
IL
or V
IH
4.5
3.70
V
I
OH
= -24 mA
5.5
4.70
I
OH
= -24 mA
V
OL
Maximum Low Level
4.5
0.1
V
I
OUT
= 50 A
Output Voltage
5.5
0.1
(Note 3)
V
IN
= V
IL
or V
IH
4.5
0.50
V
I
OL
= 24 mA
5.5
0.50
I
OL
= 24 mA
I
IN
Maximum Input
5.5
1.0
A
V
I
= V
CC
, GND
Leakage Current
I
OZ
Maximum TRI-STATE
5.5
10.0
A
V
I
= V
IL
, V
IH
Current
V
O
= V
CC
, GND
I
CCT
Maximum I
CC
/Input
5.5
1.6
mA
V
I
= V
CC
- 2.1V
I
OLD
(Note 4) Minimum Dynamic
5.5
50
mA
V
OLD
= 1.65V Max
I
OHD
Output Current
5.5
-50
mA
V
OHD
= 3.85V Min
I
CC
Maximum Quiescent
5.5
160.0
A
V
IN
= V
CC
Supply Current
or GND (Note 5)
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3
DC Electrical Characteristics for 'ACTQ Family Devices
(Continued)
Symbol
Parameter
V
CC
(V)
54ACTQ
Units
Conditions
T
A
= -55C to +125C
Guaranteed Limits
V
OLP
Quiet Output
5.0
1.5
V
Maximum Dynamic V
OL
(Notes 6, 7)
V
OLV
Quiet Output
5.0
-1.2
V
Minimum Dynamic V
OL
(Notes 6, 7)
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: I
CC
for 54ACTQ
@
25C is identical to 74ACTQ
@
25C.
Note 6: Plastic DIP package.
Note 7: Max number of outputs defined as (n). Data inputs are driven 0V to 3V. One output
@
GND.
Note 8: Max number of data inputs (n-1) inputs switching 0V to 3V ('ACTQ). Input-under-test switching: 3V to threshold (V
ILD
), 0V to threshold. (V
IHD
), f = 1 MHz.
AC Electrical Characteristics
54ACTQ
V
CC
T
A
= -55C
Symbol
Parameter
(V)
to +125C
Units
(Note 9)
C
L
= 50 pF
Min
Max
t
PHL
, t
PLH
Propagation Delay
5.0
2.0
9.0
ns
Data to Output
t
PZL
, t
PZH
Output Enable Time
5.0
2.0
12.5
ns
t
PHZ
, t
PLZ
Output Disable Time
5.0
1.0
9.0
ns
Note 9: Voltage Range 5.0 is 5.0V
0.5V.
Capacitance
Symbol
Parameter
Typ
Units
Conditions
C
IN
Input Capacitance
4.5
pF
V
CC
= OPEN
C
PD
Power Dissipation
82
pF
V
CC
= 5.0V
Capacitance
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AC Loading
AC Waveforms
DS100249-9
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
DS100249-10
FIGURE 2. Test Input Signal Levels
Amplitude
Rep. Rate
t
w
t
r
t
f
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 3. Test Input Signal Requirements
DS100249-11
FIGURE 4. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
DS100249-12
FIGURE 5. TRI-STATE Output HIGH and LOW
Enable and Disable Time
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